74HC259D,652

74HC259; 74HCT259 8-bit addressable latch Rev. 6 — 2 February 2016 Product data sheet 1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits          Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Complies with JEDEC standard no. 7A Input levels:  For 74HC259: CMOS level  For 74HCT259: TTL level  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22E exceeds 1000 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 74HC259; 74HCT259 Nexperia 8-bit addressable latch 3. Ordering information Table 1. Ordering information Type number 74HC259D Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm 74HCT259D 74HC259DB 74HCT259DB 74HC259PW 74HCT259PW 74HC259BQ 74HCT259BQ 4. Functional diagram  =  *  * ' ';   /( 4  ' 4 4 4    $ 4 $ 4 $ 4 05  Fig 1. Logic symbol 74HC_HCT259 Product data sheet 4       *      & 5                     PQD PQD Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 2 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 4   $ 4   $ 4   $ 4  4  RI '(&2'(5 /$7&+(6  /( 4   05 4   ' 4  PQD Fig 3. Functional diagram 5. Pinning information 5.1 Pinning  $ WHUPLQDO LQGH[DUHD +& +&7  9&& +& +&7 $   05 $    /(   9&&  05 $ $ 4   ' $   /( 4  4   ' 4  4   4 4  4   4 4   4 *1'    4 4  4  4 *1'   4 *1' DDM 7UDQVSDUHQWWRSYLHZ DDM (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO16, SSOP16 and TSSOP16 74HC_HCT259 Product data sheet Fig 5. Pin configuration DHVQFN16 All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 3 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 5.2 Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output GND 8 ground (0 V) D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage 6. Functional description Table 3. Function table[1] Operating mode Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X X L L L L L L L L Demultiplexer L (active HIGH 8-channel) L decoder (when D = H) L L d L L L Q=d L L L L L L L L d H L L L Q=d L L L L L L L d L H L L L Q=d L L L L L L L d H H L L L L Q=d L L L L L L d L L H L L L L Q=d L L L L L d H L H L L L L L Q=d L L L L d L H H L L L L L L Q=d L L L d H H H L L L L L L L Q=d Reset (clear) Memory (no action) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 Addressable latch H L d L L L Q = d q1 q2 q3 q4 q5 q6 q7 H L d H L L q0 Q = d q2 q3 q4 q5 q6 q7 H L d L H L q0 q1 Q = d q3 q4 q5 q6 q7 H L d H H L q0 q1 q2 Q = d q4 q5 q6 q7 H L d L L H q0 q1 q2 q3 Q = d q5 q6 q7 H L d H L H q0 q1 q2 q3 q4 Q = d q6 q7 H L d L H H q0 q1 q2 q3 q4 q5 Q = d q7 H L d H H H q0 q1 q2 q3 q4 q5 q6 [1] Q=d H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 4 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 4. Operating mode select table[1] LE MR Mode L H Addressable latch mode H H Memory mode L L Demultiplexer mode H L Reset mode [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.0 V - 20 mA - 20 mA input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to VCC + 0.5 V - 25 mA ICC supply current - +70 mA IGND ground current 70 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation IIK Tamb = 40 C to +125 C SO16 package [2] - 500 mW (T)SSOP16 package [3] - 500 mW DHVQFN16 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. [4] Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 5 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC259 74HCT259 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V output voltage 0 - VCC 0 - VCC V VCC supply voltage VI VO Tamb ambient temperature t/V input transition rise and fall rate 40 - +125 40 - +125 VCC = 2.0 V - - 625 - - - ns/V C VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V 74HC259 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V VI = VIH or VIL IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V VI = VIH or VIL - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 6 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT259 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V VOL CI input capacitance 74HC_HCT259 Product data sheet pin An, LE - 150 540 - 675 - 735 A pin D - 120 432 - 540 - 588 A pin MR - 75 270 - 338 - 368 A - 3.5 - - - - - pF All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 7 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max - 58 185 - 230 - 280 74HC259 tpd propagation delay [2] D to Qn; see Figure 6 VCC = 2.0 V VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 18 - - - - - ns - 17 31 - 39 - 48 ns VCC = 2.0 V - 58 185 - 230 - 280 ns VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns - 17 31 - 39 - 48 ns VCC = 2.0 V - 55 170 - 215 - 255 ns VCC = 4.5 V - 20 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 29 - 37 - 43 ns VCC = 2.0 V - 50 155 - 195 - 235 ns VCC = 4.5 V - 18 31 - 39 - 47 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 40 ns VCC = 2.0 V - 19 75 - 95 - 119 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 6.0 V An to Qn; see Figure 7 [2] VCC = 6.0 V LE to Qn; see Figure 8 tPHL tt tW HIGH to LOW propagation delay transition time pulse width ns [2] MR to Qn; see Figure 9 [3] see Figure 8 LE HIGH or LOW; see Figure 8 VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns MR LOW; see Figure 9 74HC_HCT259 Product data sheet VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 8 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu th set-up time hold time 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns D, An to LE; see Figure 10 and Figure 11 D to LE; see Figure 10 and Figure 11 VCC = 2.0 V 0 19 - 0 - 0 - ns VCC = 4.5 V 0 6 - 0 - 0 - ns VCC = 6.0 V 0 5 - 0 - 0 - ns VCC = 2.0 V 2 11 - 2 - 2 - ns VCC = 4.5 V 2 4 - 2 - 2 - ns 2 3 - 2 - 2 - ns - 19 - - - - - pF - 23 39 - 49 - 59 ns - 20 - - - - - ns An to LE; see Figure 10 and Figure 11 VCC = 6.0 V CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [4] D to Qn; see Figure 6 [2] 74HCT259 tpd propagation delay VCC = 4.5 V VCC = 5.0 V; CL = 15 pF An to Qn; see Figure 7 VCC = 4.5 V - 25 41 62 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - 23 39 - 49 - 59 ns - 20 - - - - - ns - 7 15 - 19 - 22 ns 19 11 - 24 - 29 - ns 18 10 - 23 - 27 - ns LE to Qn; see Figure 8 tPHL tt HIGH to LOW propagation delay transition time pulse width 51 [2] MR to Qn; see Figure 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF [3] see Figure 8 VCC = 4.5 V tW [2] LE HIGH or LOW; see Figure 8 VCC = 4.5 V MR LOW; see Figure 9 VCC = 4.5 V 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 9 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu set-up time 25 C Conditions Min Max Min Max Min Max 17 10 - 21 - 26 - ns 0 8 - 0 - 0 - ns 0 4 - 0 - 0 - ns - 19 - - - - - pF D, An to LE; see Figure 10 and Figure 11 VCC = 4.5 V hold time th 40 C to +85 C 40 C to +125 C Unit Typ[1] D to LE; see Figure 10 and Figure 11 VCC = 4.5 V An to LE; see Figure 10 and Figure 11 VCC = 4.5 V power dissipation capacitance CPD [1] fi = 1 MHz; VI = GND to VCC  1.5 V [4] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 11. Waveforms 9&& 'LQSXW 90 *1' W3+/ W3/+ 92+ 90 4QRXWSXW 92/ DDK Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Data input to output propagation delays 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 10 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 9&& 90 $QLQSXW *1' W3/+ W3+/ 92+ 90 4QRXWSXW 92/ DDK Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Address input to output propagation delays 9&& 'LQSXW *1' 9&& 90 /(LQSXW *1' W: W3+/ 92+ W3/+ 9< 90 4QRXWSXW 9; 92/ W7+/ W7/+ DDM Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Enable input to output propagation delays and pulse width 9&& 05LQSXW 90 *1' W: W3+/ 92+ 90 4QRXWSXW  92/ DDK Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Master reset input to output propagation delays 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 11 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 9&& /(LQSXW 90 *1' WVX WVX WK 9&& WK 90 'LQSXW *1' 92+ 4QRXWSXW 90 4 ' 4 ' 92/ DDK Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. Data input to latch enable input set-up and hold times 9&& $QLQSXW 90 $''5(6667$%/( *1' WVX WK 9&& /(LQSXW 90 *1' DDK Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. Address input to latch enable input set-up and hold times Table 9. Measurement points Type Input Output VM VM VX VY 74HC259 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT259 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 12 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 9, W:  QHJDWLYH SXOVH 90 9 WI WU WU WI 9,  SRVLWLYH SXOVH 9 90  90 90  W: 9&& 9&& * 9, 92 5/ 6 RSHQ '87 &/ 57 DDG Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC259 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT259 3V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 13 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 13. Package outline SOT109-1 (SO16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 14 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 14. Package outline SOT338-1 (SSOP16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 15 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 15. Package outline SOT403-1 (TSSOP16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 16 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV 627 WHUPLQDOVERG\[[PP % ' $ $ $ ( F GHWDLO; WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD & H H E   \ \ & Y 0 & $ % Z 0 & /   (K H     'K ;   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ E F ' 'K ( (K H H / Y Z \ \ PP                       1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627  02  (8523($1 352-(&7,21 ,668('$7(    Fig 16. Package outline SOT763-1 (DHVQFN16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 17 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT259 v.6 20160202 Product data sheet - 74HC_HCT259 v.5 Modifications: 74HC_HCT259 v.5 Modifications: 74HC_HCT259 v.4 Modifications: 74HC_HCT259 v.3 • Type numbers 74HC259N and 74HCT259N (SOT38-4) removed. 20120807 Product data sheet - 74HC_HCT259 v.4 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP. • Legal texts have been adapted to the new company name where appropriate. 20090225 • • Product data sheet - 74HC_HCT259 v.3 Added type number 74HC259N and 74HCT259N (DIP16 package) Added type number 74HC259DB and 74HCT259DB (SSOP16 package) 20090108 74HC_HCT259_CNV v.2 19970828 74HC_HCT259 Product data sheet • Product data sheet - 74HC_HCT259_CNV v.2 Product specification - - All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 18 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT259 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 19 of 21 © Nexperia B.V. 2017. All rights reserved 74HC259; 74HCT259 Nexperia 8-bit addressable latch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. . Rev. 6 — 2 February 2016 20 of 21 © Nexperia B.V. 2017. All rights reserved Nexperia 74HC259; 74HCT259 8-bit addressable latch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 02 February 2016