HEF4043BT,653

HEF4043B Quad R/S latch with 3-state outputs Rev. 12 — 30 January 2020 Product 1. General description The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input (1R to 4R) and an active HIGH 3-state output (1Q to 4Q). When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs (see Table 3). When OE is LOW, the latch outputs are in the high impedance OFF-state. OE does not affect the state of the latch. The high impedance off-state feature allows common bussing of the outputs. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits • • • • • Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from -40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications • Four-bit storage with output enable 4. Ordering information Table 1. Ordering information All types operate from -40 °C to +85 °C. Type number HEF4043BT Package Name Description Version SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4043B Nexperia Quad R/S latch with 3-state outputs 5. Functional diagram 4 1S 1Q 2 3 1R 6 2S 2Q 9 7 2R 3-STATE OUTPUTS 12 3S nS nQ 3Q 10 11 3R 14 4S nR 4Q 1 15 4R OE 5 OE to other latches 001aae616 Fig. 1. 001aae618 Functional diagram Fig. 2. Logic diagram for one latch 6. Pinning information 6.1. Pinning HEF4043B 4Q 1 16 VDD 1Q 2 15 4R 1R 3 14 4S 1S 4 13 n.c. OE 5 12 3S 2S 6 11 3R 2R 7 10 3Q VSS 8 9 2Q 001aae617 Fig. 3. HEF4043B Product Pin configuration SOT109-1 (SO16) All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 2 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 6.2. Pin description Table 2. Pin description Symbol Pin Description 1Q to 4Q 2, 9, 10, 1 3-state buffered latch output 1R to 4R 3, 7, 11, 15 reset input (active HIGH) 1S to 4S 4, 6, 12, 14 set input (active HIGH) OE 5 common output enable input VSS 8 ground supply voltage n.c. 13 not connected VDD 16 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state. Output Inputs OE nS nR nQ L X X Z H L H L H H X H H L L latched 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature Ptot total power dissipation Conditions VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V HEF4043B Product power dissipation Max Unit -0.5 +18 V - ±10 mA -0.5 VDD + 0.5 - ±10 mA - ±10 mA - 50 mA -65 +150 °C -40 +85 °C - 500 mW - 100 mW V Tamb -40 °C to +85 °C • P Min SO16 package per output All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 3 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +85 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current II input leakage current IOZ OFF-state output current IDD CI HEF4043B Product supply current input capacitance Conditions VDD Tamb = -40 °C Tamb = 25 °C Tamb = 85 °C Unit Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 mA VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 μA nQ output HIGH; returned to VDD 15 V - 1.6 - 1.6 - 12.0 μA nQ output LOW; returned to VSS 15 V - 1.6 - 1.6 - 12.0 μA IO = 0 A 5V - 20 - 20 - 150 μA 10 V - 40 - 40 - 300 μA 15 V - 80 - 80 - 600 μA - - - 7.5 - - pF |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 4 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; For waveforms and test circuit see Section 11.1; unless otherwise specified. Symbol Parameter Conditions VDD Extrapolation formula tPHL HIGH to LOW propagation delay nR → nQ; see Fig. 4 5V LOW to HIGH propagation delay nS → nQ; see Fig. 4 10 V 15 V tPLH tt transition time tPHZ tPLZ LOW to OFF-state propagation delay tPZH tPZL tW [1] [2] HIGH to OFF-state propagation delay nQ output; see Fig. 4 Typ Max Unit [1] 63 ns + (0.55 ns/pF)CL - 90 180 ns 24 ns + (0.23 ns/pF)CL - 35 70 ns 17 ns + (0.16 ns/pF)CL - 25 50 ns [1] 38 ns + (0.55 ns/pF)CL - 65 135 ns 10 V 14 ns + (0.23 ns/pF)CL - 25 50 ns 15 V 7 ns + (0.16 ns/pF)CL - 15 35 ns - 60 120 ns 5V 5V [1] [2] 10 ns + (1.00 ns/pF)CL 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V - 45 90 ns 10 V - 20 35 ns 15 V - 10 25 ns 5V - 50 100 ns 10 V - 20 40 ns 15 V - 10 25 ns 5V - 25 50 ns 10 V - 15 30 ns 15 V - 10 25 ns 5V - 40 80 ns 10 V - 20 45 ns 15 V - 15 35 ns nS input HIGH; 5 V minimum width; 10 V see Fig. 4 15 V 30 15 - ns 20 10 - ns 16 8 - ns nR input HIGH; 5 V minimum width; 10 V see Fig. 4 15 V 30 15 - ns 20 10 - ns 16 8 - ns OE → nQ; see Fig. 5 OE → nQ; see Fig. 5 OFF-state to HIGH propagation delay OE → nQ; see Fig. 5 OFF-state to LOW propagation delay OE → nQ; see Fig. 5 pulse width Min The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). tt is the same as tTHL and tTLH. Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD HEF4043B Product Parameter dynamic power dissipation VDD Typical formula for PD (μW) where: 5V PD = 10 V PD = 15 V PD = 11400 x fi + Σ(fo x CL) x VDD fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(fo x CL) = sum of the outputs. 2 1100 x fi + Σ(fo x CL) x VDD 2 4400 x fi + Σ(fo x CL) x VDD 2 All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 5 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 11.1. Waveforms tr VI tf 90 % input nS VM 0V 10 % tW VI input nR VM 0V tW tPLH VOH tPHL 90 % output nQ VM 10 % VOL tTLH tTHL 001aai286 tr and tf are the input rise and fall times. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times. Measurement points are given in Table 9 and test data is given in Table 10. Fig. 4. Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation delay and nQ transition time VDD OE input VSS tPLZ output LOW-to-OFF OFF-to-LOW tPZL VDD VY VX VSS tPHZ output HIGH-to-OFF OFF-to-HIGH VDD tPZH VY VX VSS outputs on outputs off outputs on 001aag355 Measurement points are given in Table 9. Fig. 5. Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ) Table 9. Measurement points Supply voltage Input Output VDD VI VM VM VX VY 5 V to 15 V VDD or 0 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD HEF4043B Product All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 6 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs VI negative pulse tW 90 % 90 % VM 10 % 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % 90 % VM VM 10 % 10 % tW 001aaj781 a. Input waveform VEXT VDD G VI RL VO DUT RT CL 001aaj915 b. Test circuit Test and measurement data is given in Table 10. Definitions test circuit: DUT = Device Under Test. RL = Load resistance; CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 5 V to 15 V VDD ≤ 20 ns 50 pF 1 kΩ open VDD GND HEF4043B Product Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 7 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 7. HEF4043B Product REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 8 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4043B v.12 20200130 Product data sheet - HEF4043B v.11 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Fig. 2: Typo corrected. HEF4043B v.11 20160324 Modifications: • HEF4043B v.10 20111118 Modifications: • HEF4043B v.9 20091216 Product data sheet - HEF4043B v.8 HEF4043B v.8 20091127 Product data sheet - HEF4043B v.7 HEF4043B v.7 20090710 Product data sheet - HEF4043B v.6 HEF4043B v.6 20081111 Product data sheet - HEF4043B v.5 HEF4043B v.5 20080729 Product data sheet - HEF4043B v.4 HEF4043B v.4 20080710 Product data sheet - HEF4043B_CNV v.3 HEF4043B_CNV v.3 19950101 Product specification - HEF4043B_CNV v.2 HEF4043B_CNV v.2 19950101 Product specification - - HEF4043B Product Product data sheet - HEF4043B v.10 Type number HEF4043BP (SOT38-4) removed. Product data sheet - HEF4043B v.9 Table 6: IOH minimum values changed to maximum All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 9 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 10 / 11 HEF4043B Nexperia Quad R/S latch with 3-state outputs Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................4 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................5 11.1. Waveforms................................................................. 6 12. Package outline.......................................................... 8 13. Revision history..........................................................9 14. Legal information......................................................10 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 January 2020 HEF4043B Product All information provided in this document is subject to legal disclaimers. Rev. 12 — 30 January 2020 © Nexperia B.V. 2020. All rights reserved 11 / 11