74HC259D-Q100,118

74HC259-Q100; 74HCT259-Q100 8-bit addressable latch Rev. 1 — 30 July 2012 Product data sheet 1. General description The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches designed for general-purpose storage applications in digital systems. They are multifunctional devices capable of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also incorporate an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The 74HC259-Q100; 74HCT259-Q100 has four modes of operation: • Addressable latch mode, in this mode data on the data line (D) is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. • Memory mode, in this mode all latches remain in their previous states and are unaffected by the data or address inputs. • Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows the state of the data input (D) with all other outputs in the LOW state. • Reset mode, in this mode all outputs are LOW and unaffected by the address inputs (A0 to A2) and data input (D). When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing more than one address bit could impose a transient wrong address. Therefore, this should only be done while in the Memory mode. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Combined demultiplexer and 8-bit latch  Serial-to-parallel capability  Output from each storage bit available  Random (addressable) data entry  Easily expandable  Common reset input 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch  Useful as a 3-to-8 active HIGH decoder  Input levels:  For 74HC259-Q100: CMOS level  For 74HCT259-Q100: TTL level  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 3. Ordering information Table 1. Ordering information Type number Package 74HC259D-Q100 Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm 74HCT259D-Q100 74HC259PW-Q100 74HCT259PW-Q100 74HC259BQ-Q100 74HCT259BQ-Q100 4. Functional diagram 13 Z9 15 G8 14 G10 9,10D DX 14 0 1 LE Q0 13 D Q1 Q2 Q3 1 2 3 A0 Q4 A1 Q5 A2 Q6 Q7 4 2 5 3 Fig 1. Logic symbol 74HC_HCT259_Q100 Product data sheet C10 8R 0 G 0 7 2 6 4 5 1 6 2 7 7 3 9 9 4 10 10 5 11 11 12 6 12 MR 15 1 7 mna573 mna572 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 2 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 1 A0 2 A1 3 A2 1-of-8 DECODER 8 LATCHES Q0 4 Q1 5 Q2 6 Q3 7 Q4 9 14 LE Q5 10 15 MR Q6 11 13 D Q7 12 mna571 Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 1 A0 terminal 1 index area 74HC259-Q100 74HCT259-Q100 16 VCC 74HC259-Q100 74HCT259-Q100 A0 1 3 14 LE 2 16 VCC 15 MR A2 A1 Q0 4 13 D A2 3 14 LE Q1 5 Q0 4 13 D Q2 6 Q1 5 12 Q7 Q3 7 Q2 6 11 Q6 8 9 15 MR Q3 7 10 Q5 GND 8 Q4 2 GND A1 9 Q4 12 Q7 GND(1) 11 Q6 10 Q5 aaa-003387 Transparent top view aaa-003386 (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input. Fig 4. Pin configuration (SO16 and TSSOP16) 74HC_HCT259_Q100 Product data sheet Fig 5. Pin configuration (DHVQFN16) All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 3 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 5.2 Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output GND 8 ground (0 V) D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage 6. Functional description Table 3. Function table[1] Operating mode Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X X L L L L L L L L Demultiplexer L (active HIGH 8-channel) L decoder (when D = H) L L d L L L Q=d L L L L L L L L d H L L L Q=d L L L L L L L d L H L L L Q=d L L L L L L L d H H L L L L Q=d L L L L L L d L L H L L L L Q=d L L L L L d H L H L L L L L Q=d L L L L d L H H L L L L L L Q=d L L L d H H H L L L L L L L Q=d Memory (no action) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 Addressable latch H L d L L L Q = d q1 q2 q3 q4 q5 q6 q7 H L d H L L q0 Q = d q2 q3 q4 q5 q6 q7 H L d L H L q0 q1 Q = d q3 q4 q5 q6 q7 H L d H H L q0 q1 q2 Q = d q4 q5 q6 q7 H L d L L H q0 q1 q2 q3 Q = d q5 q6 q7 H L d H L H q0 q1 q2 q3 q4 Q = d q6 q7 H L d L H H q0 q1 q2 q3 q4 q5 Q = d q7 H L d H H H q0 q1 q2 q3 q4 q5 q6 Reset (clear) [1] Q=d H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 4 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch Table 4. Operating mode select table[1] LE MR Mode L H Addressable latch mode H H Memory mode L L Demultiplexer mode H L Reset mode [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to VCC + 0.5 V Min Max Unit 0.5 +7.0 V - 20 mA - 20 mA - 25 mA ICC supply current - +70 mA IGND ground current 70 - mA Tstg storage temperature 65 +150 C - 500 mW Ptot [2] total power dissipation [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 5 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC259-Q100 Min Typ 74HCT259-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 - +125 40 - +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC259-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 6 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT259-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin An, LE - 150 540 - 675 - 735 A pin D - 120 432 - 540 - 588 A pin MR - 75 270 - 338 - 368 A - 3.5 - - - - - pF CI input capacitance 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 7 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max VCC = 2.0 V - 58 185 - 230 - 280 ns VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 18 - - - - - ns VCC = 6.0 V - 17 31 - 39 - 48 ns - 58 185 - 230 - 280 ns 74HC259-Q100 tpd propagation delay [2] D to Qn; see Figure 6 [2] An to Qn; see Figure 7 VCC = 2.0 V VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns - 17 31 - 39 - 48 ns VCC = 2.0 V - 55 170 - 215 - 255 ns VCC = 4.5 V - 20 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 29 - 37 - 43 ns VCC = 2.0 V - 50 155 - 195 - 235 ns VCC = 4.5 V - 18 31 - 39 - 47 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns - 14 26 - 33 - 40 ns VCC = 2.0 V - 19 75 - 95 - 119 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns VCC = 6.0 V [2] LE to Qn; see Figure 8 tPHL HIGH to LOW propagation delay MR to Qn; see Figure 9 VCC = 6.0 V tt tW transition time pulse width [3] see Figure 8 LE HIGH or LOW; see Figure 8 MR LOW; see Figure 9 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 8 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu th set-up time hold time 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 0 19 - 0 - 0 - ns VCC = 4.5 V 0 6 - 0 - 0 - ns VCC = 6.0 V 0 5 - 0 - 0 - ns VCC = 2.0 V 2 11 - 2 - 2 - ns VCC = 4.5 V 2 4 - 2 - 2 - ns 2 3 - 2 - 2 - ns - 19 - - - - - pF D, An to LE; see Figure 10 and Figure 11 D to LE; see Figure 10 and Figure 11 An to LE; see Figure 10 and Figure 11 VCC = 6.0 V CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [4] D to Qn; see Figure 6 [2] 74HCT259-Q100 tpd propagation delay VCC = 4.5 V - 23 39 - 49 - 59 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - 25 41 62 ns - 20 - - - - - ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - 23 39 - 49 - 59 ns - 20 - - - - - ns - 7 15 - 19 - 22 ns 19 11 - 24 - 29 - ns 18 10 - 23 - 27 - ns [2] An to Qn; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF [2] LE to Qn; see Figure 8 tPHL HIGH to LOW propagation delay 51 MR to Qn; see Figure 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF [3] tt transition time see Figure 8 tW pulse width LE HIGH or LOW; see Figure 8 VCC = 4.5 V VCC = 4.5 V MR LOW; see Figure 9 VCC = 4.5 V 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 9 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu set-up time 25 C Conditions Min Max Min Max Min Max 17 10 - 21 - 26 - ns 0 8 - 0 - 0 - ns 0 4 - 0 - 0 - ns - 19 - - - - - pF D, An to LE; see Figure 10 and Figure 11 VCC = 4.5 V hold time th 40 C to +85 C 40 C to +125 C Unit Typ[1] D to LE; see Figure 10 and Figure 11 VCC = 4.5 V An to LE; see Figure 10 and Figure 11 VCC = 4.5 V power dissipation capacitance CPD [1] fi = 1 MHz; VI = GND to VCC  1.5 V [4] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 11. Waveforms VCC D input VM GND tPHL tPLH VOH VM Qn output VOL 001aah123 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Data input to output propagation delays 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 10 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch VCC VM An input GND tPLH tPHL VOH VM Qn output VOL 001aah122 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Address input to output propagation delays VCC D input GND VCC VM LE input GND tW tPHL VOH tPLH VY VM Qn output VX VOL tTHL tTLH 001aaj446 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Enable input to output propagation delays and pulse width VCC MR input VM GND tW tPHL VOH VM Qn output VOL 001aah124 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Master reset input to output propagation delays 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 11 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch VCC LE input VM GND tsu tsu th VCC th VM D input GND VOH Qn output VM Q=D Q=D VOL 001aah125 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. Data input to latch enable input set-up and hold times VCC An input VM ADDRESS STABLE GND tsu th VCC LE input VM GND 001aah126 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. Address input to latch enable input set-up and hold times Table 9. Measurement points Type Input Output VM VM VX VY 74HC259-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT259-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 12 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12. Load circuit for measuring switching times Table 10. Test data Type Input VI tr, tf CL RL tPHL, tPLH 74HC259-Q100 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT259-Q100 3V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT259_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 S1 position © Nexperia B.V. 2017. All rights reserved 13 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT109-1 (SO16) 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 14 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 14. Package outline SOT403-1 (TSSOP16) 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 15 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT763-1 (DHVQFN16) 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 16 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date 74HC_HCT259_Q100 v.1 20120730 74HC_HCT259_Q100 Product data sheet Data sheet status Change notice Supersedes Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 17 of 20 74HC259-Q100; 74HCT259-Q100 Nexperia 8-bit addressable latch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT259_Q100 Product data sheet Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 18 of 20 Nexperia 74HC259-Q100; 74HCT259-Q100 8-bit addressable latch No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74HC_HCT259_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 July 2012 © Nexperia B.V. 2017. All rights reserved 19 of 20 Nexperia 74HC259-Q100; 74HCT259-Q100 8-bit addressable latch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 July 2012