74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Rev. 1 — 10 August 2012
Product data sheet
1. General description
The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC
standard no. 7A.
The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A
latch enable (LE) input and an output enable (OE) input are common to all latches.
The 74HC373-Q100; 74HCT373-Q100 consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this
condition the latches are transparent, i.e. a latch output changes state each time its
corresponding D input changes.
When LE is LOW, the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the highimpedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373-Q100; 74HCT373-Q100 is functionally identical to:
• 74HC573-Q100; 74HCT573-Q100: but different pin arrangement
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC373-Q100: CMOS level
For 74HCT373-Q100: TTL level
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Functionally identical to the 74HC573-Q100; 74HCT573-Q100
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
74HC373D-Q100
Temperature range Name
Description
Version
40 C to +125 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
40 C to +125 C
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
40 C to +125 C
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
74HCT373D-Q100
74HC373PW-Q100
74HCT373PW-Q100
74HC373BQ-Q100
74HCT373BQ-Q100
4. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
LATCH
1 TO 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
LE
11
OE
1
001aae050
Fig 1.
Functional diagram
OE
LE
1
11
EN
C1
11
3
4
7
8
13
14
17
18
D0
LE
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
2
D1
5
6
D2
9
D3
12
D4
15
D5
16
D6
19
OE
1
Fig 2.
Logic symbol
74HC_HCT373_Q100
Product data sheet
D7
3
2
1D
4
5
7
6
8
9
13
12
14
15
17
16
18
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae049
001aae048
Fig 3.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
2 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
LE
LE
LE
D
Q
LE
Fig 4.
001aae051
Logic diagram (one latch)
D0
D1
D
Q
D2
D
Q
D3
D
Q
D4
D
Q
D5
D
Q
D6
D
Q
D7
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5.
Logic diagram
74HC_HCT373_Q100
Product data sheet
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Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
3 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
+&4
+&74
9&&
4
4
'
'
'
'
4
4
WHUPLQDO
LQGH[DUHD
2(
2(
9&&
+&4
+&74
4
4
'
'
'
'
4
4
4
4
4
4
'
'
'
'
4
4
*1'
/(
*1'
/(
'
'
'
4
*1'
'
4
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 6.
Pin configuration SO20 and TSSOP20
Fig 7.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
OE
1
3-state output enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
2, 5, 6, 9, 12, 15, 16, 19
3-state latch output
D0, D1, D2, D3, D4, D5, D6, D7
3, 4, 7, 8, 13, 14, 17, 18
data input
GND
10
ground (0 V)
LE
11
latch enable input (active HIGH)
VCC
20
supply voltage
74HC_HCT373_Q100
Product data sheet
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Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
4 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
Table 3.
Function table[1]
Operating mode
Control
Input
Internal latches
Output
OE
LE
Dn
Enable and read register
(transparent mode)
L
H
L
L
L
H
H
H
Latch and read register
L
l
L
L
h
H
H
X
X
Z
Latch register and disable
outputs
[1]
H
L
X
Qn
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
-
35
mA
ICC
supply current
-
+70
mA
IGND
ground current
-
70
mA
Tstg
storage temperature
65
+150
C
-
500
mW
500
mW
500
mW
total power dissipation
Ptot
SO20 package
[1]
TSSOP20 package
[2]
DHVQFN20 package
[3]
[1]
For SO20: Ptot derates linearly with 8 mW/K above 70 C.
[2]
For TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[3]
For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
-
©
Nexperia B.V. 2017. All rights reserved
5 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC373-Q100
Min
Typ
74HCT373-Q100
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
1.2
-
V
VCC = 4.5 V
3.15
2.4
-
V
VCC = 6.0 V
4.2
3.2
-
V
9. Static characteristics
Table 6.
Static characteristics 74HC373-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Tamb = 25 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VCC = 2.0 V
-
0.8
0.5
V
VCC = 4.5 V
-
2.1
1.35
V
VCC = 6.0 V
-
2.8
1.8
V
VI = VIH or VIL
-
-
-
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
V
IO = 6.0 mA; VCC = 4.5 V
3.98
4.32
-
V
IO = 7.8 mA; VCC = 6.0 V
5.48
5.81
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
0.15
0.26
V
IO = 7.8 mA; VCC = 6.0 V
-
0.16
0.26
V
VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
0.1
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
0.5
A
ICC
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
-
8.0
A
CI
input capacitance
-
3.5
-
pF
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
6 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 6.
Static characteristics 74HC373-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 6.0 mA; VCC = 4.5 V
3.84
-
-
V
IO = 7.8 mA; VCC = 6.0 V
5.34
-
-
V
Tamb = 40 C to +85 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
-
0.33
V
IO = 7.8 mA; VCC = 6.0 V
-
-
0.33
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
5.0
A
ICC
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
80
A
-
-
V
Tamb = 40 C to +125 C
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
74HC_HCT373_Q100
Product data sheet
VCC = 2.0 V
1.5
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 6.0 mA; VCC = 4.5 V
3.7
-
-
V
IO = 7.8 mA; VCC = 6.0 V
5.2
-
-
V
VI = VIH or VIL
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Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
7 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 6.
Static characteristics 74HC373-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
-
0.4
V
IO = 7.8 mA; VCC = 6.0 V
-
-
0.4
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
10.0
A
ICC
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
-
160
A
Conditions
Min
Typ
Max
Unit
Table 7.
Static characteristics 74HCT373-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Tamb = 25 C
VIH
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
V
VOH
HIGH-level output voltage
VI = VIH or VIL
VOL
LOW-level output voltage
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
V
IO = 6.0 mA; VCC = 4.5 V
3.98
4.32
-
V
-
0.0
0.1
V
VI = VIH or VIL
IO = 20 A; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
-
0.16
0.26
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
0.1
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
-
-
0.5
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
A
ICC
additional supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
-
30
108
A
LE
-
150
540
A
OE
CI
input capacitance
-
100
360
A
-
3.5
-
pF
Tamb = 40 C to +85 C
VIH
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
8 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 7.
Static characteristics 74HCT373-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VOH
HIGH-level output voltage
VI = VIH or VIL
VOL
LOW-level output voltage
Min
Typ
Max
Unit
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 6.0 A; VCC = 4.5 V
3.84
-
-
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 6.0 mA; VCC = 4.5 V
-
-
0.33
V
VI = VIH or VIL
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
-
-
5.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
80
A
ICC
additional supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
-
-
135
A
LE
-
-
675
A
OE
-
-
450
A
Tamb = 40 C to +125 C
VIH
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
VOH
HIGH-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 6.0 mA; VCC = 4.5 V
3.7
-
-
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 6.0 mA; VCC = 4.5 V
-
-
0.4
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
-
-
10
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
160
A
ICC
additional supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
-
-
147
A
LE
-
-
735
A
OE
-
-
490
A
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
9 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 8.
Dynamic characteristics 74HC373-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
41
150
ns
VCC = 4.5 V
-
15
30
ns
VCC = 5 V; CL = 15 pF
-
12
-
ns
VCC = 6.0 V
-
12
26
ns
VCC = 2.0 V
-
50
175
ns
VCC = 4.5 V
-
18
35
ns
Tamb = 25 C
tpd
propagation delay
Dn to Qn; see Figure 8
[1]
LE to Qn; see Figure 9
ten
tdis
tt
tW
tsu
th
CPD
enable time
disable time
transition time
pulse width
set-up time
hold time
power dissipation capacitance
74HC_HCT373_Q100
Product data sheet
VCC = 5 V; CL = 15 pF
-
15
-
ns
VCC = 6.0 V
-
14
30
ns
VCC = 2.0 V
-
44
150
ns
VCC = 4.5 V
-
16
30
ns
VCC = 6.0 V
-
13
26
ns
VCC = 2.0 V
-
47
150
ns
VCC = 4.5 V
-
17
30
ns
VCC = 6.0 V
-
14
26
ns
VCC = 2.0 V
-
14
60
ns
VCC = 4.5 V
-
5
12
ns
VCC = 6.0 V
-
4
10
ns
VCC = 2.0 V
80
17
-
ns
VCC = 4.5 V
16
6
-
ns
VCC = 6.0 V
14
5
-
ns
VCC = 2.0 V
50
14
-
ns
VCC = 4.5 V
10
5
-
ns
VCC = 6.0 V
9
4
-
ns
VCC = 2.0 V
+5
8
-
ns
VCC = 4.5 V
+5
3
-
ns
VCC = 6.0 V
+5
2
-
ns
-
45
-
pF
OE to Qn; see Figure 10
OE to Qn; see Figure 10
Qn; see Figure 8 and Figure 9
[2]
[3]
[4]
LE HIGH; see Figure 9
Dn to LE; see Figure 11
Dn to LE; see Figure 11
per latch; VI = GND to VCC
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Rev. 1 — 10 August 2012
[5]
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Nexperia B.V. 2017. All rights reserved
10 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
tpd
propagation delay
Dn to Qn; see Figure 8
[1]
VCC = 2.0 V
-
-
190
ns
VCC = 4.5 V
-
-
38
ns
VCC = 6.0 V
-
-
33
ns
VCC = 2.0 V
-
-
220
ns
VCC = 4.5 V
-
-
44
ns
-
-
37
ns
VCC = 2.0 V
-
-
190
ns
VCC = 4.5 V
-
-
38
ns
-
-
33
ns
VCC = 2.0 V
-
-
190
ns
VCC = 4.5 V
-
-
38
ns
-
-
33
ns
LE to Qn; see Figure 9
VCC = 6.0 V
ten
enable time
OE to Qn; see Figure 10
[2]
VCC = 6.0 V
tdis
disable time
OE to Qn; see Figure 10
[3]
VCC = 6.0 V
tt
tW
tsu
th
transition time
pulse width
set-up time
hold time
74HC_HCT373_Q100
Product data sheet
Qn; see Figure 8 and Figure 9
[4]
VCC = 2.0 V
-
-
75
ns
VCC = 4.5 V
-
-
15
ns
VCC = 6.0 V
-
-
13
ns
LE HIGH; see Figure 9
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
Dn to LE; see Figure 11
VCC = 2.0 V
65
-
-
ns
VCC = 4.5 V
13
-
-
ns
VCC = 6.0 V
11
-
-
ns
Dn to LE; see Figure 11
VCC = 2.0 V
5
-
-
ns
VCC = 4.5 V
5
-
-
ns
VCC = 6.0 V
5
-
-
ns
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
11 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
tpd
propagation delay
Dn to Qn; see Figure 8
[1]
VCC = 2.0 V
-
-
225
ns
VCC = 4.5 V
-
-
45
ns
VCC = 6.0 V
-
-
38
ns
VCC = 2.0 V
-
-
265
ns
VCC = 4.5 V
-
-
53
ns
-
-
45
ns
VCC = 2.0 V
-
-
225
ns
VCC = 4.5 V
-
-
45
ns
-
-
38
ns
VCC = 2.0 V
-
-
225
ns
VCC = 4.5 V
-
-
45
ns
-
-
38
ns
LE to Qn; see Figure 9
VCC = 6.0 V
ten
enable time
OE to Qn; see Figure 10
[2]
VCC = 6.0 V
tdis
disable time
OE to Qn; see Figure 10
[3]
VCC = 6.0 V
tt
tW
tsu
transition time
pulse width
set-up time
74HC_HCT373_Q100
Product data sheet
Qn; see Figure 8 and Figure 9
[4]
VCC = 2.0 V
-
-
90
ns
VCC = 4.5 V
-
-
18
ns
VCC = 6.0 V
-
-
15
ns
LE HIGH; see Figure 9
VCC = 2.0 V
120
-
-
ns
VCC = 4.5 V
24
-
-
ns
VCC = 6.0 V
20
-
-
ns
Dn to LE; see Figure 11
VCC = 2.0 V
75
-
-
ns
VCC = 4.5 V
15
-
-
ns
VCC = 6.0 V
13
-
-
ns
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Rev. 1 — 10 August 2012
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Nexperia B.V. 2017. All rights reserved
12 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
th
Dn to LE; see Figure 11
[1]
hold time
Min
Typ
Max
Unit
VCC = 2.0 V
5
-
-
ns
VCC = 4.5 V
5
-
-
ns
VCC = 6.0 V
5
-
-
ns
tpd is the same as tPLH and tPHL.
[2]
ten is the same as tPZH and tPZL.
[3]
tdis is the same as tPLZ and tPHZ.
[4]
tt is the same as tTHL and tTLH.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
Table 9.
Dynamic characteristics 74HCT373-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 4.5 V
-
17
30
ns
VCC = 5 V; CL = 15 pF
-
14
-
ns
Tamb = 25 C
tpd
propagation delay
Dn to Qn; see Figure 8
[1]
LE to Qn; see Figure 9
ten
enable time
VCC = 4.5 V
-
16
32
ns
VCC = 5 V; CL = 15 pF
-
13
-
ns
-
19
32
ns
-
18
30
ns
-
5
12
ns
16
4
-
ns
12
6
-
ns
4
1
-
ns
-
41
-
pF
OE to Qn; see Figure 10
[2]
VCC = 4.5 V
tdis
disable time
OE to Qn; see Figure 10
[3]
VCC = 4.5 V
tt
transition time
Qn; see Figure 8 and Figure 9
[4]
VCC = 4.5 V
tW
pulse width
LE HIGH; see Figure 9
VCC = 4.5 V
tsu
set-up time
Dn to LE; see Figure 11
VCC = 4.5 V
th
hold time
Dn to LE; see Figure 11
VCC = 4.5 V
CPD
power dissipation capacitance
74HC_HCT373_Q100
Product data sheet
per latch;
VI = GND to (VCC 1.5 V)
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Rev. 1 — 10 August 2012
[5]
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Nexperia B.V. 2017. All rights reserved
13 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Table 9.
Dynamic characteristics 74HCT373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
-
-
38
ns
-
-
40
ns
-
-
40
ns
-
-
38
ns
-
-
15
ns
20
-
-
ns
15
-
-
ns
4
-
-
ns
-
-
45
ns
-
-
48
ns
-
-
48
ns
-
-
45
ns
-
-
18
ns
24
-
-
ns
18
-
-
ns
Tamb = 40 C to +85 C
tpd
propagation delay
Dn to Qn; see Figure 8
[1]
VCC = 4.5 V
LE to Qn; see Figure 9
VCC = 4.5 V
ten
enable time
OE to Qn; see Figure 10
tdis
disable time
OE to Qn; see Figure 10
[2]
VCC = 4.5 V
[3]
VCC = 4.5 V
tt
transition time
Qn; see Figure 8 and Figure 9
tW
pulse width
LE HIGH; see Figure 9
[4]
VCC = 4.5 V
VCC = 4.5 V
tsu
set-up time
Dn to LE; see Figure 11
th
hold time
Dn to LE; see Figure 11
VCC = 4.5 V
VCC = 4.5 V
Tamb = 40 C to +125 C
tpd
propagation delay
Dn to Qn; see Figure 8
[1]
VCC = 4.5 V
LE to Qn; see Figure 9
VCC = 4.5 V
ten
enable time
OE to Qn; see Figure 10
[2]
VCC = 4.5 V
tdis
disable time
OE to Qn; see Figure 10
[3]
VCC = 4.5 V
tt
transition time
Qn; see Figure 8 and Figure 9
VCC = 4.5 V
tW
pulse width
LE HIGH; see Figure 9
VCC = 4.5 V
tsu
set-up time Dn to LE
Dn to LE; see Figure 11
VCC = 4.5 V
74HC_HCT373_Q100
Product data sheet
[4]
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Rev. 1 — 10 August 2012
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Nexperia B.V. 2017. All rights reserved
14 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
Table 9.
Dynamic characteristics 74HCT373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
th
Dn to LE; see Figure 11
hold time Dn to LE
VCC = 4.5 V
[1]
tpd is the same as tPLH and tPHL.
[2]
ten is the same as tPZH and tPZL.
[3]
tdis is the same as tPLZ and tPHZ.
[4]
tt is the same as tTHL and tTLH.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
Min
Typ
Max
Unit
4
-
-
ns
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
VM
Dn input
t PLH
t PHL
90 %
VM
Qn output
10 %
t TLH
t THL
001aae082
Measurement points are given in Table 10.
Fig 8.
Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
VM
LE input
tW
t PHL
t PLH
90 %
VM
Qn output
10 %
t THL
t TLH
001aae083
Measurement points are given in Table 10.
Fig 9.
Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn)
74HC_HCT373_Q100
Product data sheet
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Nexperia B.V. 2017. All rights reserved
15 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
VI
OE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
10%
VOL
tPHZ
tPZH
VOH
90%
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 10.
Fig 10.
3-state enable and disable time
VM
LE input
t su
t su
th
th
VM
Dn input
001aae084
Measurement points are given in Table 10.
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE)
Table 10.
Measurement points
Type
Input
Output
VM
VM
74HC373-Q100
0.5VCC
0.5VCC
74HCT373-Q100
1.3 V
1.3 V
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
16 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
CL
RT
001aad983
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
Table 11.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC373-Q100
VCC
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HCT373-Q100
3V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HC_HCT373_Q100
Product data sheet
Load
S1 position
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Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
17 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 13. Package outline SOT163-1 (SO20)
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
18 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 14. Package outline SOT360-1 (TSSOP20)
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
19 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT764-1
20 terminals; body 2.5 x 4.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
9
y
y1 C
v M C A B
w M C
b
L
1
10
Eh
e
20
11
19
12
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
mm
c
D (1)
Dh
E (1)
Eh
0.2
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT764-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 15. Package outline SOT764-1 (DHVQFN20)
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
20 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
13. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
MIL
Military
14. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT373_Q100 v.1
20120810
Product data sheet
-
-
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
21 of 24
74HC373-Q100; 74HCT373-Q100
Nexperia
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT373_Q100
Product data sheet
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
22 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74HC_HCT373_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 August 2012
©
Nexperia B.V. 2017. All rights reserved
23 of 24
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
©
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 10 August 2012
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