74HC4040D,653

74HC4040; 74HCT4040 12-stage binary ripple counter Rev. 03 — 14 September 2005 Product data sheet 1. General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. 2. Features ■ Multiple package options ■ Complies with JEDEC standard no. 7A ■ ESD protection: ◆ HBM JESD22-A114-C exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V ■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Applications ■ Frequency dividing circuits ■ Time delay circuits ■ Control counters 4. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol Parameter Conditions Min Typ Max Unit CP to Q0 CL = 15 pF; VCC = 5 V - 14 - ns Qn to Qn+1 CL = 15 pF; VCC = 5 V - 8 - ns Type 74HC4040 tPHL, tPLH propagation delay 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 1: Quick reference data …continued GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol Parameter Conditions Min Typ Max Unit fmax maximum operating frequency CL = 15 pF; VCC = 5 V - 90 - MHz Ci input capacitance - 3.5 - pF CPD power dissipation capacitance VI = GND to VCC - 20 - pF CP to Q0 CL = 15 pF; VCC = 5 V - 16 - ns Qn to Qn+1 CL = 15 pF; VCC = 5 V - 8 - ns CL = 15 pF; VCC = 5 V - 79 - MHz - 3.5 - pF - 20 - pF Type 74HCT4040 tPHL, tPLH propagation delay fmax maximum operating frequency Ci input capacitance CPD power dissipation capacitance [1] VI = GND to VCC − 1.5 V CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 5. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC4040N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC4040D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC4040DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body SOT338-1 width 5.3 mm 74HC4040PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HC4040BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74HCT4040N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HCT4040D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC_HCT4040_3 Product data sheet SOT403-1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 2 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 2: Ordering information …continued Type number Package Temperature range Name Description Version 74HCT4040DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body SOT338-1 width 5.3 mm 74HCT4040PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HCT4040BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT403-1 6. Functional diagram 10 CP 11 MR T 12-STAGE COUNTER CD 9 7 6 5 3 2 4 13 12 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad589 Fig 1. Functional diagram CTR12 10 11 CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 9 7 6 5 3 2 4 13 12 14 15 1 10 11 + CT = 0 CT 11 001aad585 Fig 2. Logic symbol 9 7 6 5 3 2 4 13 12 14 15 1 001aad586 Fig 3. IEC logic symbol 74HC_HCT4040_3 Product data sheet 0 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 3 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter FF T 1 CP Q FF T 2 Q Q FF T 3 Q RD Q FF T 4 Q RD Q FF T 5 Q RD Q FF T 6 Q Q RD Q RD RD MR Q0 FF T 7 Q Q1 FF T 8 Q Q2 Q FF T 9 Q RD FF T 10 Q RD Q6 Q Q3 Q7 Q FF T 11 Q RD Q FF T 12 Q RD Q8 Q5 Q4 Q Q RD RD Q9 Q10 Q11 001aad588 Fig 4. Logic diagram 7. Pinning information Q11 1 16 VCC Q5 2 15 Q10 1 terminal 1 index area Q5 2 15 Q10 14 Q9 Q4 3 14 Q9 13 Q7 Q6 4 12 Q8 Q3 5 5 Q2 6 11 MR Q2 6 Q1 7 10 CP Q1 7 GND 8 9 Q0 001aad583 13 Q7 4040 GND(1) 12 Q8 11 MR 10 CP 9 4 Q3 Q0 Q6 8 3 GND Q4 4040 16 VCC Q11 7.1 Pinning 001aad584 Transparent top view (1) The substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 4 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 7.2 Pin description Table 3: Pin description Symbol Pin Description Q11 1 output 11 Q5 2 output 5 Q4 3 output 4 Q6 4 output 6 Q3 5 output 3 Q2 6 output 2 Q1 7 output 1 GND 8 ground (0 V) Q0 9 output 0 CP 10 clock input (HIGH-to-LOW, edge-triggered) MR 11 master reset input (active HIGH) Q8 12 output 8 Q7 13 output 7 Q9 14 output 9 Q10 15 output 10 VCC 16 positive supply voltage 8. Functional description 8.1 Function table Table 4: Function table Input Output CP MR Q0 to Q11 ↑ L no change ↓ L count X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 5 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 8.2 Timing diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP input MR input Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad587 Fig 7. Timing diagram 9. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7 V IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output diode current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V - ±25 mA ICC quiescent supply current - ±50 mA IGND ground current - ±50 mA Tstg storage temperature −65 +150 °C DIP16 package - 750 mW SO16, SSOP16, TSSOP16 and DHVQFN16 packages - 500 mW power dissipation Ptot [1] Tamb = −40 °C to +125 °C [1] For DIP16 packages: above 70 °C, Ptot derates linearly with 12 mW/K. For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 °C, Ptot derates linearly with 8 mW/K. 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 6 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 10. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit type 74HC4040 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature see Section 11 and 12 per device −40 - +125 °C tr, tf input rise and fall times except for Schmitt-trigger inputs VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns type 74HCT4040 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature see Section 11 and 12 per device −40 - +125 °C tr, tf input rise and fall times except for Schmitt-trigger inputs VCC = 2.0 V - - - ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - - ns 11. Static characteristics Table 7: Static characteristics for 74HC4040 Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 2.0 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - V IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - V Tamb = 25 °C VIH VIL VOH LOW-level input voltage HIGH-level output voltage VI = VIH or VIL 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 7 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 7: Static characteristics for 74HC4040 …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - 0 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V ILl input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; - - 8.0 µA - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4.0 mA; VCC = 4.5 V 3.84 - - V IO = −5.2 mA; VCC = 6.0 V; 5.34 - - V IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V VCC = 6.0 V CI input capacitance Tamb = −40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILl input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; - - 80.0 µA VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 6.0 V Tamb = −40 °C to +125 °C VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 8 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 7: Static characteristics for 74HC4040 …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4.0 mA; VCC = 4.5 V 3.7 - - V IO = −5.2 mA; VCC = 6.0 V; 5.2 - - V IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V VI = VIH or VIL ILl input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160.0 µA Table 8: Static characteristics for 74HCT4040 Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 4.5 V 4.4 4.5 - V IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = 20 µA; VCC = 4.5 V - 0 0.1 V Tamb = 25 °C VOL LOW-level output voltage VI = VIH or VIL IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V ILl input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 µA ∆ICC additional quiescent supply current VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A CP - 85 306 µA MR - 110 396 µA - 3.5 - pF CI input capacitance Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 9 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 8: Static characteristics for 74HCT4040 …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −4.0 mA; VCC = 4.5 V 3.84 - - V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.33 V VI = VIH or VIL ILl input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80.0 µA ∆ICC additional quiescent supply current VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A CP - - 383 µA MR - - 495 µA Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −4.0 mA; VCC = 4.5 V 3.7 - - V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.4 V VOL LOW-level output voltage VI = VIH or VIL ILl input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160.0 µA ∆ICC additional quiescent supply current VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A CP - - 417 µA MR - - 539 µA 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 10 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 12. Dynamic characteristics Table 9: Dynamic characteristics for type 74HC4040 GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit propagation delay CP to Q0 see Figure 8 VCC = 2.0 V; CL = 50 pF - 47 150 ns VCC = 4.5 V; CL = 50 pF - 17 30 ns VCC = 5.0 V; CL = 15 pF - 14 - ns VCC = 6.0 V; CL = 50 pF - 14 26 ns VCC = 2.0 V; CL = 50 pF - 28 100 ns VCC = 4.5 V; CL = 50 pF - 10 20 ns VCC = 5.0 V; CL = 15 pF - 8 - ns VCC = 6.0 V; CL = 50 pF - 8 17 ns VCC =2.0 V; CL = 50 pF - 61 185 ns VCC = 4.5 V; CL = 50 pF - 22 37 ns VCC = 6.0 V; CL = 50 pF - 18 31 ns VCC = 2.0 V; CL = 50 pF - 19 75 ns VCC = 4.5 V; CL = 50 pF - 7 15 ns VCC = 6.0 V; CL = 50 pF - 6 13 ns VCC = 2.0 V; CL = 50 pF 80 14 - ns VCC = 4.5 V; CL = 50 pF 16 5 - ns VCC = 6.0 V; CL = 50 pF 14 4 - ns VCC = 2.0 V; CL = 50 pF 80 22 - ns VCC = 4.5 V; CL = 50 pF 16 8 - ns VCC = 6.0 V; CL = 50 pF 14 6 - ns VCC = 2.0 V; CL = 50 pF 50 8 - ns VCC = 4.5 V; CL = 50 pF 10 3 - ns VCC = 6.0 V; CL = 50 pF 9 2 - ns VCC = 2.0 V; CL = 50 pF 6.0 27 - MHz VCC = 4.5 V; CL = 50 pF 30 82 - MHz VCC = 5.0 V; CL = 15 pF - 90 - MHz VCC = 6.0 V; CL = 50 pF 35 98 - MHz - 20 - pF Tamb = 25 °C tPHL, tPLH propagation delay Qn to Qn+1 tPHL tTHL, tTLH tW propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH trec fmax CPD recovery time MR to CP maximum operating frequency see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 power dissipation capacitance 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 11 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 9: Dynamic characteristics for type 74HC4040 …continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +85 °C tPHL, tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 tPHL tTHL, tTLH tW propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH trec fmax recovery time MR to CP maximum operating frequency see Figure 8 VCC = 2.0 V; CL = 50 pF - - 190 ns VCC = 4.5 V; CL = 50 pF - - 38 ns VCC = 6.0 V; CL = 50 pF - - 33 ns see Figure 8 VCC = 2.0 V; CL = 50 pF - - 125 ns VCC = 4.5 V; CL = 50 pF - - 25 ns VCC = 6.0 V; CL = 50 pF - - 21 ns see Figure 8 VCC = 2.0 V; CL = 50 pF - - 230 ns VCC = 4.5 V; CL = 50 pF - - 46 ns VCC = 6.0 V; CL = 50 pF - - 39 ns see Figure 8 VCC = 2.0 V; CL = 50 pF - - 95 ns VCC = 4.5 V; CL = 50 pF - - 19 ns VCC = 6.0 V; CL = 50 pF - - 16 ns see Figure 8 VCC = 2.0 V; CL = 50 pF 100 - - ns VCC = 4.5 V; CL = 50 pF 20 - - ns VCC = 6.0 V; CL = 50 pF 17 - - ns see Figure 8 VCC = 2.0 V; CL = 50 pF 100 - - ns VCC = 4.5 V; CL = 50 pF 20 - - ns VCC = 6.0 V; CL = 50 pF 17 - - ns see Figure 8 VCC = 2.0 V; CL = 50 pF 65 - - ns VCC = 4.5 V; CL = 50 pF 13 - - ns VCC = 6.0 V; CL = 50 pF 11 - - ns see Figure 8 VCC = 2.0 V; CL = 50 pF 4.8 - - MHz VCC = 4.5 V; CL = 50 pF 24 - - MHz VCC = 6.0 V; CL = 50 pF 28 - - MHz 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 12 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 9: Dynamic characteristics for type 74HC4040 …continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 propagation delay MR to Qn tPHL tTHL, tTLH output transition time clock pulse width HIGH or LOW tW master reset pulse width; HIGH recovery time MR to CP trec maximum operating frequency fmax [1] see Figure 8 VCC = 2.0 V; CL = 50 pF - - 225 ns VCC = 4.5 V; CL = 50 pF - - 45 ns VCC = 6.0 V; CL = 50 pF - - 38 ns see Figure 8 VCC = 2.0 V; CL = 50 pF - - 150 ns VCC = 4.5 V; CL = 50 pF - - 30 ns VCC = 6.0 V; CL = 50 pF - - 26 ns see Figure 8 VCC = 2.0 V; CL = 50 pF - - 280 ns VCC = 4.5 V; CL = 50 pF - - 56 ns VCC = 6.0 V; CL = 50 pF - - 48 ns see Figure 8 VCC = 2.0 V; CL = 50 pF - - 110 ns VCC = 4.5 V; CL = 50 pF - - 22 ns VCC = 6.0 V; CL = 50 pF - - 19 ns see Figure 8 VCC = 2.0 V; CL = 50 pF 120 - - ns VCC = 4.5 V; CL = 50 pF 24 - - ns VCC = 6.0 V; CL = 50 pF 20 - - ns see Figure 8 VCC = 2.0 V; CL = 50 pF 120 - - ns VCC = 4.5 V; CL = 50 pF 24 - - ns VCC = 6.0 V; CL = 50 pF 20 - - ns see Figure 8 VCC = 2.0 V; CL = 50 pF 75 - - ns VCC = 4.5 V; CL = 50 pF 15 - - ns VCC = 6.0 V; CL = 50 pF 13 - - ns see Figure 8 VCC = 2.0 V; CL = 50 pF 4.0 - - MHz VCC = 4.5 V; CL = 50 pF 20 - - MHz VCC = 6.0 V; CL = 50 pF 24 - - MHz CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 13 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 10: Dynamic characteristics for type 74HCT4040 GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit propagation delay CP to Q0 see Figure 8 VCC = 4.5 V; CL = 50 pF - 19 40 ns VCC = 5.0 V; CL = 15 pF - 16 - ns VCC = 4.5 V; CL = 50 pF - 10 20 ns VCC = 5.0 V; CL = 15 pF - 8 - ns Tamb = 25 °C tPHL, tPLH propagation delay Qn to Qn+1 see Figure 8 tPHL propagation delay MR to Qn VCC = 4.5 V; CL = 50 pF; see Figure 8; - 23 45 ns tTHL, tTLH output transition time VCC = 4.5 V; CL = 50 pF; see Figure 8; - 7 15 ns tW clock pulse width HIGH or LOW VCC = 4.5 V; CL = 50 pF; see Figure 8; 16 7 - ns master reset pulse width; HIGH VCC = 4.5 V; CL = 50 pF; see Figure 8; 16 6 - ns trec recovery time MR to CP VCC = 4.5 V; CL = 50 pF; see Figure 8; 10 2 - ns fmax maximum operating frequency see Figure 8 30 72 - MHz - 79 - MHz - 20 - pF VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF CPD [1] power dissipation capacitance per package Tamb = −40 °C to +85 °C tPHL, tPLH propagation delay CP to Q0 VCC = 4.5 V; CL = 50 pF; see Figure 8; - - 50 ns propagation delay Qn to Qn+1 VCC = 4.5 V; CL = 50 pF; see Figure 8; - - 25 ns tPHL propagation delay MR to Qn VCC = 4.5 V; CL = 50 pF; see Figure 8; - - 56 ns tTHL, tTLH output transition time VCC = 4.5 V; CL = 50 pF; see Figure 8; - - 19 ns tW clock pulse width HIGH or LOW VCC = 4.5 V; CL = 50 pF; see Figure 8; 20 - - ns master reset pulse width; HIGH VCC = 4.5 V; CL = 50 pF; see Figure 8; 20 - - ns trec recovery time MR to CP VCC = 4.5 V; CL = 50 pF; see Figure 8; 13 - - ns fmax maximum operating frequency VCC = 4.5 V; CL = 50 pF; see Figure 8; 24 - - MHz propagation delay CP to Q0 VCC = 4.5 V; CL = 50 pF; see Figure 8; - - 60 ns propagation delay Qn to Qn+1 VCC = 4.5 V; CL = 50 pF; see Figure 8 - - 30 ns Tamb = −40 °C to +125 °C tPHL, tPLH 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 14 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter Table 10: Dynamic characteristics for type 74HCT4040 …continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit tPHL propagation delay MR to Qn VCC = 4.5 V; CL = 50 pF; see Figure 8 - - 68 ns tTHL, tTLH output transition time VCC = 4.5 V; CL = 50 pF; see Figure 8 - - 22 ns tW clock pulse width HIGH or LOW VCC = 4.5 V; CL = 50 pF; see Figure 8 24 - - ns master reset pulse width; HIGH VCC = 4.5 V; CL = 50 pF; see Figure 8 24 - - ns trec recovery time MR to CP VCC = 4.5 V; CL = 50 pF; see Figure 8 15 - - ns fmax maximum operating frequency VCC = 4.5 V; CL = 50 pF; see Figure 8 20 - - MHz [1] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 13. Waveforms VI VM MR input 1/fmax tW trem VI VM CP input tPHL tPLH Q0 or Qn output tW tPHL VM tTLH tTHL 001aad590 74HC4040: VM = 50 %; VI = GND to VCC. 74HCT4040: VM = 1.3 V; VI = GND to 3 V. Fig 8. Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition times, maximum clock pulse frequency, master reset (MR) pulse width, master reset to output (Qn) propagation delays and master reset to clock (CP) removal time. 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 15 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter VCC PULSE GENERATOR VI VO DUT RT CL mna101 Definitions for test circuit: CL = load capacitance including jig and probe capacitance (See Section 12 for the value). RT = termination resistance should be equal to output impedance ZO of the pulse generator. Fig 9. Test circuit 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 16 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.02 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.1 0.3 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT38-1 050G09 MO-001 SC-503-16 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 10. Package outline SOT38-1 (DIP16) 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 17 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 18 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT338-1 (SSOP16) 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 19 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 13. Package outline SOT403-1 (TSSOP16) 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 20 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 14. Package outline SOT763-1 (DHVQFN16) 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 21 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 15. Revision history Table 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74HC_HCT4040_3 20050914 Product data sheet - - 74HC_HCT4040_CNV_2 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors • Reference to family specifications is replaced by the actual information: Section 5 “Ordering information”, Section 7 “Pinning information”, Section 9 “Limiting values”, Section 10 “Recommended operating conditions”, Section 11 “Static characteristics”, Figure 9 “Test circuit” • Section 14 “Package outline” (DHVQFN16) added 74HC_HCT4040_CNV_2 19901231 Product specification - 74HC_HCT4040_3 Product data sheet - - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 22 of 24 74HC4040; 74HCT4040 Philips Semiconductors 12-stage binary ripple counter 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Trademarks 18. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 20. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74HC_HCT4040_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 14 September 2005 23 of 24 Philips Semiconductors 74HC4040; 74HCT4040 12-stage binary ripple counter 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 10 11 12 13 14 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information . . . . . . . . . . . . . . . . . . . . 23 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 September 2005 Document number: 74HC_HCT4040_3 Published in The Netherlands