74HC161D-Q100J

74HC161-Q100 Presettable synchronous 4-bit binary counter; asynchronous reset Rev. 2 — 4 October 2018 Product data sheet 1. General description The 74HC161-Q100 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Complies with JEDEC standard no. 7A CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2 000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Multiple package options 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 3. Ordering information Table 1. Ordering information Type number Package 74HC161D-Q100 Temperature range Name Description Version -40 °C to +125 °C plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SO16 74HC161PW-Q100 -40 °C to +125 °C 4. Functional diagram 1 9 15 7 10 TC 3 D0 Q0 14 4 D1 Q1 13 5 D2 Q2 12 6 D3 Q3 11 9 PE CEP CET CP 2 3 4 MR CTR4 R M1 G3 G4 C2/1,3,4+ 14 1,2D 13 5 12 6 11 15 4 CT = 15 7 Fig. 1. 10 2 1 mna905 mna906 Logic symbol Fig. 2. 3 4 D0 9 10 7 2 1 PE D1 6 D2 D3 PARALLEL LOAD CIRCUITRY CET TC CEP 15 BINARY COUNTER CP MR Q0 14 Fig. 3. 5 IEC logic symbol Q1 13 Q2 12 Q3 11 mna907 Functional diagram 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset D1 D0 D2 D3 CET CEP PE D FF0 Q D CP RD FF1 Q D CP Q RD FF2 Q D CP Q RD FF3 Q CP Q RD Q CP MR Q0 Q1 Q2 Q3 TC mna910 Fig. 4. Logic diagram 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 5. Pinning information 5.1. Pinning 74HC161 MR 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 9 74HC161 PE MR 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 Fig. 5. 9 PE aaa-024397 aaa-024396 Pin configuration SOT109-1 (SO16) Fig. 6. Pin configuration SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset (active LOW) CP 2 clock input (LOW-to-HIGH, edge-triggered) D0, D1, D2, D3 3, 4, 5, 6 data input CEP 7 count enable input GND 8 ground (0 V) PE 9 parallel enable input (active LOW) CET 10 count enable carry input Q0, Q1, Q2, Q3 14, 13, 12, 11 flip-flop output TC 15 terminal count output VCC 16 supply voltage 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 6. Functional description Table 3. Function table[1] Operating Input modes MR CP CEP CET PE Dn Qn TC Reset (clear) L X X X X X L L H ↑ X X l l L L Parallel load Output H ↑ X X l h H [2] Count H ↑ h h h X count [2] Hold (do nothing) H X l X h X qn [2] H X X l h X qn L [1] [2] H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH) 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 aaa-012187 Fig. 7. State diagram 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 5 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset MR PE D0 D1 D2 D3 CP CEP CET Q0 Q1 Q2 Q3 TC 12 reset 13 14 15 0 1 2 count preset inhibit mna909 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit. Fig. 8. Typical timing sequence 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current IO output current ICC Min Max Unit -0.5 +7.0 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA VO = -0.5 V to VCC + 0.5 V - ±25 mA supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions [1] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP16 package: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 6 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Min Typ Max Unit 2.0 5.0 6.0 V 0 - VCC V 0 - VCC V -40 +25 +125 °C VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C Min Typ VIH VIL VOH VOL -40 °C to +85 °C -40 °C to +125 °C Unit Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2; VCC = 6.0 V HIGH-level input voltage LOW-level input voltage 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 μA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 μA CI input capacitance - 3.5 - - - - - pF 74HC161_Q100 Product data sheet VI = VCC or GND; VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 14. Symbol Parameter tpd propagation delay Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 61 190 - 240 - 285 ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns VCC = 6.0 V - 18 32 - 41 - 48 ns VCC = 2.0 V - 69 215 - 270 - 325 ns VCC = 4.5 V - 25 43 - 54 - 65 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 37 - 46 - 55 ns VCC = 2.0 V - 33 150 - 190 - 225 ns VCC = 4.5 V - 12 30 - 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 10 - - - - - ns VCC = 6.0 V - 10 26 - 38 - 31 ns VCC = 2.0 V - 63 210 - 265 - 315 ns VCC = 4.5 V - 23 42 - 53 - 63 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns VCC = 6.0 V - 18 36 - 45 - 54 ns VCC = 2.0 V - 63 220 - 275 - 330 ns VCC = 4.5 V - 23 44 - 55 - 66 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns VCC = 6.0 V - 18 37 - 47 - 56 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns CP to Qn; see Fig. 9 [1] CP to TC; see Fig. 9 CET to TC; see Fig. 10 tPHL HIGH to LOW propagation delay MR to Qn; see Fig. 11 MR to TC; see Fig. 11 tt tW transition time pulse width see Fig. 9 and Fig. 10 [2] CP; HIGH or LOW; see Fig. 9 MR; LOW; see Fig. 11 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset Symbol Parameter trec recovery time tsu set-up time Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 100 19 - 125 - 150 - ns VCC = 4.5 V 20 7 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 80 25 - 100 - 120 - ns VCC = 4.5 V 16 9 - 20 - 24 - ns VCC = 6.0 V 14 7 - 17 - 20 - ns VCC = 2.0 V 100 30 - 125 - 150 - ns VCC = 4.5 V 20 11 - 25 - 30 - ns VCC = 6.0 V 17 9 - 21 - 26 - ns VCC = 2.0 V 170 47 - 215 - 255 - ns VCC = 4.5 V 34 17 - 43 - 51 - ns VCC = 6.0 V 29 14 - 37 - 43 - ns VCC = 2.0 V 0 -14 - 0 - 0 - ns VCC = 4.5 V 0 -5 - 0 - 0 - ns VCC = 6.0 V 0 -4 - 0 - 0 - ns VCC = 2.0 V 4.6 13 - 3.6 - 3.0 - MHz VCC = 4.5 V 23 40 - 18 - 15 - MHz - 44 - - - - - MHz 27 48 - 21 - 18 - MHz - 33 - - - - - pF MR to CP; see Fig. 11 Dn to CP; see Fig. 12 PE to CP; see Fig. 12 CEP, CET to CP; see Fig. 13 th hold time fmax maximum frequency Dn, PE, CEP, CET to CP; see Fig. 12 and Fig. 13 CP; see Fig. 9 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD [1] [2] [3] power dissipation capacitance VI = GND to VCC; VCC = 5 V; [3] fi = 1 MHz tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi × N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPHL VOH Qn, TC output tPLH 90 % 90 % VM 10 % VOL 10 % tTHL tTLH aaa-012353 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum frequency VI CET input VM GND tPLH tPHL VOH 90 % TC output VOL 10 % 90 % VM 10 % tTLH tTHL aaa-012354 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition times VI VM MR input GND t rec tW VI CP input VM GND t PHL VOH Qn, TC output VM VOL mna913 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 11. The master reset (MR) pulse width, master reset to output (Qn, TC) propagation delays, and the master reset to clock (CP) recovery times 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset VI VM PE input GND tsu VI tsu th th VM CP input GND tsu VI tsu th th VM Dn input GND aaa-012356 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 12. The data input (Dn) and parallel enable input (PE) set-up and hold times CEP, CET input VI VM GND tsu VI CP input th tsu th VM GND aaa-012358 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 13. The count enable input (CEP) and count enable carry input (CET) set-up and hold times Table 8. Measurement points Input Output VM VI VM 0.5 × VCC GND to VCC 0.5 × VCC 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RT RL S1 open CL 001aad983 Test data is given in Table 9. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig. 14. Test circuit for measuring switching times Table 9. Test data Input S1 position Load VI tr, tf CL RL tPHL, tPLH VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 12 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 15. Package outline SOT109-1 (SO16) 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 13 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 16. Package outline SOT403-1 (TSSOP16) 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 14 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC161_Q100 v.2 20181004 Product data sheet - 74HC161_Q100 v.1 Modifications: • • 74HC161_Q100 v.1 74HC161_Q100 Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 20170103 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 - © Nexperia B.V. 2018. All rights reserved 15 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 14. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 16 / 17 74HC161-Q100 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................7 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 13 12. Abbreviations............................................................ 15 13. Revision history........................................................15 14. Legal information......................................................16 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 4 October 2018 74HC161_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 October 2018 © Nexperia B.V. 2018. All rights reserved 17 / 17