74HC163PW-Q100J

74HC163-Q100; 74HCT163-Q100 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 2 — 12 October 2018 Product data sheet 1. General description The 74HC163-Q100; 74HCT163-Q100 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula: This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Complies with JEDEC standard no. 7A Input levels: • For 74HC163: CMOS level • For 74HCT163: TTL level Synchronous counting and loading 2 count enable inputs for n-bit cascading Synchronous reset Positive-edge triggered clock ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω) Multiple package options 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 3. Ordering information Table 1. Ordering information Type number Package 74HC163D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT163D-Q100 74HC163PW-Q100 74HCT163PW-Q100 4. Functional diagram 9 7 10 3 PE D0 CEP 4 5 6 D1 D2 D3 CET 2 CP 1 MR 3 D0 9 PE Q0 Q1 Q2 Q3 13 12 D INH 2 CP CP Logic symbol Fig. 2. 1 9 7 10 2 3 2R TC 15 BINARY COUNTER Q0 14 11 aaa-012184 Fig. 1. 6 D3 10 CET 15 7 CEP 14 5 D2 PARALLEL LOAD CIRCUITRY 1 MR TC 4 D1 Q1 13 Q2 12 Q3 11 aaa-012186 Functional diagram CTR4 M1 G3 G4 C2/1,3,4+ 14 1,2D 4 13 5 12 6 11 4CT = 15 15 aaa-012185 Fig. 3. IEC logic symbol 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset D0 D1 D2 D3 CET CEP PE MR D CP CP FF 1 Q D CP Q Q0 FF 2 Q D CP Q Q1 FF 3 Q D CP Q Q2 FF 4 Q Q Q3 TC aaa-012189 Fig. 4. Logic diagram 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 5. Pinning information 5.1. Pinning 74HC163 74HCT163 MR 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 9 74HC163 74HCT163 PE MR 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 PE aaa-012182 aaa-012181 Fig. 5. 9 Pin configuration SOT109-1 (SO16) Fig. 6. Pin configuration SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description MR 1 synchronous master reset (active LOW) CP 2 clock input (LOW-to-HIGH, edge triggered) D0, D1, D2, D3 3, 4, 5, 6 data input CEP 7 count enable input GND 8 ground (0 V) PE 9 parallel enable input (active LOW) CET 10 count enable carry input Q0, Q1, Q2, Q3 14, 13, 12, 11 flip-flop output TC 15 terminal count output VCC 16 supply voltage 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 6. Functional description Table 3. Function table[1] Operating mode Inputs Outputs MR CP CEP CET PE Dn Qn TC Reset (clear) I ↑ X X X X L L Parallel load h ↑ X X I I L L L h ↑ X X I h H Count h ↑ h h h X count Hold (do nothing) h X I X h X qn L h X X I h X qn L [1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH); H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 aaa-012187 Fig. 7. State diagram 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 5 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset MR PE D0 D1 D2 D3 CP CEP CET Q0 Q1 Q2 Q3 TC 12 13 reset preset 14 15 0 count 1 2 inhibit aaa-012188 Sequence reset outputs to zero; preset to binary 12; count to 13, 14, 15, zero, one and two; inhibit. Fig. 8. Typical timing sequence 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK Min Max Unit -0.5 +7.0 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation [1] Conditions SO16 package [1] - 500 mW TSSOP16 package [1] - 500 mW For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 6 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC163-Q100 74HCT163-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C Min Typ -40 °C to +85 °C -40 °C to +125 °C Unit Max Min Max Min Max 74HC163-Q100 VIH VIL VOH VOL VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V HIGH-level input voltage LOW-level input voltage IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 μA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 μA CI input capacitance - 3.5 - - - - - pF 74HC_HCT163_Q100 Product data sheet VI = VCC or GND; VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset Symbol Parameter Conditions 25 °C Min Typ -40 °C to +85 °C -40 °C to +125 °C Unit Max Min Max Min Max 74HCT163-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH VI = VIH or VIL; VCC = 4.5 V HIGH-level output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V - 0 0.1 - 0.1 - 0.1 V - 0.15 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 μA - - 8.0 - 80.0 - 160.0 μA IO = -4.0 mA VOL VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage IO = 20 μA IO = 4.0 mA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ΔICC per input pin; VI = VCC - 2.1 V; additional supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A CI input capacitance 74HC_HCT163_Q100 Product data sheet VI = VCC or GND; VCC = 5.5 V pin MR - 95 342 - 427.5 - 465.5 μA pin CP - 110 396 - 495 - 539 μA pin CEP and Dn - 25 90 - 112.5 - 122.5 μA pin CET - 75 270 - 337.5 - 367.5 μA pin PE - 30 108 - 135 - 147 μA - 3.5 - - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 14. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 55 185 - 230 - 280 ns VCC = 4.5 V - 20 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 31 - 39 - 48 ns VCC = 2.0 V - 69 215 - 270 - 320 ns VCC = 4.5 V - 25 43 - 54 - 65 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 37 - 46 - 55 ns VCC = 2.0 V - 36 120 - 150 - 180 ns VCC = 4.5 V - 13 24 - 30 - 36 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns VCC = 6.0 V - 10 20 - 26 - 31 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 175 58 - 220 - 265 - ns VCC = 4.5 V 35 21 - 44 - 53 - ns VCC = 6.0 V 30 17 - 37 - 45 - ns 74HC163-Q100 tpd propagation CP to Qn; see Fig. 9 delay VCC = 2.0 V [1] CP to TC; see Fig. 9 CET to TC; see Fig. 10 tt tW tsu transition time pulse width set-up time see Fig. 9 and Fig. 10 [2] CP; HIGH or LOW; see Fig. 9 MR, Dn to CP; see Fig. 11 and Fig. 12 PE to CP; see Fig. 11 CEP, CET to CP; see Fig. 13 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset Symbol Parameter th fmax hold time maximum frequency Conditions 25 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 0 -14 - 0 - 0 - ns VCC = 4.5 V 0 -5 - 0 - 0 - ns VCC = 6.0 V 0 -4 - 0 0 - ns VCC = 2.0 V 5 15 - 4 - 4 - MHz VCC = 4.5 V 27 46 - 22 - 18 - MHz - 51 - - - - - MHz 32 55 - 26 - 21 - MHz - 33 - - - - - pF - 23 39 - 49 - 59 ns - 20 - - - - - ns VCC = 4.5 V - 29 49 - 61 - 74 ns VCC = 5.0 V; CL = 15 pF - 25 - - - - - ns VCC = 4.5 V - 17 32 - 44 - 48 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns - 7 15 - 19 - 22 ns 20 6 - 25 - 30 - ns 20 9 - 25 - 30 - ns 20 11 - 25 - 30 - ns 40 24 - 50 - 60 - ns 0 -5 - 0 - 0 - ns 26 45 - 21 - 17 - MHz - 50 - - - - - MHz Dn, PE, CEP, CET, MR to CP; see Fig. 11, Fig. 12 and Fig. 13 CP; see Fig. 9 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD -40 °C to +85 °C power VI = GND to VCC; VCC = 5 V; dissipation fi = 1 MHz capacitance [3] 74HCT163-Q100 tpd propagation CP to Qn; see Fig. 9 delay VCC = 4.5 V [1] VCC = 5.0 V; CL = 15 pF CP to TC; see Fig. 9 CET to TC; see Fig. 10 tt tW transition time see Fig. 9 and Fig. 10 [2] pulse width CP; HIGH or LOW; see Fig. 9 VCC = 4.5 V VCC = 4.5 V tsu set-up time MR, Dn to CP; see Fig. 11 and Fig. 12 VCC = 4.5 V PE to CP; see Fig. 11 VCC = 4.5 V CEP, CET to CP; see Fig. 13 VCC = 4.5 V th hold time Dn, PE, CEP, CET, MR to CP; see Fig. 11, Fig. 12 and Fig. 13 VCC = 4.5 V fmax maximum frequency CP; see Fig. 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset Symbol Parameter CPD [1] [2] [3] Conditions 25 °C power VI = GND to VCC - 1.5 V; dissipation VCC = 5 V; fi = 1 MHz capacitance [3] -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 35 - - - - - pF tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPHL VOH Qn, TC output tPLH 90 % 90 % VM 10 % VOL 10 % tTHL tTLH aaa-012353 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum frequency VI CET input VM GND tPLH VOH 90 % TC output VOL tPHL 10 % 90 % VM tTLH 10 % tTHL aaa-012354 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition times 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset VI VM PE input GND tsu VI tsu th th VM CP input GND tsu VI tsu th th VM Dn input GND aaa-012356 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig. 11. The data input (Dn) and parallel enable input (PE) set-up and hold times VI VM MR input GND tsu VI CP input tsu th th VM GND aaa-012357 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig. 12. The master reset (MR) set-up and hold times CEP, CET input VI VM GND VI CP input tsu tsu th th VM GND aaa-012358 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig. 13. The count enable input (CEP) and count enable carry input (CET) set-up and hold times Table 8. Measurement points Type Input Output VM VI VM 74HC163-Q100 0.5 x VCC GND to VCC 0.5 x VCC 74HCT163-Q100 1.3 V GND to 3 V 1.3 V 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 12 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VCC VO DUT RT RL S1 open CL 001aad983 Test data is given in Table 9. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig. 14. Test circuit for measuring switching times Table 9. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH 74HC163-Q100 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT163-Q100 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 13 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 11. Application information The 74HC163-Q100; 74HCT63-Q100 facilitate designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous reset. other inputs Q0 Q1 Q2 output Q3 reset aaa-012190 Fig. 15. Modulo-5 counter other inputs Q0 Q1 Q2 output Q3 reset aaa-012191 Fig. 16. Modulo-11 counter 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 14 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 17. Package outline SOT109-1 (SO16) 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 15 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 18. Package outline SOT403-1 (TSSOP16) 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 16 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT163_Q100 v.2 20181012 Product data sheet - 74HC_HCT163_Q100 v.1 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Typo corrected for pin name Q0: Fig. 5 and Fig. 6. 74HC_HCT163_Q100 v.1 20140619 74HC_HCT163_Q100 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 - © Nexperia B.V. 2018. All rights reserved 17 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. 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The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 18 / 19 74HC163-Q100; 74HCT163-Q100 Nexperia Presettable synchronous 4-bit binary counter; synchronous reset Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................7 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 9 10.1. Waveforms and test circuit...................................... 11 11. Application information............................................14 12. Package outline........................................................ 15 13. Abbreviations............................................................ 17 14. Revision history........................................................17 15. Legal information......................................................18 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 12 October 2018 74HC_HCT163_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2018 © Nexperia B.V. 2018. All rights reserved 19 / 19