MKDV32GCL-STL

MK SD NAND Product Datasheet Commercial Grade Product List MKDV32GCL-STL / MKDV64GCL-STL http://www.mkfounder.com 1 SD NAND Revision History Version Rev 1.0 Date 2020/10/31 Description Original version Notice : The datasheet is prepared and approved by MK Founder semiconductor co., LTD. MK Founder reserves the right to change products or specifications without notice. ©2021 MK Founder semiconductor co., LTD. All rights reserved. 2 SD NAND Table Of Contents 1 Introduction ....................................................................................................................................... 4 2 Product List ....................................................................................................................................... 4 3 Features ............................................................................................................................................ 4 4 Physical Characteristics .................................................................................................................... 5 4.1 Temperature ........................................................................................................................................... 5 5 Pin Assignments(SD Mode& SPI Mode) ............................................................................................ 5 6 Usage................................................................................................................................................ 6 6.1 SD Bus Mode protocol ........................................................................................................................... 6 Command ......................................................................................................................................................... 6 Response .......................................................................................................................................................... 6 Data .................................................................................................................................................................. 6 6.2 Card Initialize.......................................................................................................................................... 8 Normal SD initial flow ................................................................................................................................... 9 SD card Initialize Procedure............................................................................................................................... 9 SD3.0 initial flow for UHS-I(IO 1.8v) switch .................................................................................................... 10 6.3 DC Characteristics ................................................................................................................................ 11 DC Characteristics......................................................................................................................................... 11 Peak Voltage and Leak Current ...................................................................................................................... 11 Signal Capacitance........................................................................................................................................ 11 7 Internal Information ......................................................................................................................... 12 7.1 Registers .............................................................................................................................................. 12 7.1.1 OCR Register ........................................................................................................................................ 13 OCR register definition ...................................................................................................................................... 13 7.1.2 CID Register .......................................................................................................................................... 14 7.1.3 CSD Register ......................................................................................................................................... 15 7.1.4 RCA Register ......................................................................................................................................... 16 7.1.5 DSR Register ......................................................................................................................................... 16 8 Power Scheme ................................................................................................................................ 16 8.1 Power Up.............................................................................................................................................. 16 8.2 Power Up Time ..................................................................................................................................... 17 8.2.1 Power On or Power Cycle ..................................................................................................................... 18 8.2.2 Power Supply Ramp Up ........................................................................................................................ 18 8.2.3 Power Supply Ramp Up ........................................................................................................................ 18 9 Package Dimensions ....................................................................................................................... 19 10 Reference Design .......................................................................................................................... 20 3 SD NAND 1 Introduction MK SD NAND is an embedded storage solution designed in a LGA package form. The operation of SD is similar to an SD card which is an commercial standard. SD NAND consists of NAND flash and a high performance controller. 3.3V supply voltage is required for the NAND area (VCC). SD NAND is fully compliant with SD2.0 interface, which allows most of general CPU to utilize. SD NAND has high performance, high quality and low power consumption. 2 Product List Part No. MKDV32GCL-STL MKDV64GCL-STL Actual Capacity Package LGA-8 LGA-8 3,810MByte 7,618MByte 3 Features ⚫ ⚫ ⚫ ⚫ ⚫ Support up to 50MHz clock frequency Supports SPI Mode Built-in HW ECC Engine and highly reliable NAND management mechanism C10, U1, V10 Smaller package LGA-8 4 Size 6x8mm 6x8mm SD NAND 4 Physical Characteristics 4.1 Temperature 1) Operation Conditions Temperature Range: Ta = -25℃ to 85 ℃ 2) Storage Conditions Temperature Range: Tstg = −55 ℃to 150℃ 5 Pin Assignments(SD Mode& SPI Mode) TOP VIEW 5 SD NAND a. Type Key: S=power supply; I= input; O=output using push-pull drivers; PP=I/O using push-pull drivers. b. The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after the SET_BUS_WIDTH Type Key: S=power supply; I=input; O=output using push-pull drivers; PP=I/O using push-pull drivers. c. At power up this line has a 50 kilohm pull-up enabled in the card. This resistor serves two functions: Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command. 6 Usage 6.1 SD Bus Mode protocol The SD bus allows the dynamic configuration of the number of data line from 1 to 4 Bi-directional data signal. After power up by default, the SD card will use only DAT0. After initialization, host can change the bus width. Multiplied SD cards connections are available to the host. Common VDD, VSS and CLK signal connections are available in the multiple connections. However, Command, Respond and Data lined (DAT0-DAT3) shall be divided for each device from host. This feature allows easy trade off between hardware cost and system performance. Communication over the SD bus is based on command and data bit stream initiated by a start bit and terminated by stop bit. Command Commands are transferred serially on the CMD line. A command is a token to starts an operation from host to the device. Commands are sent to an addressed single card (addressed Command) or to all connected cards (Broad cast command). Response Responses are transferred serially on the CMD line. A response is a token to answer to a previous received command. Responses are sent from an addressed single card or from all connected cards. Data Data can be transfer from the card to the host or vice versa. Data is transferred via the data lines. 6 SD NAND SD NAND (A) CLK CMD DAT0 - DAT3 VDD VSS Host card Clock signal Bi-directional Command/ Response Signal 4 Bi-directional data signal Power supply GND 7 SD NAND 6.2 Card Initialize To initialize the SD NAND, follow the following procedure is recommended example. 1) Supply Voltage for initialization Host System can apply the Operating Voltage from initialization to the card. Apply more than 74 cycles of Dummy-clock to the SD card. 2) Select operation mode (SD mode or SPI mode) In case of SPI mode operation, host should drive 1 pin (CD/DAT3) of SD Card I/F to “Low” level. Then, issue CMD0. In case of SD mode operation, host should drive or detect 1 pin of SD Card I/F (Pull up register of 1 pin is pull up to “High” normally). Card maintain selected operation mode except re-issue of CMD0 or power on below is SD mode initialization procedure. 3) Send the ACMD41 with Arg = 0 and identify the operating voltage range of the Card. 4) Apply the indicated operating voltage to the card. Reissue ACMD41 with apply voltage storing and repeat ACMD41 until the busy bit is cleared. (Bit 31 Busy = 1) If response time out occurred, host can recognize not SD Card. 5) Issue the CMD2 and get the Card ID (CID). 6) Issue the CMD3 and get the RCA. (RCA value is randomly changed by access, not equal zero) 7) Issue the CMD7 and move to the transfer state. If necessary, Host may issue the ACMD42 and disabled the pull up resistor for Card detect. 8) Issue the ACMD13 and poll the Card status as SD Memory Card.Check SD_CARD_TYPE value. If significant 8 bits are “all zero”, that means SD Card. If it is not, stop initialization. 9) Issue CMD7 and move to standby state. Issue CMD9 and get CSD. Issue CMD10 and get CID. 10) Back to the Transfer state with CMD7. 11) Issue ACMD6 and choose the appropriate bus-width. Then the Host can access the Data between the SD card as a storage device. 8 SD NAND Normal SD initial flow SD card Initialize Procedure 9 SD NAND SD3.0 initial flow for UHS-I(IO 1.8v) switch 10 SD NAND 6.3 DC Characteristics Item Supply Voltage High Level Input Low Level Voltage High Level Output Low Level Voltage Standby Current Operation Write Current (*) Read Input Voltage Setup Time DC Characteristics Symbol MIN. MAX. VDD 2.7 3.6 VIH VDD+0.3 VDD×0.625 VIL VSS-0.3 VDD×0.25 VOH － VDD×0.75 VOL － VDD×0.125 － 0.25 (32Gb) ICC1 － 0.05 － － － ICC2 Vrs 30 (32Gb) 28 (32Gb) 250 Unit V V V V V mA mA ms Note IOH = -2mA , VDD=VDD min IOL = 2mA , VDD=VDD min VDD = 3.6V , Clock 25MHz VDD = 3.3V, Clock STOP, Ta=25℃ 3.3V / 25MHz, 50MHz From 0V to VDD min *) Peak Current: RMS value over a 10usec period Peak Voltage and Leak Current Item Peak voltage on all lines Input Leakage Current for all pins Output Leakage Current for all outputs Item Pull up Resistance Total bus capacitance for each signal line Card capacitance for signal pin Pull up Resistance inside card ( pin1 ) Capacity Conneted to Power line Symbol Min. -0.3 Max. VDD+0.3 -10 10 -10 10 Signal Capacitance Min. Max. Unit V uA uA Symbol RCMD 10 RDAT CL ─ 100 kΩ 40 pF CCARD ─ 10 pF RDAT3 CC 10 90 ─ 5 11 Note Unit kΩ uF Note 1 card CHOST+CBUS≦30pF SD NAND 7 Internal Information 7.1 Registers The SD NAND has six registers and SD Status information: OCR, CID, CSD, RCA,DSR, SCR and SD Status. DSR IS NOT SUPPORTED in this card. There are two types of register groups. MMC compatible registers: OCR, CID, CSD, RCA, DSR, and SCR SD card Specific: SD Status SD card Registers Resister Name OCR CID CSD RCA DSR SCR SD Status Bit Width 32 128 128 16 16 64 512 Description Operation Conditions (VDU Voltage Profile and Busy Status Card Identification information Card specific information Relative Card Address Not Implemented (Programmable Card Driver): Driver Stage Register SD Memory Card‟s special features Status bits and Card features 12 SD NAND 7.1.1 OCR Register This 32-bit register describes operating voltage range and status bit in the power supply. OCR register definition OCR bit 31 Card power up status bit(busy) 30 Card Capacity Status 29-25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 reserved Switching to 1.8V Accepted(S18A) 3.6 - 3.5 3.5 - 3.4 3.4 - 3.3 3.3 - 3.2 3.2 - 3.1 3.1 - 3.0 3.0 - 2.9 2.9 - 2.8 2.8 - 2.7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved for Low Voltage Range Reserved Reserved Reserved reserved 9 8 7 6 5 4 3-0 Initial 32Gb VDD voltage window 64Gb “0” = busy “1” = “0”= SD Memory Card All „0‟ 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 All 0 bit 23-4: Describes the SD Card Voltage bit 31 indicates the card power up status. Value “1” is set after power up and initialization procedurehas been completed. 13 SD NAND 7.1.2 CID Register The CID (Card Identification) register is 128-bit width. It contains the card identification information. (Refer Appendix 3. for the detail) The Value of CID Register is vender specific. CID Register Field MID OID PNM PRV PSN - a. b. 8 16 40 8 32 4 MDT CRC - Width CID-slice 12 7 1 [127:120] [119:104] [103:64] TBD [63:56] [55:24] [23:20] [19:8] [7:1] [0:0] Initial Value 32Gb 64Gb TB TBD TBD TBD TB (a) (Product serial number) All “0b” (a) (Manufacture date) (b) (CRC) 1b Depends on the SD Card. Controlled by Production Lot. Depends on the CID Register 14 -- SD NAND 7.1.3 CSD Register CSD is Card-Specific Data register provides information on 128bit width. Some field of this register can writable by PROGRAM_CSD (CMD27). Field CSD_STRUCTURE TAAC NSAC TRAN_SPEED CCC READ_BL_LEN READ_BL_PARTIAL WRITE_BLK_MISALIG READ_BLK_MISALIGN DSR_IMP C_SIZE ERASE_BLK_EN SECTOR_SIZE WP_GRP_SIZE WP_GRP_ENABLE R2W_FACTOR WRITE_BL_LEN WRITE_BL_PARTIAL FILE_FORMAT_GRP COPY PERM_WRITE_PROTE TMP_WRITE_PROTEC FILE_FORMAT CRC - Cell Width Type 2 R 6 R 8 R 8 R 8 R 12 R 4 R 1 R 1 R 1 R 1 R 6 R 22 R 1 R 1 R 7 R 7 R 1 R 2 R 3 R 4 R 1 R 2 R 1 R (1 1 R/W (1 1 R/W 1 R/W 2 R 2 R 7 R/W 1 - CSD Register CSD Slice [127:126] [125:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79:79] [78:78] [77:77] [76:76] [75:70] [69:48] TBD [47:47] [46:46] [45:39] [38:32] [31:31] [30:29] [28:26] [25:22] [21:21] [20:16] [15:15] [14:14] [13:13] [12:12] [11:10] [9:8] [7:1] [0:0] Initial Value 32Gb 64Gb 01b All “0b” 0_0001_110b (1ms) 00000000 0_0110_010b 0101_1011_0101 1001b 0b 0b 0b 0b All “0b” TBD TBD 0b 1b 11_1111_1 000_0000 0b 00b 010b 1001b 0b All “0b” 0b 0b 0b 0b 00b All “0b” (CRC) 1b Cell Type:R: Read Only, R/W: Writable and Readable, R/W(1): One-time Writable / Readable Note: Erase of one data block is not allowed in this card. This information is indicated by “ERASE_BLK_EN”. Host System should refer this value before one data block size erase. 15 -- SD NAND 7.1.4 RCA Register The writable 16bit relative card address register carries the card address in SD Card mode. 7.1.5 DSR Register This register is not implemented on this car. 8 Power Scheme 8.1 Power Up 'Power up time' is defined as voltage rising time from 0 volt to VDD min. 'Supply ramp up time' provides the time that the power is built up to the operating level (Host Supply Voltage) and the time to wait until the SD NAND can accept the first command, The host shall supply power to the card so that the voltage is reached to Vdd_min within 250ms and start to supply at least 74 SD clocks to the SD NAND with keeping CMD line to high. 16 SD NAND 8.2 Power Up Time Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up. 17 SD NAND 8.2.1 Power On or Power Cycle Followings are requirements for Power on and Power cycle to assure a reliable Tailor™ SD hard reset. (1) Voltage level shall be below 0.5V (2) Duration shall be at least 1ms. 8.2.2 Power Supply Ramp Up The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is stable between VDD(min.) and VDD(max.) and host can supply SDCLK. Followings are recommendation of Power ramp up: (1) Voltage of power ramp up should be monotonic as much as possible. (2) The minimum ramp up time should be 0.1ms. (3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply. 8.2.3 Power Supply Ramp Up When the host shuts down the power, the VDD shall be lowered to less than 0.5Volt for a minimum period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by the host to avoid a situation that the operating current is drawn through the signal lines. If the host needs to change the operating voltage, a power cycle is required. Power cycle means the power is turned off and supplied again. Power cycle is also needed for accessing cards that are already in Inactive State. To create a power cycle the host shall follow the power down description before power up the card (i.e. the VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms). 18 SD NAND 9 Package Dimensions 19 SD NAND 10 Reference Design RDAT and RCMD (10K~100 kΩ) are pull-up resistors protecting the CMD and the DAT lines against bus floating when SD NAND is in a high-impedance mode. The host shall pull-up all DAT0-3 lines by RDAT, even if the host uses the SD NAND as 1 bit mode-only in SD mode. It is recommended to have 2.2uF capacitance on VDD. Rclk reference 0~120 Ω. 20