ESD5651N
ESD5651N
4.5V, Single Li-ion Battery Port Surge Protector
http//:www.sh-willsemi.com
Descriptions
The ESD5651N is a bi-directional TVS (Transient Voltage
Suppressor). It is specifically designed to protect sensitive
electronic components which are connected to power lines,
from over-stress caused by ESD (Electrostatic Discharge),
EFT (Electrical Fast Transients) and Lightning.
DFN1006-2L (Bottom View)
The ESD5651N may be used to provide ESD protection up to
±30kV
(contact
and
air
discharge)
according
to
IEC61000-4-2, and withstand peak pulse current up to 35A
(8/20μs) according to IEC61000-4-5.
Pin1
Pin2
The ESD5651N is available in DFN1006-2L package.
Standard products are Pb-free and Halogen-free.
Circuit diagram
Features
Reverse stand-off voltage: ±4. 5V Max.
Transient protection for each line according to
IEC61000-4-2 (ESD): ±30kV (contact and air discharge)
Pin1
IEC61000-4-4 (EFT): 40A (5/50ns)
IEC61000-4-5 (surge): 35A (8/20μs)
Capacitance: CJ = 65pF typ.
Low leakage current
Low clamping voltage: VCL = 6.5V typ. @ IPP = 16A (TLP)
Solid-state silicon technology
Power lines
Cellular handsets
Tablets
Microprocessors
Portable Electronics
Will Semiconductor Ltd.
Pin2
3 = Device code
* = Month code ( A~Z)
Marking (Top View)
Applications
*
3
Order information
Device
Package
Shipping
ESD5651N-2/TR DFN1006-2L 10000/Tape&Reel
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ESD5651N
Absolute maximum ratings
Parameter
Symbol
Rating
Unit
Peak pulse power (tp = 8/20μs)
Ppk
525
W
Peak pulse current (tp = 8/20μs)
IPP
35
A
ESD according to IEC61000-4-2 air discharge
VESD
ESD according to IEC61000-4-2 contact discharge
Junction temperature
TJ
Operating temperature
TOP
Lead temperature
TL
Storage temperature
TSTG
±30
kV
±30
125
o
-40~85
o
260
o
-55~150
o
C
C
C
C
Electrical characteristics (TA=25 oC, unless otherwise noted)
I
VRWM Reverse stand-off voltage
IR
Reverse leakage current
VCL
Clamping voltage
IPP
Peak pulse current
IPP
IHOLD
VHOLD
VCL VTRIG
VRWM
ITRIG
IR
IR
ITRIG
VRWM VTRIG
VHOLD
VCL
V
IHOLD
VTRIG Reverse trigger voltage
ITRIG
Reverse trigger current
VHOLD Reverse holding voltage
IHOLD
IPP
Reverse holding current
Definitions of electrical characteristics
Will Semiconductor Ltd.
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Revision 1.5, 2018/4/23
ESD5651N
o
Electrical characteristics (TA=25 C, unless otherwise noted)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
±4.5
V
1
μA
Reverse stand-off voltage
VRWM
Reverse leakage current
IR
Reverse trigger voltage
VTRIG
ITRIG = 2μA
4.7
V
Reverse holding voltage
VHOLD
IHOLD = 50mA
4.6
V
VRWM = 4.5V
Clamping voltage
1)
VCL
IPP = 16A, tp = 100ns
6.5
V
Clamping voltage
2)
VCL
VESD = 8kV
6.5
V
Clamping voltage
3)
Dynamic resistance
VCL
1)
Junction capacitance
IPP = 1A, tp = 8/20μs
6
V
IPP = 20A, tp = 8/20μs
11
V
IPP = 35A, tp = 8/20μs
15
V
RDYN
Ω
0.12
VR = 0V, f = 1MHz
65
80
pF
VR = 4.5V, f = 1MHz
45
60
pF
CJ
Notes:
1) TLP parameter: Z0 = 50Ω, tp = 100ns, tr = 2ns, averaging window from 60ns to 80ns. RDYN is calculated from 4A to
16A.
2)
Contact discharge mode, according to IEC61000-4-2.
3)
Non-repetitive current pulse, according to IEC61000-4-5.
Will Semiconductor Ltd.
3
Revision 1.5, 2018/4/23
ESD5651N
o
100
90
Front time: T1= 1.25 T = 8s
100
90
Time to half-value: T2= 20s
Current (%)
Peak pulse current (%)
Typical characteristics (TA=25 C, unless otherwise noted)
50
T2
10
10
0
0
20
T
T1
tr = 0.7~1ns
CJ - Junction capacitance (pF)
VC - Clamping voltage (V)
70
Pulse waveform: tp = 8/20s
Pin2 to Pin1
Pin1 to Pin2
0
5
10
15
20
25
Time (ns)
Contact discharge current waveform per IEC61000-4-2
8/20μs waveform per IEC61000-4-5
15
14
13
12
11
10
9
8
7
6
5
4
t
60ns
30ns
Time (s)
30
35
f = 1MHz
VAC = 50mV
65
60
55
50
45
40
-5
40
-4
-3
IPP - Peak pulse current (A)
-2
-1
0
1
2
3
4
5
VR - Reverse voltage (V)
Clamping voltage vs. Peak pulse current
Capacitance vs. Reverse voltage
100
% of Rated power
Peak pulse power (W)
1000
100
10
1
10
100
Pulse time (s)
60
40
20
0
1000
0
25
50
75
100
125
150
o
TA - Ambient temperature ( C)
Non-repetitive peak pulse power vs. Pulse time
Will Semiconductor Ltd.
80
Power derating vs. Ambient temperature
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Revision 1.5, 2018/4/23
ESD5651N
o
Typical characteristics (TA=25 C, unless otherwise noted)
ESD clamping
ESD clamping
(+8kV contact discharge per IEC61000-4-2)
(-8kV contact discharge per IEC61000-4-2)
20
16
TLP current (A)
12
8
4
0
-4
-8
Z0 = 50
-12
tr = 2ns
-16
tp = 100ns
-20
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
TLP voltage (V)
TLP Measurement
Will Semiconductor Ltd.
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Revision 1.5, 2018/4/23
ESD5651N
PACKAGE OUTLINE DIMENSIONS
DFN1006-2L
b
L
E
(Ⅰ)
(Ⅱ)
(Ⅲ)
D
e
Top View
Bottom View
(Ⅰ)
A3
A1
A
(Ⅱ)
Side View
Dimensions in Millimeters
Symbol
Min.
Typ.
Max.
A
0.34
0.45
0.53
A1
0.00
0.02
0.05
A3
0.12 Ref.
D
0.95
1.00
1.08
E
0.55
0.60
0.68
b
0.20
0.25
0.30
L
0.45
0.50
0.55
e
0.65 BSC
Recommended land pattern (Unit: mm)
0.55
0.60
0.30
Notes:
0.85
This recommended land pattern is for reference
purposes only. Please consult your manufacturing
1.40
Will Semiconductor Ltd.
group to ensure your PCB design guidelines are met.
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Revision 1.5, 2018/4/23
ESD5651N
TAPE AND REEL INFORMATION
RD
Reel Dimensions
Tape Dimensions
W
P1
Quadrant Assignments For PIN1 Orientation In Tape
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
RD
Reel Dimension
W
Overall width of the carrier tape
P1
Pitch between successive cavity centers
Pin1
Pin1 Quadrant
Will Semiconductor Ltd.
User Direction of Feed
7inch
13inch
1 8mm
12mm
16mm
2mm
4mm
8mm
Q1
Q2
Q3
7
Q4
Revision 1.5, 2018/4/23
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