WD3153
WD3153
3-Channel LED Driver
Http//:www.sh-willsemi.com
Descriptions
The WD3153 is a 3-channel LED driver designed to
LED0
1
10
SCL
LED1
2
9
SDA
LED2
3
8
CHRG
without processor control.
INTN
4
7
SET
Three independent LED channels have accurate
VCC
5
6
NC
produce variety of lighting effects. The device has a
program memory for creating variety of lighting
sequences. When the program memory has been
loaded, the WD3153 can operate independently
programmable current sinks, from 0mA to 25mA with 5
GND
Pin configuration (Top view)
steps and 8-bit flexible PWM control. Each channel
can be configured into each of the three program
execution engines. Program execution engines have
program
memory
for
creating
desired
lighting
sequences with PWM control.
3153
WDYW
Features
Supply voltage: 2.4V to 5.5V
Three independently programmable LED outputs
DFN2X2-10L
with 8-bit PWM control and 3-bit current setting
(from 0mA to 25mA)
Autonomous
operation
3153
with
three
program
execution engines
Y
= Year code
W
= Week code
2
Direct I C register control for lighting
I C Compatible Interface
= Device code
Marking
2
Power supply support 1.8V to 5.5V
Data transfers up to 400kbps
INTN interrupt function
Typical LED output saturation voltage 80mV
LED output current accuracy ±2% and current
Order information
Device
Package
Shipping
WD3153D-10/TR
DFN2X2-10L
3000/Reel&Tape
matching ±1%
Operating temperature: -40℃ to 85℃
Built-in oscillator with ±5% accuracy
ESD HBM 4kV
Support charging indication under low battery
DFN2X2-10L package
condition
Directly start up breathing light on LED0
Breathing period: 5s or continuous
Applications
Low power consumption
Smart Phones
Operating current: 80uA
Tablets
Less than 1uA in shut down mode
Indicator lights
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WD3153
Typical applications
VBAT
CHRG
VBUS
VBAT
VCC
30K
CHRG
VCC
1uF
10K
Charger
GND
VIO
SET
INTN
LED0
G
B
VIO
SET
4.7KΩ
*3
WD3153
VBAT
1uF
GND
R
VBAT
WD3153
CPU
R
INTN
LED1
SCL
SCL
LED2
SDA
SDA
G
VBAT
B
Fig1 Charging Indicator Application
4.7KΩ
*3
INTN
LED0
CPU
INTN
LED1
SCL
SCL
LED2
SDA
SDA
Fig2 Adapter Plug In Indicator Application
Pin descriptions
No.
Name
I/O
Description
1
LED0
Analog
LED driver current sink terminal
2
LED1
Analog
LED driver current sink terminal
3
LED2
Analog
LED driver current sink terminal
4
INTN
Open drain
5
VCC
Power
6
NC
Not internally connected
7
SET
I
Charge indicator set.
0: LED0 output 5mA/5S period
1: LED0 output 5mA continuous
8
CHRG
I
Charge indicator input. Internal pull-down resistor of 15KΩ
between CHRG and GND.
9
SDA
I/O
10
SCL
I
EP
GND
Ground
Interrupt output
2.4V~5.5V power supply
2
I C serial interface data input/output. 1.8V/5.5V compatible
2
I C serial interface clock. 1.8V/5.5V compatible
Connect to ground.
Block diagram
VBG
OSC
UVLO
OTP
VCC
SET
CHRG
LED0
Control
Logic
Constant
Current
LED
Driver
INTN
SCL
SDA
I2C
LED1
LED2
REG
GND
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WD3153
Absolute maximum ratings (1)
Parameter
MIN
MAX
Unit
Power supply VCC
-0.3
6.0
V
Analog pins (LED0, LED1, LED2)
-0.3
6.0
V
Digital pins (SDA, SCL, INTN)
-0.3
Storage temperature Tstg
-65
VCC+0.3V
with 6.0 max
V
150
℃
Junction temperature TJMAX
150
℃
Maximum lead temperature
260
℃
Junction-to-ambient thermal resistance (DFN10L)
ESD HBM
Latch-up
(1)
℃/W
45
-4
4
kV
-450
450
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
MIN
MAX
Unit
Power supply VCC
2.4
5.5
V
Digital pins
1.8
VCC
V
Junction temperature TJ
-40
125
℃
Ambient temperature TA
-40
85
℃
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WD3153
Electronics Characteristics
Unless otherwise specified, TA = 25℃ and VCC = 3.6V.
Symbol
Description
ISD
Shut down current
ISB
Standby current
Test Conditions
MIN
CHIPEN=0 (device off)
CHIPEN=1 (device on);
LE0~2=0 (all LEDs off)
TYP
MAX
Unit
0.1
1
uA
35
50
uA
80
120
uA
5
%
CHIPEN=1 (device on);
ICC
Operating current
LE0~2=1 (all LEDs on);
LCFG0~2=03h (all LEDs set
to 15mA);
FOSC
Oscillator frequency
Internal
-5
LED driver (LED0, LED1, LED2) electrical characteristics (GCR=01h, PWM0~2=FFh)
IMAX
Maximum sink current
LCFG0~2=04h
24.25
25
25.75
LCFG0~2=03h
14.55
15
15.45
LCFG0~2=02h
9.7
10
10.3
LCFG0~2=01h
4.85
5
5.15
LCFG0~2=00h
(2)
mA
0
Imatch
Matching (2)
LCFG0~2=03h, 15mA Set
VSAT
Saturation voltage (3)
LCFG0~2=03h
FLED
PWM switching frequency
-1
+1
%
80
100
mV
PWM_HF=0
237.5
250
262.5
Hz
PWM_HF=1
475
500
525
Hz
Output current accuracy is the difference between the actual value of the output current and programmed value of
this current. Matching is the maximum difference from the average. For the constant current outputs on the part, the
following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average
output current of all outputs (AVG). Two matching numbers are calculated: (MAX - AVG)/AVG and (AVG - MIN)/AVG.
The largest number of the two (worst case) is considered the matching figure. Note that some manufacturers have
different definitions in use.
(3)
Saturation voltage is defined as the voltage when the LED current has dropped 10% from the set value.
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WD3153
Logic interface characteristics
Unless otherwise specified: limits for typical values are for TA = 25℃ and minimum and maximum limits apply over the
operating ambient temperature range (-40℃ < TA < 85℃); VCC=3.6V and range (2.4V < VCC < 5.5V).
Symbol
VDD_I2C
Description
MIN
2
Power supply range for I C
TYP
1.65
MAX
Unit
5.5
V
Logic input SCL and SDA characteristics
VIH
Input high level
1.2
V
VIL
Input low level
IIH
High level input current
5
nA
IIL
Low level input current
5
nA
0.6
V
Logic output SDA characteristics
VOL
Output low level (IOUT = 3mA)
IL
0.3
Output leakage current
0.5
V
1
uA
400
kHz
2
I C timing requirements (4)
2
FSCL
I C clock frequency
tBUF
Bus-free time between a STOP and a START condition
1.3
uS
Hold time (repeated) START condition
0.6
uS
tLOW
Clock low time
1.3
uS
tHIGH
Clock high time
0.6
uS
Setup time for a repeated START condition
1.3
uS
Data hold time
0.05
uS
tSU,DAT
Data setup time
0.1
uS
tR
Rise time of SCL
0.3
uS
tF
Fall time of SCL
0.3
uS
tHD,STA
tSU,STA
tHD,DAT
tSU,STO
TSP
Cb
(4)
Set-up time for STOP condition
0.6
uS
SCL input deglitch
200
nS
SDA input deglitch
250
nS
Capacitive load for each bus line
400
pF
Specification is ensured by design and is not tested in production.
2
Fig4 is the timing parameters of I C interface (SCL, SDA).
Stop
Start
Start
Stop
VIH
VIL
SDA
tBUF
tLOW
tF
tHIGH
TDEG
VIH
VIL
SCL
tHD,STA
tR
tHD,DAT
tSU,DAT
tSU,STA
tSU,STO
2
Fig4 I C timing parameters
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WD3153
Option Mode
Power On Reset
Power On Reset (POR) will activate when VCC rises above 2V (typical), which will reset all the internal
registers to the default values, and then the chip will enter the Shut Down Mode.
The POR flag bit will be set to “1” when POR operation occurs, which will be cleared by a read of the Flags
Register. Usually the POR flag bit can be used to check whether a unexpected POR event has taken place.
Software Reset
Reset is down always if “55h” is written to Reset Register. All the internal registers are reset to the default
values and the chip will enter the Shut Down Mode.
Shut Down Mode
The WD3153 enters into Shut Down Mode when CHRG is low, and CHIPEN bit (GCR Register) is set to 0 or
SCL is pulled to low for over 130ms.
In the Shut Down Mode, the internal registers (except Flags) are reset to the default values and all blocks are
2
turned off. The current consumption is less than 1uA. The I C interface is accessible, but only Reset and GCR
Registers can be configured.
Standby Mode
When CHIPEN bit (GCR Register) is set to “1”, WD3153 enters into Standby Mode.
In the Standby Mode, the needed internal blocks (VBG, UVLO, OSC, OTP etc) are enabled. All the registers
can be configured. And the power consumption is about 33uA.
Operating Mode
If LE bit (LCTR Register) is set to “1”, the chip will enter operating mode.
In the operating mode, the power consumption is about 80uA.
Under Voltage Lock Out
The WD3153 has an internal comparator that monitors the voltage of VCC and force the WD3153 into Shut
Down Mode if VCC drops to 2.2V. If VCC rises above 2.2V, setting the CHIPEN bit to “1”, the WD3153 will
enter into Standby Mode again.
If the UVLO monitor threshold is tripped, the UVLO flag bit is set to “1” in the Flags Register. Upon a read, the
Flag register can be cleared.
Over Temperature Protect
IF the WD3153 reaches 135℃, the LED driver block will be disabled, until temperature drops below 120℃,
2
and the OTP flag bit will be set to “1” in the Flags Register, until there is an I C read of Flags Register.
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WD3153
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I C Interface
Interface Overview
2
The I C interface is built in the WD3153. It can be compatible with 1.8V to 5.5V. It provides access to the
programmable functions and registers on the device.
This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the
bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines
should be connected to a positive supply, via a pull-up resistor (4.7kΩ) and remain HIGH even when the bus
is idle.
Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction.
New data should be sent during the low SCL state. This protocol permits a single data line to transfer both
command/control information and data using the synchronous serial clock.
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and
a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following
sections provide further details of this process.
The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop
Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a
Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a
transaction. This allows another device to be accessed, or a register read cycle.
Stop
Start
SDA
MSB
SCL
1
2
3,4,5,6
7
LSB
Ack
MSB
8
9
1
2
3,4,5,6
LSB
Ack
8
9
7
Fig5 I2C data transactions
Addressing Transfer Formats
The WD3153 operates as a slave device with the 7-bit address. If 8-bit address is used for programming, the
8th bit is 1 for read and 0 for write.
Bit7
Bi6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IADR
IADR
IADR
IADR
IADR
IADR
IADR
R/W
Before any data is transmitted, the master transmits the address of the slave being addressed. The slave
device should send an acknowledge signal on the SDA line, once it recognizes its address.
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WD3153
The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W)
depends on the bit sent after the slave address - the eighth bit.
When the slave address is sent, each device in the system compares this slave address with its own. If there
is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the
state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.
The default device address is 45h. The WD3153 allows the user to modify the device address. Through
configuration the register IADR (address 77h), the address can be replaced by other values.
Bit7
Bi6
Bit5
ASEL
DA
Bit4
Bit3
Bit2
Bit1
Bit0
When ASEL = 0, device address =45h (default);
When ASEL = 1, device address = DA.
Once the device address is redefined, the master must use the new address. After power-on-reset or soft
reset, the device address will be reset to the default value (45h).
Control Register Write Cycle
①
Master device generates start condition.
②
Master device sends slave address IADR and the data direction bit (R/W=0).
③
Slave device sends acknowledge signal if the slave address is correct.
④
Master sends control register address (8bits).
⑤
Slave sends acknowledge signal.
⑥
Master sends data byte to be written to the addressed register (8bits).
⑦
Slave sends acknowledge signal.
⑧
If master will send further data bytes the control register address will be incremented by one after
acknowledge signal.
⑨
Write cycle ends when the master creates stop condition.
Start
Stop
SDA
SCL
RAD
1
2,3,4,5,6
R/W
Ack
8
9
7
Ack
ADDR1
1
2,3,4,5,6,7
8
9
Ack
DATA1
1
2,3,4,5,6,7
8
9
DATA2
1
2,3,4,5,6,7
8
Ack
……
Ack
9
……
9
2
Fig6 I C Write Cycle
Control Register Read Cycle
①
Master device generates a start condition. Master device sends slave address IADR and the data
direction bit (R/W=0).
②
Slave device sends acknowledge signal if the slave address is correct.
③
Master sends control register address (8 bits).
④
Slave sends acknowledge signal.
⑤
Master device generates repeated start condition.
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WD3153
⑥
Master sends the slave address IADR and the data direction bit (R/W=1).
⑦
Slave sends acknowledge signal if the slave address is correct.
⑧
Slave sends data byte from addressed register.
⑨
If the master device sends acknowledge signal, the control register address will be incremented by one.
Slave device sends data byte from addressed register.
⑩
Read cycle ends when the master does not generate acknowledge signal after data byte and generates
stop condition.
Start
SDA
IADR
SCL
1
R/W
Ack
8
9
7
2,3,4,5,6
Ack
ADDR1
1
8
2,3,4,5,6,7
9
Repeat Start
Stop
SDA
IADR
SCL
1
2,3,4,5,6
R/W
Ack
8
9
7
Ack
DATA1
1
2,3,4,5,6,7
8
DATA2
9
1
Ack
……
Ack
9
……
9
8
2,3,4,5,6,7
Stop Start
Stop
SDA
SCL
IADR
1
2,3,4,5,6
7
R/W
Ack
8
9
Ack
DATA1
1
2,3,4,5,6,7
8
9
2
Fig7 I C Read Cycle
Interrupt
INTN is the interrupt open-drain output pin. It will output low when the following 4 conditions occur:
a.
Power on Reset
b.
The programmable lighting sequence running time duration is complete
c.
Under Voltage Lock Out
d.
Over Temperature Protect
The interrupt function is enabled by the high 5-bits of Register GCR. When the interrupt occurs, the master
reads the ISR register to determine the interrupt source. The ISR register is read-only and can be cleared. If
no new interrupt is generated, the INTN will output high.
LED Controller
LED Controller Overview
The WD3153 has three independent programmable channels (LED0, LED1, LED2). Trigger connections
between channels are common for all channels. All channels have own program memories for storing
complex patterns. Brightness control and patterns are done with 8-bit PWM control to get accurate and
smooth color control.
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WD3153
Disabled
Each channel can be configured to disabled mode. LED output current will be 0 during this mode.
LED Output Current Setting
LED output current is defined by IMAX bit (Register LCFG0~3).
PWM Setting
Set PWM output value from 0 to 255 by Register PWM0~2.
Direct Control Mode
2
I C direct control mode is enabled by the MD bit of Register LCFGx. Changes to the PWM value registers are
reflected immediately to the LED brightness.
The WD3153 has fade-in and fade-out function.
Fade-in / out close
LCFGx-FI = 0
LCFGx-FO = 0
Fade-in / out open
Fade-in
LCFGx-FI = 1
LCFGx-FO = 1
Fade-out
time
Set PWM=FFH
Set PWM=00H
Fig8 Fade-in and Fade-out Function
Program Execution Engines
Use of program execution engines is the other LED output PWM control method available in the WD3153.
The device has 3 program execution engines. These engines can be enabled by MD bit of Register LCFGx,
and create PWM controlled lighting patterns to the mapped LED outputs according to program codes
developed by the user. Program coding is done using programming commands. Programs are loaded into
SRAM memory and engine control bits are used to run these programs autonomously. The engines have
different operation modes, program execution states, and program counters. Each engine has its own section
of the SRAM memory.
The LED pattern is illustrated in the Fig9 below. The cycle is defined with T0~T4 (Fig9). It is possible to
program very fast and also very low ramps. The repeat time is defined by REPEAT bits of LEDxT2.
T0
T1
T2
T3
T4
T1
T2
T3
T4
One Cycle
Fig9 LED Lighting Pattern for Program Execution Engines
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WD3153
Auto Charging Indication
In application of mobile phone, when battery voltage is too low and the PMU cannot work, the LED driver
2
cannot be controlled by application processor via I C interface. In this case, extra LED control circuit is
necessary to be built in for charging status indication.
WD3153 provides the auto charging indication function for low battery voltage application. When the external
USB power is inserts to phone, the pin CHRG is pulled high, WD3153 will enter active state automatically. The
predefined pattern output only on pin LED0, the LED1 and LED2 keep off status. The pattern parameter is
showed in fig10. The maximum current is 5mA, breathing period is about 5s or continuous, which is set by
SET pin (SET=L, period is 5s; SET=H, continuous). Once the CHRG pin goes low, the device comes back to
Shut Down state again and stops LED0 output.
Current
1.04S
2.08S
0.13S
2.08S
1.04S
2.08S
0.13S
2.08S
1.04S
Time
Fig10 Auto Charging Indication Pattern Parameter
The auto charging indication function should be closed by configured FCTR register CHRG_EN bit to 1 when
2
the processor is able to configure WD3153 via I C interface, then the lighting effects will have no relation with
the CHRG status.
When special charger IC is used and pin CHRG is recommend to be connected to status pin of charger IC
(Fig1), the pin LED0 of WD3153 can indicate the real battery charging status.
When no charger IC is applied, and battery charging is managed by PMU (Fig2), no real charging status
signal can be adapted, so the LED0 status can only indicate whether the USB power is plugged in or not.
When the pull-up resistance is 30KΩ, VBUS range can be 5V ~ 15V.
Synchronously Lighting
In Real Color Breathing Lighting application, the SYN_EN (Register LEDSYN) should be set to 1. The three
LED channels will lighting synchronously. The color can be set by IMAX (Register LCFG0~3) and PWM duty
(Register PWM0~2).
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Register Definition
Register List
Addr (HEX)
Register
Function
00
Chip ID and Software Reset Register
Chip ID and Reset all registers
01
Operation Enable Register
Chip enable and interrupt enable
02
Interrupt Register
Interrupt status
03
Function Control Register
Function enable
30
Channel Enable Register
Channel enable
31~33
Lighting Mode Register
LED0~LED2 lighting mode
34~36
PWM Control Register
PWM value of LED0~2
37/3A/3D
T1 & T2 Setting Register
T1 & T2 setting
38/3B/3E
T3 & T4 Setting Register
T3 & T4 setting
39/3C/3F
T0 & Repeat time Setting Register
T0 & repeat time setting
Redefined ID Register
Redefined ID
77
Register Maps
Addr
Register
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00h
RSTR
WR
0
0
1
1
0
0
1
1
01h
GCR
WR
LIE2
LIE1
LIE0
UVLO_IE
OTP_IE
02h
ISR
R
LIS2
LIS1
LIS0
PUIS
UVLO_IS
03h
FCTR
WR
30h
LCTR
WR
31h
LCFG0
WR
0
FO
FI
MD
0
IMAX
32h
LCFG1
WR
0
FO
FI
MD
0
IMAX
33h
LCFG2
WR
0
FO
FI
MD
0
IMAX
34h
PWM0
WR
PWM
35h
PWM1
WR
PWM
36h
PWM2
WR
PWM
37h
LED0T0
WR
0
T1
0
T2
38h
LED0T1
WR
0
T3
0
T4
39h
LED0T2
WR
3Ah
LED1T0
WR
0
T1
0
T2
3Bh
LED1T1
WR
0
T3
0
T4
3Ch
LED1T2
WR
3Dh
LED2T0
WR
0
T1
0
T2
3Eh
LED2T1
WR
0
T3
0
T4
3Fh
LED2T2
WR
4Ah
LEDSYN
WR
77h
IADR
WR
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Reserved
Reserved
OTP_IS
CHIPEN
Reserved
OTP_EN UVLO_EN CHRG_EN PWM_HF
Reserved
LE2
T0
LE1
LOG_EN
LE0
REPEAT
T0
REPEAT
T0
REPEAT
Reserved
ASEL
SYN_EN
Reserved
DA[6:0]
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WD3153
Register Description
Chip ID and Software Reset Register RSTR
Address: 00h
Default value: 33h
Bit7
Bi6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RST
RST
RST
RST
RST
RST
RST
RST
Description:
Symbol
Bit
Type
RST
7:0
WR
Active
Description
Chip ID: 33h
Reset: write 55h to RSTR, reset logic and all registers.
Global Control Register GCR
Address: 01h
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
LIE2
LIE1
LIE0
UVLO_IE
OTP_IE
Bit2
Bit1
Reserved
Bit0
CHIPEN
Description:
Symbol
Bit
Type
Active
Description
LIE2
7
WR
High
LED2 interrupt enable
LIE1
6
WR
High
LED1 interrupt enable
LIE0
5
WR
High
LED0 interrupt enable
UVLO_IE
4
WR
High
UVLO interrupt enable
OTP_IE
3
WR
High
OTP interrupt enable
Reserved
2:1
WR
ENABLE
0
WR
High
Chip enable.
Interrupt Register ISR
Address: 02h
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
Bit2
LIS2
LIS1
LIS0
PUIS
UVLO_IS
OTP_IS
Bit1
Bit0
Reserved
Description:
Symbol
Bit
Type
Active
LIS2
7
WR
High
LED2 interrupt status (0: no interrupt; 1: interrupt)
LIS1
6
WR
High
LED1 interrupt status (0: no interrupt; 1: interrupt)
LIS0
5
WR
High
LED0 interrupt status (0: no interrupt; 1: interrupt)
PUIS
4
WR
High
Power on reset interrupt.
UVLO_IS
3
R
High
UVLO interrupt status (1: under voltage)
OTP_IS
2
R
High
OTP interrupt status (1: over temperature)
Reserved
1:0
WR
Will Semiconductor Ltd.
Description
13
Nov. 2017 - Rev. 1.2
WD3153
Function Control Register FCTR
Address: 03h
Default value: 11h
Bit7
Bi6
Bit5
Reserved
Bit4
Bit3
Bit2
Bit1
Bit0
OTP_EN
UVLO_EN
CHRG_EN
PWM_HF
LOG_EN
Description:
Symbol
Bit
Type
Active
Description
Reserved
7:5
WR
OTP_EN
4
WR
High
Over Temperature Protection enable
UVLO_EN
3
WR
High
Under Voltage Lock Out enable
CHRG_EN
2
WR
Low
Charge function enable
PWM_HF
1
WR
LOG_EN
0
WR
PWM Frequency Shift (0: 250Hz; 1: 500Hz)
High
Log and Linear Shift (0: linear; 1: Log)
LED Control Register LCTR
Address: 30h
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
Reserved
Bit2
Bit1
Bit0
LE2
LE1
LE0
Bit1
Bit0
Description:
Symbol
Bit
Type
Active
Description
Reserved
7:3
WR
LE2
2
WR
High
LED2 enable.
LE1
1
WR
High
LED1 enable.
LE0
0
WR
High
LED0 enable.
Lighting Mode Register LCFG0~2
Address: 31~33h
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
0
FO
FI
MD
0
Bit2
IMAX
Description:
Symbol
Bit
Type
Active
Description
Fade-out enable
FO
6
WR
High
1: Fade-out time = T3
0: Disable.
This function is enabled during Direct Control Mode
Fade-in enable
FI
5
WR
High
1: Fade-in time = T1
0: Disable
This function is enabled during Direct Control Mode
Will Semiconductor Ltd.
14
Nov. 2017 - Rev. 1.2
WD3153
Lighting mode control
MD
4
WR
High
0: Direct Control Mode
1: Programmable Lighting Mode
Output current setting
000: 0mA (default)
IMAX
2:0
001: 5mA
WR
010: 10mA
011: 15mA
1xx: 25mA
PWM Control Register PWM0~2
Address: 34~36h
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit1
Bit0
PWM
Description:
Symbol
Bit
Type
Active
Description
Output PWM value setting
PWM
7:0
WR
0: no PWM
255: 100% duty
T1 & T2 Setting Register LEDiT0
Address: 37h, 3Ah, 3Dh
Default value: 00h
Bit7
Bi6
0
Bit5
Bit4
Bit3
T1
Bit2
0
T2
Description:
Symbol
Bit
Type
Active
Description
Fade-in time setting
T1
6:4
WR
000: 0.13s
001: 0.26s
010: 0.52s
011: 1.04s
100: 2.08s
101: 4.16s
110: 8.32s
111: 16.64s
Hold time setting after fade-in
T2
2:0
WR
000: 0.13s
001: 0.26s
010: 0.52s
011: 1.04s
100: 2.08s
101: 4.16s
Others: 4.16s
Will Semiconductor Ltd.
15
Nov. 2017 - Rev. 1.2
WD3153
T3 & T4 Setting Register LEDiT1
Address: 38h, 3Bh, 3Eh
Default value: 00h
Bit7
Bi6
Bit5
0
Bit4
Bit3
T3
Bit2
Bit1
0
Bit0
T4
Description:
Symbol
Bit
Type
Active
Description
Fade-out time setting
T3
6:4
WR
000: 0.13s
001: 0.26s
010: 0.52s
011: 1.04s
100: 2.08s
101: 4.16s
110: 8.32s
111: 16.64s
Hold time setting after fade-out
T4
2:0
WR
000: 0.13s
001: 0.26s
010: 0.52s
011: 1.04s
100: 2.08s
101: 4.16s
110: 8.32s
111: 16.64s
T0 & Repeat time Setting Register LEDiT2
Address: 39h, 3Ch, 3Fh
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
Bit2
T0
Bit1
Bit0
REPEAT
Description:
Symbol
Bit
Type
Active
Description
Delay time setting before auto blinking
T0
7:4
WR
000: 0s
001: 0.13s
010: 0.26s
011: 0.52s
100: 1.04s
101: 2.08s
110: 4.16s
111: 8.32s
1000: 16.64s
Others: 16.64s
Blinking times setting
0000: Continuous blinking
REPEAT
3:0
WR
0001: 1 time
0010: 2 times
……
1111: 15 times
Will Semiconductor Ltd.
16
Nov. 2017 - Rev. 1.2
WD3153
Synchronously Lighting Register LEDSYN
Address: 4Ah
Default value: 00h
Bit7
Bi6
Bit5
Bit4
Bit3
Reserved
Bit2
SYN_EN
Bit1
Bit0
Reserved
Description:
Symbol
Bit
Type
Reserved
7:3
WR
SYN_EN
2
WR
Reserved
1:0
WR
Active
High
Description
Synchronously Lighting enable
Redefined ID Register IADR
Address: 77h
Default value: 45h
Bit7
Bi6
Bit5
Bit4
ASEL
Bit3
Bit2
Bit1
Bit0
DA
Description:
Symbol
Bit
Type
Active
Description
ID select:
ASEL
7
WR
High
0: ID 45h (default)
1: ID DA[6:0]
DA
6:0
Will Semiconductor Ltd.
WR
Redefined ID only if ASEL=1
17
Nov. 2017 - Rev. 1.2
PACKAGE OUTLINE DIMENSIONS
DFN2x2-10L
D
K
1
D2
b
e
E
E2
R
L
TOP VIEW
BOTTOM VIEW
A1
A
A3
SIDE VIEW
Symbol
Dimensions in Millimeters
Min.
Typ.
Max.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
0.20 Ref.
b
0.15
0.20
0.25
D
1.90
2.00
2.10
E
1.90
2.00
2.10
D2
0.80
0.90
1.00
E2
1.30
1.40
1.50
e
0.30
0.40
0.50
K
0.15
0.25
0.35
L
0.25
0.30
0.35
R
Will Semiconductor Ltd.
0.10 Ref.
TAPE AND REEL INFORMATION
Reel Dimensions
RD
Reel Dimensions
Tape Dimensions
W
P1
Quadrant Assignments For PIN1 Orientation In Tape
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
RD
Reel Dimension
W
Overall width of the carrier tape
P1
Pitch between successive cavity centers
Pin1
Pin1 Quadrant
Will Semiconductor Ltd.
User Direction of Feed
7inch
13inch
1 8mm
12mm
16mm
2mm
4mm
8mm
Q1
Q2
Q3
Q4
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