ESP8685H2

ESP8685 Series Datasheet Ultra­Low­Power SoC with RISC­V Single­Core CPU Supporting IEEE 802.11b/g/n (2.4 GHz Wi­Fi) and Bluetooth® 5 (LE) 2 MB or 4 MB flash in the 4×4 mm QFN package Including: ESP8685H2 ESP8685H4 Version 1.0 Espressif Systems Copyright © 2022 www.espressif.com Product Overview ESP8685 is an ultra-low-power and highly-integrated MCU-based SoC solution that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The block diagram of ESP8685 is shown below. Espressif’s ESP8685 Wi-Fi + Bluetooth® Low Energy SoC Wireless MAC and Baseband Core System RISC-V 32-bit Microprocessor RF 2.4 GHz Balun + Switch Wi-Fi Baseband Wi-Fi MAC 2.4 GHz Transmitter Cache SRAM Bluetooth LE Link Controller 2.4 GHz Receiver JTAG ROM Bluetooth LE Baseband RF Synthesizer RTC Peripherals SPI0/1 SPI2 Flash GPIO RTC GPIO I2C UART eFuse Controller I2S RMT RWDT ⚙ TWAI® ⚙ GDMA LED PWM RTC Memory Temperature Sensor RTC Super WDT DIG ADC Controller MWDT General-purpose Timers USB Serial/ JTAG PMU Brownout Detector Security SHA ⚙ RSA AES ⚙ RNG HMAC ⚙ Secure ⚙ Boot System Timer ⚙ Digital ⚙ Signature Flash Encryption Modules having power in specific power modes: Active Active and Modem-sleep Active, Modem-sleep, and Light-sleep; All modes ⚙ optional in Light-sleep Figure 1: Block Diagram Solution Highlights • A complete Wi­Fi subsystem that complies • Storage capacities ensured by 400 KB of with IEEE 802.11b/g/n protocol and supports SRAM (16 KB for cache) and 384 KB of ROM on Station mode, SoftAP mode, SoftAP + Station the chip mode, and promiscuous mode • Reliable security features ensured by • A Bluetooth LE subsystem that supports – Cryptographic hardware accelerators that features of Bluetooth 5 and Bluetooth mesh support AES-128/256, Hash, RSA, HMAC, • State­of­the­art power and RF performance digital signature and secure boot • 32­bit RISC­V single­core processor with a – Random number generator four-stage pipeline that operates at up to 160 – Permission control on accessing internal MHz Espressif Systems memory, external memory, and peripherals 2 Submit Documentation Feedback ESP8685 Datasheet v1.0 – External memory encryption and decryption ideal for various scenarios and complex applications • Rich set of peripheral interfaces and GPIOs, Features Wi­Fi CPU and Memory • 32-bit RISC-V single-core processor, up to 160 • IEEE 802.11 b/g/n-compliant MHz • Supports 20 MHz, 40 MHz bandwidth in 2.4 • CoreMark® score: GHz band – 1 core at 160 MHz: 407.22 CoreMark; 2.55 • 1T1R mode with data rate up to 150 Mbps CoreMark/MHz • Wi-Fi Multimedia (WMM) • 384 KB ROM • TX/RX A-MPDU, TX/RX A-MSDU • 400 KB SRAM (16 KB for cache) • Immediate Block ACK • 8 KB SRAM in RTC • Fragmentation and defragmentation • SiP flash (see details in Chapter 1 ESP8685 • Transmit opportunity (TXOP) Series Comparison) • Automatic Beacon monitoring (hardware TSF) • Access to flash accelerated by cache • 4 × virtual Wi-Fi interfaces • Supports flash in-Circuit Programming (ICP) • Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP Advanced Peripheral Interfaces mode, and promiscuous mode • 15 × programmable GPIOs Note that when ESP8685 scans in Station mode, • Digital interfaces: the SoftAP channel will change along with the Station channel – 3 × SPI (SPI0 and SPI1 are used to connect the SiP flash. Only SPI2 is available) • Antenna diversity • 802.11mc FTM – 2 × UART • Supports external power amplifier – 1 × I2C – 1 × I2S – Remote control peripheral, with 2 transmit channels and 2 receive channels Bluetooth – LED PWM controller, with up to 6 channels • Bluetooth LE: Bluetooth 5, Bluetooth mesh – Full-speed USB Serial/JTAG controller • High power mode (18 dBm) – General DMA controller (GDMA), with 3 • Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps transmit channels and 3 receive channels – 1 × TWAI® controller compatible with ISO • Advertising extensions 11898-1 (CAN Specification 2.0) • Multiple advertisement sets • Analog interfaces: • Channel selection algorithm #2 – 2 × 12-bit SAR ADCs, up to 6 channels • Internal co-existence mechanism between Wi-Fi – 1 × temperature sensor and Bluetooth to share the same antenna Espressif Systems 3 Submit Documentation Feedback ESP8685 Datasheet v1.0 • Timers: • Flash encryption – 2 × 54-bit general-purpose timers • 4096-bit OTP, up to 1792 bits for use – 3 × watchdog timers • Cryptographic hardware acceleration: – 1 × 52-bit system timer – AES-128/256 (FIPS PUB 197) • Permission Control Low Power Management • SHA Accelerator (FIPS PUB 180-4) • RSA Accelerator • Power Management Unit with four power modes • Random Number Generator (RNG) Security • HMAC • Digital signature • Secure boot Applications (A Non­exhaustive List) With ultra-low power consumption, ESP8685 is an ideal choice for IoT devices in the following areas: – Wi-Fi speaker • Smart Home – Light control – Logger toys and proximity sensing toys – Smart button • Smart Agriculture – Smart plug – Smart greenhouse – Indoor positioning – Smart irrigation – Agriculture robot • Industrial Automation – Industrial robot • Retail and Catering – Mesh network – POS machines – Human machine interface (HMI) – Service robot – Industrial field bus • Audio Device – Internet music players • Health Care – Health monitor – Live streaming devices – Baby monitor – Internet radio players • Consumer Electronics • Generic Low-power IoT Sensor Hubs – Smart watch and bracelet • Generic Low-power IoT Data Loggers – Over-the-top (OTT) devices Espressif Systems 4 Submit Documentation Feedback ESP8685 Datasheet v1.0 Contents Contents Product Overview 2 Solution Highlights 2 Features 3 Applications 4 1 ESP8685 Series Comparison 9 1.1 ESP8685 Series Nomenclature 9 1.2 Comparison 9 2 Pin Definition 10 2.1 Pin Layout 10 2.2 Pin Description 11 2.3 Power Scheme 14 2.4 Strapping Pins 15 3 Functional Description 17 3.1 17 3.2 3.3 3.4 CPU and Memory 3.1.1 CPU 17 3.1.2 Internal Memory 17 3.1.3 Address Mapping Structure 18 3.1.4 Cache 18 System Clocks 19 3.2.1 CPU Clock 19 3.2.2 RTC Clock 19 Analog Peripherals 19 3.3.1 Analog-to-Digital Converter (ADC) 19 3.3.2 Temperature Sensor 19 Digital Peripherals 20 3.4.1 General Purpose Input / Output Interface (GPIO) 20 3.4.2 Serial Peripheral Interface (SPI) 27 3.4.3 Universal Asynchronous Receiver Transmitter (UART) 27 3.4.4 I2C Interface 27 3.4.5 I2S Interface 27 3.4.6 Remote Control Peripheral 28 3.4.7 LED PWM Controller 28 3.4.8 General DMA Controller 28 3.4.9 USB Serial/JTAG Controller 28 ® 3.4.10 TWAI Controller 3.5 28 Radio and Wi-Fi 29 3.5.1 2.4 GHz Receiver 29 3.5.2 2.4 GHz Transmitter 29 3.5.3 Clock Generator 29 3.5.4 Wi-Fi Radio and Baseband 30 Espressif Systems 5 Submit Documentation Feedback ESP8685 Datasheet v1.0 Contents 3.6 3.5.5 Wi-Fi MAC 30 3.5.6 Networking Features 30 Bluetooth LE 30 3.6.1 Bluetooth LE Radio and PHY 31 3.6.2 Bluetooth LE Link Layer Controller 31 3.7 Low Power Management 31 3.8 Timers 32 3.9 3.8.1 General Purpose Timers 32 3.8.2 System Timer 32 3.8.3 Watchdog Timers 32 Cryptographic Hardware Accelerators 33 3.10 Physical Security Features 33 3.11 Peripheral Pin Configurations 33 4 Electrical Characteristics 35 4.1 Absolute Maximum Ratings 35 4.2 Recommended Operating Conditions 35 4.3 DC Characteristics (3.3 V, 25 °C) 35 4.4 ADC Characteristics 36 4.5 Current Consumption 36 4.6 Reliability 37 4.7 Wi-Fi Radio 37 4.8 4.7.1 Wi-Fi RF Transmitter (TX) Specifications 38 4.7.2 Wi-Fi RF Receiver (RX) Specifications 38 Bluetooth LE Radio 40 4.8.1 Bluetooth LE RF Transmitter (TX) Specifications 40 4.8.2 Bluetooth LE RF Receiver (RX) Specifications 41 5 Package Information 44 6 Related Documentation and Resources 45 Revision History 46 Espressif Systems 6 Submit Documentation Feedback ESP8685 Datasheet v1.0 List of Tables List of Tables 1 ESP8685 Series Member Comparison 2 ESP8685H2 Pin Description 11 3 ESP8685H4 Pin Description 12 4 Description of ESP8685 Power-up and Reset Timing Parameters 15 5 Strapping Pins 16 6 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 16 7 IO MUX Pin Functions 20 8 Power-Up Glitches on Pins 21 9 Peripheral Signals via GPIO Matrix 22 10 Peripheral Pin Configurations 33 11 Absolute Maximum Ratings 35 12 Recommended Operating Conditions 35 13 DC Characteristics (3.3 V, 25 °C) 35 14 ADC Characteristics 36 15 Current Consumption Depending on RF Modes 36 16 Current Consumption Depending on Work Modes 36 17 Reliability Qualifications 37 18 Wi-Fi Frequency 37 19 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 38 20 TX EVM Test 38 21 RX Sensitivity 38 22 Maximum RX Level 39 23 RX Adjacent Channel Rejection 39 24 Bluetooth LE Frequency 40 25 Transmitter Characteristics - Bluetooth LE 1 Mbps 40 26 Transmitter Characteristics - Bluetooth LE 2 Mbps 40 27 Transmitter Characteristics - Bluetooth LE 125 Kbps 41 28 Transmitter Characteristics - Bluetooth LE 500 Kbps 41 29 Receiver Characteristics - Bluetooth LE 1 Mbps 42 30 Receiver Characteristics - Bluetooth LE 2 Mbps 42 31 Receiver Characteristics - Bluetooth LE 125 Kbps 43 32 Receiver Characteristics - Bluetooth LE 500 Kbps 43 Espressif Systems 9 7 Submit Documentation Feedback ESP8685 Datasheet v1.0 List of Figures List of Figures 1 Block Diagram 2 2 ESP8685 Series Nomenclature 9 3 ESP8685H2 Pin Layout (Top View) 10 4 ESP8685H4 Pin Layout (Top View) 11 5 ESP8685 Power Scheme 14 6 ESP8685 Power-up and Reset Timing 15 7 Setup and Hold Times for the Strapping Pins 16 8 Address Mapping Structure 18 9 QFN28 (4×4 mm) Package 44 Espressif Systems 8 Submit Documentation Feedback ESP8685 Datasheet v1.0 1 ESP8685 Series Comparison 1. ESP8685 Series Comparison 1.1 ESP8685 Series Nomenclature ESP8685 H x Flash Flash temperature H: High temperature Chip series Figure 2: ESP8685 Series Nomenclature 1.2 Comparison Table 1: ESP8685 Series Member Comparison Ordering Code SiP Flash Ambient Temperature (°C) Package (mm) ESP8685H2 2 MB –40 ∼ 105 QFN28 (4*4) ESP8685H4 4 MB –40 ∼ 105 QFN28 (4*4) 1 SiP refers to flash integrated into the package. Espressif Systems 9 Submit Documentation Feedback ESP8685 Datasheet v1.0 2 Pin Definition 2. Pin Definition 22 GPIO19 23 U0RXD 24 U0TXD 25 XTAL_N 26 XTAL_P 27 VDDA 28 VDDA 2.1 Pin Layout LNA_IN 1 21 GPIO18 VDD3P3 2 20 NC VDD3P3 3 19 NC XTAL_32K_P 4 18 NC XTAL_32K_N 5 GPIO2 6 CHIP_EN 7 ESP8685 17 VDD3P3_CPU 16 GPIO10 15 GPIO9 GPIO8 14 MTDO 13 MTCK 12 VDD3P3_RTC 11 MTDI 10 9 MTMS GPIO3 8 29 GND Figure 3: ESP8685H2 Pin Layout (Top View) Espressif Systems 10 Submit Documentation Feedback ESP8685 Datasheet v1.0 22 GPIO19 23 U0RXD 24 U0TXD 25 XTAL_N 26 XTAL_P 28 VDDA 27 VDDA 2 Pin Definition LNA_IN 1 21 GPIO18 VDD3P3 2 20 NC VDD3P3 3 19 NC XTAL_32K_P 4 18 VDD_SPI XTAL_32K_N 5 GPIO2 6 CHIP_EN 7 ESP8685H4 17 VDD3P3_CPU 16 GPIO10 15 GPIO9 GPIO8 14 MTDO 13 MTCK 12 VDD3P3_RTC 11 MTDI 10 9 GPIO3 MTMS 8 29 GND Figure 4: ESP8685H4 Pin Layout (Top View) 2.2 Pin Description Table 2: ESP8685H2 Pin Description Name No. Type Power Domain Function LNA_IN 1 I/O — RF input and output VDD3P3 2 PA — Analog power supply VDD3P3 3 PA — Analog power supply XTAL_32K_P 4 I/O/T VDD3P3_RTC GPIO0, ADC1_CH0, XTAL_32K_P XTAL_32K_N 5 I/O/T VDD3P3_RTC GPIO1, ADC1_CH1, XTAL_32K_N GPIO2 6 I/O/T VDD3P3_RTC GPIO2, ADC1_CH2, FSPIQ High: on, enables the chip. CHIP_EN 7 I VDD3P3_RTC Low: off, the chip powers off. Note: Do not leave the CHIP_EN pin floating. Espressif Systems 11 Submit Documentation Feedback ESP8685 Datasheet v1.0 2 Pin Definition Name No. Type Power Domain Function GPIO3 8 I/O/T VDD3P3_RTC GPIO3, ADC1_CH3 MTMS 9 I/O/T VDD3P3_RTC GPIO4, ADC1_CH4, FSPIHD, MTMS MTDI 10 I/O/T VDD3P3_RTC GPIO5, ADC2_CH0, FSPIWP MTDI VDD3P3_RTC 11 PD — MTCK 12 I/O/T VDD3P3_CPU GPIO6, FSPICLK, MTCK MTDO 13 I/O/T VDD3P3_CPU GPIO7, FSPID, MTDO GPIO8 14 I/O/T VDD3P3_CPU GPIO8 GPIO9 15 I/O/T VDD3P3_CPU GPIO9 GPIO10 16 I/O/T VDD3P3_CPU GPIO10, VDD3P3_CPU 17 PD — Input power supply for CPU IO NC 18 — — NC NC 19 — — NC NC 20 — — NC GPIO18 21 I/O/T VDD3P3_CPU GPIO18, USB_D- GPIO19 22 I/O/T VDD3P3_CPU GPIO19, USB_D+ U0RXD 23 I/O/T VDD3P3_CPU GPIO20, U0RXD U0TXD 24 I/O/T VDD3P3_CPU GPIO21, U0TXD XTAL_N 25 — — External crystal output XTAL_P 26 — — External crystal input VDDA 27 PA — Analog power supply VDDA 28 PA — Analog power supply GND 29 G — Ground Input power supply for RTC FSPICS0 1 PA : analog power supply; PD : power supply for RTC IO; I: input; O: output; T: high impedance. 2 The pin function in this table refers only to some fixed settings and do not cover all cases for signals that can be input and output through the GPIO matrix. For more information on the GPIO matrix, please refer to Table 9. Table 3: ESP8685H4 Pin Description Name No. Type Power Domain Function LNA_IN 1 I/O — RF input and output VDD3P3 2 PA — Analog power supply VDD3P3 3 PA — Analog power supply XTAL_32K_P 4 I/O/T VDD3P3_RTC GPIO0, ADC1_CH0, XTAL_32K_P XTAL_32K_N 5 I/O/T VDD3P3_RTC GPIO1, ADC1_CH1, XTAL_32K_N GPIO2 6 I/O/T VDD3P3_RTC GPIO2, ADC1_CH2, FSPIQ High: on, enables the chip. CHIP_EN 7 I VDD3P3_RTC Low: off, the chip powers off. Note: Do not leave the CHIP_EN pin floating. GPIO3 8 I/O/T VDD3P3_RTC GPIO3, ADC1_CH3 MTMS 9 I/O/T VDD3P3_RTC GPIO4, ADC1_CH4, FSPIHD, MTMS MTDI 10 I/O/T VDD3P3_RTC GPIO5, ADC2_CH0, FSPIWP MTDI VDD3P3_RTC 11 PD — MTCK 12 I/O/T VDD3P3_CPU Espressif Systems Input power supply for RTC GPIO6, 12 Submit Documentation Feedback FSPICLK, MTCK ESP8685 Datasheet v1.0 2 Pin Definition Name No. Type Power Domain Function MTDO 13 I/O/T VDD3P3_CPU GPIO7, GPIO8 14 I/O/T VDD3P3_CPU GPIO8 GPIO9 15 I/O/T VDD3P3_CPU GPIO9 GPIO10 16 I/O/T VDD3P3_CPU GPIO10, VDD3P3_CPU 17 PD — Input power supply for CPU IO VDD_SPI 18 PD — For internal use only NC 19 — — NC NC 20 — — NC GPIO18 21 I/O/T VDD3P3_CPU GPIO18, USB_D- GPIO19 22 I/O/T VDD3P3_CPU GPIO19, USB_D+ U0RXD 23 I/O/T VDD3P3_CPU GPIO20, U0RXD U0TXD 24 I/O/T VDD3P3_CPU GPIO21, U0TXD XTAL_N 25 — — External crystal output XTAL_P 26 — — External crystal input VDDA 27 PA — Analog power supply VDDA 28 PA — Analog power supply GND 29 G — Ground FSPID, MTDO FSPICS0 1 PA : analog power supply; PD : power supply for RTC IO; I: input; O: output; T: high impedance. 2 The pin function in this table refers only to some fixed settings and do not cover all cases for signals that can be input and output through the GPIO matrix. For more information on the GPIO matrix, please refer to Table 9. Espressif Systems 13 Submit Documentation Feedback ESP8685 Datasheet v1.0 2 Pin Definition 2.3 Power Scheme ESP8685 has four input power pins: • VDDA1 • VDDA2 • VDD3P3_RTC • VDD3P3_CPU VDDA1 and VDDA2 are the input power supply for the analog domain. RTC IO is powered from VDD3P3_RTC. The RTC domain is powered from Low Power Voltage Regulator, which is powered from VDD3P3_RTC. The Digital System domain is powered from Digital System Voltage Regulator, which is powered from VDD3P3_CPU and VDD3P3_RTC at the same time. Digital IO is powered from VDD3P3_CPU. The power scheme diagram is shown in Figure 5. Figure 5: ESP8685 Power Scheme Notes on CHIP_EN: Figure 6 shows the power-up and reset timing of ESP8685. Details about the parameters are listed in Table 4. Espressif Systems 14 Submit Documentation Feedback ESP8685 Datasheet v1.0 2 Pin Definition t0 t1 2.8 V VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU VIL_nRST CHIP_EN Figure 6: ESP8685 Power­up and Reset Timing Table 4: Description of ESP8685 Power­up and Reset Timing Parameters Parameter t0 t1 Min Description (µs) Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and VDD3P3_CPU rails, and activating CHIP_EN Duration of CHIP_EN signal level < VIL_nRST (refer to its value in 50 50 Table 13) to reset the chip 2.4 Strapping Pins ESP8685 series has three strapping pins: • GPIO2 • GPIO8 • GPIO9 Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG register. During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is powered down or shut down. Types of system reset include: • power-on reset • RTC watchdog reset • brownout reset • analog super watchdog reset • crystal clock glitch detection reset By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to an external high-impedance circuit, the latched bit value will be ”1” To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host MCU’s GPIOs to control the voltage level of these pins when powering on ESP8685 series. After reset, the strapping pins work as normal-function pins. Espressif Systems 15 Submit Documentation Feedback ESP8685 Datasheet v1.0 2 Pin Definition Table 5 lists detailed booting configurations of the strapping pins. Table 5: Strapping Pins Booting Mode 1 Pin Default SPI Boot Download Boot GPIO2 N/A 1 1 GPIO8 N/A Don’t care 1 1 0 GPIO9 Internal weak pull-up Enabling/Disabling ROM Messages Print During Booting Pin Default Functionality When the value of eFuse field EFUSE_UART_PRINT_CONTROL is 0 (default), print is enabled and not controlled by GPIO8. GPIO8 N/A 1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled. 2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled. 3, print is disabled and not controlled by GPIO8. 1 The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected behavior. Figure 7 shows the setup and hold times for the strapping pins before and after the CHIP_EN signal goes high. Details about the parameters are listed in Table 6. t0 CHIP_EN t1 VIL_nRST VIH Strapping pin Figure 7: Setup and Hold Times for the Strapping Pins Table 6: Parameter Descriptions of Setup and Hold Times for the Strapping Pins Min Parameter Description t0 Setup time before CHIP_EN goes from low to high 0 t1 Hold time after CHIP_EN goes high 3 Espressif Systems (ms) 16 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3. Functional Description This chapter describes the functions of ESP8685. 3.1 CPU and Memory 3.1.1 CPU ESP8685 has a low-power 32-bit RISC-V single-core microprocessor with the following features: • four-stage pipeline that supports a clock frequency of up to 160 MHz • RV32IMC ISA • 32-bit multiplier and 32-bit divider • up to 32 vectored interrupts at seven priority levels • up to 8 hardware breakpoints/watchpoints • up to 16 PMP regions • JTAG for debugging 3.1.2 Internal Memory ESP8685’s internal memory includes: • 384 KB of ROM: for booting and core functions. • 400 KB of on­chip SRAM: for data and instructions, running at a configurable frequency of up to 160 MHz. Of the 400 KB SRAM, 16 KB is configured for cache. • RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in Deep-sleep mode. • 4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID. • SiP flash : See details in Chapter 1 ESP8685 Series Comparison. Espressif Systems 17 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.1.3 Address Mapping Structure Figure 8: Address Mapping Structure Note: The memory space with gray background is not available for use. 3.1.4 Cache ESP8685 has an eight-way set associative cache. This cache is read-only and has the following features: • size: 16 KB • block size: 32 bytes • pre-load function • lock function • critical word first and early restart Espressif Systems 18 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.2 System Clocks 3.2.1 CPU Clock The CPU clock has three possible sources: • external main crystal clock • fast RC oscillator (typically about 17.5 MHz, and adjustable) • PLL clock The application can select the clock source from the three clocks above. The selected clock source drives the CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock source would be the external main crystal clock divided by 2. Note: ESP32-C3 is unable to operate without an external main crystal clock. 3.2.2 RTC Clock The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible sources: • external low-speed (32 kHz) crystal clock • internal slow RC oscillator (typically about 136 kHz, and adjustable) • internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256) The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources: • external main crystal clock divided by 2 • internal fast RC oscillator divide-by-N clock (typically about 17.5 MHz, and adjustable) 3.3 Analog Peripherals 3.3.1 Analog­to­Digital Converter (ADC) ESP8685 integrates two 12-bit SAR ADCs. • ADC1 supports measurements on 5 channels, and is factory-calibrated. • ADC2 supports measurements on 1 channel, and is not factory-calibrated. For ADC characteristics, please refer to Table 14. 3.3.2 Temperature Sensor The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via an ADC into a digital value. The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O load. Generally, the chip’s internal temperature is higher than the operating ambient temperature. Espressif Systems 19 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.4 Digital Peripherals 3.4.1 General Purpose Input / Output Interface (GPIO) ESP8685 has 15 GPIO pins which can be assigned various functions by configuring corresponding registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC. All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are configured as an input, the input value can be read by software through the register. Input GPIOs can also be set to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as the UART, etc. For low-power operations, the GPIOs can be set to holding state. The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while peripheral output signals can be configured to any IO pins. Table 7 shows the IO MUX functions of each pin. Table 7: IO MUX Pin Functions Name No. Function 0 Function 1 Function 2 Reset Notes XTAL_32K_P 4 GPIO0 GPIO0 — 0 R XTAL_32K_N 5 GPIO1 GPIO1 — 0 R GPIO2 6 GPIO2 GPIO2 FSPIQ 1 R GPIO3 8 GPIO3 GPIO3 — 1 R MTMS 9 MTMS GPIO4 FSPIHD 1 R MTDI 10 MTDI GPIO5 FSPIWP 1 R MTCK 12 MTCK GPIO6 FSPICLK 1* G MTDO 13 MTDO GPIO7 FSPID 1 G GPIO8 14 GPIO8 GPIO8 — 1 — GPIO9 15 GPIO9 GPIO9 — 3 — GPIO10 16 GPIO10 GPIO10 FSPICS0 1 G GPIO18 21 GPIO18 GPIO18 — 0 USB, G GPIO19 22 GPIO19 GPIO19 — 0* USB U0RXD 23 U0RXD GPIO20 — 3 G U0TXD 24 U0TXD GPIO21 — 4 — Reset The default configuration of each pin after reset: • 0 - input disabled, in high impedance state (IE = 0) • 1 - input enabled, in high impedance state (IE = 1) • 2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1) • 3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1) • 4 - output enabled, pull-up resistor enabled (OE = 1, WPU = 1) • 0* - input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1). See details in Notes • 1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is Espressif Systems 20 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1) 1, input enabled, in high impedance state (IE = 1) We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power consumption. You may add pull-up and pull-down resistors in your PCB design referring to Table 13, or enable internal pull-up and pull-down resistors during software initialization. Notes • R - These pins have analog functions. • USB - GPIO18 and GPIO19 are USB pins. The pull-up value of a USB pin is controlled by the pin’s pull-up value together with USB pull-up value. If any of the two pull-up values is 1, the pin’s pull-up resistor will be enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP bit. • G - These pins have glitches during power-up. See details in Table 8. Table 8: Power­Up Glitches on Pins Typical Time Period Pin Glitch1 MTCK Low-level glitch 5 MTDO Low-level glitch 5 GPIO10 Low-level glitch 5 U0RXD Low-level glitch 5 GPIO18 Pull-up glitch 1 (ns) 50000 Low-level glitch: the pin is at a low level during the time period; High-level glitch: the pin is at a high level during the time period; Pull-up glitch: the pin is pulled up during the time period; Pull-down glitch: the pin is pulled down during the time period. Table 9 shows the peripheral input/output signals via GPIO matrix. Please pay attention to the configuration of the bit GPIO_FUNCn_OEN_SEL: • GPIO_FUNCn_OEN_SEL = 1: the output enable is controlled by the corresponding bit n of GPIO_ENABLE_REG: – GPIO_ENABLE_REG = 0: output is disabled; – GPIO_ENABLE_REG = 1: output is enabled; • GPIO_FUNCn_OEN_SEL = 0: use the output enable signal from peripheral, for example SPIQ_oe in the column “Output enable signal when GPIO_FUNCn_OEN_SEL = 0” of Table 9. Note that the signals such as SPIQ_oe can be 1 (1’d1) or 0 (1’d0), depending on the configuration of corresponding peripherals. If it is 1’d1 in the “Output enable signal when GPIO_FUNCn_OEN_SEL = 0”, it indicates that once the register GPIO_FUNCn_OEN_SEL is cleared, the output signal is always enabled by default. Note: Signals are numbered consecutively, but not all signals are valid. • For input signals, only 6 ~ 11, 45, 53, 54, 63 ~ 68, 97 ~ 100 are valid. • For output signals, only 6 ~ 11, 45 ~ 50, 53 ~ 58, 63 ~ 73, 97 ~ 100, 123 ~ 125 are valid. Espressif Systems 21 Submit Documentation Feedback ESP8685 Datasheet v1.0 Signal No. Input Signal Default value Direct Input through IO Output Signal MUX Output enable signal when GPIO_FUNCn_OEN_SEL= 0 Direct Output through IO_MUX 22 Submit Documentation Feedback ESP8685 Datasheet v1.0 0 - - - - 1’d1 no 1 - - - - 1’d1 no 2 - - - - 1’d1 no 3 - - - - 1’d1 no 4 - - - - 1’d1 no 5 - - - - 1’d1 no 6 U0RXD_in 0 yes U0TXD_out 1’d1 yes 7 U0CTS_in 0 no U0RTS_out 1’d1 no 8 U0DSR_in 0 no U0DTR_out 1’d1 no 9 U1RXD_in 0 no U1TXD_out 1’d1 no 10 U1CTS_in 0 no U1RTS_out 1’d1 no 11 U1DSR_in 0 no U1DTR_out 1’d1 no 12 I2S_MCLK_in 0 no I2S_MCLK_out 1’d1 no 13 I2SO_BCK_in 0 no I2SO_BCK_out 1’d1 no 14 I2SO_WS_in 0 no I2SO_WS_out 1’d1 no 15 I2SI_SD_in 0 no I2SO_SD_out 1’d1 no 16 I2SI_BCK_in 0 no I2SI_BCK_out 1’d1 no 17 I2SI_WS_in 0 no I2SI_WS_out 1’d1 no 18 gpio_bt_priority 0 no gpio_wlan_prio 1’d1 no 19 gpio_bt_active 0 no gpio_wlan_active 1’d1 no 20 - - - - 1’d1 no 21 - - - - 1’d1 no 22 - - - - 1’d1 no 23 - - - - 1’d1 no 24 - - - - 1’d1 no 3 Functional Description Espressif Systems Table 9: Peripheral Signals via GPIO Matrix No. Input Signal Default value Direct Input through IO Output Signal MUX Output enable signal when GPIO_FUNCn_OEN_SEL= 0 Direct Output through IO_MUX 23 Submit Documentation Feedback ESP8685 Datasheet v1.0 25 - - - - 1’d1 no 26 - - - - 1’d1 no 27 - - - - 1’d1 no 28 cpu_gpio_in0 0 no cpu_gpio_out0 cpu_gpio_out_oen0 no 29 cpu_gpio_in1 0 no cpu_gpio_out1 cpu_gpio_out_oen1 no 30 cpu_gpio_in2 0 no cpu_gpio_out2 cpu_gpio_out_oen2 no 31 cpu_gpio_in3 0 no cpu_gpio_out3 cpu_gpio_out_oen3 no 32 cpu_gpio_in4 0 no cpu_gpio_out4 cpu_gpio_out_oen4 no 33 cpu_gpio_in5 0 no cpu_gpio_out5 cpu_gpio_out_oen5 no 34 cpu_gpio_in6 0 no cpu_gpio_out6 cpu_gpio_out_oen6 no 35 cpu_gpio_in7 0 no cpu_gpio_out7 cpu_gpio_out_oen7 no 36 - - - usb_jtag_tck 1’d1 no 37 - - - usb_jtag_tms 1’d1 no 38 - - - usb_jtag_tdi 1’d1 no 39 - - - usb_jtag_tdo 1’d1 no 40 - - - - 1’d1 no 41 - - - - 1’d1 no 42 - - - - 1’d1 no 43 - - - - 1’d1 no 44 - - - - 1’d1 no 45 ext_adc_start 0 no ledc_ls_sig_out0 1’d1 no 46 - - - ledc_ls_sig_out1 1’d1 no 47 - - - ledc_ls_sig_out2 1’d1 no 48 - - - ledc_ls_sig_out3 1’d1 no 49 - - - ledc_ls_sig_out4 1’d1 no 50 - - - ledc_ls_sig_out5 1’d1 no 51 rmt_sig_in0 0 no rmt_sig_out0 1’d1 no 3 Functional Description Espressif Systems Signal No. Input Signal Default value Direct Input through IO Output Signal MUX Output enable signal when GPIO_FUNCn_OEN_SEL= 0 Direct Output through IO_MUX 24 Submit Documentation Feedback ESP8685 Datasheet v1.0 52 rmt_sig_in1 0 no rmt_sig_out1 1’d1 no 53 I2CEXT0_SCL_in 1 no I2CEXT0_SCL_out I2CEXT0_SCL_oe no 54 I2CEXT0_SDA_in 1 no I2CEXT0_SDA_out I2CEXT0_SDA_oe no 55 - - - gpio_sd0_out 1’d1 no 56 - - - gpio_sd1_out 1’d1 no 57 - - - gpio_sd2_out 1’d1 no 58 - - - gpio_sd3_out 1’d1 no 59 - - - I2SO_SD1_out 1’d1 no 60 - - - - 1’d1 no 61 - - - - 1’d1 no 62 - - - - 1’d1 no 63 FSPICLK_in 0 yes FSPICLK_out_mux FSPICLK_oe yes 64 FSPIQ_in 0 yes FSPIQ_out FSPIQ_oe yes 65 FSPID_in 0 yes FSPID_out FSPID_oe yes 66 FSPIHD_in 0 yes FSPIHD_out FSPIHD_oe yes 67 FSPIWP_in 0 yes FSPIWP_out FSPIWP_oe yes 68 FSPICS0_in 0 yes FSPICS0_out FSPICS0_oe yes 69 - - - FSPICS1_out FSPICS1_oe no 70 - - - FSPICS2_out FSPICS2_oe no 71 - - - FSPICS3_out FSPICS3_oe no 72 - - - FSPICS4_out FSPICS4_oe no 73 - - - FSPICS5_out FSPICS5_oe no 74 twai_rx 1 no twai_tx 1’d1 no 75 - - - twai_bus_off_on 1’d1 no 76 - - - twai_clkout 1’d1 no 77 - - - - 1’d1 no 78 - - - - 1’d1 no 3 Functional Description Espressif Systems Signal No. Input Signal Default value Direct Input through IO Output Signal MUX Output enable signal when GPIO_FUNCn_OEN_SEL= 0 Direct Output through IO_MUX 25 Submit Documentation Feedback ESP8685 Datasheet v1.0 79 - - - - 1’d1 no 80 - - - - 1’d1 no 81 - - - - 1’d1 no 82 - - - - 1’d1 no 83 - - - - 1’d1 no 84 - - - - 1’d1 no 85 - - - - 1’d1 no 86 - - - - 1’d1 no 87 - - - - 1’d1 no 88 - - - - 1’d1 no 89 - - - ant_sel0 1’d1 no 90 - - - ant_sel1 1’d1 no 91 - - - ant_sel2 1’d1 no 92 - - - ant_sel3 1’d1 no 93 - - - ant_sel4 1’d1 no 94 - - - ant_sel5 1’d1 no 95 - - - ant_sel6 1’d1 no 96 - - - ant_sel7 1’d1 no 97 sig_in_func_97 0 no sig_in_func97 1’d1 no 98 sig_in_func_98 0 no sig_in_func98 1’d1 no 99 sig_in_func_99 0 no sig_in_func99 1’d1 no 100 sig_in_func_100 0 no sig_in_func100 1’d1 no 101 - - - - 1’d1 no 102 - - - - 1’d1 no 103 - - - - 1’d1 no 104 - - - - 1’d1 no 105 - - - - 1’d1 no 3 Functional Description Espressif Systems Signal No. Input Signal Default value Direct Input through IO Output Signal MUX Output enable signal when GPIO_FUNCn_OEN_SEL= 0 Direct Output through IO_MUX 26 Submit Documentation Feedback ESP8685 Datasheet v1.0 106 - - - - 1’d1 no 107 - - - - 1’d1 no 108 - - - - 1’d1 no 109 - - - - 1’d1 no 110 - - - - 1’d1 no 111 - - - - 1’d1 no 112 - - - - 1’d1 no 113 - - - - 1’d1 no 114 - - - - 1’d1 no 115 - - - - 1’d1 no 116 - - - - 1’d1 no 117 - - - - 1’d1 no 118 - - - - 1’d1 no 119 - - - - 1’d1 no 120 - - - - 1’d1 no 121 - - - - 1’d1 no 122 - - - - 1’d1 no 123 - - - CLK_OUT_out1 1’d1 no 124 - - - CLK_OUT_out2 1’d1 no 125 - - - CLK_OUT_out3 1’d1 no 126 - - - - 1’d1 no 127 - - - usb_jtag_trst 1’d1 no 3 Functional Description Espressif Systems Signal 3 Functional Description 3.4.2 Serial Peripheral Interface (SPI) ESP8685 features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can be configured to operate in SPI memory mode, while SPI2 can be configured to operate in general-purpose SPI modes. • SPI Memory mode In SPI memory mode, SPI0 and SPI1 are used to connect the SiP flash in chip package. Data is transferred in bytes. Up to four-line SDR reads and writes are supported. The clock frequency is configurable to a maximum of 120 MHz. • SPI2 General­purpose SPI (GP­SPI) mode When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master and slave modes. The host’s clock frequency is configurable. Data is transferred in bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA. – In master mode, the clock frequency is 80 MHz at most, and the four modes of SPI transfer format are supported. – In slave mode, the clock frequency is 60 MHz at most, and the four modes of SPI transfer format are also supported. 3.4.3 Universal Asynchronous Receiver Transmitter (UART) ESP8685 has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces connect to GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU. 3.4.4 I2C Interface ESP8685 has an I2C bus interface which is used for I2C master mode or slave mode, depending on your configuration. The I2C interface supports: • standard mode (100 Kbit/s) • fast mode (400 Kbit/s) • up to 800 Kbit/s (constrained by SCL and SDA pull-up strength) • 7-bit and 10-bit addressing mode • double addressing mode • 7-bit broadcast address You can configure instruction registers to control the I2C interface for more flexibility. 3.4.5 I2S Interface ESP8685 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK clock frequency, from 10 kHz up to 40 MHz, is supported. The I2S interface supports TDM PCM, TDM MSB alignment, TDM LSB alignment, TDM Phillips, and PDM TX interface. It connects to the GDMA controller. Espressif Systems 27 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.4.6 Remote Control Peripheral The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive waveform. 3.4.7 LED PWM Controller The LED PWM controller can generate independent digital waveform on six channels. The LED PWM controller: • can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be up to 18 bits. • has multiple clock sources, including APB clock and external main crystal clock. • can operate when the CPU is in Light-sleep mode. • supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator. 3.4.8 General DMA Controller ESP8685 has a general DMA controller (GDMA) with six independent channels, i.e. three transmit channels and three receive channels. These six channels are shared by peripherals with DMA feature. The GDMA controller implements a fixed-priority scheme among these channels, whose priority can be configured. The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and memory-to-memory data transfer at a high speed. All channels can access internal RAM. Peripherals on ESP8685 with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC. 3.4.9 USB Serial/JTAG Controller ESP8685 integrates a USB Serial/JTAG controller. This controller has the following features: • CDC-ACM virtual serial port and JTAG adapter functionality • USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not support the faster 480 Mbit/s high-speed transfer mode) • programming SiP flash • CPU debugging with compact JTAG instructions • a full-speed USB PHY integrated in the chip 3.4.10 TWAI® Controller ESP8685 has a TWAI® controller with the following features: • compatible with ISO 11898-1 protocol (CAN Specification 2.0) • standard frame format (11-bit ID) and extended frame format (29-bit ID) • bit rates from 1 Kbit/s to 1 Mbit/s • multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required) • 64-byte receive FIFO Espressif Systems 28 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description • acceptance filter (single and dual filter modes) • error detection and handling: error counters, configurable error interrupt threshold, error code capture, arbitration lost capture 3.5 Radio and Wi­Fi ESP8685 radio consists of the following blocks: • 2.4 GHz receiver • 2.4 GHz transmitter • bias and regulators • balun and transmit-receive switch • clock generator 3.5.1 2.4 GHz Receiver The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, ESP8685 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and baseband filters. 3.5.2 2.4 GHz Transmitter The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of the power amplifier. Additional calibrations are integrated to cancel any radio imperfections, such as: • carrier leakage • I/Q amplitude/phase matching • baseband nonlinearities • RF nonlinearities • antenna matching These built-in calibration routines reduce the cost, time, and specialized equipment required for product testing. 3.5.3 Clock Generator The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators and dividers. The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the transmitter. Espressif Systems 29 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.5.4 Wi­Fi Radio and Baseband ESP8685 Wi-Fi radio and baseband support the following features: • 802.11b/g/n • 802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth • 802.11n MCS32 • 802.11n 0.4 µs guard interval • data rate up to 150 Mbps • RX STBC (single spatial stream) • adjustable transmitting power • antenna diversity ESP8685 supports antenna diversity with an external RF switch. This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections. 3.5.5 Wi­Fi MAC ESP8685 implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS) STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled automatically with minimal host interaction to minimize the active duty period. ESP8685 Wi-Fi MAC applies the following low-level protocol functions automatically: • 4 × virtual Wi-Fi interfaces • infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode • RTS protection, CTS protection, Immediate Block ACK • fragmentation and defragmentation • TX/RX A-MPDU, TX/RX A-MSDU • transmit opportunity (TXOP) • Wi-Fi multimedia (WMM) • GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise • automatic beacon monitoring (hardware TSF) • 802.11mc FTM 3.5.6 Networking Features Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols over Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported. 3.6 Bluetooth LE ESP8685 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and Bluetooth mesh. Espressif Systems 30 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.6.1 Bluetooth LE Radio and PHY Bluetooth Low Energy radio and PHY in ESP8685 support: • 1 Mbps PHY • 2 Mbps PHY for higher data rates • coded PHY for longer range (125 Kbps and 500 Kbps) • listen before talk (LBT), implemented in hardware • antenna diversity with an external RF switch This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections. 3.6.2 Bluetooth LE Link Layer Controller Bluetooth Low Energy Link Layer Controller in ESP8685 supports: • LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data • multiple advertisement sets • simultaneous advertising and scanning • multiple connections in simultaneous central and peripheral roles • adaptive frequency hopping and channel assessment • LE channel selection algorithm #2 • connection parameter update • high duty cycle non-connectable advertising • LE privacy 1.2 • LE data packet length extension • link layer extended scanner filter policies • low duty cycle directed advertising • link layer encryption • LE Ping 3.7 Low Power Management With the use of advanced power-management technologies, ESP8685 can switch between different power modes: • Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen. • Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band, Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active. • Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip. Wi-Fi and Bluetooth LE connection can remain active. • Deep-sleep mode: CPU and most peripherals are powered down. Only the RTC memory is powered on. Wi-Fi connection data are stored in the RTC memory. The RTC timer or the RTC GPIOs can wake up the chip from the Deep-sleep mode. Espressif Systems 31 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description For power consumption in different power modes, please refer to Table 16. 3.8 Timers 3.8.1 General Purpose Timers ESP8685 is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers and 54-bit auto-reload-capable up/down-timers. The timers’ features are summarized as follows: • a 16-bit clock prescaler, from 1 to 65536 • a 54-bit time-base counter programmable to be incrementing or decrementing • able to read real-time value of the time-base counter • halting and resuming the time-base counter • programmable alarm generation • level interrupt generation 3.8.2 System Timer ESP8685 integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The system timer has the following features: • counters with a fixed clock frequency of 16 MHz • three types of independent interrupts generated according to alarm value • two alarm modes: target mode and period mode • 52-bit target alarm value and 26-bit periodic alarm value • automatic reload of counter value • counters can be stalled if the CPU is stalled or in OCD mode 3.8.3 Watchdog Timers ESP8685 contains three watchdog timers: one in each of the two timer groups (called Main System Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order to detect and recover from booting errors. Watchdog timers have the following features: • four stages, each with a programmable timeout value. Each stage can be configured, enabled and disabled separately • interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or system reset for RWDT upon expiry of each stage • 32-bit expiry counter • write protection, to prevent RWDT and MWDT configuration from being altered inadvertently • flash boot protection If the boot process from an SPI flash does not complete within a predetermined period of time, the watchdog will reboot the entire main system. Espressif Systems 32 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description 3.9 Cryptographic Hardware Accelerators ESP8685 is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS PUB 197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), and RSA3072. The chip also supports independent arithmetic, such as Big Integer Multiplication and Big Integer Modular Multiplication. The maximum operation length for RSA and Big Integer Modular Multiplication is 3072 bits. The maximum factor length for Big Integer Multiplication is 1536 bits. 3.10 Physical Security Features • Transparent flash encryption (AES-XTS algorithm) with software inaccessible key prevents unauthorized readout of your application code or data. • Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature) can be booted. • HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity verification and other purposes. • Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity verification. • World Controller provides two running environments for software. All hardware and software resources are sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed by hardware in the general world, thus establishing a security boundary. 3.11 Peripheral Pin Configurations Table 10: Peripheral Pin Configurations Interface Signal Pin Function ADC ADC1_CH0 XTAL_32K_P Two 12-bit SAR ADCs ADC1_CH1 XTAL_32K_N ADC1_CH2 GPIO2 ADC1_CH3 GPIO3 ADC1_CH4 MTMS ADC2_CH0 MTDI MTDI MTDI MTCK MTCK MTMS MTMS MTDO MTDO U0RXD_in Any GPIO pins JTAG UART JTAG for software debugging U0CTS_in Two UART channels with hardware flow control and GDMA U0DSR_in U0TXD_out U0RTS_out U0DTR_out U1RXD_in U1CTS_in U1DSR_in Espressif Systems 33 Submit Documentation Feedback ESP8685 Datasheet v1.0 3 Functional Description Interface Signal Pin Function Any GPIO pins One I2C channel in slave or master mode U1TXD_out U1RTS_out U1DTR_out I2C I2CEXT0_SCL_in I2CEXT0_SDA_in I2CEXT1_SCL_in I2CEXT1_SDA_in I2CEXT0_SCL_out I2CEXT0_SDA_out I2CEXT1_SCL_out I2CEXT1_SDA_out LED PWM ledc_ls_sig_out0~5 Any GPIO pins Six independent PWM channels I2S I2S0O_BCK_in Any GPIO pins Stereo input and output from/to the audiocodec I2S_MCLK_in I2SO_WS_in I2SI_SD_in I2SI_BCK_in I2SI_WS_in I2SO_BCK_out I2S_MCLK_out I2SO_WS_out I2SO_SD_out I2SI_BCK_out I2SI_WS_out I2SO_SD1_out SPI2 FSPICLK_in/_out_mux Any GPIO pins FSPICS0_in/_out • Master mode and slave mode of SPI, Dual SPI, Quad SPI, and QPI FSPICS1~5_out • Four modes of SPI transfer format FSPID_in/_out • Configurable SPI frequency FSPIQ_in/_out • 64-byte FIFO or GDMA buffer FSPIWP_in/_out FSPIHD_in/_out Remote Control RMT_SIG_IN0~1 Peripheral RMT_SIG_OUT0~1 USB Serial/JTAG USB_D+ GPIO19 USB-to-serial converter, and USB-to-JTAG USB_D- GPIO18 converter twai_rx Any GPIO pins Compatible with ISO 11898-1 protocol TWAI Any GPIO pins Two channels for an IR transceiver of various waveforms twai_tx twai_bus_off_on twai_clkout Espressif Systems 34 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the device. These are stress ratings only, and do not refer to the functional operation of the device. Table 11: Absolute Maximum Ratings Symbol VDDA, Parameter VDD3P3, VDD3P3_RTC, Min Voltage applied to power supply pins VDD3P3_CPU per power domain TST ORE Storage temperature Max Unit –0.3 3.6 V –40 150 °C Max Unit 4.2 Recommended Operating Conditions Table 12: Recommended Operating Conditions Symbol Parameter VDDA, VDD3P3 Voltage applied to power supply VDD3P3_RTC pins per power domain VDD3P3_CPU2 Voltage applied to power supply pin IV DD 3 TA Min Typ 3.0 3.3 3.6 V 3.0 3.3 3.6 V Current delivered by external power supply 0.5 — — A Operating ambient temperature –40 — 105 °C 1 For more information, please refer to Section 2.3 Power Scheme. 2 To write eFuse, VDD3P3_CPU should not be higher than 3.3 V. 3 If you use a single power supply, the recommended output current is 500 mA or more. 4.3 DC Characteristics (3.3 V, 25 °C) Table 13: DC Characteristics (3.3 V, 25 °C) Symbol Parameter CIN Pin capacitance VIH Min Typ — High-level input voltage 0.75 × VDD 1 Max 2 — Unit — pF 1 VDD + 0.3 V 1 VIL Low-level input voltage –0.3 — 0.25 × VDD IIH High-level input current — — 50 nA Low-level input current — — 50 nA — — V IIL VOH VOL 2 2 High-level output voltage 0.8 × VDD Low-level output voltage 1 1 V — — 0.1 × VDD V — 40 — mA — 28 — mA 1 IOH IOL High-level source current (VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3) Low-level sink current (VDD1= 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3) RP U Pull-up resistor — 45 — kΩ RP D Pull-down resistor — 45 — kΩ Cont’d on next page Espressif Systems 35 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics Table 13 – cont’d from previous page Symbol VIH_nRST VIL_nRST Parameter Min Chip reset release voltage Typ 0.75 × VDD Chip reset voltage 1 –0.3 1 VDD is the I/O voltage for a particular power domain of pins. 2 VOH and VOL are measured using high-impedance load. Max Unit 1 — VDD + 0.3 — 0.25 × VDD V 1 V 4.4 ADC Characteristics Table 14: ADC Characteristics Symbol Parameter Min ADC connected to an external DNL (Differential nonlinearity)1 7 LSB –12 12 LSB — 100 kSPS 2 ATTEN0 0 750 mV ATTEN1 0 1050 mV ATTEN2 0 1300 mV ATTEN3 0 2500 mV ambient temperature at 25 °C; Wi-Fi off Sampling rate — Effective Range Unit –7 100 nF capacitor; DC signal input; INL (Integral nonlinearity) Max 1 To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value. 2 kSPS means kilo samples-per-second. 4.5 Current Consumption The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF port. All transmitters’ measurements are based on a 100% duty cycle. Table 15: Current Consumption Depending on RF Modes Work mode Peak Description (mA) TX Active (RF working) RX 802.11b, 1 Mbps, @21 dBm 335 802.11g, 54 Mbps, @19 dBm 285 802.11n, HT20, MCS7, @18.5 dBm 276 802.11n, HT40, MCS7, @18.5 dBm 278 802.11b/g/n, HT20 84 802.11n, HT40 87 Table 16: Current Consumption Depending on Work Modes Work mode Modem-sleep1, 2 Light-sleep Espressif Systems Description The CPU is powered on 3 Typ Unit 160 MHz 20 mA 80 MHz 15 mA 130 µA — 36 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics Deep-sleep RTC timer + RTC memory 5 µA Power off CHIP_PU is set to low level, the chip is powered off 1 µA 1 The current consumption figures in Modem-sleep mode are for cases where the CPU is powered on and the cache idle. 2 When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. Therefore, current consumption changes accordingly. 3 In Modem-sleep mode, the CPU frequency changes automatically. The frequency depends on the CPU load and the peripherals used. 4.6 Reliability Table 17: Reliability Qualifications Test Item Test Conditions Test Standard 125 °C, 1000 hours JESD22-A108 ESD (Electro-Static HBM (Human Body Mode)1± 2000 V JS-001 Discharge Sensitivity) CDM (Charge Device Mode)2± 1000 V JS-002 HTOL (High Temperature Operating Life) Current trigger ± 200 mA Latch up JESD78 Voltage trigger 1.5 × VDDmax Bake 24 hours @125 °C Preconditioning J-STD-020, JESD47, Moisture soak (level 3: 192 hours @30 °C, 60% RH) IR reflow solder: 260 + 0 °C, 20 seconds, three times TCT (Temperature Cycling Test) JESD22-A113 –65 °C / 150 °C, 500 cycles JESD22-A104 130 °C, 85% RH, 96 hours JESD22-A118 150 °C, 1000 hours JESD22-A103 – 40 °C, 1000 hours JESD22-A119 uHAST (Highly Accelerated Stress Test, unbiased) HTSL (High Temperature Storage Life) LTSL (Low Temperature Storage Life) 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 4.7 Wi­Fi Radio Table 18: Wi­Fi Frequency Parameter Center frequency of operating channel Espressif Systems Min Typ Max (MHz) (MHz) (MHz) 2412 — 2484 37 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics 4.7.1 Wi­Fi RF Transmitter (TX) Specifications Table 19: TX Power with Spectral Mask and EVM Meeting 802.11 Standards Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 21.0 — 802.11b, 11 Mbps — 21.0 — 802.11g, 6 Mbps — 21.0 — 802.11g, 54 Mbps — 19.0 — 802.11n, HT20, MCS0 — 20.0 — 802.11n, HT20, MCS7 — 18.5 — 802.11n, HT40, MCS0 — 20.0 — 802.11n, HT40, MCS7 — 18.5 — Rate Table 20: TX EVM Test Rate Min Typ SL1 (dB) (dB) (dB) 802.11b, 1 Mbps, @21 dBm — –24.5 –10 802.11b, 11 Mbps, @21 dBm — –24.5 –10 802.11g, 6 Mbps, @21 dBm — –21.0 –5 802.11g, 54 Mbps, @19 dBm — –27.0 –25 802.11n, HT20, MCS0, @20 dBm — –22.5 –5 802.11n, HT20, MCS7, @18.5 dBm — –28.5 –27 802.11n, HT40, MCS0, @20 dBm — –22.5 –5 802.11n, HT40, MCS7, @18.5 dBm — –28.5 –27 1 SL stands for standard limit value. 4.7.2 Wi­Fi RF Receiver (RX) Specifications Table 21: RX Sensitivity Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — –98.4 — 802.11b, 2 Mbps — –96.0 — 802.11b, 5.5 Mbps — –93.0 — 802.11b, 11 Mbps — –88.6 — 802.11g, 6 Mbps — –93.8 — 802.11g, 9 Mbps — –92.2 — 802.11g, 12 Mbps — –91.0 — 802.11g, 18 Mbps — –88.4 — 802.11g, 24 Mbps — –85.8 — 802.11g, 36 Mbps — –82.0 — Rate Cont’d on next page Espressif Systems 38 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics Table 21 – cont’d from previous page Min Typ Max (dBm) (dBm) (dBm) 802.11g, 48 Mbps — –78.0 — 802.11g, 54 Mbps — –76.6 — 802.11n, HT20, MCS0 — –93.6 — 802.11n, HT20, MCS1 — –90.8 — 802.11n, HT20, MCS2 — –88.4 — 802.11n, HT20, MCS3 — –85.0 — 802.11n, HT20, MCS4 — –81.8 — 802.11n, HT20, MCS5 — –77.8 — 802.11n, HT20, MCS6 — –76.0 — 802.11n, HT20, MCS7 — –74.8 — 802.11n, HT40, MCS0 — –90.0 — 802.11n, HT40, MCS1 — –88.0 — 802.11n, HT40, MCS2 — –85.2 — 802.11n, HT40, MCS3 — –82.0 — 802.11n, HT40, MCS4 — –78.8 — 802.11n, HT40, MCS5 — –74.6 — 802.11n, HT40, MCS6 — –73.0 — 802.11n, HT40, MCS7 — –71.4 — Rate Table 22: Maximum RX Level Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 5 — 802.11b, 11 Mbps — 5 — 802.11g, 6 Mbps — 5 — 802.11g, 54 Mbps — 0 — 802.11n, HT20, MCS0 — 5 — 802.11n, HT20, MCS7 — 0 — 802.11n, HT40, MCS0 — 5 — 802.11n, HT40, MCS7 — 0 — Rate Table 23: RX Adjacent Channel Rejection Rate Min Typ Max (dB) (dB) (dB) 802.11b, 1 Mbps — 35 — 802.11b, 11 Mbps — 35 — 802.11g, 6 Mbps — 31 — 802.11g, 54 Mbps — 20 — 802.11n, HT20, MCS0 — 31 — Cont’d on next page Espressif Systems 39 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics Table 23 – cont’d from previous page Rate Min Typ Max (dB) (dB) (dB) 802.11n, HT20, MCS7 — 16 — 802.11n, HT40, MCS0 — 25 — 802.11n, HT40, MCS7 — 11 — 4.8 Bluetooth LE Radio Table 24: Bluetooth LE Frequency Parameter Min Typ Max (MHz) (MHz) (MHz) 2402 — 2480 Center frequency of operating channel 4.8.1 Bluetooth LE RF Transmitter (TX) Specifications Table 25: Transmitter Characteristics ­ Bluetooth LE 1 Mbps Parameter Description Min RF power control range RF transmit power Carrier frequency offset and drift Modulation characteristics In-band spurious emissions Typ Max Unit –27.00 0 18.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn | — 1.75 — kHz Max |fn − fn−5 | — 1.46 — kHz |f1 − f0 | — 0.80 — kHz ∆ f 1avg — 250.00 — kHz — 190.00 — kHz ∆ f 2avg /∆ f 1avg — 0.83 — — ± 2 MHz offset — –37.62 — dBm ± 3 MHz offset — –41.95 — dBm > ± 3 MHz offset — –44.48 — dBm Min ∆ f 2max (for at least 99.9% of all ∆ f 2max ) dBm Table 26: Transmitter Characteristics ­ Bluetooth LE 2 Mbps Parameter RF transmit power Carrier frequency offset and drift Description Min RF power control range Max Unit –27.00 0 18.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 20.80 — kHz Max |f0 − fn | — 1.30 — kHz Max |fn − fn−5 | — 1.33 — kHz |f1 − f0 | — 0.70 — kHz ∆ f 1avg — 498.00 — kHz dBm Cont’d on next page Modulation characteristics Espressif Systems Typ 40 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics Table 26 – cont’d from previous page Parameter Description Min Min ∆ f 2max (for at least Max Unit — 430.00 — kHz ∆ f 2avg /∆ f 1avg — 0.93 — — ± 4 MHz offset — –43.55 — dBm ± 5 MHz offset — –45.26 — dBm > ± 5 MHz offset — –45.26 — dBm 99.9% of all ∆ f 2max ) In-band spurious emissions Typ Table 27: Transmitter Characteristics ­ Bluetooth LE 125 Kbps Parameter Description Min RF power control range RF transmit power Carrier frequency offset and drift Modulation characteristics Max Unit –27.00 0 18.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 17.50 — kHz Max |f0 − fn | — 0.45 — kHz |fn − fn−3 | — 0.70 — kHz |f0 − f3 | — 0.30 — kHz ∆ f 1avg — 250.00 — kHz — 235.00 — kHz ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.00 — dBm > ± 3 MHz offset — –42.50 — dBm Min ∆ f 1max (for at least 99.9% of all∆ f 2max ) In-band spurious emissions Typ dBm Table 28: Transmitter Characteristics ­ Bluetooth LE 500 Kbps Parameter RF transmit power Carrier frequency offset and drift Modulation characteristics Description Min RF power control range Max Unit –27.00 0 18.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn | — 0.88 — kHz |fn − fn−3 | — 1.00 — kHz |f0 − f3 | — 0.20 — kHz ∆ f 2avg — 208.00 — kHz — 190.00 — kHz ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.30 — dBm > ± 3 MHz offset — –42.80 — dBm Min ∆ f 2max (for at least 99.9% of all ∆ f 2max ) In-band spurious emissions Typ dBm 4.8.2 Bluetooth LE RF Receiver (RX) Specifications Espressif Systems 41 Submit Documentation Feedback ESP8685 Datasheet v1.0 4 Electrical Characteristics Table 29: Receiver Characteristics ­ Bluetooth LE 1 Mbps Parameter Description Sensitivity @30.8% PER — — –97 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 8 — dB F = F0 + 1 MHz — –3 — dB F = F0 – 1 MHz — –4 — dB F = F0 + 2 MHz — –29 — dB F = F0 – 2 MHz — –31 — dB F = F0 + 3 MHz — –33 — dB F = F0 – 3 MHz — –27 — dB F ≥ F0 + 4 MHz — –29 — dB F ≤ F0 – 4 MHz — –38 — dB — — –29 — dB F = Fimage + 1 MHz — –41 — dB F = Fimage – 1 MHz — –33 — dB 30 MHz ~ 2000 MHz — –5 — dBm 2003 MHz ~ 2399 MHz — –18 — dBm 2484 MHz ~ 2997 MHz — –15 — dBm 3000 MHz ~ 12.75 GHz — –5 — dBm — — –30 — dBm Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Out-of-band blocking performance Intermodulation Min Typ Max Unit Table 30: Receiver Characteristics ­ Bluetooth LE 2 Mbps Parameter Description Sensitivity @30.8% PER — — –93 — dBm Maximum received signal @30.8% PER — — 3 — dBm Co-channel C/I — — 10 — dB F = F0 + 2 MHz — –7 — dB F = F0 – 2 MHz — –7 — dB F = F0 + 4 MHz — –28 — dB F = F0 – 4 MHz — –26 — dB F = F0 + 6 MHz — –26 — dB F = F0 – 6 MHz — –27 — dB F ≥ F0 + 8 MHz — –29 — dB F ≤ F0 – 8 MHz — –28 — dB — — –28 — dB F = Fimage + 2 MHz — –26 — dB F = Fimage – 2 MHz — –7 — dB 30 MHz ~ 2000 MHz — –5 — dBm 2003 MHz ~ 2399 MHz — –19 — dBm 2484 MHz ~ 2997 MHz — –16 — dBm 3000 MHz ~ 12.75 GHz — –5 — dBm — — –29 — dBm Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Out-of-band blocking performance Intermodulation Espressif Systems 42 Submit Documentation Feedback Min Typ Max Unit ESP8685 Datasheet v1.0 4 Electrical Characteristics Table 31: Receiver Characteristics ­ Bluetooth LE 125 Kbps Parameter Description Sensitivity @30.8% PER — — –105 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 3 — dB F = F0 + 1 MHz — –6 — dB F = F0 – 1 MHz — –6 — dB F = F0 + 2 MHz — –33 — dB F = F0 – 2 MHz — –43 — dB F = F0 + 3 MHz — –37 — dB F = F0 – 3 MHz — –47 — dB F ≥ F0 + 4 MHz — –40 — dB F ≤ F0 – 4 MHz — –50 — dB — — –40 — dB F = Fimage + 1 MHz — –50 — dB F = Fimage – 1 MHz — –37 — dB Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Min Typ Max Unit Table 32: Receiver Characteristics ­ Bluetooth LE 500 Kbps Parameter Description Sensitivity @30.8% PER — — –100 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 3 — dB F = F0 + 1 MHz — –2 — dB F = F0 – 1 MHz — –3 — dB F = F0 + 2 MHz — –32 — dB F = F0 – 2 MHz — –33 — dB F = F0 + 3 MHz — –23 — dB F = F0 – 3 MHz — –40 — dB F ≥ F0 + 4 MHz — –34 — dB F ≤ F0 – 4 MHz — –44 — dB — — –34 — dB F = Fimage + 1 MHz — –46 — dB F = Fimage – 1 MHz — –23 — dB Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Espressif Systems 43 Submit Documentation Feedback Min Typ Max Unit ESP8685 Datasheet v1.0 5 Package Information 5. Package Information · Figure 9: QFN28 (4×4 mm) Package Note: • All dimensions are in millimeters. • For information about tape, reel, and product marking, please refer to Espressif Chip Packaging Information. Espressif Systems 44 Submit Documentation Feedback ESP8685 Datasheet v1.0 6 Related Documentation and Resources 6. Related Documentation and Resources Related Documentation • Certificates https://espressif.com/en/support/documents/certificates • Documentation Updates and Update Notification Subscription https://espressif.com/en/support/download/documents Developer Zone • ESP-IDF and other development frameworks on GitHub. https://github.com/espressif • ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. https://esp32.com/ • The ESP Journal – Best Practices, Articles, and Notes from Espressif folks. https://blog.espressif.com/ • See the tabs SDKs and Demos, Apps, Tools, AT Firmware. https://espressif.com/en/support/download/sdks-demos Products • ESP8685 Series SoCs – Browse through all ESP8685 SoCs. https://espressif.com/en/products/socs?id=ESP8685 • ESP8685 Series Modules – Browse through all ESP8685-based modules. https://espressif.com/en/products/modules?id=ESP8685 • ESP8685 Series DevKits – Browse through all ESP8685-based devkits. https://espressif.com/en/products/devkits?id=ESP8685 • ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters. https://products.espressif.com/#/product-selector?language=en Contact Us • See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples (Online stores), Become Our Supplier, Comments & Suggestions. https://espressif.com/en/contact-us/sales-questions Espressif Systems 45 Submit Documentation Feedback ESP8685 Datasheet v1.0 Revision History Revision History Date Version Release Notes • Added a new variant ESP8685H4; • Updated Figure Block Diagram to show power modes; • Added CoreMark score in Features; 2022-04-08 v1.0 • Updated Figure ESP8685 Power Scheme and related descriptions; • Updated Table Peripheral Signals via GPIO Matrix; • Added note 2 to Table Recommended Operating Conditions; • Other updates to wording. 2021-07-30 v0.5 Espressif Systems Preliminary release 46 Submit Documentation Feedback ESP8685 Datasheet v1.0 Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND ACCURACY. NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. www.espressif.com All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Copyright © 2022 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.