NJU7181RB1-TE1

NJU7181 SIGNAL LEVEL SENSOR SYSTEM PACKAGE OUTLINE GENERAL DESCRIPTION The NJU7181 is a signal level sensor system IC. It sends a High flag to the microprocessor or other equipments whenever it detects the existence of the audio signal. The NJU7181 includes a delay circuit which allows the IC continue to hold the flag after the absence of the audio signal. This holding time can be adjusted with external capacitor. Together with its adjustable Input Sensitivity (by external resistor) & its characteristic of low current consumption and low operating voltage, NJU7181 is suitable for Eco-Design of Energy-using Products and for battery operated applications. NJU7181RB1 MSOP8 (TVSP8) NJU7181KU1 FEATURES • Operating Voltage 0.9 to 5.5V • Low Operating Current 55µA typ. • Delay circuit for long Recovery time • Adjustable Recovery time by external capacitor • Adjustable Input Sensitivity by external resistance • C-MOS Technology • Package Outline MSOP8 (TVSP8)* ESON8 *MEET JEDEC MO-187-DA / THIN TYPE APPLICATIONS • Power Saving for battery operated devices • Muting Application • Memory saving for recording devices • Half- duplex transmission application BLOCK DIAGRAM V+ ON OFF V+ External Trigger OUT D Level Detector Delay L CLR Latch IN Version 5.4E –1– NJU7181 PIN CONFIGURATION MSOP8 (TVSP8) ESON8 1 8 8 7 6 4 5 1 2 3 4 Surface No. Symbol 1 2 3 4 8 7 6 5 Backside Function 1 IN 2 AMP_OUT 3 TRIN External Trigger Input 4 GND Ground 5 CAP_D Delay Time Capacitor 6 RES_D Delay Time Resister 7 OUT 8 V + 5 AC Input Amplifier Output DC Output Supply Voltage –2– NJU7181 „ ABSOLUTE MAXIMUM RATING (Ta=25°C) PARAMETER SYMBOL + Supply Voltage V Power Dissipation PD RATING UNIT V mW Maximum Input Voltage VIMAX +7 MSOP8 (TVSP8): 470 (Note1) ESON8: 450 + 0 ~ V (Note2) Operating Temperature Range Topr -40 ~ +85 °C Storage Temperature Range Tstg -40 ~ +125 °C V (Note1) EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting (Note2) Don’t put Input Voltage more than Power Supply Voltage. „ ELECTRICAL CHARACTERISTICS + (Ta=25°C, V =3V, R1=10kΩ, R2=100kΩ, Rd=220kΩ, Cd=10nF) PARAMETER SYMBOL TEST CONDITION + Operating Voltage V Operating Current IDD No signal, RL=∞ Input Sensitivity VINS f=1kHz MIN. TYP. MAX. UNIT 0.9 - 5.5 V - 55 100 µA -45 -41.5 -38 dBV 1.0 1.5 2.0 Sec Delay Time 1 Tdelay1 Delay Time 2 Tdelay2 V =0.9V 1.0 1.5 2.0 Sec Delay Time 3 Tdelay3 Cd =10µF - 1,500 - Sec MIN. TYP. MAX. UNIT + „ DC CHARACTERISTICS DC Output Terminal (7pin) (Ta=25°C) PARAMETER SYMBOL TEST CONDITION High Level Output Voltage VOH ISOURCE =1mA Low Level Output Voltage VOL ISINK =1mA + + V V -0.2 - V 0 - 0.2 V External Trigger Switch Terminal (3pin) (Ta=25°C) High Level Input Voltage VIH V -0.2 + - V + V Low Level Input Voltage VIL 0 - 0.2 V –3– NJU7181 „ TEST CIRCUIT VDD 1mA V 10uF + 8 V+ 1nF 220kΩ VDD 7 6 5 OUT RES_D CAP_D NJU7181 IN 10uF + 10kΩ AMP_OUT 2 TRIN 3 100kΩ GND 4 A 10pF IDD 22kΩ IN 1 –4– NJU7181 „ APPLICATION CIRCUIT Audio Signal Input Main Path Audio Signal Output V+ External Trigger 100kΩ ON OFF V+ DC Output D Level Detector Delay CD Ci R1 L CLR Latch High or Low DC voltage inform ation (to Micro Processor, etc) RD=220kΩ R2 Input sensitivity (Detection level) Audio Signal Input Delay Time (Adjustable from a few second to a few minutes by CD ) DC Output (NJU7181) Low High Low –5– NJU7181 Attack Time: Note: OUTPUT + Input 10kΩ 8 7 6 5 V+ OUT RES_D CAP_D NJU7181 IN 1 AMP_OUT 2 100kΩ 10pF TRIN 3 GND 4 100kΩ Supply De-coupling capacitor has to be placed near IC (especially w hen IC socket is being used). 10nF + 10uF 10uF 220kΩ VDD External Control (Control from MicroProcessor, etc.) Feedback Capacitor is required to prevent the possibility to of oscillation in the input stage. –6– NJU7181 „ APPLICATION NOTE • DC Output Waveform Scenario Scenario 1: Power-ON – Output will be high initially when NJU7181 is first powered up even if there is no input signal detected. POWER ON with no signal detected Power On Power No Signal detected (Low) Trigger No Input Signal detected Audio Signal Input Delay TIme : Tdelay DC Output (NJU7181) High LOW LOW Scenario 2: Only Audio Signal detected – Output will be or maintain high when either an input signal or trigger signal is detected. The delay circuit will only be activated when both signals is not present. NJU7181 will then hold the output level for a delay time which can be adjusted by the Capacitor value @ pin 5. Audio signal present Power On Power No Signal detected (Low) Trigger Audio Signal Input Signal Detected Delay TIme : Tdelay LOW High LOW –7– NJU7181 Scenario 3: Trigger Signal detected (Case 1) – Output will be or maintain high when either an input signal or trigger signal is detected. The delay circuit will only be activated when both signals is not present. Output is set to Low state when a delay time passes. Output is set to High state when either an input signal or trigger signal is detected again. Case 1: Trigger signal present (After output LOW) Power On Power Trigger detected Trigger Audio Signal Input Signal Detected Delay TIme : Tdelay Delay TIme : Tdelay High due to triggger High DC Output (NJU7181) LOW LOW LOW Scenario 4: Trigger Signal detected (Case 2) – Output will be or maintain high when either an input signal or trigger signal is detected. When hold time is shorter than a delay time, output maintains High state (Counter RESET). NJU7181 will then hold the output level for a delay time which can be adjusted by the Capacitor value @ pin 5. Case 2: Trigger signal present (During output HIGH) Power On Power Trigger detected Trigger Audio Signal Input Signal Detected Hold Time Delay TIme : Tdelay High DC Output (NJU7181) LOW LOW When hold time is shorter than Tdelay , DC_Output maintains High state. (Counter RESET) –8– NJU7181 ¡ Input Sensitivity [Ta =25°C] The input sensitivity is defined as follows. VINS=20*log(R1/R2) – 21.5 [dBV] ----- (1) Note) The input sensitivity recommends the setting of -60dBV (1mVrms) or more. Note) The R2 value should be 100kΩ or more. ¡ Frequency Response The input capacitor “Ci” forms HPF with “R1”. The cut-off frequency is defined as follows. Please decide C1 value in consideration of the frequency response necessary for the signal-detecting. fc=1/(2π×Ci×R1) [Hz] ----- (2) ¡ Delay time [With RD = 220Kohm] The Recovery time is defined as follows. 8 Tdelay=1.5*10 *CR [sec] ----- (3) –9– NJU7181 „ TERMINAL DESCRIPTION Terminal SYMBOL FUNCTION 1 IN AC Input 0.3V 2 AMP_OUT Amplifier Output 0.3V 3 TRIN External Trigger Input - 5 CAP_D Delay Time Capacitor EQUIVALENT CIRCUIT VOLTAGE 0V – 10 – NJU7181 „ TERMINAL DESCRIPTION Terminal SYMBOL FUNCTION 6 RES_D Delay Time Resistor 3uA x RD 7 OUT DC Output 0 or V 8 V Supply Voltage V + EQUIVALENT CIRCUIT VOLTAGE + + – 11 – NJU7181 „ TYPICAL CHARACTERISTICS Operating Current Vs Operating Voltage Operating current Vs Temperature Cd = 10nF, Rd = 220kΩ, No Input VDD = 3V, Cd = 10nF, Rd = 220kΩ, No Input 100 100 90 80 70 60 105°C 50 25°C 40 -40°C 30 Operating Current, Icc (µA) Operating Current, Icc (µA) 90 80 70 60 50 40 20 30 10 0 0 1 2 3 4 5 6 7 20 -50 8 -25 0 Operating Voltage, + (V) 50 75 100 125 150 Temperature, (°C) Output Voltage Vs Output Current Source Output Voltage Vs Output Current Sink VDD = 3V, Ta = 25°C, Cd = 10nF, Rd = 220kΩ, Output = High VDD = 3V, Ta = 25°C, Cd = 10nF, Rd = 220kΩ, Output = High 3.5 3.5 -40°C 3.0 3.0 2.5 Output voltage, VOL (V) Output voltage, VOH (V) 25 105°C 2.0 1.5 1.0 2.5 105°C 2.0 1.5 1.0 -40°C 0.5 0.5 0.0 0.001 0.01 0.1 1 10 0.0 0.001 100 0.01 Output Source Current, (mA) 6 10 100 Output Voltage Vs Temperature Output Voltage Vs Temperature VDD = 3V, Cd = 10nF, Rd = 220kΩ, Output = High, Current Source = 1mA VDD = 3V, Cd = 10nF, Rd = 220kΩ, Output = High, Current Sink = 1mA 0.3 0.25 Output Voltage, Vout (V) OutPut Voltage, Vout (V) 1 Output Sink Current, (mA) 5 4 3 2 1 0 -50 0.1 0.2 0.15 0.1 0.05 -25 0 25 50 75 Temperature, (°C) 100 125 150 0 -50 -25 0 25 50 75 100 125 150 Temperature, (°C) – 12 – NJU7181 „ TYPICAL CHARACTERISTICS Input Sensitivity Vs Temperature Input Sensitivity Vs Supply Voltage -35 -35 -36 -36 -37 -37 -38 -38 Input Sensitivity (dBV) Input Sensitivity (dBV) VDD = 3V, Cd = 10nF, Rd = 220kΩ, R1=10kΩ, R2=100kΩ -39 -40 -41 -42 -43 105°C -39 -40 -41 25°C -42 -43 -44 -44 -45 -45 -46 -50 VDD = 3V, Ta = 25°C, Cd = 10nF, Rd = 220kΩ, R1=10kΩ, R2=100kΩ -40°C -46 -25 0 25 50 75 100 125 150 0 1 2 Temperature, (°C) 3 4 5 6 7 Supply Voltage VDD, (V) Delay Time Vs Capacitor Gain vs Frequency VDD = 3V, Ta = 25°C, Rd = 220kΩ, R1=10kΩ, R2=100kΩ VDD = 3V, Ta = 25°C, Cd = 10nF, Rd = 220kΩ, Measure @ pin 2 (AMP_OUT) 50 10000 45 1000 40dB(R1=1kΩ, R2=100kΩ) 40 35 30 10 Gain (dB) Delay Time (sec) 100 1 25 20 15 0.1 20dB(R1=10kΩ, R2=100kΩ) 10 0.01 0.001 10pF 0.0001 100pF 0.00001 5 1nF 0.001 10nF 0.01 100nF 0.1 Capacitor Value (Cd) 1uF 1 10uF 10 0 10 100 1,000 10,000 100,000 1,000,000 Frequency (Hz) [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. – 13 –