SCT63240
SILICONCONTENT
TECHNOLOGY
TECHNOLOGYHigh-Efficiency PMIC for Wireless Power Transmitter
20W High-Integration,
FEATURES
DESCRIPTION
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The SCT63240 is a highly integrated Power
Management IC allows achieving high performance,
high efficiency and cost effectiveness of wireless
power transmitter system compliant with WPC
specification to support up to 20W power transfer,
working with a wireless application specific controller
or a general MCU based transmitter controller.
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•
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VIN Input Voltage Range: 4.2V-20V
PVIN Input Voltage Range: 1V~17V
Up to 20W Power Transfer
Integrated Full-Bridge Power Stage with 13-mΩ
Rdson of Power MOSFETs
Integrated High Efficiency 5V-1A Step-down
DC/DC Converter
Optimized for EMI Reduction
Build-in 3.3V-200mA LDO
Provide 2.5V Voltage Reference
Integrated Lossless Input Current Sensor with
±2% accuracy for FOD and current
Demodulation
3.3V and 5V PWM Signal Logic Compatible
Input Under-Voltage Lockout
Over Current Protection
Over Temperature Protection
3mm*4mm QFN-19L Package
This device integrates a 4-MOSFETs full bridge
power stage，gate drivers, a 5V step-down DC/DC
converter, a 3.3V LDO, a 2.5V accurate voltage
reference and input current sensor for both system
efficiency and easy-to-use.
The proprietary gate driving scheme optimizes the
performance of EMI reduction to save the system
cost and design. The proprietary lossless current
sensing circuitry with ±2% accuracy monitors input
current of full bridge to support Foreign Object
Detection FOD and current demodulation. The buildin 5V step-down DC/DC converter and 3.3V low
dropout regulator LDO can provide power supplies
to transmitter controller and external circuitries.
APPLICATIONS
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•
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The SCT63240 features input Under-Voltage Lockout UVLO, over current, short circuit protection, and
over temperature protection.
WPC Compliant Wireless Chargers of 5W to
15W Systems for Mobiles, Tablets and Wearable
Devices
General Wireless Power Transmitters for
Consumer, Industrial and Medical Equipment
Proprietary Wireless Chargers and Transmitters
The SCT63240 is available in a compact 3mm*4mm
QFN package.
TYPICAL APPLICATION
Power Transfer Efficiency with 15W RX @ Vout=12V
C3
VIN
PVIN1
GND
PGND
PVIN2
C4
L1
BST3
PVIN
C1
90.00
C2
80.00
70.00
BST1
C8
SW3
C5
SW1
SCT63240
VDD
SW2
V3P3
BST2
EN
ISNS
PWM1
VREF
C9
C6
Efficiency(%)
VIN
60.00
50.00
40.00
30.00
20.00
PWM2
10.00
C7
AGND
0.00
0
3
6
9
12
15
Output Power(W)
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SCT63240
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
SCT63240FIA(1)
(1) For Tape & Reel, Add Suffix R (e.g. SCT63240FIAR)
PACKAGE DISCRIPTION
3240
QFN-19L
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise noted(1)
EN PWM1 PWM2 AGND ISNS VREF
DESCRIPTION
MIN
MAX
UNIT
VIN
-0.3
24
V
PVIN1, PVIN2
-0.3
20
V
SW1,SW2
-1
20
V
SW3
-1
24
V
BST1,BST2
-0.3
26
V
BST3
-0.3
30
V
BST1-SW1,BST2-SW2,BST3-SW3
VDD, V3P3, VREF, ISNS, EN,
PWM1, PWM2
Operating junction temperature TJ(2)
-0.3
6
V
-0.3
6
V
-40
125
°C
Storage temperature TSTG
-65
150
°C
(1)
CONFIDEN TIAL P relimi nary D atashe et
19
PVIN1
18
17
16
15
1
PGND
14
13
BST1
12
SW1
11
SW2
10
BST2
2
PVIN2
3
4
5
6
7
8
9
VIN
GND
SW3
BST3
VDD
V3P3
Figure 1. Top view 19-Lead QFN 3mm*4mm
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
(2)
PIN FUNCTIONS
NAME
NO.
PVIN1
1
PGND
2
PVIN2
3
VIN
4
GND
SW3
5
6
PIN FUNCTION
Input supply voltage of half-bridge FETs Q1 and Q2. Connected to the drain of high
side FET Q1. a local bypass capacitor from PVIN1 pin to PGND pin should be added.
Path from PVIN1 pin to high frequency bypass capacitor and PGND must be as short
as possible.
PGND is the common power ground of the full bridge, connected to the source
terminal of low side FETs Q2 and Q4 internally.
Input supply voltage of half-bridge FETs Q3 and Q4. Connected to the drain of high
side FET Q1. Local bypass capacitor from PVIN1 pin to PGND pin should be added.
Path from PVIN1 pin to high frequency bypass capacitor and PGND must be as short
as possible.
Input supply voltage of the Buck converter. Add a local bypass capacitor from VIN pin
to GND pin. Path from VIN pin to high frequency bypass capacitor and GND must be
as short as possible.
Power ground of the Buck converter.
Switching output of the Buck converter. Connect SW3 to an external power inductor.
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SCT63240
BST3
7
VDD
8
V3P3
9
BST2
10
SW2
SW1
11
12
BST1
13
VREF
ISNS
14
15
AGND
16
PWM2
17
PWM1
18
EN
19
Power supply bias for the high-side power MOSFET gate driver of Buck converter.
Connect a 0.1uF capacitor from BST3 pin to SW3 pin.
Output voltage of the Buck converter. Connect 22uF capacitor from this pin to GND
pin. VDD is also the input power supply for gate driver of power stage, the 3.3V LDO
and the 2.5V voltage reference.
3.3V LDO output. Connect 1uF capacitor to ground.
Power supply bias for the high-side power MOSFET gate driver of Q3 as shown in the
block diagram. Connect a 0.1uF capacitor from BST2 pin to SW2 pin.
Switching node of the half-bridge FETs Q3 and Q4.
Switching node of the half-bridge FETs Q1 and Q2.
Power supply bias for the high-side power MOSFET gate driver of Q1 as shown in the
block diagram. Connect a 0.1uF capacitor from BST1 pin to SW1 pin.
Output of the 2.5V LDO. Connect a 1uF capacitor to ground.
Current detection output. The voltage of the pin is proportional to the input current.
Analog ground of the IC
PWM logic input to the FET Q3 and Q4 as shown in the Block Diagram. Logic HIGH
turns off the low-side FET Q4, and turns on the high-side FET Q3. Logic LOW turns off
the high-side FET Q3 and turns on the low-side FET Q4. When PWM input is in the tristate mode, both Q3 and Q4 are turned off.
PWM logic input to the FET Q1 and Q2 as shown in the Block Diagram. Logic HIGH
turns off the low-side FET Q2, and turns on the high-side FET Q1. Logic LOW turns off
the high-side FET Q1 and turns on the low-side FET Q2. When PWM input is in the tristate mode, both Q1 and Q2 are turned off.
Enable pin. Pull the pin high or keep it floating to enable the IC. When the device is
enabled, Buck converter will start to work if VIN higher than UVLO threshold. After
VDD is established, power stage responds to PWM input logic then.
CONFIDEN TIAL P relimi anry D atashe et
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
VIN
DEFINITION
Input voltage range
Input voltage range
Operating junction temperature
PVIN
TJ
MIN
MAX
UNIT
4.2
1
-40
20
17
125
V
°C
MIN
MAX
UNIT
-2
+2
kV
-1
+1
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-001-2014
specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014specification, all pins(2)
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
THERMAL METRIC
Junction to ambient thermal resistance(1)
Junction to case thermal
resistance(1)
DFN-19L
42
45
UNIT
°C/W
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SCT63240
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT63240 is mounted, thermal pad size, and external environmental factors. The PCB board is a heat sink
that is soldered to the leads of the SCT63240. Changing the design or configuration of the PCB board changes the efficiency of the
heat sink and therefore the actual RθJA and RθJC.
ELECTRICAL CHARACTERISTICS
VIN=VPVIN1=VPIN2=12V, VDD=5V, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
MIN
Input supplies and UVLO
VIN
Operating input voltage
PVIN
Operating input voltage
TYP
MAX
UNIT
4.2
20
V
1
17
V
3.6
400
3.8
440
1
3
V
mV
V
mV
μA
VIN rising
ISHDN
VIN UVLO Threshold
Hysteresis
VDD UVLO Threshold
Hysteresis
Shutdown current from VIN pin
ISHDN_PVIN
Shutdown current from PVIN1,PVIN2
EN=0V, PVIN=12V
1
3
uA
ISHDN_VDD
Shutdown current from VDD
18
26
uA
IVINQ
Quiescent current from VIN pin
IPVINQ
Quiescent current from PVIN1, PVIN2
EN=0V, VDD=5.5V
EN floating, VDD=5.5V, no
switching, no loading on Buck
and LDO
EN floating, VDD=5.5V, no
switching, no loading on Buck
and LDO
EN floating, VDD=5.5V, no
switching, no loading on Buck
and LDO
VIN_UVLO
VDD_UVLO
VDD rising
EN=0V, VIN=12V
210
uA
50
uA
270
uA
ENABLE INPUTS and PWM logic
VEN_H
Enable high threshold
1.18
V
VEN_L
Enable low threshold
1.1
V
VIH
PWM1, PWM2 Logic level high
V3P3=3.3V, VDD=5V
VIL
PWM1, PWM2 Logic level low
V3P3=3.3V, VDD=5V
VTS
PWM1, PWM2 Tri-state voltage
CONFIDEN TIAL P relimi nary D atashe et
IQ
Quiescent current from VDD pin
2.65
V
1.2
0.55
V
2
V
Power Stage
RDSON_Q1
High-side MOSFETQ1 on-resistance
VBST1-VSW1=5V
13
mΩ
RDSON_Q2
Low-side MOSFETQ2 on-resistance
VDD=5V
13
mΩ
RDSON_Q3
High-side MOSFETQ3 on-resistance
VBST2-VSW2=5V
13
mΩ
RDSON_Q4
Low-side MOSFETQ4 on-resistance
VDD=5V
13
mΩ
ILIM
How-side current limit threshold
Buck converter
FSW
Switching frequency
VDD
ILIM_HS
THIC_W
Output voltage
High-side power MOSFET peak
current limit threshold
Over current protection hiccup wait
time
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12.5
A
540
600
660
4.925
5
5.075
All Rights Reserved
KHz
V
1.5
A
0.85
ms
SCT63240
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
27
ms
RDSON_H
Over current protection hiccup restart
time
High side FET on-resistance
380
mΩ
RDSON_L
Low side FET on-resistance
200
mΩ
TSS
Internal soft-start time
2
ms
3.3V LDO
V3P3
Output voltage
I3P3
Output current Capability
200
mA
ISC1
Short current
50
mA
THIC_R
Cout=1uF, VDD=5V
2.5V REFFERENCE OUTPUT
V2P5
Output voltage reference
Cout=1uF, VDD=5V
3.267
2.475
3.3
2.5
3.333
2.525
V
V
I3P3
Output current Capability
100
mA
ISC2
Short current
40
mA
Current Sense
VISNS0
Voltage with no input current
RISNS
Input current to output voltage gain
IPGND=0A ,Tj=25℃
PWM1=PWM2=0V
VISNS=VISNS0+IPGND*RISNS
VISNS1
Voltage with 0.6A input current
VISNS2
Voltage with 1A input current
0.585
0.6
0.615
V
0.98
1
1.02
V/A
IPVIN=0.6A, Tj=25℃
1.176
1.2
1.224
V
IPVIN=1A, Tj=25℃
1.568
1.6
1.632
V
CONFIDEN TIAL P relimi anry D atashe et
Protection
TSD
Thermal shutdown threshold
Hysteresis
TJ rising
155
35
°C
°C
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SCT63240
90.00
90.00
80.00
80.00
70.00
70.00
60.00
60.00
Efficiency(%)
Efficiency(%)
TYPICAL CHARACTERISTICS
50.00
40.00
30.00
50.00
40.00
30.00
20.00
20.00
10.00
10.00
Vout=5V
Vout=9V
0.00
0.00
0
1
2
3
4
0
5
2
6
8
10
Figure 2. Transfer Efficiency with 5W RX@ Vout=5V
Figure 3. Transfer Efficiency with 10W RX@ Vout=9V
90.00
100.00
80.00
95.00
70.00
90.00
60.00
50.00
40.00
CONFIDEN TIAL P relimi nary D atashe et
30.00
20.00
10.00
Vout=12V
Efficiency(%)
Efficiency(%)
4
Output Power(W)
Output Power(W)
85.00
80.00
75.00
VIN=5V
70.00
VIN=9V
65.00
VIN=12V
60.00
0.00
0
3
6
9
12
0
15
0.2
0.4
0.8
1
Iload(A)
Output Power(W)
Figure 4. Transfer Efficiency with 15W RX@ Vout=12V
Figure 5. Buck Converter Efficiency
3.5
3
3
2.7
2.4
Vsense(V)
2.5
Vout(V)
0.6
2
1.5
1
2.1
1.8
1.5
1.2
0.5
0.9
0.6
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0
Figure 6. 3.3V LDO Iout vs Vout
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
Iin(A)
Iout(A)
Figure 7. Current Sense Output Voltage vs Iin
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2
2.2
SCT63240
FUNCTIONAL BLOCK DIAGRAM
VIN
BST3
Q5
VDD
Enable
SW3
BUCK
Controller
BIAS
EN logic
VIN UVLO
Reference
EN
Q6
GND
AGND
VDD
V3P3
3.3V
LDO
VDD
UVLO
3-stage
logic
PWM1
VREF
2.5V
LDO
3-stage
logic
CONFIDEN TIAL P relimi anry D atashe et
PWM2
PVN2
PVN1
Over Current
Detection
Over Current
Detection
BST2
BST1
Q1
Q3
SW1
VDD
PWM1
Control
PWM2
Control
Q2
SW2
VD
D
Q4
Current sense
I/V
ISNS
PGND
Figure 8. Functional Block Diagram
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SCT63240
OPERATION
Overview
The SCT63240 is a highly integrated power management unit optimized for wireless power transmitter
applications. This device integrates the power functions required to a wireless power transmitter including 5V buck
converter as power supply for external transmitter controller and internal 5V power supply to increase system
efficiency, full bridge power stage to convert DC input power to AC output for driving LC resonant circuit, lossless
current sensing with ±2% accuracy, 3.3V output LDO for powering MCU and a 2.5V reference voltage.
The SCT63240 has four power input pins. VIN is connected to the power FETs of buck converter. PVIN1 and
PVIN2 are connected to the power FETs of the full bridge and conducts high currents for power transfer. VDD is
the output feedback pin of the 5V output buck converter and at the mean while as the power supply for internal
two LDOs and full bridge MOSFET's gate driver.
VIN and PVIN1, PVIN2 can be powered separately for more flexibility of system power design. The operating
voltage range for VIN is from 4.2V to 20V. An Under-voltage Lockout(UVLO) circuit monitors the voltage of VIN
pin and disable the IC operation when VIN voltage falls below the UVLO threshold of 3.2V typically. The maximum
operating voltage for PVIN is up to 17V while the minimum voltage accepted can be down to 1V. Another UVLO
circuit also supervise the VDD voltage which is the power supply for gate drivers of full bridge MOSFETs. Full
bridge will work when VDD UVLO release.
Two independent PWM signals control two separate half bridge MOSFETs with internal adaptive non-overlap
circuitry to prevent the shoot-through of MOSFETs in each bridge. PWM logics are compatible for both 3.3V and
5V IOs so the SCT63240 can accept PWM signal from the controller with using either 3.3V or 5V power supply.
The buck converter and full bridge of power MOSFETs includes proprietary designed gate driver scheme to resist
switching node ringing without sacrificing MOSFET turn-on and turn-off time, which further erases high frequency
radiation EMI noise caused by the MOSFETs hard switching. This allows the user to reduce the system cost and
design effort for EMI reduction.
CONFIDEN TIAL P relimi nary D atashe et
The SCT63240 full protection features include VIN and VDD under-voltage lockout, over current protection with
cycle-by-cycle current limit and hiccup mode, output hard short protection for buck converter and 4-MOSFETs full
bridge, current limit and current fold back at hard short for two LDOs and whole chip thermal shutdown protection.
Enable and Start up Sequence
When the VIN pin voltage rises above 3.6V and the EN pin voltage exceeds the enable threshold of 1.18V, the
buck converter and two LDOs enable at once. And the device disables when the VIN pin voltage falls below 3.2V
or when the EN pin voltage is below 1.1V. VDD ramp up after buck converter works, and also the V3V and VREF
output do. Once VDD rise up to 3.8V and V3V is higher than 3V, 4-MOSFETs full bridge allows PWM signal to
control for switching. PWM input cannot control full bridge of MOSFETs if VDD drop to 3.36V or V3V drop to 2.7V.
An internal 1.5uA pull up current source to EN pin allows the device enable when EN pin is floating to simply the
system design. If an application requires a higher system under voltage lockout threshold, two external resistors
divider(R1 and R2) in Figure 9 can be used to achieve an expected system UVLO. The UVLO rising and falling
threshold can be calculated by Equation 1 and Equation 2 respectively.
VIN
Vrise
R1
= 1.18 ∗ (1 + ) − 1.5uA ∗ R
R2
1.5uA
(1)
EN
Vfall
R1
= 1.1 ∗ (1 + ) − 5.5uA ∗ R1
R2
4uA
R1
(2)
R2
20K
+
1.21V
Figure9. System UVLO by enable divider
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SCT63240
5V Output Buck Converter
The SCT63240 fully integrates synchronous buck converter with up to 20V input voltage and 5V fixed output
voltage, which offers up to 1A output current capability. The device employs 600KHz fixed frequency peak current
mode control with the internal loop compensation network and built-in 2ms soft-start which makes this buck
converter easily to be used by minimizing the off-chip component count. Pulse Skipping Modulation(PSM) is
adopted to improve the light load efficiency.
The buck converter's output, a fixed 5V voltage, supports the power requirement on system such as transmitter
controller or mechanical fan meanwhile it is also the power supply of the SCT63240's 3.3V LDO, VREF LDO and
gate drivers of 4-MOSFETs full bridge. Connect 22uF capacitor from VDD to GND and add a 0.1uF local bypass
ceramic capacitor placed close to the IC.
The converter has proprietary designed gate driver scheme to resist switching node ringing without sacrificing
MOSFET turn-on and turn-off time, which further erases high frequency radiation EMI noise caused by the
MOSFETs hard switching.
An external 100nF ceramic bootstrap capacitor between BST3 and SW3 pin powers floating high-side power
MOSFET gate driver. The bootstrap capacitor voltage is charged from an integrated voltage regulator when highside power MOSFET is off and low-side power MOSFET is on.
Buck converter implements over current protection with cycle-by-cycle limiting high-side MOSFET peak current
and also low-side MOSFET valley current to avoid inductor current running away during unexpected overload and
hiccup protection in output hard short condition. When overload or hard short happens, the converter cannot
provide output current to satisfy loading requirement even though the inductor current has already been clamped
at over current limitation. Thus, output voltage drops below regulated voltage continuously. When output voltage
under regulation lasts for 850 us, the converter stops switching; After remaining OFF for 13.6 ms，the device will
attempt to restart from soft-start.
CONFIDEN TIAL P relimi anry D atashe et
The hiccup protection mode above greatly reduces the average short circuit current to alleviate thermal issues
and protect the regulator.
Full bridge and PWM Control
The SCT63240 integrate full bridge power stage with only 13mohm on-resistance for each power MOSFET
optimized for wireless power transmitter driving the LC resonant circuit. This full bridge is able to operate in a wide
switching frequency range from 20KHz to 400KHz for different applications which is completely compatible with
WPC's frequency requirement from 100KHz to 205KHz.
PWM1 input controls the half bridge comprised of high side MOSFET Q1 and low side MOSFET Q2, and PWM2
input controls the half bridge comprised of high side MOSFET Q3 and low side MOSFET Q4 as shown in block
diagram. The PWM1 and PWM2 independently control the SW1 and SW2 duty cycle and frequency. Logic HIGH
will turn off low side FET and turn on high side FET, and logic LOW will turn off high side FET and turn on low side
FET.
PWM1 and PWM2 also support tri-state input. When PWM input logic first enters tri-state either from logic HIGH
or logic LOW, the states of its controlled FETs stay the same. If the PWM input stays in the tri-state for more than
60ns, its controlled FETs are all turned off, and the corresponding SW output becomes high impedance. The FETs
stay off until the PWM logic reaches logic HIGH or logic LOW threshold.
An external 100nF ceramic bootstrap capacitor between BST1 and SW1 pin powers floating high-side power
MOSFET Q1's gate driver, and the other 100nF bootstrap capacitor between BST2 and SW2 pin powers for the
Q2's. When low side FET is on which means SW is low, the bootstrap capacitor is charged through internal path
by VDD power supply rail.
PWM cannot been kept as high level for more than 2ms since the voltage of bootstrap capacitor will be
discharged by internal leakage current if high side FET keeps on.
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SCT63240
Full Bridge Over Current Protection
The SCT63240 integrates cycle-by-cycle current limit and hiccup mode for over-current protection. The current of
the high side FET Q1 和 Q3 is sensed and compared to the current limit threshold during each switching cycle. If
the current exceeds the threshold, 12.5A typical, the high side FET turns off immediately in present cycle to avoid
current increasing even PWM signal is still kept in high level. The over current counter is incremented. If one high
side FET occurs over current in 5 consecutive cycles, then all 4 internal FETs are turned off regardless of the
PWM inputs. The full bridge enters hiccup mode and will attempt to restart after a time-out period of 24ms typically.
Current Sense
The SCT63240 has a proprietary lossless average current sensing circuit that measures the average input current
of full bridge with ±2% accuracy and reports a proportional voltage directly to the ISNS pin. This voltage
information on ISNS pin can be send to specialized controller or general MCU for Foreign Object Detection FOD
and current demodulation.
When the full bridge of MOSFETs does not work, no current flows to PGND. The DC bias voltage on ISNS pin is
600mV.This DC bias helps set up a suitable voltage bias for the following analog to digital converter in MCU or
amplifier for current demodulation. The average input current to voltage conversion gain on ISNS is 1V/A. The
equation 3 represent the corresponding relation for the output voltage on ISNS pin and average current to PGND
from full bridge.
VISNS = 600mV + IPGND ∗ 1V/A
(3)
3.3V LDO
The SCT63240 has an integrated low-dropout voltage regulator which powered from VDD and supply regulated
3.3V voltage on V3V pin. The output current capability is 200mA. This LDO can be used to bias the supply voltage
of MCU directly.
It is recommended to connect a decoupling ceramic capacitor of 1uF to 10uF to the V3V pin. Capacitor values
outside of the range may cause instability of the internal linear regulator.
CONFIDEN TIAL P relimi nary D atashe et
VREF Voltage Reference Output
The SCT63240 also has an integrated low-dropout voltage regulator which powered from VDD and supply
regulated 2.5V voltage on VREF pin. The accuracy of the VREF voltage is ±1% and output current capability is
100mA . This voltage regulator can be used as the supply voltage or a reference voltage to external IC and circuit.
It is recommended to connect a decoupling ceramic capacitor of 1uF to 10uF to the VREF pin. Capacitor values
outside of the range may cause instability of the internal linear regulator.
Thermal Shutdown
The SCT63240 protects the device from the damage during excessive heat and power dissipation condition.
Once the junction temperature exceeds 155C, the thermal sensing circuit stops Buck converter, two LDOs and full
bridge of 4-MOSFETs' working. When the junction temperature falls below 120C, then the device restarts.
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SCT63240
APPLICATION INFORMATION
Typical Application
VIN=4.2V~17V
4
C6
10uF
7
C8
22uF
5V
C5
0.1uF 5
C7
0.1uF
6
L1
10uH
VIN
PVIN1
GND
PGND
BST3
PVIN2
SW1
VDD
C9
1uF
C1
0.1uF
C2
22uF
3
C3
0.1uF
C4
22uF
13
R2
0ohm
C12
0.1uF
SW2
V3P3
C10
1uF
BST2
EN
18
R5
100K
ISNS
PWM1
17
PWM2
C14
12
11
10
R1
0ohm
19
PWM1
R4
SCT63240
9
3.3V
2
SW3
BST1
8
1
VREF
PWM2
AGND
C11
0.1uF
R3
C13
15
14
16
2.5V
C15
1uF
R6
100K
CONFIDEN TIAL P relimi anry D atashe et
Figure 10. Same Input to VIN and PVIN
VIN=4.2V~20V
4
C6
10uF
7
C8
22uF
L1
5V
C5
0.1uF 5
C7
0.1uF
6
10uH
PVIN1
VIN
GND
PGND
BST3
PVIN2
VDD=5V
8
VDD
C9
1uF
9
3.3V
2
C1
0.1uF
C2
22uF
3
C3
0.1uF
C4
22uF
SW3
BST1
SW1
PVIN=1V~17V
1
13
R2
0ohm
18
17
PWM2
R5
100K
C14
12
V3P3
SW2
BST2
11
10
R1
0ohm
PWM1
R4
SCT63240
C10
1uF
19
C12
0.1uF
EN
PWM1
PWM2
ISNS
VREF
AGND
C11
0.1uF
R3
C13
15
14
16
2.5V
C15
1uF
R6
100K
Figure 11. Separate Input to VIN and PVIN
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SCT63240
Application Waveforms
Figure 12. Power Up
Figure 13. Power Down
CONFIDEN TIAL P relimi nary D atashe et
Figure 14. VDD Ripple and SW3 @VIN=9V, IOUT=20mA
Figure 15. VDD Ripple and SW3 @VIN=9V, IOUT=600mA
Figure 16. Full bridge @Vin=5V, RX=5W
Figure 17. Full bridge @Vin=9V, RX=10W
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SCT63240
Layout Guideline
Proper PCB layout is a critical for SCT63240’s stable and efficient operation. The traces conducting fast switching
currents or voltages are easy to interact with stray inductance and parasitic capacitance to generate noise and
degrade performance. For better results, follow these guidelines as below:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bypass capacitors from PVIN to PGND should put next to PVIN and PGND pin as close as possible
especially for the two small capacitors.
PGND connect to bottom layer by via between capacitors.
Bypass capacitors from VIN to GND should put next to VIN and GND pin as close as possible especially for
the small capacitor.
Buck converter output capacitor's ground should connect to GND directly to minimize the power loop.
VDD pin can connect to the DC/DC's output capacitor from bottom layer, connect to the point behind the
capacitor while not connect to inductor.
Bypass capacitor for VDD place next to VDD pin.
Bypass capacitor for V3P3 place next to V3P3 pin.
Bypass capacitor for VREF place next to VREF pin.
AGND pin connect to common ground by Kelvin connection.
CONFIDEN TIAL P relimi anry D atashe et
Figure 24. PCB Layout Example
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SCT63240
PACKAGE INFORMATION
CONFIDEN TIAL P relimi nary D atashe et
FCQFN-19L (3x4) Package Outline Dimensions
Symbol
A
A1
b
b1
c
D
Nd
Ne
e
e1
E
L
L1
L2
L3
L4
Min.
0.80
0
0.20
2.90
3.90
0.35
1.95
0.45
2.25
0.075
Dimensions in Millimeters
Nom.
0.85
0.02
0.25
0.18 REF
0.203 REF
3.00
2.50 BSC
2.00 BSC
0.50 BSC
1.00 BSC
4.00
0.40
2.00
0.50
2.30
0.125
Max.
0.90
0.05
0.30
3.10
4.10
0.45
2.05
0.55
2.35
0.175
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO-220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not include mold flash.
Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
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SCT63240
TAPE AND REEL INFORMATION
Orderable Device
SCT63240FIAR
Reel Width
12
Package Type
QFN 3mmx4mm
A
Ø329±1
Pins
19
SPQ
5000
REEL DIMENSIONS
B
C
12.8±1
Ø100±1
D
Ø13.3±0.3
t
2.0±0.3
CONFIDEN TIAL P relimi anry D atashe et
TAPE DIMENSIONS
W
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
t
(mm)
P
(mm)
12+0.30
−0.10
3.40±0.10
4.40±0.10
1.14±0.10
0.25±0.02
8±0.10
E
(mm)
F
(mm)
P2
(mm)
D
(mm)
D1
(mm)
P0
(mm)
10P0
(mm)
1.75±0.10
5.50±0.05
2.00±0.05
1.500+0.10
1.500+0.25
4.00±0.10
40.0±0.20
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SCT63240
RELATED PARTS
PN
DESCRIPTION
SCT63241
COMMENTS
20W High-Integration, HighEfficiency PMIC for Wireless
Power Transmitter
Optimize for 5W and multi-coil TX
No 5V-1A Step-down DC/DC
converter compared with
SC63240. External 5V power
supply is needed.
•
•
•
•
•
•
•
•
•
•
•
•
VIN=4.2V~20V
4
C6
10uF
C5
0.1uF 5
6
7
VIN Input Voltage Range: 4.2V-20V
PVIN Input Voltage Range: 1V~17V
Up to 20W Power Transfer
Integrated High Efficiency Full-Bridge Power Stage
Optimized for EMI
Build in 3.3V-200mA LDO
Provide 2.5V Voltage Reference
Integrated Input Current sense with ±2% accuracy for
FOD and modulation
3.3V and 5V PWM Signal compatible
Input Under-Voltage Lockout
Over current protection
3mm*4mm QFN-19L Package
PVIN1
VIN
GND
PGND
GND
PVIN2
VDD=5V
8
VDD
C9
1uF
9
3.3V
2
C1
0.1uF
C2
22uF
3
C3
0.1uF
C4
22uF
NC
BST1
SW1
PVIN=1V~17V
1
13
R2
0ohm
18
17
PWM2
R5
100K
C14
12
V3P3
SW2
BST2
11
10
R1
0ohm
PWM1
R4
SCT63241
C10
1uF
19
C12
0.1uF
EN
PWM1
PWM2
ISNS
VREF
AGND
C11
0.1uF
R3
C13
15
14
16
2.5V
C15
1uF
R6
100K
Figure 25. SCT63241 Typical Application
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
16
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