WUSB3801Q-12/TR

WUSB3801 WUSB3801 USB Type-C Configuration Channel Flippable Adapter http//:www.willsemi.com Description Features The WUSB3801 is a Type-C Configuration Channel  (CC) Flippable Adapter chip with low power and high efficiency. The WUSB3801 supports USB Type-C Cable and Connector Specification Release 1.2 compatible channel  Global power saving and active mode identification of USB Type-C connector and auto  Pin or I2C controllable detection of different power roles based on chip  Support auto CC ports configuration settings. This chip is compatible with USB Type-C  Support SRC/SNK/DRP power mode Cable and Connector Specification Release 1.2 for  Support DRP with Try.SNK or Try.SRC varies of applications.  Support different current model controls and identifications (Default, 1.5A and 3.0A) The WUSB3801 supports PIN control mode and I2C  control mode through CTRL pin settings, and re-uses SDA (INOUT1)/SCL (INOUT2)/INTB (OUT3) pins to and current source with high precision  realize necessary functions in different control modes. ROLE pin is used for Source (SRC)/Sink (SNK)/Dual Role Power (DRP) mode selection of Type-C logic Accurate internal CC termination resistance High voltage EOS protection and DC 25V tolerance on CC1, CC2 and VBUSD pins  Wide single power supply range: 2.7 ~ 5.5V  QFN1616-12L packaging available working state. The global enable signal comes from (1.6x1.6x0.35mm) ENB pin with internal pull-up resistor for more Order Information feasibility. Applications  Smart-phones  Laptops  Tablets Will Semiconductor Ltd. 1 Device Package Shipping WUSB3801Q-12/TR QFN1616-12L 3000/Reel&Tape Jul, 2016 - Rev. 1.1 WUSB3801 Revision History Version Date Owner Description 0.0 2015-03 Y. Shen Initial draft 0.1 2015-03 Y. Shen Support high voltage mode and ENB as global reset 0.2 2015-04 Y. Shen Type-C 1.1 compatible 0.3 2015-08 Y. Shen 0.4 2015-10 Y. Shen Support DRP with Try.SNK or Try.SRC 0.5 2015-11 Y. Shen WUSB3801QB marking change from B* to G* 0.6 2015-11 Y. Shen Add recommend land pattern Update Ihost from 110μA to 122.5μA. Update Idevice from 28μA to 22.5μA Type-C 1.2 compatible Add general marking M Use a clear function description for ID pin Update high voltage DC from 20V to 25V Update ESD HBM from 3500V to ±4000V Update ESD CDM from 1500V to ±1500V Update USB Max tri-state input threshold from VDD-0.5 to 2.9V Update VH and VL for logic threshold voltage from 0.8*VDD to 1.05V 1.0 2016-05 X. Chen and from 0.2*VDD to 0.4V Update Vth_BUS from 0.78*VDD to 3.2V Update Ihost max from 140μA to 160μA Correct figures for threshold of Comparison and Status Relationship Update all state diagrams based on chip functions Refine all descriptions and diagrams Remove repetitious descriptions as those in USB Type-C Specification Will Semiconductor Ltd. 2 Jul, 2016 - Rev. 1.1 WUSB3801 Pin Configuration (Top View) Marking Information VDD ENB GND ID 12 11 10 9 12 11 10 9 Pin1 Dot by Marking 1 8 CC2 2 7 SDA/ INOUT1 2 7 3 4 5 6 INTB/ OUT3 SCL/ INOUT2 CTRL 8 VBUSD 1 ROLE CC1 3 5 4 6 A = Device Code * = Month Code (A~Z) VDDVDD VDD VBUS Will Semiconductor Ltd. 3 GND TX2+ TX2VBUS RX1+ ID GND TX1- VDD VBUS CC2 CC1 TX1+ PMIC CC Logic &Configuration GND SDA SCL TYPE-C CONNECTOR TX1± RX1± CC1 ADDR 2 D+ INTB 2 0 CC2 VDD D+ Redriver 2 D- 2 VBUS TX± RX± SBU2 2 TX2± RX2± SBU1 2 USB3 MUX(switch) Processor 2 VBUS RX2+ 2 1 RX2- SW D- USB2 D± RX1- 2 GND Application Block Diagram Jul, 2016 - Rev. 1.1 WUSB3801 Pin Descriptions Table 1. Pin Descriptions Pin Name Type 1 CC1 I/O 2 CC2 I/O 3 ROLE AI Tri-state input control signal for working mode selection Floating － DRP VDD － SRC GND － SNK 4 VBUSD AI VBUS detection and high voltage protection: DC 25V AC lighting surge Detect VBUS voltage Tri-state input control signal for PIN or I2C control mode selection Floating － PIN control mode VDD － I2C control mode with control address 7b’1101000 GND － I2C control mode with control address 7b’1100000 5 CTRL AI 6 INTB/ OUT3 DO 7 SDA/ INOUT1 I/O Function Type-C CC logic channel signal High voltage EOS protection Type-C CC logic channel signal High voltage EOS protection Interruption output signal for I2C control mode OUT3: Audio Acc. connection indification I2C data input/output; INOUT1 and INOUT2 combined to identify the charging current mode when a SRC/SNK is connected 8 SCL/ INOUT2 I/O I2C clock input; INOUT1 and INOUT2 combined to identify the charging current mode when a SRC/SNK is connected 9 ID AO Open drain output signal for SRC or DRP operating as SRC 10 GND G Global ground 11 ENB AI Global enable signal 12 VDD P Power Will Semiconductor Ltd. 4 Comments Start from SNK when power on Start from SNK when power on INTB output Low active H － No connection L － Audio Acc. connected INOUT2 and INOUT1 in PIN control mode indifications 2b’11 – Default 2b’10 － 1.5A 2b’00 － 3.0A 2b’01 － No connection Output Low when detects CC channel is connected as SRC or DRP operating as SRC － H － Power saving L － Active 2.7 ~ 5.5V Jul, 2016 - Rev. 1.1 WUSB3801 Block Diagram Host current ctrl GND ENB CTRL LOGIC VDD BGR Port setting SRC/SNK/DRP Cal. 80uA±20%  180uA±8%  330uA±8% CC1 Vref 2 / 4 / CC1 ROLE 5.1kΩ ±10% CTRL I/O CTRL SDA (out1) SCL (out2) INTB (out3) CC2 Vbusd I2C 2 / CC2 Register Vref VDD VBUSD CC2 CC1 COMP 5.1kΩ ±10% Vbusd ID Will Semiconductor Ltd. 5 Jul, 2016 - Rev. 1.1 WUSB3801 Absolute Maximum Ratings Table 2. Absolute Maximum Ratings Symbol Description Range Unit VBUSD VBUS pin voltage -0.3 ~ 25 V VCCx CC pin voltage -0.3 ~ 25 V VDD Power supply -0.3 ~ 6.0 V VIO Input IO voltage -0.3 ~ 3.6 V Tsto Storage temperature -65 ~ 150 ˚C VHBM ESD HBM ±4000 V VCDM ESD CDM ±1500 V The range is for stress ratings only. Stress exceeding the range specified in the Absolute Maximum Ratings may cause substantial damage to the device. Prolonged exposure to extreme conditions within the range may also affect device reliability. Recommended Operation Conditions Table 3. Recommended Operation Conditions Symbol Description Test Condition Min. Typ. Max. Unit 2.7 - 5.5 V VDD Power supply - VEN_L ENB pin Low voltage level VDD=3.6V - - 0.4 V VEN_H ENB pin High voltage level VDD=3.6V 1.15 - - V VID_L/ VINTB_L ID/INTB pin Low voltage level Open drain output VDD=3.6V ISink= -2mA - - 0.4 V VIO3_th USB tri-state input threshold VDD=3.6V 0.7 - 2.9 V Tj Junction temperature - -40 - 125 ˚C Will Semiconductor Ltd. 6 Jul, 2016 - Rev. 1.1 WUSB3801 Electronics Characteristics (VDD=3.6V, Ta=25oC, unless otherwise noted) Table 4. Electrical Characteristics Parameters Symbol Test Conditions ENB=Low CC pins unattached Active current IDD_active Min. Typ. Max. Unit - 22.5 45 μA - 122.5 160 μA ENB=Low In Attached.SRC state Default current mode Power saving IDD_disab ENB=High - - 1 μA Logic threshold VH VDD=3.6V 1.05 - - V voltage VL VDD=3.6V - - 0.4 V IH 3.0A mode setting 304 330 356 μA IM 1.5A mode setting 166 180 194 μA ID Default mode setting 64 80 96 μA Rd - 4.6 5.1 5.6 kΩ Vth_H 3.0A mode setting 1.16 1.23 1.31 V Vth_M 1.5A mode setting 0.61 0.66 0.70 V Vth_D Default mode setting 0.15 0.2 0.25 V Vth_BUS VDD=3.6V 2.9 3.2 3.5 V current Current source Resistor load Comparator threshold voltage VBUS detection threshold voltage Will Semiconductor Ltd. 7 Jul, 2016 - Rev. 1.1 WUSB3801 Function Descriptions General Description The WUSB3801 is a Type-C Configuration Channel Flippable Adapter chip with low power and high efficiency. The WUSB3801 supports channel identification of USB Type-C connector and auto detection of different power roles based on chip settings. It has high voltage protection circuits on CC1/CC2/VBUSD pins and supports both DC up to 25V and AC lighting surge. This chip is compatible with USB Type-C Cable and Connector Specification Release 1.2 for varies of applications. Logic Control Block The logic control block receives the outer control signals, detects CC connection status using voltage level comparisons of CC pins for different connection topologies and settings, and outputs the detected information of communication path. Comparison results showing CC signals voltage range are sent to logic control block for state machine and then the connection status of related working mode will be identified. When connection status changes, the logic control block will update outputs of pins and registers. The figures as below show the boundaries of status. Threshold of Comparison and Status Relationship VDD 2.7~5.5V VDD No Connection 2.7~5.5V Not Valid 2.6V 2.04V Below 2.6V Connection for 330µA 3.0A 1.23V 1.6V 1.5A Below 1.6V Connection for 80/180µA 0.66V Default 0.2V No Connection 0V 0V Source Will Semiconductor Ltd. Sink 8 Jul, 2016 - Rev. 1.1 WUSB3801 Work Mode Feature According to CC connection status and detection results, the chip can work as SRC (Host), SNK (Device) or DRP mode which are shown in the following figures. SRC State Diagram Directed from any state AudioAccessory AudioAcc Removed Unattached.SRC DebugAcc Removed Connection Detected Connection Removed AudioAcc Detected for tCCDebounce DebugAcc Removed DebugAcc Detected for tCCDebounce AttachWait.SRC DebugAccessory Sink Detected for tCCDebounce Sink Removed Attached.SRC SNK with Accessory Support State Diagram Directed from any state Accessory Toggle Dead Battery Unattached.SNK VBUS Removed Connection Detected Connection Removed Unattached. Accessory AudioAcc or DebugrAcc Detected Accessory Toggle Accessory Removed AudioAcc Removed AudioAccessory AttachWait. Accessory AudioAcc Detected for tCCDebounce DebugAcc Detected for tCCDebounce AttachWait.SNK DebugAcc Removed Source Detected for tCCDebounce and VBUS Detected DebugAccessory Attached.SNK Will Semiconductor Ltd. 9 Jul, 2016 - Rev. 1.1 WUSB3801 DRP with Accessory and Try.SRC Support State Diagram DebugAcc Removed Directed from any state DebugAccessory AudioAcc Removed DRP Toggle Unattached.SRC Dead Battery DRP Toggle Connection Detected AudioAccessory Unattached.SNK Connection Detected AttachWait.SNK Connection Removed Connection Removed for tPDDebounce Source Detected for tCCDebounce and VBUS Detected VBUS Removed Attached.SNK AttachWait.SRC DebugAcc Detected for tCCDebounce Sink Detected for tCCDebounce Sink Detected for tPDDebounce Try.SRC Source Detected for tCCDebounce and VBUS Detected AudioAcc Detected for tCCDebounce Source not Detected for tPDDebounce Sink Removed tDRPTry and no Sink Detected Attached.SRC Sink Removed TryWait.SNK Source Detected for tCCDebounce and VBUS Detected DRP with Accessory and Try.SNK Support State Diagram DebugAcc Removed DebugAccessory Directed from any state Directed from any state AudioAcc Removed DRP Toggle Unattached.SRC Dead Battery DRP Toggle Connection Detected AudioAccessory Unattached.SNK Connection Detected Try.SNK AttachWait.SNK VBUS Removed Source Detected for tCCDebounce and VBUS Detected Attached.SNK Will Semiconductor Ltd. Connection Removed Connection Removed for tPDDebounce Source Detected for tPDDebounce and VBUS Detected tDRPTry and Sink not Detected AudioAcc Detected for tCCDebounce AttachWait.SRC Sink Detected for tCCDebounce Source not Detected for tPDDebounce after tDRPTry TryWait.SRC Sink Removed DebugAcc Detected for tCCDebounce Sink Detected for tCCDebounce Attached.SRC Sink Detected for tPDDebounce 10 Jul, 2016 - Rev. 1.1 WUSB3801 Communication Interfaces I2C Interface The chip can take communications over I2C bus which supports up to 400 kHz clock when CTRL pin is not floating (connected to VDD or GND). Two setting values would result in different I2C device addresses as shown in Table 7. Table 7. Address Table Controlled by CTRL Pin Pin Setting Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Address 1 VDD 1 1 0 1 0 0 0 Address 2 GND 1 1 0 0 0 0 0 I2C Bus Timing I2C BUS Timing Diagram Will Semiconductor Ltd. 11 Jul, 2016 - Rev. 1.1 WUSB3801 Electrical Characteristics of I2C Table 8. Electrical Characteristics of I2C Symbol fSCL Test Parameter SCL clock frequency 2 Min. Typ. Max. Unit - - - 400 kHz 3.6 V Conditions VDD_I2C Power supply range for I C - 1.65 - VIH Logic high level voltage (Note 1) - 1.2 - VIL Logic low level voltage (Note 1) - - - 0.4 V Isink Sink current at low level (open drain) (Note 1) - - 1.6 - mA - 1.3 - - μs - 0.6 - - μs tBUF tHD_STA Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated V tLOW LOW period of the SCL clock - 1.3 - - μs tHIGH HIGH period of the SCL clock - 0.6 - - μs tSU_STA Set-up time for a repeated START condition - 0.6 - - μs - 0 - - μs tHD_DAT Data hold time between SDA and SCL falling edge tSU_DAT Data set-up time - 100 - - ns tr Rise time for SDA and SCL signals (Note 2) - - - 300 ns tf Fall time for SDA and SCL signals (Note 2) - - - 300 ns tSU_STO Set-up time for STOP condition - 0.6 - - μs Tdeg Width of deglitch at input termination SCL - 200 - ns SDA - 250 - ns Cb Capacitive load for each bus line - - - 400 pF Note 1: Guaranteed by design Note 2: tr and tf are timing from 0.3*VDD to 0.7*VDD Will Semiconductor Ltd. 12 Jul, 2016 - Rev. 1.1 WUSB3801 I2C Register Map Table 9. I2C Register Map Addr. Register Type 01H Device ID R 02H Control R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Version ID: 00010 Try Current Support SNK/SRC Mode (SRC) 1: No Bit0 Vendor ID: 110 Acc. 0: Yes Bit1 Work Mode 01: Try.SNK 00: Default 00: SNK 10: Try.SRC 01: 1.5A 01: SRC 00/11: No Try 10: 3.0A 10: DRP Interruption Control 1 Detach/Attach 03H Interruption R/ Reserved Clear 00：No Interruption 01：Attached 10：Detached VBUS Detection as SNK 04H CC Status R 0: VBUS not detected 1: VBUS detected Charging Current Plugged Port Status Detection as Plug Orientation SNK 00: Standby 01: Default 10: 1.5A 11: 3.0A 000: Standby 00: Standby 001: SNK 01: CC1 connected 010: SRC 10: CC2 connected 011: Audio Accessory 11: CC1 and CC2 100: Debug Accessory connected Function Description Registers are used for read/write settings in I2C control mode. Status of USB Type-C connector is detected and updated in register map automatically by internal state machine. When any update occurs in register map after the last I2C reads, the chip would keep the interruption pin (INTB) at low level. Otherwise, the chip would cancel the interruption signal (INTB=1). Will Semiconductor Ltd. 13 Jul, 2016 - Rev. 1.1 WUSB3801 Typical Application Schematics DRP Mode for I2C Control with USB2.0 DRP Mode for I2C Control with USB3.0/3.1 Will Semiconductor Ltd. 14 Jul, 2016 - Rev. 1.1 WUSB3801 Package Outline Dimensions QFN1616-12L Top View Bottom View Symbol Side View Dimensions in millimeter MIN. NOM. MAX. A 0.30 0.35 0.40 A1 0.00 0.02 0.05 A3 0.127 Ref. b 0.15 0.20 0.25 D 1.55 1.60 1.65 E 1.55 1.60 1.65 e 0.40 BSC. L 0.25 0.30 0.35 L1 0.45 0.50 0.55 Will Semiconductor Ltd. 15 Jul, 2016 - Rev. 1.1 WUSB3801 Recommend Land Pattern All dimensions are in millimeters Will Semiconductor Ltd. 16 Jul, 2016 - Rev. 1.1