PMS152
8bit OTP Type SuLED IO Controller
Datasheet
Version 0.02 – Jan. 24, 2018
Copyright 2018 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688
www.padauk.com.tw
PMS152
8bit OTP Type SuLED IO Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
PMS152 is NOT designed for AC RC step-down powered, high power ripple or high EFT
requirement application. Please do NOT apply PMS152 to those application products.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Table of content
1. Features ................................................................................................................................. 8
1.1.
Special Features .....................................................................................................................8
1.2.
System Features .....................................................................................................................8
1.3.
CPU Features .........................................................................................................................8
1.4.
Package Information ...............................................................................................................8
2. General Description and Block Diagram ............................................................................ 9
3. Pin Definition and Functional Description ....................................................................... 10
4. Device Characteristics ....................................................................................................... 16
4.1.
AC/DC Device Characteristics ..............................................................................................16
4.2.
Absolute Maximum Ratings...................................................................................................17
4.3.
Typical ILRC frequency vs. VDD ...........................................................................................18
4.4.
Typical IHRC frequency deviation vs. VDD ...........................................................................18
4.5.
Typical ILRC Frequency vs. Temperature .............................................................................19
4.6.
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz) .......................................... 19
4.7.
Typical operating current vs. VDD @ system clock = ILRC/n ................................................ 20
4.8.
Typical operating current vs. VDD @ system clock = IHRC/n ...............................................20
4.9.
Typical operating current vs. VDD @ system clock = 4MHz EOSC / n (reserved) ................. 21
4.10.
Typical operating current vs. VDD @ system clock = 32KHz EOSC / n (reserved)................ 21
4.11.
Typical operating current vs. VDD @ system clock = 1MHz EOSC / n (reserved) ................. 22
4.12.
Typical IO driving current (IOH) and sink current (IOL) .............................................................22
4.13.
Typical IO input high/low threshold voltage (VIH/VIL) ..............................................................23
4.14.
Typical resistance of IO pull high device ...............................................................................24
4.15.
Typical power down current (IPD) and power save current (IPS) .............................................. 24
5. Functional Description ....................................................................................................... 26
5.1.
Program Memory - OTP ........................................................................................................26
5.2.
Boot Procedure .....................................................................................................................26
5.2.1. Timing charts for reset conditions.................................................................................27
5.3.
Data Memory - SRAM ...........................................................................................................28
5.4.
Oscillator and Clock ..............................................................................................................28
5.4.1. Internal High RC oscillator and Internal Low RC oscillator ......................................... 28
5.4.2. Chip calibration ..........................................................................................................29
5.4.3. IHRC Frequency Calibration and System Clock ........................................................29
©Copyright 2018, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
5.4.4. External Crystal Oscillator .........................................................................................30
5.4.5. System Clock and LVR level .....................................................................................32
5.4.6. System Clock Switching ............................................................................................33
5.5.
Comparator ...........................................................................................................................34
5.5.1
Internal reference voltage (Vinternal R) ...........................................................................35
5.5.2
Using the comparator ................................................................................................37
5.5.3
Using the comparator and band-gap 1.20V ...............................................................38
5.6
16-bit Timer (Timer16) ..........................................................................................................39
5.7
8-bit Timer (Timer2) with PWM generation ............................................................................41
5.8
5.7.1
Using the Timer2 to generate periodical waveform ....................................................42
5.7.2
Using the Timer2 to generate 8-bit PWM waveform...................................................44
5.7.3
Using the Timer2 to generate 6-bit PWM waveform...................................................45
11-bit PWM Generators ........................................................................................................46
5.8.1
PWM Waveform ........................................................................................................46
5.8.2
Hardware Diagram ....................................................................................................47
5.8.3
Equations for 11-bit PWM Generator .........................................................................48
5.9
WatchDog Timer ...................................................................................................................49
5.10
Interrupt ................................................................................................................................50
5.11
Power-Save and Power-Down ..............................................................................................52
5.11.1 Power-Save mode (“stopexe”) ...................................................................................52
5.11.2 Power-Down mode (“stopsys”) ..................................................................................53
5.11.3 Wake-up ....................................................................................................................53
5.12
IO Pins ..................................................................................................................................55
5.13
Reset and LVR......................................................................................................................56
5.13.1 Reset .........................................................................................................................56
5.13.2 LVR reset ..................................................................................................................56
6. IO Registers ........................................................................................................................ 57
6.1.
ACC Status Flag Register (flag), IO address = 0x00 .............................................................57
6.2.
Stack Pointer Register (sp), IO address = 0x02 ....................................................................57
6.3.
Clock Mode Register (clkmd), IO address = 0x03 .................................................................57
6.4.
Interrupt Enable Register (inten), IO address = 0x04 ............................................................58
6.5.
Interrupt Request Register (intrq), IO address = 0x05 ...........................................................58
6.6.
Timer16 mode Register (t16m), IO address = 0x06...............................................................59
6.7.
MISC Register (misc), IO address = 0x08 .............................................................................59
6.8.
External Oscillator setting Register (eoscr), IO address = 0x0a............................................. 60
6.9.
Interrupt Edge Select Register (integs), IO address = 0x0c ...................................................60
6.10.
Port A Digital Input Enable Register (padier), IO address = 0x0d .......................................... 60
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
6.11.
Port B Digital Input Enable Register (pbdier), IO address = 0x0e .......................................... 61
6.12.
Port A Data Register (pa), IO address = 0x10 .......................................................................61
6.13.
Port A Control Register (pac), IO address = 0x11 .................................................................61
6.14.
Port A Pull-High Register (paph), IO address = 0x12 ............................................................61
6.15.
Port B Data Register (pb), IO address = 0x14 .......................................................................61
6.16.
Port B Control Register (pbc), IO address = 0x15 .................................................................61
6.17.
Port B Pull-High Register (pbph), IO address = 0x16 ............................................................61
6.18.
Comparator Control Register (gpcc), IO address = 0x18 .......................................................62
6.19.
Comparator Selection Register (gpcs), IO address = 0x19 ....................................................62
6.20.
Timer2 Control Register (tm2c), IO address = 0x1c ..............................................................63
6.21.
Timer2 Scalar Register (tm2s), IO address = 0x17................................................................63
6.22.
Timer2 Counter Register (tm2ct), IO address = 0x1d ............................................................64
6.23.
Timer2 Bound Register (tm2b), IO address = 0x09 ...............................................................64
6.24.
PWMG0 control Register (pwmg0c), IO address = 0x20 .......................................................64
6.25.
PWMG Clock Register (pwmgclk), IO address = 0x21 ..........................................................65
6.26.
PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22 ..................................... 65
6.27.
PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23 ....................................... 65
6.28.
PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x24 .................... 65
6.29.
PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x25 ...................... 65
6.30.
PWMG1 control Register (pwmg1c), IO address = 0x26 .......................................................66
6.31.
PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28 ..................................... 66
6.32.
PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29 ....................................... 66
6.33.
PWMG2 control Register (pwmg2c), IO address = 0x2C.......................................................67
6.34.
PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E ..................................... 67
6.35.
PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F ....................................... 67
7. Instructions ......................................................................................................................... 68
7.1.
Data Transfer Instructions .....................................................................................................69
7.2.
Arithmetic Operation Instructions ..........................................................................................72
7.3.
Shift Operation Instructions ...................................................................................................74
7.4.
Logic Operation Instructions..................................................................................................75
7.5.
Bit Operation Instructions ......................................................................................................78
7.6.
Conditional Operation Instructions ........................................................................................79
7.7.
System control Instructions ...................................................................................................80
7.8.
Summary of Instructions Execution Cycle .............................................................................82
7.9.
Summary of affected flags by Instructions .............................................................................82
8. Code Options ...................................................................................................................... 83
9. Special Notes ...................................................................................................................... 84
©Copyright 2018, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
9.1.
Warning ................................................................................................................................84
9.2.
Using IC ................................................................................................................................84
9.2.1. IO pin usage and setting ............................................................................................84
9.2.2. Interrupt .....................................................................................................................85
9.2.3. System clock switching ..............................................................................................85
9.2.4. Watchdog ..................................................................................................................85
9.2.5. TIMER time out .........................................................................................................85
9.2.6. IHRC .........................................................................................................................86
9.2.7. LVR ...........................................................................................................................86
9.2.8. Instructions ................................................................................................................86
9.2.9. BIT definition .............................................................................................................86
9.2.10. Programming Writing .................................................................................................86
9.3.
Using ICE..............................................................................................................................87
©Copyright 2018, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
Revision History:
Revision
Date
0.01
2017/07/21
Description
st
1 version
1. Amend the address and phone number of PADAUK Technology Co.,Ltd.
0.02
2018/01/24
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Amend Section 1.3 CPU Features
Amend Section 4.1 AC/DC Device Characteristics
Amend Section 4.3 Typical ILRC frequency vs. VDD
Amend Section 4.4 Typical IHRC frequency deviation vs. VDD
Amend Section 4.5 Typical ILRC Frequency vs. Temperature
Amend Section 4.6 Typical IHRC Frequency vs. Temperature
Amend Section 4.7 Typical operating current vs. VDD @ system clock = ILRC/n
Amend Section 4.8 Typical operating current vs. VDD @ system clock = IHRC/n
Amend Section 4.9 Typical operating current vs. VDD @ system clock = 4MHz EOSC / n
Amend Section 4.10 Typical operating current vs. VDD @ system clock = 32KHz EOSC / n
Amend Section 4.11 Typical operating current vs. VDD @ system clock = 1MHz EOSC / n
Amend Section 4.13 Typical IO input high/low threshold voltage (VIH/VIL)
Amend Section 4.15 Typical power down current and power save current
Delete Section 4.16 Timing charts for boot up conditions
Amend Section 5.1. Program Memory – OTP
Add Section 5.2.1 Timing charts for reset conditions
Amend Table 2: Three oscillation circuits
Amend Section 5.4.3. IHRC Frequency Calibration and System Clock
Amend Section 5.4.4. External Crystal Oscillator
Amend Section 5.4.5. System Clock and LVR level
Amend Fig.3: Options of System Clock
Amend Section 5.5.2. Using the comparator
Amend Section 5.5.3 Using the comparator and band-gap 1.20V
Amend Section 5.10 Interrupt
Amend Section 5.11.1 Power-Save mode
Amend Section 5.11.2 Power-Down mode
Amend Section 5.11.3 Wake-up
Amend Section 6.3. Clock Mode Register
Amend Section 6.7 MISC Register
Amend Section 6.10. Port A Digital Input Enable Register
Amend Section 6.11. Port B Digital Input Enable Register
Delete Section 6.13. MISC2 Register
Amend Section 6.14. Port A Pull-High Register
Amend Section 6.19. Comparator Selection Register.
Amend Section 6.20. Timer2 Control Register
Amend Section 6.21. Timer2 Scalar Register
Delete the Symbol “pc0” in Chapter 7
Amend Chapter 8 Code Options
Amend Section 9.2.1. IO pin usage and setting
Amend Section 9.2.7 LVR
Amend Section 9.2.9 BIT definition
Amend Section 9.2.10. Programming Writing
Amend Section 9.3. Using ICE
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
1. Features
1.1. Special Features
General purpose series
Please don’t apply to AC RC step-down powered, high power ripple or high EFT requirement application
Operating temperature range: -20°C ~ 70°C
1.2. System Features
1.25KW OTP program memory
80 Bytes data RAM
One hardware 16-bit timer
One hardware 8-bit timers with 6/7/8-bit PWM generation
One set triple 11bit SuLED (Super LED) PWM generators and timers
One hardware comparator
14 IO pins with optional pull-high resistor
Three different IO Driving capability group to meet different application requirements
(1) PB3, PB5, PB7 Drive/ Sink Current= 5mA/30mA
(2) Other IOs (except PA5) Drive/ Sink Current = 5mA/10mA
(3) PA5 Sink Current = 10mA
Every IO pin can be configured to enable wake-up function
1
Clock sources: IHRC, ILRC & EOSC(XTAL mode, Reserved )
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast
Eight levels of LVR: 4.5V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V and 1.8V
Two selectable external interrupt pins: PA0/PB5, PB0/PA4
Band-gap circuit to provide 1.20V reference voltage
1.3. CPU Features
One processing unit operating mode
86 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer
of Indirect addressing mode
IO space and memory space are independent
1.4. Package Information
PMS152-S16: SOP16 (150mil)
PMS152-1J16A: QFN3*3-16pin (0.5mm pitch)
PMS152-S14: SOP14 (150mil)
PMS152-M10: MSOP10 (118mil)
PMS152-S08: SOP8 (150mil)
PMS152-U06: SOT23-6 (60mil)
1
Please contact our sales representative.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
2. General Description and Block Diagram
The PMS152 family is an IO-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs RISC
architecture and all the instructions are executed in one cycle except that some instructions are two cycles that
handle indirect memory access.
1.25KW bits OTP program memory and 80 bytes data SRAM are inside, one hardware comparator is built inside
the chip to compare signal between two pin or with either internal reference voltage VinternalR or internal band-gap
reference voltage. PMS152 also provides three hardware timers: one 16-bit timer, one 8-bit timer with PWM
generation, and one new triple 11-bit timer with SuLED PWM generation (PWMG0, PWMG1 & PWMG2) are
included.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
3. Pin Definition and Functional Description
PMS152-S16 (SOP16-150mil)
PMS152-1J16A (QFN3*3-16P-0.5pitch)
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
PMS152-S14 (SOP14-150mil)
PMS152-M10 (MSOP10-118mil)
PMS152-S08 (SOP8-150mil)
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
PMS152-U06 (SOT23-6 60mil)
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
PA7 /
X1
IO
ST /
CMOS
(1) Bit 7 of port A. It can be configured as input or output with pull-up resistor.
(2) X1 is Crystal XIN when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
PA6 /
X2
IO
ST /
CMOS
(1) Bit 6 of port A. It can be configured as input or output with pull-up resistor.
(2) X2 is Crystal XOUT when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
PA5 /
PRSTB /
PG2PWM
(1) Bit 5 of port A. It can be configured as input or open-drain output pin.
IO (OD)
ST /
CMOS
(2) Hardware reset.
(3) Output of 11-bit PWM generator PWMG2.
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode.
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input, two-state output with pull-up
resistor by software independently
PA4 /
CIN+ /
CIN1- /
INT1A /
PG1PWM
(2) Plus input source of comparator.
IO
ST /
CMOS /
Analog
(3) Minus input source 1 of comparator.
(4) External interrupt line 1A. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
(5) Output of 11-bit PWM generator PWMG1.
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PA3 /
IO
CIN0- /
ST /
(2) Minus input source 0 of comparator.
TM2PWM /
CMOS /
(4) Output of 11-bit PWM generator PWMG02
PG2PWM
Analog
When this pin is configured as analog input, please use bit 3 of register padier to
(3) PWM output from Timer2
disable the digital input to prevent current leakage. The bit 3 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PA0 /
CO /
PG0PWM /
INT0
IO
ST /
CMOS
(2) Output of comparator.
(3) Output of 11-bit PWM generator PWMG0.
(4) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
The bit 0 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input, two-state output with pull-up
PB7 /
CIN5- /
PG1PWM
IO
ST /
CMOS /
Analog
resistor independently by software
(2) Minus input source 5 of comparator.
(3) Output of 11-bit PWM generator PWMG1.
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent current leakage. The bit 7 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 6 of port B. It can be configured as digital input, two-state output with pull-up
PB6 /
IO
CIN4- /
ST /
PG1PWM
CMOS /
Analog
resistor independently by software
(2) Minus input source 4 of comparator.
(3) Output of 11-bit PWM generator PWMG1.
When this pin is configured as analog input, please use bit 6 of register pbdier to
disable the digital input to prevent current leakage. The bit 6 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 5 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PB5 /
IO
PG0PWM /
ST /
(2) Output of 11-bit PWM generator PWMG0.
(3) External interrupt line 0A. It can be used as an external interrupt line 0. Both
INT0A
CMOS
rising edge and falling edge are accepted to request interrupt service and
configurable by register setting.
The bit 5 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 4 of port B. It can be configured as digital input, two-state output with pull-up
PB4 /
IO
TM2PWM /
ST /
PG0PWM
CMOS
resistor independently by software
(2) PWM output from Timer2
(3) Output of 11-bit PWM generator PWMG0.
The bit 4 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
PB3 /
PG2PWM
IO
ST /
CMOS
(1) Bit 3 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
(2) Output of 11-bit PWM generator PWMG2
The bit 3 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as digital input, two-state output with pull-up
PB2 /
IO
TM2PWM /
ST /
PG2PWM
CMOS
resistor independently by software
(2) PWM output from Timer2
(3) Output of 11-bit PWM generator PWMG2
The bit 2 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
IO
PB1
ST /
CMOS
Bit 1 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software.
The bit 1 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as digital input, and two-state output mode
PB0 /
INT1
with pull-up resistor independently by software.
IO
(2) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
ST /
edge and falling edge are accepted to request interrupt service and configurable
CMOS
by register setting.
If bit 0 of pbdier register is set to “0” to disable digital input, wake-up from
power-down by toggling this pin is also disabled.
VDD
VDD
Positive power
GND
GND
Ground
Notes: IO: Input/Output;
ST: Schmitt Trigger input;
OD: Open Drain;
Analog: Analog input pin
CMOS: CMOS voltage level
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
4. Device Characteristics
4.1. AC/DC Device Characteristics
o
o
All data are acquired under the conditions of Ta= -20 C ~ 75 C, VDD=5.0V, fSYS =2MHz unless noted.
Symbol
VDD
LVR%
fSYS
VPOR
IOP
IPD
IPS
Description
Operating Voltage
Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
IHRC/4
IHRC/8
ILRC
Min
Typ
Max
Unit
1.8*
-5
5.0
5.5
5
V
%
8M
4M
2M
Hz
0
0
0
55K
Power On Reset Voltage
Operating Current
Power Down Current
(by stopsys command)
Power Save Current
(by stopexe command)
VIL
Input low voltage for IO lines
VIH
Input high voltage for IO lines
1.8*
1
15
1
0.6
V
mA
uA
uA
uA
5
uA
0
0.1 VDD
0
0.2 VDD
0.8 VDD
VDD
0.7 VDD
VDD
V
V
o
Conditions (Ta=25 C)
* Subject to LVR tolerance
VDD ≧ 3.5V
VDD ≧ 2.5V
VDD ≧ 1.8V
VDD = 3.0V
* Subject to LVR tolerance
fSYS=IHRC/16=1MIPS@5.0V
fSYS=ILRC=55KHz@3.3V
fSYS= 0Hz, VDD =5.0V
fSYS= 0Hz, VDD =3.3V
VDD =5.0V; fSYS= ILRC
Only ILRC module is enabled.
PA5
Others IO
PA5
Others IO
IO lines sink current
IOL
PA7, PA6, PA5, PA4, PA3, PA0
10
PB6, PB4, PB2, PB1, PB0
10
PB7, PB5, PB3
30
mA
VDD=5.0V, VOL=0.5V
mA
VDD=5.0V, VOH=4.5V
IO lines drive current
IOH
VIN
IINJ (PIN)
PA5
0
PA7, PA6, PA4, PA3, PA0
-5
PB7, PB6, PB5, PB4, PB3
-5
PB2, PB1, PB0
-5
Input voltage
Injected current on pin
RPH
Pull-high Resistance
VBG
Band-gap Reference Voltage
fIHRC
tINT
-0.3
Frequency of IHRC after
VDD +0.3
V
1
mA
VDD +0.3≧VIN≧ -0.3
KΩ
VDD =5.0V
100
200
1.145*
1.20*
1.255*
15.76*
16*
16.24*
15.20*
16*
16.80*
13.60*
16*
18.40*
V
©Copyright 2018, PADAUK Technology Co. Ltd
30
Page 16 of 87
VDD =2.2V ~ 5.5V
o
o
-20 C CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
//
system clock is ILRC
CLKMD
=
0x34；
//
switch to IHRC/2, ILRC CAN NOT be disabled here
CLKMD.2
=
0；
//
ILRC CAN be disabled at this time
…
Case 2: Switching system clock from ILRC to EOSC
…
//
system clock is ILRC
CLKMD
=
0xA6；
//
switch to IHRC, ILRC CAN NOT be disabled here
CLKMD.2
=
0；
//
ILRC CAN be disabled at this time
…
Case 3: Switching system clock from IHRC/2 to ILRC
//
system clock is IHRC/2
CLKMD
…
=
0xF4；
//
switch to ILRC, IHRC CAN NOT be disabled here
CLKMD.4
=
0；
//
IHRC CAN be disabled at this time
…
Case 4: Switching system clock from IHRC/2 to EOSC
…
//
system clock is IHRC/2
CLKMD
=
0XB0；
//
switch to EOSC, IHRC CAN NOT be disabled here
CLKMD.4
=
0；
//
IHRC CAN be disabled at this time
…
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
CLKMD
=
0X14；
//
system clock is IHRC/2, ILRC is enabled here
//
switch to IHRC/4
…
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
CLKMD
=
0x30；
//
system clock is ILRC
//
CAN NOT switch clock from ILRC to IHRC/2 and
turn off ILRC oscillator at the same time
©Copyright 2018, PADAUK Technology Co. Ltd
Page 33 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.5. Comparator
One hardware comparator is built inside the PMS152; Fig.4 shows its hardware diagram. It can compare
signals between two pins or with either internal reference voltage Vinternal
R
or internal band-gap reference
voltage. The two signals to be compared, one is the plus input and the other one is the minus input. For the
minus input of comparator can be PA3, PA4, Internal band-gap 1.20 volt, PB6, PB7 or Vinternal R selected by bit
[3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc register.
The output result can be enabled to output to PA0 directly, or sampled by Time2 clock (TM2_CLK) which
comes from Timer2 module. The output can be also inversed the polarity by bit 4 of gpcc register, the
comparator output can be used to request interrupt service.
Fig.4: Hardware diagram of comparator
©Copyright 2018, PADAUK Technology Co. Ltd
Page 34 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.5.1
Internal reference voltage (Vinternal R)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig.5 to Fig.8 shows four conditions to have different reference
voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from
(1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.5=1
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
V internal R =
4
(n+1)
* VDD +
32
* VDD, n = gpcs[3:0] in decimal
Fig.5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
gpcs.5=1
8R
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
V internal R =
(n+1)
24
* VDD, n = gpcs[3:0] in decimal
Fig.6: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
©Copyright 2018, PADAUK Technology Co. Ltd
Page 35 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Case 3 : gpcs.5= 1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.5=1
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
V internal R =
5
(n+1)
* VDD +
40
* VDD, n = gpcs[3:0] in decimal
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
VDD
8R
16 stages
8R
gpcs.5=1
8R
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
V internal R =
(n+1)
32
* VDD, n = gpcs[3:0] in decimal
Fig.8: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
©Copyright 2018, PADAUK Technology Co. Ltd
Page 36 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.5.2
Using the comparator
Case I:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input. Vinternal R is
configured as the above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R =
(1/4)*VDD + [(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
gpcs
= 0b1_0_00_1001;
// Vinternal R = VDD*(18/32)
gpcc
= 0b1_0_0_0_000_0;
// enable comp, - input: PA3, + input: Vinternal R
padier = 0bxxxx_0_xxx;
// disable PA3 digital input to prevent leakage current
or
$ GPCS
VDD*18/32;
$ GPCC
Enable, N_PA3, P_R;
// - input: N_xx，+ input: P_R(Vinternal R)
PADIER = 0bxxxx_0_xxx;
Case 2:
Choosing Vinternal R as minus input with (14/32)*VDD voltage level and PA4 as plus input, the comparator
result will be inversed and then output to PA0. Vinternal R is configured as the above Figure “gpcs[5:4] =
2b’10” and gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD + [(13+1)/40]*VDD = [(13+9)/40]*VDD =
(22/40)*VDD.
gpcs
= 0b1_0_10_1101;
// output to PA0, Vinternal R = VDD*(22/40)
gpcc
= 0b1_0_0_1_011_1;
// Inverse output, - input: Vinternal R, + input: PA4
padier = 0bxxx_0_xxxx;
// disable PA4 digital input to prevent leakage current
or
$ GPCS
Output, VDD*22/40;
$ GPCC
Enable, Inverse, N_R, P_PA4;
// - input: N_R(Vinternal R)，+ input: P_xx
PADIER = 0bxxx_0_xxxx;
Note: When selecting output to PA0 output, GPCS will affect the PA3 output function in ICE. Though the IC
is fine, be careful to avoid this error during emulation.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 37 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.5.3
Using the comparator and band-gap 1.20V
The internal band-gap module can provide 1.20 volt, it can measure the external supply voltage level. The
band-gap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input, the
supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage level of
Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest to
band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD= [ 32 / (N+1) ] * 1.20 volt ;
Case 1:
$ GPCS VDD*12/40;
//
$ GPCC Enable, BANDGAP, P_R;
//
4.0V * 12/40 = 1.2V
- input: BANDGAP, + input: P_R(Vinternal R)
….
if
(GPC_Out)
{
// or GPCC.6
//
when VDD﹥4V
//
when VDD﹤4V
}
else
{
}
©Copyright 2018, PADAUK Technology Co. Ltd
Page 38 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.6 16-bit Timer (Timer16)
A 16-bit hardware timer (Timer16) is implemented in the PMS152, the clock sources of Timer16 may come
from system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator (IHRC),
internal low RC oscillator (ILRC), PA4 and PA0, a multiplex is used to select clock output for the clock source.
Before sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used for wide
range counting. The 16-bit counter performs up-counting operation only, the counter initial values can be
stored from memory by stt16 instruction and the counting values can be loaded to memory by ldt16 instruction.
A selector is used to select the interrupt condition of Timer16, whenever overflow occurs, the Timer16 interrupt
can be triggered. The hardware diagram of Timer16 is shown as Fig.9. The interrupt source of Timer16 comes
from one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge trigger or falling edge trigger
which is specified in the bit 5 of integs register (address 0x0C).
PA4
Fig.9: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
st
to define the Timer16; 1 parameter is used to define the clock source of Timer16, 2
nd
parameter is used to
define the pre-scalar and the last one is to define the interrupt source. The detail description is shown as
below:
T16M
IO_RW
0x06
st
$ 7~5: STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
// 1 par.
$ 4~3: /1, /4, /16, /64
// 2 par.
$ 2~0: BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
// 3 par.
©Copyright 2018, PADAUK Technology Co. Ltd
nd
Page 39 of 87
rd
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
User can define the parameters of T16M based on system requirement, some examples are shown below and
more examples please refer to “Help Application Note IC Introduction Register Introduction T16M” in
IDE utility.
$ T16M SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if using System Clock = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 125KHz, about every 512 mS to generate INTRQ.2=1
$ T16M EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
$ T16M PA0_F, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
$ T16M STOP;
// stop Timer16 counting
If Timer16 is operated at free running, the frequency of interrupt can be described as below:
FINTRQ_T16M = Fclock source ÷ P ÷ 2n+1
Where, F is the frequency of selected clock source to Timer16;
P is the selection of t16m [4:3]; (1, 4, 16, 64)
th
N is the n bit selected to request interrupt service, for example: n=10 if bit 10 is selected.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 40 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.7 8-bit Timer (Timer2) with PWM generation
An 8-bit hardware timer (Timer2) with PWM generation is implemented in the PMS152. Please refer to Fig.10
shown the hardware diagram of Timer2, the clock sources of Timer2 may come from system clock, internal high
RC oscillator (IHRC), internal low RC oscillator (ILRC), external crystal oscillator (EOSC), PA0, PB0, PA4 and
comparator. Bit [7:4] of register tm2c are used to select the clock of Timer2. If IHRC is selected for Timer2 clock
source, the clock sent to Timer2 will keep running when using ICE in halt state. The output of Timer2 can be
sent to pin PB2, PA3 or PB4, depending on bit [3:2] of tm2c register. A clock pre-scaling module is provided with
divided-by- 1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register; one scaling module with
divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In conjunction of pre-scaling
function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide range and flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by
tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register in period mode. The upper bound register is used to define the period of timer or duty of PWM. There
are two operating modes for Timer2: period mode and PWM mode; period mode is used to generate periodical
output waveform or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit,
7-bit or 8-bit PWM resolution, Fig.11 shows the timing diagram of Timer2 for both period mode and PWM mode.
Fig.10: Timer2 hardware diagram
©Copyright 2018, PADAUK Technology Co. Ltd
Page 41 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Time out and
Interrupt request
Time out and
Interrupt request
Time out and
Interrupt request
Counter
Counter
Counter
0x3F
0xFF
0xFF
bound
bound
bound
Time
Event Trigger
Output-pin
Event Trigger
Time
Output-pin
Time
Output-pin
Time
Time
Mode 0 – Period Mode
Event Trigger
Mode 1 – 8-bit PWM Mode
Time
Mode 1 – 6-bit PWM Mode
Fig.11: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
5.7.1
Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷
[ 2 × (127＋1) × 1 × (0＋1) ] = 31.25KHz
Example 2:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0111_11111, S1=64 , S2 = 31
frequency of output = 8MHz ÷ ( 2 × (127＋1) × 64 × (31＋1) ) =15.25Hz
©Copyright 2018, PADAUK Technology Co. Ltd
Page 42 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Example 3:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 2 × (15＋1) × 1 × (0＋1) ) = 250KHz
Example 4:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 2 × (1＋1) × 1 × (0＋1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform from PA3 is shown as below:
Void
FPPA0 (void)
{
. ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
…
tm2ct = 0x0;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
8-bit PWM, pre-scalar = 1, scalar = 2
tm2c = 0b0001_10_0_0;
//
system clock, output=PA3, period mode
while(1)
{
nop;
}
}
©Copyright 2018, PADAUK Technology Co. Ltd
Page 43 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
5.7.2
Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = ( K＋1 ) ÷ 256
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
©Copyright 2018, PADAUK Technology Co. Ltd
Page 44 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
FPPA0 (void)
{
.ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x0;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
8-bit PWM, pre-scalar = 1, scalar = 2
tm2c = 0b0001_10_1_0;
//
system clock, output=PA3, PWM mode
while(1)
{
nop;
}
}
5.7.3
Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K＋1 ) ÷ 64] × 100%
Where,
tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (1 ~ 31)
Users can set Timer2 to be 7-bit PWM mode instead of 6-bit mode by using TM2_Bit code option. At that
time, the calculation factors of the above equations become 128 instead of 64.
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
©Copyright 2018, PADAUK Technology Co. Ltd
Page 45 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(0+1) ÷ 64] × 100% =1.5%
5.8 11-bit PWM Generators
One set of triple 11-bit SuLED (Super LED) hardware PWM generator is implemented in the PMS152. It consists
of three PWM generators (PWMG0, PWMG1 & PWMG2). Their individual outputs are listed as below:
PWMG0 – PA0, PB4, PB5
PWMG1 – PA4, PB6, PB7
PWMG2 – PA3, PB2, PB3, PA5 (open drain output only)
5.8.1
PWM Waveform
A PWM output waveform (Fig.12) has a time-base (TPeriod = Time of Period) and a time with output high
level (Duty Cycle). The frequency of the PWM output is the inverse of the period (fPWM = 1/TPeriod).
Fig.12: PWM Output Waveform
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8bit OTP Type SuLED IO Controller
5.8.2
Hardware Diagram
Fig.13 shows the hardware diagram of the whole set of SuLED 11-bit hardware PWM generators. Those
three PWM generators use a common Up-Counter and clock source selector to create the time base, and
so the start points (the rising edge) of the PWM cycle are synchronized. The clock source can be IHRC or
system clock. The PWM signal output pins that can be selected via pwmgxc register selection. The period
of PWM waveform is defined by the common PWM upper bound high and low registers, and the duty cycle
of individual PWM waveform is defined by the individual set in the PWM duty high and low registers.
The additional OR and XOR logic of PWMG0 channel is used to create the complementary switching
waveforms with dead zone control. Comparator output can control the PWM waveform by selecting
GPC_PWM code option.
Fig.13: Hardware diagram of whole set of triple SuLED 11-bit PWM generators
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PMS152
8bit OTP Type SuLED IO Controller
0x7FF
Counter_Bound[10:1]
Duty[10:0]
Time
Time
Output
Output Timing Diagram for 11- bit PWM generation
Fig.14: Output Timing Diagram of 11-bit PWM Generator
5.8.3
Equations for 11-bit PWM Generator
If FIHRC is the frequency of IHRC oscillator and IHRC is the chosen clock source for 11-bit PWM generator,
the PWM frequency and duty cycle in time will be:
Frequency of PWM Output = FIHRC ÷ [ CB +1 ]
Duty Cycle of PWM Output (in time) = (1/FIHRC) * [ DB10_1 + DB0 * 0.5 + 0.5]
Where, Duty_Bound[10:1] = {pwmgxdth[7:0],pwmgxdtl[7:6]} = DB10_1; duty bound
Duty_Bound[0] = pwmgxdtl[5] = DB0
Counter_Bound[10:1] = {pwmgcubh[7:0], pwmgcubl[7:6]} = CB; counter bound
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PMS152
8bit OTP Type SuLED IO Controller
5.9
WatchDog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC. WDT can be cleared by power-on-reset
or by command wdreset at any time. There are four different timeout periods of watchdog timer to be chosen
by setting the misc register, it is:
8k ILRC clocks period if register misc[1:0]=00 (default)
16k ILRC clocks period if register misc[1:0]=01
64k ILRC clocks period if register misc[1:0]=10
256k ILRC clocks period if register misc[1:0]=11
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for save operation. Besides, the watchdog period will also be shorter than expected
after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these events to ensure
enough clock periods before WDT timeout.
When WDT is timeout, PMS152 will be reset to restart the program execution. The relative timing diagram of
watchdog timer is shown as Fig.15.
VDD
tSBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig.15: Sequence of Watch Dog Time Out
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PMS152
8bit OTP Type SuLED IO Controller
5.10 . Interrupt
There are eight interrupt lines for PMS152:
External interrupt PA0/PB5
External interrupt PB0/PA4
Timer16 interrupt
GPC interrupt
PWMG interrupt
Timer2 interrupt
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig.16. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it.
The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.
Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can
use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler
in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to
prevent address conflicts.
Fig.16: Hardware diagram of interrupt controller
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
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8bit OTP Type SuLED IO Controller
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. And so on, two bytes stack memory is for pushaf. For interrupt operation, the
following sample program shows how to handle the interrupt, noticing that it needs four bytes stack memory to
handle one level interrupt and pushaf.
void
FPPA0 (void)
{
...
$
INTEN
INTRQ
=
PA0;
// INTEN =1; interrupt request when PA0 level changed
0;
// clear INTRQ
ENGINT
// global interrupt enable
...
DISGINT
// global interrupt disable
...
}
void
Interrupt
(void)
//
interrupt service routine
{
PUSHAF
If
//
store ALU and FLAG register
//
Here for PA0 interrupt service routine
(INTRQ.0)
{
INTRQ.0
=
0;
...
}
...
POPAF
//
restore ALU and FLAG register
}
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8bit OTP Type SuLED IO Controller
5.11 Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power with
wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up. Table 5 shows the differences in oscillator modules between Power-Save mode (“stopexe”)
and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
ILRC
EOSC
STOPSYS
Stop
Stop
Stop
STOPEXE
No Change
No Change
No Change
Table 5: Differences in oscillator modules between STOPSYS and STOPEXE
5.11.1
Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all
the oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting
if its clock source is not the system clock. Wake-up from input pins can be considered as a continuation
of normal execution, the detail information for Power-Save mode shows below:
IHRC, ILRC and EOSC oscillator modules: No change, keep active if it was enabled.
System clock: Disable, therefore, CPU stops execution.
OTP memory is turned off.
Timer16, Timer2: Stop counting if system clock is selected by clock source or the corresponding oscillator
module is disabled; Otherwise, it keeps counting.
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1) or Timer16 or Timer2 or Timer3.
An example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M
…
WORD
STT16
stopexe;
ILRC, /1, BIT8
count =
count;
// Timer16 setting
0;
…
The initial counting value of Timer16 is zero and the system will be woken up after the Timer16 counts 256
ILRC clocks.
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8bit OTP Type SuLED IO Controller
5.11.2 Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using
the “stopsys” instruction, this chip will be put on Power-Down mode directly. The following shows the
internal status of PMS152 detail when “stopsys” command is issued:
All the oscillator modules are turned off.
OTP memory is turned off.
The contents of SRAM and registers remain unchanged.
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1)
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CLKMD
=
0xF4;
//
Change clock from IHRC to ILRC
CLKMD.4
=
0;
//
disable IHRC
STOPSYS;
//
enter power-down
if
//
if wakeup happen and check OK, then return to high speed,
//
else stay in power-down mode again
//
Change clock from ILRC to IHRC/2
…
while (1)
{
(…)
break;
}
CLKMD
=
0x34;
5.11.3 Wake-up
After entering the Power-Down or Power-Save modes, the PMS152 can be resumed to normal operation
by toggling IO pins. Timer16 and Timer2 interrupt is available for Power-Save mode ONLY. Table 6
shows the differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
T16 Interrupt
STOPSYS
Yes
No
STOPEXE
Yes
Yes
Table 6: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMS152, registers padier should be properly set to enable the
wake-up function for every corresponding pin. The time for normal wake-up is about 3000 ILRC clocks
counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by misc register,
and the time for fast wake-up is about 45 ILRC clocks from IO toggling.
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8bit OTP Type SuLED IO Controller
Suspend mode
Wake-up mode
STOPEXE suspend
or
Fast wake-up
STOPSYS suspend
STOPEXE suspend
or
Normal wake-up
STOPSYS suspend
Wake-up time (tWUP) from IO toggle
45 * TILRC,
Where TILRC is the time period of ILRC
3000 * TILRC,
Where TILRC is the clock period of ILRC
Please notice that when Code Option is set to Fast boot-up, no matter which wake-up mode is selected in
misc.5, the wake-up mode will be forced to be FAST. If Normal boot-up is selected, the wake-up mode is
determined by misc.5.
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8bit OTP Type SuLED IO Controller
5.12 IO Pins
All the pins can be independently set into two states output or input by configuring the data registers (pa, pb),
control registers (pac, pbc) and pull-high registers (paph, pbph). All these pins have Schmitt-trigger input
buffer and output driver with CMOS level. When it is set to output low, the pull-up resistor is turned off
automatically. If user wants to read the pin state, please notice that it should be set to input mode before
reading the data port; if user reads the data port when it is set to output mode, the reading data comes from
data register, NOT from IO pad. As an example, Table 7 shows the configuration table of bit 0 of port A. The
hardware diagram of IO buffer is also shown as Fig.17.
pa.0
X
X
0
1
1
pac.0 paph.0
0
0
1
1
1
Description
0
1
X
0
1
Input without pull-up resistor
Input with pull-up resistor
Output low without pull-up resistor
Output high without pull-up resistor
Output high with pull-up resistor
Table 7: PA0 Configuration Table
RD pull-high latch
D
WR pull-high latch
Q
(weak P -MOS)
-
pull-high
latch
D
Q
Q1
Data
latch
WR data latch
PAD
RD control latch
D
WR control latch
Q
Control
M
latch
U
X
RD Port
Data Bus
padier.x or pbdier.x
Wakeup module
Interrupt module
(PA0,PB5,PB0,PA4)
Analog Module
Fig.17: Hardware diagram of IO buffer
Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output
mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent leakage
current for those pins are selected to be analog function. When PMS152 is put in power-down or power-save
mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins needed to
wake-up system must be set to input mode and set the corresponding bits of registers padier and pbdier to
high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin, pbdier.0 for
PB0, padier.4 for PA4 and pbdier.5 for PB5.
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8bit OTP Type SuLED IO Controller
5.13 Reset and LVR
5.13.1 Reset
There are many causes to reset the PMS152, once reset is asserted, most of all the registers in PMS152
will be set to default values, system should be restarted once abnormal cases happen, or by jumping
program counter to address 0x0. The data memory is in uncertain state when reset comes from power-up
and LVR; however, the content will be kept when reset comes from PRSTB pin or WDT timeout.
5.13.2 LVR reset
By code option, there are 8 different levels of LVR for reset ~ 4.5V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V and
1.8V; usually, user selects LVR reset level to be in conjunction with operating frequency and supply voltage.
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8bit OTP Type SuLED IO Controller
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit
Reset
R/W
7-4
-
-
3
0
R/W
2
0
R/W
Description
Reserved. Please do not use.
OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
of low nibble in addition operation and the other one is borrow from the high nibble into low
nibble in subtraction operation.
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
1
0
R/W
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
0
0
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit
Reset
R/W
7-0
-
R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer.
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit
Reset
R/W
Description
System clock (CLK) selection:
Type 0, clkmd[3]=0
7-5
111
R/W
Type 1, clkmd[3]=1
000: IHRC÷4
000: IHRC÷16
001: IHRC÷2
001: IHRC÷8
010: IHRC
010: ILRC÷16 (ICE does NOT Support.)
011: EOSC÷4
011: IHRC÷32
100: EOSC÷2
100: IHRC÷64
101: EOSC
101: EOSC÷8
110: ILRC÷4
111: ILRC (default)
11x: reserved
4
1
R/W
Internal High RC Enable. 0 / 1: disable / enable
3
0
R/W
2
1
R/W
1
1
R/W
Watch Dog Enable. 0 / 1: disable / enable
0
0
R/W
Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1
Internal Low RC Enable. 0 / 1: disable / enable
If ILRC is disabled, watchdog timer is also disabled.
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8bit OTP Type SuLED IO Controller
6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
Reset
R/W
Description
7
0
R/W
Reserved
6
0
R/W
Enable interrupt from Timer2. 0 / 1: disable / enable
5
0
R/W
Enable interrupt from PWMG. 0 / 1: disable / enable
4
0
R/W
Enable interrupt from comparator. 0 / 1: disable / enable
3
0
R/W
Reserved
2
0
R/W
Enable interrupt from Timer16 overflow. 0 / 1: disable / enable
1
0
R/W
Enable interrupt from PB0/PA4. 0 / 1: disable / enable
0
0
R/W
Enable interrupt from PA0/PB5. 0 / 1: disable / enable
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset
R/W
7
-
R/W
6
-
R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Description
Reserved
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from PWMG, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Reserved
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PB0/PA4, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0/PB5, this bit is set by hardware and cleared by software.
0 / 1: No Request / request
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8bit OTP Type SuLED IO Controller
6.6. Timer16 mode Register (t16m), IO address = 0x06
Bit
Reset
R/W
Description
Timer16 Clock source selection.
000: disable
001: CLK (system clock)
010: reserved
7-5
000
R/W
011: PA4 falling edge (from external pin)
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Timer16 clock pre-divider.
00: ÷1
4-3
00
R/W
01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when the selected bit status is
changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2-0
000
R/W
2 : bit 10 of Timer16
3 : bit 11 of Timer16
4 : bit 12 of Timer16
5: bit 13 of Timer16
6: bit 14 of Timer16
7: bit 15 of Timer16
6.7. MISC Register (misc), IO address = 0x08
Bit
Reset
R/W
7-6
-
-
Description
Reserved. (keep 0 for future compatibility)
Enable fast Wake up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake up.
5
0
WO
The wake-up time is 3000 ILRC clocks (Not for fast boot-up)
1: Fast wake up.
The wake-up time is 45 ILRC clocks.
4
-
-
Reserved.
3
-
-
Reserved.
2
0
WO
Disable LVR function.
0 / 1 : Enable / Disable
Watch dog time out period
00: 8k ILRC clock period
1-0
00
WO
01: 16k ILRC clock period
10: 64k ILRC clock period
11: 256k ILRC clock period
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8bit OTP Type SuLED IO Controller
6.8. External Oscillator setting Register (eoscr), IO address = 0x0a
Bit
7
Reset
0
R/W
WO
6-5
00
WO
4-1
0
0
WO
Description
0 / 1 : Disable / Enable
Enable external crystal oscillator.
External crystal oscillator selection.
00 : reserved
01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator (reserved)
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
Reserved. Please keep 0 for future compatibility.
Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
6.9. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
7-5
Reset
-
R/W
-
4
0
WO
3-2
00
WO
1-0
00
WO
Description
Reserved.
Timer16 edge selection.
0 : rising edge of the selected bit to trigger interrupt
1 : falling edge of the selected bit to trigger interrupt
PB0/PA4 edge selection.
00: both rising edge and falling edge of the selected bit to trigger interrupt
01: rising edge of the selected bit to trigger interrupt
10: falling edge of the selected bit to trigger interrupt
11: reserved.
PA0/PB5 edge selection.
00: both rising edge and falling edge of the selected bit to trigger interrupt
01: rising edge of the selected bit to trigger interrupt
10: falling edge of the selected bit to trigger interrupt
11: reserved.
6.10. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
7
1
WO
6
1
WO
5
1
WO
4
1
WO
3
1
WO
2-1
1
WO
0
1
WO
Description
Enable PA7 digital input and wake-up event. 1 / 0: enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Enable PA6 digital input and wake-up event. 1 / 0: enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Enable PA5 digital input and wake-up event. 1 / 0: enable / disable.
This bit can be set to low to disable wake-up from PA5 toggling.
Enable PA4 digital input and wake-up event. 1 / 0: enable / disable.
This bit should be set to low when PA4 is assigned as comparator input to prevent leakage
current. If this bit is set to low, PA4 can NOT be used to wake-up the system.
Enable PA3 digital input and wake-up event. 1 / 0: enable / disable.
This bit should be set to low when PA3 is assigned as comparator input to prevent leakage
current. If this bit is set to low, PA3 can NOT be used to wake-up the system.
Reserved
Enable PA0 digital input and wake-up event and interrupt request.
1 / 0: enable / disable.
This bit can be set to low to disable wake-up from PA0 toggling and interrupt request from
this pin.
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8bit OTP Type SuLED IO Controller
6.11. Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset
R/W
Description
Enable PB7~PB0 digital input and wake-up event. 1 / 0: enable / disable.
7-0
0xFF
WO
The bit should be set to low when the pad is assigned as comparator input to prevent
leakage current. If the bit is set to low, the pad can NOT be used to wake-up the system.
6.12. Port A Data Register (pa), IO address = 0x10
Bit
Reset
R/W
7-0
0x00
R/W
Description
Data register for Port A.
6.13. Port A Control Register (pac), IO address = 0x11
Bit
Reset
R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
7-0
0x00
R/W
corresponding pin of port A.
0 / 1: input / output
Please note : PA5 is an open drain output.
6.14. Port A Pull-High Register (paph), IO address = 0x12
Bit
Reset
R/W
Description
Port A pull-high register. This register is used to enable the internal pull-high device on each
7-0
0x00
R/W
corresponding pin of port A and this pull high function is active only for input mode.
0 / 1 : disable / enable
6.15. Port B Data Register (pb), IO address = 0x14
Bit
Reset
R/W
7-0
0x00
R/W
Description
Data register for Port B.
6.16. Port B Control Register (pbc), IO address = 0x15
Bit
Reset
R/W
7-0
0x00
R/W
Description
Port B control register. This register is used to define input mode or output mode for each
corresponding pin of port B.
0 / 1: input / output
6.17. Port B Pull-High Register (pbph), IO address = 0x16
Bit
Reset
R/W
7-0
0x00
R/W
Description
Port B pull-high register. This register is used to enable the internal pull-high device on each
corresponding pin of port B and this pull high function is active only for input mode.
0 / 1 : disable / enable
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PMS152
8bit OTP Type SuLED IO Controller
6.18. Comparator Control Register (gpcc), IO address = 0x18
Bit
Reset
R/W
Description
Enable comparator. 0 / 1 : disable / enable
7
0
R/W
When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
6
-
RO
0: plus input < minus input
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
5
0
R/W
0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
4
0
R/W
0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
3-1
000
R/W
010 : Internal 1.20 volt band-gap reference voltage
011 : Vinternal R
100 : PB6 (not for EV5)
101 : PB7 (not for EV5)
11X: reserved
Selection the plus input (+) of comparator.
0
0
R/W
0 : Vinternal R
1 : PA4
6.19. Comparator Selection Register (gpcs), IO address = 0x19
Bit
Reset
R/W
Description
Comparator output enable (to PA0).
7
0
WO
0 / 1 : disable / enable
(Please avoid this situation: GPCS will affect the PA3 output function when selecting output
to PA0 output in ICE.)
6
0
-
Reserved
5
0
WO
Selection of high range of comparator.
4
0
WO
Selection of low range of comparator.
3-0
0000
WO
Selection the voltage level of comparator.
0000 (lowest) ~ 1111 (highest)
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Page 62 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
6.20. Timer2 Control Register (tm2c), IO address = 0x1c
Bit
Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC or IHRC *2 (by code option TM2_source) (ICE doesn’t support IHRC *2.)
0011 : EOSC
0100 : ILRC
0101 : comparator output
011x : reserved
7-4
0000
R/W
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3-2
00
R/W
01 : PB2
10 : PA3
11 : PB4
TM2 Mode
1
0
R/W
0: Period Mode
1: PWM Mode
Inverse the polarity of result output of TM2.
0
0
R/W
0: polarity is NOT inversed.
1: polarity is inversed.
6.21. Timer2 Scalar Register (tm2s), IO address = 0x17
Bit
Reset
R/W
7
0
WO
Description
PWM resolution selection.
0 : 8-bit
1 : 6-bit or 7-bit (by code option TM2_bit) (ICE doesn’t support 7-bit.)
Timer2 clock pre-scalar.
00 : ÷ 1
6-5
00
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4-0
00000
WO
Timer2 clock scalar.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
6.22. Timer2 Counter Register (tm2ct), IO address = 0x1d
Bit
Reset
R/W
7-0
0x00
R/W
Description
Bit [7:0] of Timer2 counter register.
6.23. Timer2 Bound Register (tm2b), IO address = 0x09
Bit
Reset
R/W
7-0
0x00
WO
Description
Timer2 bound register.
6.24. PWMG0 control Register (pwmg0c), IO address = 0x20
Bit
Reset
R/W
Description
7
-
-
6
-
RO
Output status of PWMG0 generator.
5
0
WO
Enable to inverse the polarity of PWMG0 generator output. 0 / 1: disable / enable.
Reserved.
PWMG0 output selection.
4
0
WO
0: PWMG0 Output
1: PWMG0 XOR PWMG1 or PWMG0 OR PWMG1 (by pwmg0c.0)
PWMG0 Output Port Selection
000: PWMG0 Output Disable
001: PWMG0 Output to PB5
3-1
000
R/W
010: Reserved
011: PWMG0 Output to PA0
100: PWMG0 Output to PB4
1xx: Reserved
PWMG0 output pre- selection.
0
0
R/W
0: PWMG0 XOR PWMG1
1: PWMG0 OR PWMG1
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Page 64 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
6.25. PWMG Clock Register (pwmgclk), IO address = 0x21
Bit
7
Reset
0
R/W
WO
PWMG Disable/ Enable
0: PWMG Disable
1: PWMG Enable
PWMG clock pre-scalar.
000: ÷1
001: ÷2
010: ÷4
011: ÷8
100: ÷16
101: ÷32
110: ÷64
111: ÷128
6-4
000
WO
3-1
-
-
0
0
Description
WO
Reserved
PWMG clock source selection
0: System Clock
1: IHRC or IHRC*2 (by code option PWM_Source)
6.26. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22
Bit
Reset
R/W
7-0
-
WO
Description
Bit[10:3] of PWMG0 Duty.
6.27. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23
Bit
Reset
R/W
7-5
-
WO
4-0
-
-
Description
Bit[2:0] of PWMG0 Duty.
Reserved
Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.
6.28. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x24
Bit
Reset
R/W
7-0
-
WO
Description
Bit[10:3] of PWMG Counter Bound.
6.29. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x25
Bit
Reset
R/W
7-5
-
WO
4-0
-
-
Description
Bit[2:0] of PWMG Counter Bound.
Reserved
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
6.30. PWMG1 control Register (pwmg1c), IO address = 0x26
Bit
Reset
R/W
7
-
-
6
-
RO
Output status of PWMG1 generator
5
0
R/W
Enable to inverse the polarity of PWMG1 generator output. 0 / 1: disable / enable.
R/W
PWMG1 output selection:
0: PWMG1
1: PWMG2
4
0
Description
Reserved
3-1
000
R/W
PWMG1 Output Port Selection:
000: PWMG1 Output Disable
001: PWMG1 Output to PB6
010: Reserved
011: PWMG0 Output to PA4
100: PWMG0 Output to PB7
1xx: Reserved
0
-
R/W
Reserved
6.31. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28
Bit
Reset
R/W
7-0
-
WO
Description
Bit[10:3] of PWMG1 Duty
6.32. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29
Bit
Reset
R/W
7-5
-
WO
4-0
-
-
Description
Bit[2:0] of PWMG1 Duty.
Reserved
Note: It’s necessary to write PWMG1 Duty_Value Low Register before writing PWMG1 Duty_Value High Register.
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Page 66 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
6.33. PWMG2 control Register (pwmg2c), IO address = 0x2C
Bit
Reset
R/W
7
-
-
6
-
RO
Output status of PWMG2 generator.
5
0
R/W
Enable to inverse the polarity of PWMG2 generator output. 0 / 1: disable / enable.
R/W
PWMG2 output selection:
0: PWMG2
1: PWMG2 ÷2
4
0
Description
Reserved.
3-1
000
R/W
PWMG2 Output Port Selection:
000: PWMG2 Output Disable
001: PWMG2 Output to PB3
010: Reserved
011: PWMG2 Output to PA3
100: PWMG2 Output to PB2
101: PWMG2 Output to PA5
1xx: Reserved
0
-
R/W
Reserved
6.34. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E
Bit
Reset
R/W
7-0
-
WO
Description
Bit[10:3] of PWMG2 Duty
6.35. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F
Bit
Reset
R/W
7-5
-
WO
4-0
-
-
Description
Bit[2:0] of PWMG2 Duty
Reserved
Note: It’s necessary to write PWMG2 Duty_Value Low Register before writing PWMG2 Duty_Value High Register.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 67 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7. Instructions
Symbol
ACC
a
sp
flag
Description
Accumulator (Abbreviation of accumulator)
Accumulator (symbol of accumulator in program)
Stack pointer
ACC status flag register
I
Immediate data
&
Logical AND
|
Logical OR
←
Movement
^
Exclusive logic OR
+
Add
－
Subtraction
〜
NOT (logical complement, 1’s complement)
〒
NEG (2’s complement)
OV
Overflow (The operational result is out of range in signed 2’s complement number system)
Z
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
C
unsigned number system)
Auxiliary Carry
AC
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
M.n
Only addressed in 0~0x3F (0~63) is allowed
IO.n
Only addressed in 0~0x3F (0~63) is allowed
©Copyright 2018, PADAUK Technology Co. Ltd
Page 68 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7.1. Data Transfer Instructions
mov
a, I
mov
M, a
mov
a, M
mov
a, IO
mov
IO, a
ldt16
word
Move immediate data into ACC.
Example: mov
a, 0x0f;
Result:
a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from ACC into memory
Example: mov
MEM, a;
Result:
MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result:
a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from IO into ACC
Example: mov
a, pa ;
Result:
a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from ACC into IO
Example: mov
pb, a;
Result:
pb ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
T16val ;
// declare a RAM word
…
clear
lb@ T16val ;
// clear T16val (LSB)
clear
hb@ T16val ;
// clear T16val (MSB)
stt16
T16val ;
// initial T16 with 0
…
set1
t16m.5 ;
// enable Timer16
…
set0
t16m.5 ;
// disable Timer 16
ldt16
T16val ;
// save the T16 counting value to T16val
….
------------------------------------------------------------------------------------------------------------------------
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
stt16
word
idxm
a, index
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
T16val ;
// declare a RAM word
…
mov
a, 0x34 ;
mov
lb@ T16val , a ; // move 0x34 to T16val (LSB)
mov
a, 0x12 ;
mov
hb@ T16val , a ; // move 0x12 to T16val (MSB)
stt16
T16val ;
// initial T16 with 0x1234
…
---------------------------------------------------------------------------------------------------------------------Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
----------------------------------------------------------------------------------------------------------------------word
RAMIndex ;
// declare a RAM pointer
…
mov
a, 0x5B ;
// assign pointer to an address (LSB)
mov
lb@RAMIndex, a ;
// save pointer to RAM (LSB)
mov
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
mov
hb@RAMIndex, a ; // save pointer to RAM (MSB)
…
idxm
a, RAMIndex ;
// mov memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
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Page 70 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
Idxm
xch
pushaf
popaf
index, a
M
Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
RAMIndex ;
// declare a RAM pointer
…
mov
a, 0x5B ;
// assign pointer to an address (LSB)
mov
lb@RAMIndex, a ;
// save pointer to RAM (LSB)
mov
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
mov
hb@RAMIndex, a ; // save pointer to RAM (MSB)
…
mov
a, 0xA5 ;
idxm
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
-----------------------------------------------------------------------------------------------------------------------Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------.romadr 0x10 ;
// ISR entry address
pushaf ;
// put ACC and flag into stack memory
…
// ISR program
…
// ISR program
popaf ;
// restore ACC and flag from stack memory
reti ;
-----------------------------------------------------------------------------------------------------------------------Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
Result:
sp ← sp - 2 ;
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 71 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7.2. Arithmetic Operation Instructions
add
a, I
add
a, M
add
M, a
addc
a, M
addc
M, a
addc
a
addc
M
nadd
a, M
Add immediate data with ACC, then put result into ACC
Example: add
a, 0x0f ;
Result:
a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result:
a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result:
MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result:
a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result:
MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add carry with ACC, then put result into ACC
Example: addc
a;
Result:
a←a+C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result:
MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add negative logic (2’s complement) of ACC with memory
Example:
nadd
a, MEM ;
Result:
a ← 〒a + MEM
Affected flags: 『Y』Z
nadd
M, a
a, I
sub
a, M
『Y』AC
『Y』OV
Add negative logic (2’s complement) of memory with ACC
Example:
nadd
Result:
MEM ←
MEM, a ;
〒MEM + a
Affected flags: 『Y』Z
sub
『Y』C
『Y』C
『Y』AC
『Y』OV
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result:
a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in memory from ACC, then put result into ACC
Example: sub
a, MEM ;
Result:
a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 72 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
sub
M, a
subc
a, M
subc
M, a
subc
a
subc
M
inc
dec
clear
M
M
M
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result:
MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result:
a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result:
MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result:
a←a-C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result:
MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Increment the content of memory
Example: inc
MEM ;
Result:
MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Decrement the content of memory
Example: dec
MEM;
Result:
MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Clear the content of memory
Example: clear
MEM ;
Result:
MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 73 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7.3. Shift Operation Instructions
sr
a
src
sr
a
M
src
sl
slc
sl
slc
Shift right of ACC, shift 0 to bit 7
Example: sr
a;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
Example: sr MEM ;
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
M
a
a
M
M
swap
a
Shift right of memory with carry bit 7 to flag
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC shift 0 to bit 0
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
Example: swap
a;
Result:
a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 74 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7.4. Logic Operation Instructions
and
a, I
and
a, M
and
M, a
or
a, I
or
a, M
or
M, a
xor
a, I
xor
IO, a
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and
a, 0x0f ;
Result:
a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result:
a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result:
MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result:
a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result:
a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result:
MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result:
a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and IO register, then put result into IO register
Example:
xor
a, M
xor
M, a
xor
pa, a ;
Result:
pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result:
a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
not
a
not
M
neg
neg
a
M
Perform 1’s complement (logical complement) of ACC
Example: not
a;
Result:
a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
// ACC=0X38
not
a;
// ACC=0XC7
-----------------------------------------------------------------------------------------------------------------------Perform 1’s complement (logical complement) of memory
Example: not
MEM ;
Result:
MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
// mem = 0x38
not
mem ;
// mem = 0xC7
-----------------------------------------------------------------------------------------------------------------------Perform 2’s complement of ACC
Example: neg
a;
Result:
a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
// ACC=0X38
neg
a;
// ACC=0XC8
-----------------------------------------------------------------------------------------------------------------------Perform 2’s complement of memory
Example: neg
MEM;
Result:
MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
// mem = 0x38
not
mem ;
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 76 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
comp
a, M
Compare ACC with the content of memory
Example:
comp
a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z
『Y』C
『Y』AC
『Y』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
comp
a, mem ;
mov
a, 0x42 ;
mov
mem, a ;
mov
a, 0x38 ;
comp
a, mem ;
// Z flag is set as 1
// C flag is set as 1
-----------------------------------------------------------------------------------------------------------------------comp
M, a
Compare ACC with the content of memory
Example:
comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z
©Copyright 2018, PADAUK Technology Co. Ltd
『Y』C
『Y』AC
Page 77 of 87
『Y』OV
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7.5. Bit Operation Instructions
set0
IO.n
set1
IO.n
swapc
IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C
Set bit n of IO port to high
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C
『N』AC
『N』OV
『N』AC
『N』OV
Swap the nth bit of IO port with carry bit
Example:
Result:
swapc
IO.0;
C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example1 (serial output) :
-----------------------------------------------------------------------------------------------------------------------...
set1
pac.0 ;
// set PA.0 as output
flag.1 ;
// C=0
...
set0
swapc
set1
swapc
pa.0 ;
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=0
// C=1
// move C to PA.0 (bit operation), PA.0=1
...
-----------------------------------------------------------------------------------------------------------------------Application Example2 (serial input) :
-----------------------------------------------------------------------------------------------------------------------...
set0
pac.0 ;
// set PA.0 as input
...
swapc
pa.0 ;
// read PA.0 to C (bit operation)
src
a;
// shift C to bit 7 of ACC
swapc
pa.0 ;
// read PA.0 to C (bit operation)
src
a;
// shift new C to bit 7, old C
...
-----------------------------------------------------------------------------------------------------------------------set0
M.n
Set bit n of memory to low
Example:
set0
MEM.5 ;
Result: set bit 5 of MEM to low
set1
M.n
Affected flags: 『N』Z 『N』C
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C
©Copyright 2018, PADAUK Technology Co. Ltd
『N』AC
『N』OV
『N』AC
『N』OV
Page 78 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
7.6. Conditional Operation Instructions
ceqsn
a, I
ceqsn
a, M
cneqsn
a, M
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a – I)
Example: ceqsn
a, 0x55 ;
inc
MEM ;
goto
error ;
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example:
cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC
cneqsn
a, I
『Y』OV
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example:
cneqsn
inc
goto
a,0x55 ;
MEM ;
error ;
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
t0sn
IO.n
t1sn
IO.n
t0sn
M.n
t1sn
M.n
izsn
a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
Example: izsn
a;
Result:
a ← a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 79 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
dzsn
a
izsn
M
dzsn
M
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
a;
Result:
A ← A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Increment memory and skip next instruction if memory is zero
Example: izsn
MEM;
Result:
MEM ← MEM + 1, skip next instruction if MEM= 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Decrement memory and skip next instruction if memory is zero
Example: dzsn
MEM;
Result:
MEM ← MEM - 1, skip next instruction if MEM = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
7.7. System control Instructions
call
label
goto
label
ret
ret
reti
nop
I
Function call, address can be full range address space
Example: call
function1;
Result: [sp] ← pc + 1
pc ← function1
sp ← sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Go to specific address which can be full range address space
Example: goto
error;
Result:
Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 80 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
pcadd
engint
disgint
stopsys
stopexe
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------…
mov
a, 0x02 ;
pcadd
a;
// PC 33Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
(6) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-up resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32KHz (reserved)
10 : for middle frequency, ex : 455KHz, 1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 84 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
*Use DISGINT in the main program to disable all interrupts
*When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
{
// enter DISGINT status automatically, no more interrupt is
accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status
will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function.
9.2.3. System clock switching
System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Example : Switch system clock from ILRC to IHRC/2
CLKMD
=
CLKMD.2 =
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
// ILRC can be disabled at this time
ERROR: Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD
=
0x50;
// MCU will hang
9.2.4. Watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5. TIMER time out
When select T16M counter BIT8 as 1 to generate interrupt, the first interrupt will occur when the counter
reaches to 0x100 (BIT8 from 0 to 1) and the second interrupt will occur when the counter reaches 0x300(BIT8
from 0 to 1). Therefore, selecting BIT8 as 1 to generate interrupt means that the interrupt occurs every 512
counts. Please notice that if T16M counter is restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 85 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
9.2.6.
IHRC
(1)
The IHRC frequency calibration is performed when IC is programmed by the writer.
(2)
Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the
actual IHRC frequency after molding may be deviated or becomes out of spec. Normally , the
frequency is getting slower a bit.
(3)
It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
(4)
Users can make some compensatory adjustments according to their own experiences. For example,
users can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7.
LVR
User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8.
Instructions
(1) PMS152 supports 86 instructions.
(2) The instruction execution cycle of PMS152 is shown as below:
Instruction
Condition
CPU
goto, call, pcadd, ret, reti
ceqsn, cneqsn, t0sn, t1sn, dzsn, izsn
9.2.9.
2T
Condition is fulfilled
2T
Condition is not fulfilled
1T
idxm
2T
Others
1T
BIT definition
Bit access of RAM is only available for address from 0x00 to 0x3F.
9.2.10. Programming Writing
Put the jumper over the CN39 (P201CS/CD16A) location. Put the PMS152-S14 to move down one space
over it. Put the PMS152-M10 to move down three spaces over it. Put the PMS152-S08 to move down four
spaces over it.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 86 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
PMS152
8bit OTP Type SuLED IO Controller
9.3. Using ICE
PDK5S-I-S01/2 supports PMS152 1-FPPA MCU emulation work, the following items should be noted
when using PDK5S-I-S01 to emulate PMS152:
PDK5S-I-S01/2 doesn’t support the function of the set of 11-bit SuLED hardware PWM generators.
PDK5S-I-S01/2 doesn’t support the instruction NADD/COMP of PMS152.
PDK5S-I-S01/2 doesn’t support SYSCLK=ILRC/16 of PMS152.
PDK5S-I-S01/2 doesn’t support the function Tm2.gpcrs of PMS152.
The PA3 output function will be affected when GPCS selects output to PA0 output.
Fast Wakeup time is different from PDK5S-I-S01/2: 128 SysClk, PMS152: 45 ILRC.
Watch dog time out period is different from PDK5S-I-S01/2:
WDT period
PDK5S-I-S01/2
PMS152
misc[1:0]=00
2048 * TILRC
8192 * TILRC
misc[1:0]=01
4096 * TILRC
16384 * TILRC
misc[1:0]=10
16384 * TILRC
65536 * TILRC
misc[1:0]=11
256 * TILRC
262144 * TILRC
©Copyright 2018, PADAUK Technology Co. Ltd
Page 87 of 87
PDK-DS-PMS152-EN_V002 – Jan. 24, 2018
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