PMS150C-U06

PMS150C 8bit OTP Type IO Controller Data Sheet Version 0.04 – Jan. 24, 2018 Copyright  2018 by PADAUK Technology Co., Ltd., all rights reserved 6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C. TEL: 886-3-572-8688  www.padauk.com.tw PMS150C 8 bit IO-Type Controller IMPORTANT NOTICE PADAUK Technology reserves the right to make changes to its products or to terminate production of its products at any time without notice. Customers are strongly recommended to contact PADAUK Technology for the latest information and verify whether the information is correct and complete before placing orders. PADAUK Technology products are not warranted to be suitable for use in life-support applications or other critical applications. PADAUK Technology assumes no liability for such applications. Critical applications include, but are not limited to, those that may involve potential risks of death, personal injury, fire or severe property damage. PADAUK Technology assumes no responsibility for any issue caused by a customer’s product design. Customers should design and verify their products within the ranges guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products, customers should design a product with adequate operating safeguards. PMS150C is NOT designed for AC RC step-down powered, high power ripple or high EFT requirement application, please do NOT apply PMS150C to those application products. ©Copyright 2018, PADAUK Technology Co. Ltd Page 2 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller Table of Contents 1. Features ............................................................................................................................... 8 1.1. System Features ...................................................................................................................8 1.2. CPU Features .......................................................................................................................8 1.3. Package Information .............................................................................................................8 2. General Description and Block Diagram .......................................................................... 9 3. Pin Functional Description .............................................................................................. 10 4. Device Characteristics ..................................................................................................... 12 5. 4.1. DC/AC Characteristics ........................................................................................................12 4.2. Absolute Maximum Ratings .................................................................................................13 4.3. Typical IHRC Frequency vs. VDD (calibrated to 16MHz) .....................................................14 4.4. Typical ILRC Frequency vs. VDD ........................................................................................14 4.5. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz) ........................................15 4.6. Typical ILRC Frequency vs. Temperature ...........................................................................15 4.7. Typical Operating Current vs. VDD and CLK=IHRC/n .........................................................16 4.8. Typical Operating Current vs. VDD and CLK=ILRC/n..........................................................16 4.9. Typical IO pull high resistance .............................................................................................17 4.10. Typical IO driving current (IOH) and sink current (IOL) ...........................................................17 4.11. Typical IO input high/low threshold voltage (VIH/VIL) ............................................................18 4.12. Typical power down current (IPD) and power save current (IPS) ............................................19 Functional Description ..................................................................................................... 20 5.1. Program Memory – OTP .....................................................................................................20 5.2. Boot Procedure ...................................................................................................................20 5.2.1. Timing charts for reset conditions ...........................................................................21 5.3. Data Memory – SRAM ........................................................................................................22 5.4. Oscillator and clock .............................................................................................................22 5.4.1. Internal High RC oscillator and Internal Low RC oscillator ......................................22 5.4.2. IHRC calibration .....................................................................................................22 5.4.3. IHRC Frequency Calibration and System Clock ......................................................23 5.4.4. System Clock and LVR levels .................................................................................24 5.5. Comparator .........................................................................................................................25 ©Copyright 2018, PADAUK Technology Co. Ltd Page 3 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller 5.5.1. Internal reference voltage (Vinternal R) ........................................................................26 5.5.2. Using the comparator .............................................................................................28 5.5.3. Using the comparator and band-gap 1.20V ............................................................29 5.6. 16-bit Timer (Timer16).........................................................................................................30 5.7. 8-bit timer (Timer2) with PWM generation ...........................................................................31 5.7.1. Using the Timer2 to generate periodical waveform .................................................32 5.7.2. Using the Timer2 to generate 8-bit PWM waveform ................................................33 5.7.3. Using the Timer2 to generate 6-bit PWM waveform ................................................34 5.8. Watchdog Timer ..................................................................................................................36 5.9. Interrupt...............................................................................................................................37 5.10. Power-Save and Power-Down ............................................................................................40 5.10.1. Power-Save mode (“stopexe”) ................................................................................40 5.10.2. Power-Down mode (“stopsys”)................................................................................41 5.10.3. Wake-up .................................................................................................................42 6. 5.11. IO Pins ................................................................................................................................43 5.12. Reset ..................................................................................................................................44 IO Registers ....................................................................................................................... 44 6.1. ACC Status Flag Register (flag), IO address = 0x00 ...........................................................44 6.2. Stack Pointer Register (sp), IO address = 0x02 ...................................................................44 6.3. Clock Mode Register (clkmd), IO address = 0x03................................................................44 6.4. Interrupt Enable Register (inten), IO address = 0x04...........................................................45 6.5. Interrupt Request Register (intrq), IO address = 0x05 .........................................................45 6.6. Timer 16 mode Register (t16m), IO address = 0x06 ............................................................45 6.7. External Oscillator setting Register (eoscr, write only), IO address = 0x0a ..........................46 6.8. Interrupt Edge Select Register (integs), IO address = 0x0c .................................................46 6.9. Port A Digital Input Enable Register (padier), IO address = 0x0d ........................................46 6.10. Port A Data Registers (pa), IO address = 0x10 ...................................................................46 6.11. Port A Control Registers (pac), IO address = 0x11 ..............................................................46 6.12. Port A Pull-High Registers (paph), IO address = 0x12 .........................................................46 6.13. MISC Register (misc), IO address = 0x1b ...........................................................................47 6.14. Comparator Control Register (gpcc), IO address = 0x1A.....................................................47 6.15. Comparator Selection Register (gpcs), IO address = 0x1E .................................................48 6.16. Timer2 Control Register (tm2c), IO address = 0x1C ............................................................48 6.17. Timer2 Counter Register (tm2ct), IO address = 0x1D ..........................................................48 ©Copyright 2018, PADAUK Technology Co. Ltd Page 4 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller 7. 6.18. Timer2 Bound Register (tm2b), IO address = 0x09 .............................................................49 6.19. Timer2 Scalar Register (tm2s), IO address = 0x17 ..............................................................49 Instructions ....................................................................................................................... 50 7.1. Data Transfer Instructions ...................................................................................................51 7.2. Arithmetic Operation Instructions ........................................................................................54 7.3. Shift Operation Instructions .................................................................................................55 7.4. Logic Operation Instructions ................................................................................................56 7.5. Bit Operation Instructions ....................................................................................................58 7.6. Conditional Operation Instructions.......................................................................................58 7.7. System control Instructions .................................................................................................59 7.8. Summary of Instructions Execution Cycle ...........................................................................61 7.9. Summary of affected flags by Instructions ...........................................................................62 8. Code Options .................................................................................................................... 63 9. Special Notes .................................................................................................................... 64 9.1. Warning ...............................................................................................................................64 9.2. Using IC ..............................................................................................................................64 9.2.1. IO pin usage and setting .........................................................................................64 9.2.2. Interrupt ..................................................................................................................64 9.2.3. System clock switching ...........................................................................................65 9.2.4. Power down mode, wakeup and watchdog .............................................................65 9.2.5. TIMER time out.......................................................................................................65 9.2.6. IHRC.......................................................................................................................65 9.2.7. LVR ........................................................................................................................66 9.2.8. Instructions .............................................................................................................66 9.2.9. RAM definition ........................................................................................................66 9.2.10. Program writing ......................................................................................................66 9.3. Using ICE ............................................................................................................................67 ©Copyright 2018, PADAUK Technology Co. Ltd Page 5 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller Revision History: Revision Date 0.01 2016/03/09 0.02 2016/11/03 0.03 2017/12/04 0.04 2018/01/24 Description st 1 version 1. Amend Chapter 2 Block Diagram 2. Amend Chapter 4.1 Pull-high Resistance typical value 3. Add Chapter 5.5 and all descriptions about the Comparator 4. Add Chapter 5.7 and all descriptions about Timer2 with PWM generation 1. Amend Section 1.1 System Features 2. Add Section 1.3 Package Information 3. Amend Chapter 3 Pin Functional Description: PMS150C-U06, PMS150C-S08, PMS150C-D08 4. Amend Section 4.1 DC/AC Characteristics: “VIL” and “VIH” 5. Amend Section 4.11 Typical IO input high/low threshold voltage 6. Add Section 4.12. Typical power down current (IPD) and power save current (IPS) 7. Add Section 5.2.1 Timing charts for reset conditions 8. Amend Section 5.4 Oscillator and clock 9. Amend Section 5.4.3 IHRC Frequency Calibration and System Clock 10. Amend Section 5.4.4 System Clock and LVR levels 11. Amend Fig.2 Options of System Clock 12. Amend Section 5.5.2 description about the comparator Case A and Case B 13. Amend Section 5.6 16-bit Timer 14. Amend Section 5.8 Watchdog Timer 15. Amend Section 5.9 Interrupt 16. Amend Fig.12 Hardware diagram of Interrupt controller 17. Amend Section 5.10.1 Power-Save mode 18. Amend Section 5.10.3 Wake-up 19. Amend Section 6.3 Clock Mode Register 20. Amend Section 6.13 MISC Register 21. Amend Section 6.14. Comparator Control Register 22. Amend Section 6.16. Timer2 Control Register 23. Delete the Symbol “pc0” in Chapter 7 24. Add Chapter 8 Code Options 25. Amend Section 9.2.1 IO pin usage and setting 26. Amend Section 9.2.4 Power down mode, wakeup and watchdog 27. Add Section 9.2.6 IHRC 28. Amend Section 9.2.7 LVR 29. Amend Section 9.2.10 Program writing 30. Amend Section 9.3 Using ICE 1. Amend the address and phone number of PADAUK Technology Co.,Ltd. 2. Amend Section 1.2 CPU Features 3. Amend Section 5.4.4 System Clock and LVR levels 4. Amend Section 5.5.2 Using the comparator 5. Amend Section 5.5.3 Using the comparator and band-gap 1.20V 6. Amend Section 5.9 Interrupt 7. Amend Section 5.10.1 Power-Save mode 8. Amend Section 5.10.2 Power-Down mode 9. Amend Section 5.10.3 Wake-up 10. Amend Section 6.15 Comparator Selection Register (gpcs) ©Copyright 2018, PADAUK Technology Co. Ltd Page 6 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller Major Differences between PMS150B and PMS150C Item Function PMS150B PMS150C o 1 Frequency of ILRC o 110KHz@5V, 25 C 62KHz@5V, 25 C (much smaller variant with VDD (much smaller variant with VDD changes) changes) 2 LVR levels 2.8V, 2.2V, 2.0V 3 Data RAM 60 bytes 4 Input pull-up resistor of PA5 No o 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V 64 bytes Yes o o o 5 Operation temperature 0 C ~70 C -20 C ~70 C 6 Power save current (stopexe) 40uA@3.3V 3uA @3.3V 7 IO Sink / Drive current 17mA / -7mA@5V 8 Watchdog timeout period 4096, 16384, 65536 TILRC 8k, 16k, 64k, 256k TILRC 9 Wake-up time (tWUP) Fast: 1024 TIHRC Fast: 32 TILRC Slow: 1024 TILRC Slow: 2048 TILRC 10 Boot-up time Fast: 2048 TIHRC Fast: 32 TILRC Slow: 1024 TILRC Slow: 2048 TILRC 11 System reserved OTP area 0x3F8 ~ 0x3FF (8 words) 0x3F0 ~ 0x3FF (16 words) 12 ILRC modes for system CLK ILRC, ILRC/4 ILRC, ILRC/4, ILRC/16 Normal: 14.5mA / -10.5mA@5V Low: 5mA / -3.5mA@5V PDK3S-I-00x 13 Supporting ICE (recommended not to use) 5S-I-S0xx 5S-I-S0xx 14 8-bit Timer2 with PWM No Yes 15 Comparator No Yes ©Copyright 2018, PADAUK Technology Co. Ltd Page 7 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller 1. Features 1.1. System Features  1KW OTP program memory  64 Bytes data RAM  One hardware 16-bit timer  One hardware 8-bit timer with PWM generation  One general purpose comparator  Support fast wake-up  Every IO pin can be configured to enable wake-up function  6 IO pins with optional drive/sink current and pull-high resistor  Clock sources: internal high RC oscillator and internal low RC oscillator  Eight levels of LVR ~ 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V  One external interrupt pin 1.2. CPU Features  One processing unit operating mode  79 Powerful instructions  Most instructions are 1T execution cycle  Programmable stack pointer and adjustable stack level  All data memories are available for use as an index pointer  IO space and memory space are independent 1.3. Package Information  PMS150C Series  PMS150C - U06: SOT23-6 (60mil);  PMS150C - S08: SOP8 (150mil);  PMS150C - D08: DIP8 (300mil) ©Copyright 2018, PADAUK Technology Co. Ltd Page 8 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller 2. General Description and Block Diagram The PMS150C is an IO-Type, fully static, OTP-based controller; it employs RISC architecture and most the instructions are executed in one cycle except that few instructions are two cycles that handle indirect memory access. 1KW bits OTP program memory and 64 bytes data SRAM are inside. Besides, one hardware 16-bit timer, one hardware 8-bit timer with PWM generation and one general purpose comparator are also provided in the PMS150C. ©Copyright 2018, PADAUK Technology Co. Ltd Page 9 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller 3. Pin Functional Description Pin Name Pin & Buffer Description Type This pin can be used as: (1) Bit 7 of port A. It can be configured as digital input, two-state output with pull-up IO resistor by software independently. PA7 / ST / CIN3- CMOS / When this pin is configured as analog input, please use bit 7 of register padier to Analog disable the digital input to prevent current leakage. This pin can be used to (2) Minus input source 3 of comparator. wake-up system during sleep mode; however, wake-up function is also disabled if bit 7 of padier register is “0”. This pin can be used as: (1) Bit 6 of port A. It can be configured as digital input, two-state output with pull-up IO resistor by software independently. PA6 / ST / CIN2- CMOS / When this pin is configured as analog input, please use bit 6 of register padier to Analog disable the digital input to prevent current leakage. This pin can be used to (2) Minus input source 2 of comparator. wake-up system during sleep mode; however, wake-up function is also disabled if bit 6 of padier register is “0”. ©Copyright 2018, PADAUK Technology Co. Ltd Page 10 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller Pin Name Pin & Buffer Description Type The functions of this pin can be: (1) Bit 5 of port A. It can be configured as input or open-drain output pin with PA5 / PRST# IO ST / CMOS pull-up resistor. (2) Hardware reset. This pin can be used to wake-up system during sleep mode; however, wake-up function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in series to have high noise immunity when this pin is in input mode. This pin can be used as: (1) Bit 4 of port A. It can be configured as digital input, two-state output with pull-up resistor by software independently. PA4 / IO CIN+ / ST / CIN4- / CMOS / TM2PWM Analog (2) Plus input source of comparator. (3) Minus input source 4 of comparator. (4) Output of 8-bit Timer2 (TM2) When this pin is configured as analog input, please use bit 4 of register padier to disable the digital input to prevent current leakage. This pin can be used to wake-up system during sleep mode; however, wake-up function is also disabled if bit 4 of padier register is “0”. This pin can be used as: (1) Bit 3 of port A. It can be configured as digital input, two-state output with pull-up PA3 / CIN1- / TM2PWM IO ST / CMOS / Analog resistor by software independently. (2) Minus input source 1 of comparator. (3) Output of 8-bit Timer2 (TM2) When this pin is configured as analog input, please use bit 3 of register padier to disable the digital input to prevent current leakage. This pin can be used to wake-up system during sleep mode; however, wake-up function is also disabled if bit 3 of padier register is “0”. The functions of this pin can be: (1) Bit 0 of port A. It can be configured as input or output with pull-up resistor. PA0 / IO INT0 / ST / CO CMOS (2) External interrupt line 0. Both rising edge and falling edge are accepted to request interrupt service. (3) Output of comparator This pin can be used to wake up system during sleep mode; however, wake-up function from this pin is also disabled when bit 0 of padier register is “0”. VDD Positive power GND Ground Notes: IO: Input/Output; ST: Schmitt Trigger input; Analog: Analog input pin; CMOS: CMOS voltage level ©Copyright 2018, PADAUK Technology Co. Ltd Page 11 of 67 PDK-DS-PMS150C-EN-V004 – Jan. 24, 2018 PMS150C 8 bit IO-Type Controller 4. Device Characteristics 4.1. DC/AC Characteristics All data are acquired under the conditions of VDD=5.0V, fSYS=2MHz unless noted. Symbol Description Min Typ Max Unit VDD LVR% fSYS VPOR IOP IPD IPS Operating Voltage 2.0* 5.5 V Low Voltage Reset tolerance -5 5 % System clock (CLK)* = IHRC/2 IHRC/4 IHRC/8 ILRC 0 0 0 8M 4M 2M Power On Reset Voltage 62K 1.9 Operating Current Power Down Current (by stopsys command) VIH Input high voltage for IO lines 2.1 VDD ≧ 3.0V VDD ≧ 2.2V VDD ≧ 2.0V VDD =5.0V V 0.3 mA 13 uA fSYS=IHRC/16=1MIPS@3.3V fSYS=ILRC=62kHz@3.3V 0.5 uA fSYS= 0Hz, VDD =3.3V 3 (by stopexe command) Input low voltage for IO lines 2.0 * Subject to LVR tolerance VDD =3.3V; Power Save Current VIL Hz Conditions uA Band-gap, LVR, IHRC are OFF, ILRC module is ON. 0 0.1 VDD V 0.8 VDD VDD V 0.6 VDD VDD PA5 Others IO IO lines sink current IOL Normal 10 14.5 19 Low 3.5 5.0 6.5 Normal -7.5 -10.5 -13.5 Low -2.6 -3.5 -4.4 Input voltage -0.3 mA VDD=5.0V, VOL=0.5V mA VDD=5.0V, VOH=4.5V IO lines drive current IOH VIN IINJ (PIN) RPH fIHRC Injected current on pin calibration* V 1 mA 100 Pull-high Resistance Frequency of IHRC after VDD+0.3 KΩ 220 15.76* 16* 16.24* 15.20* 16* 16.80* 62* VDD +0.3≧VIN≧ -0.3 VDD=5.0V VDD=3.3V o @25 C MHz VDD =2.0V~5.5V, KHz -20 C