NRF52833-QIAA-R7

nRF52833 Product Specification v1.5 4452_021 v1.5 / 2021-11-08 Feature list Features: • ® Bluetooth 5.1, IEEE 802.15.4-2006, 2.4 GHz transceiver • ® -96 dBm sensitivity in 1 Mbps Bluetooth low energy mode • 512 kB flash and 128 kB RAM • Advanced on-chip interfaces ® • -103 dBm sensitivity in 125 kbps Bluetooth low energy mode (long range) • USB 2.0 full speed (12 Mbps) controller • -20 to +8 dBm TX power, configurable in 4 dB steps • High-speed 32 MHz SPI • On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series • Type 2 near field communication (NFC-A) tag with wake-on • Supported data rates: • • field ® • Bluetooth 5.1 – 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps • IEEE 802.15.4-2006 – 250 kbps • Proprietary 2.4 GHz – 2 Mbps, 1 Mbps • 42 general purpose I/O pins • EasyDMA automated data transfer between memory and Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using ® • Single-ended antenna output (on-chip balun) • • 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption) • • 4.9 mA peak current in TX (0 dBm) • 4.6 mA peak current in RX • 64 level comparator RSSI (1 dB resolution) • 15 level low-power comparator with wake-up from System OFF • • ® ® 217 EEMBC CoreMark score running from flash memory • 52 µA/MHz running CoreMark from flash memory • 38 µA/MHz running CoreMark from RAM • Watchpoint and trace debug modules (DWT, ETM, and ITM) • Serial wire debug (SWD) Rich set of security features • 12-bit, 200 ksps ADC – 8 configurable channels with mode ® • Nordic SoftDevice ready with support for concurrent multiprotocol programmable gain ARM Cortex -M4 32-bit processor with FPU, 64 MHz • • Programmable peripheral interconnect (PPI) peripherals Bluetooth • Touch-to-pair support • Secure boot ready • Temperature sensor • 4x four channel pulse width modulator (PWM) unit with EasyDMA • Audio peripherals – I2S, digital microphone interface (PDM) • 5x 32-bit timer with counter mode • Up to 4x SPI master/3x SPI slave with EasyDMA • Up to 2x I2C compatible two-wire master/slave • 2x UART (CTS/RTS) with EasyDMA • Quadrature decoder (QDEC) • Flash access control list (ACL) • 3x real-time counter (RTC) • Debug control and configuration • Single crystal operation • Access port protection (CTRL-AP) • Operating temperature from -40 to 105 °C • Package variants Secure erase Flexible power management ™ • aQFN 73 package, 7 x 7 mm • 1.7 V to 5.5 V supply voltage range • QFN40 package, 5 x 5 mm • On-chip DC/DC and LDO regulators with automated low current modes • WLCSP package, 3.175 x 3.175 mm • Automated peripheral power management • Fast wake-up using 64 MHz internal oscillator • 0.6 µA at 3 V in System OFF mode, no RAM retention • 1.5 µA at 3 V in System ON mode, no RAM retention, wake on RTC 4452_021 v1.5 ii Feature list Applications: • • Advanced computer peripherals and I/O devices • Mouse • Keyboard • Multi-touch trackpad • • Internet of things (IoT) • Smart home sensors and controllers • Industrial IoT sensors and controllers Interactive entertainment devices Advanced wearables • Remote controls • Health/fitness sensor and monitor devices • Gaming controllers • Wireless payment enabled devices 4452_021 v1.5 iii Contents Feature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1 Revision history. 2 About this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 2.1 Document status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Peripheral chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Fields and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 DUMMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 15 15 15 3 Block diagram. 17 4 Core components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Floating point interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 CPU and support module configuration . . . . . . . . . . . . . . . . . . . . . 4.1.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 RAM - Random access memory . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Flash - Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 NVMC — Non-volatile memory controller . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Writing to flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Erasing a page in flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Writing to user information configuration registers (UICR) . . . . . . . . . . . . . 4.3.4 Erasing user information configuration registers (UICR) . . . . . . . . . . . . . . . 4.3.5 Erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 Access port protection behavior . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 NVMC power failure protection . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 Partial erase of a page in flash . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 FICR — Factory information configuration registers . . . . . . . . . . . . . . . . . . 4.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 UICR — User information configuration registers . . . . . . . . . . . . . . . . . . . 4.5.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 EasyDMA error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 EasyDMA array list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 AHB multilayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1 DAP - Debug access port . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.2 Access port protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.3 CTRL-AP - Control access port . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.4 Debug Interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4452_021 v1.5 iv 18 18 18 18 19 19 20 20 20 22 23 23 24 24 24 24 24 24 25 25 25 30 30 30 40 40 44 45 46 46 47 48 48 51 53 4.8.5 Real-time debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.8.6 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 6 Power and clock management. . . . . . . . . . . . . . . . . . . . . . . . 55 5.1 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 POWER — Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Main supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 USB supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 System OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 System ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 RAM power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 CLOCK — Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 HFCLK controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 LFCLK controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 56 61 62 66 67 68 68 69 70 80 82 82 84 87 95 Peripherals. 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.1.1 Peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.1.2 Peripherals with shared ID . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.1.3 Peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.1.4 Bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.1.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.1.6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.1.7 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.2 AAR — Accelerated address resolver . . . . . . . . . . . . . . . . . . . . . . . 101 6.2.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2.2 Resolving a resolvable address . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2.3 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2.4 IRK data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3 ACL — Access control lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.4 CCM — AES CCM mode encryption . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.1 Keystream generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.2 Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.3 Decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.4 AES CCM and RADIO concurrent operation . . . . . . . . . . . . . . . . . . . 112 6.4.5 Encrypting packets on-the-fly in radio transmit mode . . . . . . . . . . . . . . . 112 6.4.6 Decrypting packets on-the-fly in RADIO receive mode . . . . . . . . . . . . . . . 113 6.4.7 CCM data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.8 EasyDMA and ERROR event . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.4.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.4.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.5 COMP — Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4452_021 v1.5 v 6.5.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 ECB — AES electronic codebook mode encryption . . . . . . . . . . . . . . . . . . 6.6.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 ECB data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 EGU — Event generator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 GPIO — General purpose input/output . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 GPIOTE — GPIO tasks and events . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 Pin events and tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.2 Port event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.3 Tasks and events pin configuration . . . . . . . . . . . . . . . . . . . . . . 6.9.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 I2S — Inter-IC sound interface . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 Transmitting and receiving . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.3 Left right clock (LRCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.4 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.5 Master clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.6 Width, alignment and format . . . . . . . . . . . . . . . . . . . . . . . . 6.10.7 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.8 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.9 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 LPCOMP — Low-power comparator . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 MWU — Memory watch unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 NFCT — Near field communication tag . . . . . . . . . . . . . . . . . . . . . . 6.13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.2 Operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.5 Frame assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.6 Frame disassembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.7 Frame timing controller . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.8 Collision resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.9 Antenna interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.10 NFCT antenna recommendations . . . . . . . . . . . . . . . . . . . . . . 4452_021 v1.5 vi 124 124 125 127 134 134 135 135 135 135 138 138 139 141 141 142 144 148 149 150 150 151 151 155 155 156 156 157 157 158 158 160 162 164 165 174 175 176 176 177 183 183 184 197 198 200 201 201 202 203 204 205 206 206 6.13.11 Battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.12 Digital Modulation Signal . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.14 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.15 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 PDM — Pulse density modulation interface . . . . . . . . . . . . . . . . . . . . 6.14.1 Master clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.2 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.3 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.5 Hardware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 PPI — Programmable peripheral interconnect . . . . . . . . . . . . . . . . . . . 6.15.1 Pre-programmed channels . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 PWM — Pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . . 6.16.1 Wave counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.2 Decoder with EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 QDEC — Quadrature decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.1 Sampling and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.2 LED output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.3 Debounce filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.4 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.5 Output/input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 RADIO — 2.4 GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.1 Packet configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.2 Address configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.3 Data whitening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.4 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.5 Radio states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.6 Transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.7 Receive sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.8 Received signal strength indicator (RSSI) . . . . . . . . . . . . . . . . . . . . 6.18.9 Interframe spacing (IFS) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.10 Device address match . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.11 Bit counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.12 Direction finding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.13 IEEE 802.15.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.14 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.16 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 RNG — Random number generator . . . . . . . . . . . . . . . . . . . . . . . 6.19.1 Bias correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.2 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 4452_021 v1.5 vii 207 207 208 208 227 227 228 228 229 229 230 231 231 238 238 240 240 245 246 249 256 256 257 265 266 267 267 268 268 268 269 280 280 281 282 283 283 284 284 286 287 287 288 289 289 294 303 304 339 345 345 345 345 348 6.20 RTC — Real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.2 Resolution versus overflow and the PRESCALER . . . . . . . . . . . . . . . . . 6.20.3 COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.4 Overflow features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.5 TICK event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.6 Event control feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.7 Compare feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.8 TASK and EVENT jitter/delay . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.9 Reading the COUNTER register . . . . . . . . . . . . . . . . . . . . . . . 6.20.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21 SAADC — Successive approximation analog-to-digital converter . . . . . . . . . . . . 6.21.1 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.2 Reference voltage and gain settings . . . . . . . . . . . . . . . . . . . . . 6.21.3 Digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.5 Continuous sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.6 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.7 Event monitoring using limits . . . . . . . . . . . . . . . . . . . . . . . . 6.21.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22 SPI — Serial peripheral interface master . . . . . . . . . . . . . . . . . . . . . 6.22.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23 SPIM — Serial peripheral interface master with EasyDMA . . . . . . . . . . . . . . 6.23.1 SPI master transaction sequence . . . . . . . . . . . . . . . . . . . . . . . 6.23.2 D/CX functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23.3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23.7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24 SPIS — Serial peripheral interface slave with EasyDMA . . . . . . . . . . . . . . . . 6.24.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24.3 SPI slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25 SWI — Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26 TEMP — Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27 TWI — I2C compatible two-wire interface . . . . . . . . . . . . . . . . . . . . . 6.27.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . 6.27.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27.4 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27.5 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27.6 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 4452_021 v1.5 viii 348 348 348 349 350 350 350 351 353 355 356 361 361 362 364 364 364 366 366 366 367 367 382 383 383 386 390 391 392 393 394 394 395 396 407 408 409 409 409 411 412 423 425 425 425 425 431 432 432 432 433 433 434 435 6.27.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.27.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28 TIMER — Timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28.1 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28.2 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28.3 Task delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28.4 Task priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29 TWIM — I2C compatible two-wire interface master with EasyDMA . . . . . . . . . . . 6.29.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29.2 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29.3 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 6.29.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29.6 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . 6.29.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29.9 Pullup resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30 TWIS — I2C compatible two-wire interface slave with EasyDMA . . . . . . . . . . . . 6.30.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.2 TWI slave responding to a read command . . . . . . . . . . . . . . . . . . . 6.30.3 TWI slave responding to a write command . . . . . . . . . . . . . . . . . . . 6.30.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 6.30.5 Terminating an ongoing TWI transaction . . . . . . . . . . . . . . . . . . . . 6.30.6 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.7 Slave mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 6.30.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31 UART — Universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . 6.31.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.4 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.5 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.6 Suspending the UART . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.7 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.8 Using the UART without flow control . . . . . . . . . . . . . . . . . . . . . 6.31.9 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . . 6.31.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32 UARTE — Universal asynchronous receiver/transmitter with EasyDMA . . . . . . . . . 6.32.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.2 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.3 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.5 Using the UARTE without flow control . . . . . . . . . . . . . . . . . . . . 6.32.6 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . . 6.32.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.8 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33 USBD — Universal serial bus device . . . . . . . . . . . . . . . . . . . . . . . 4452_021 v1.5 ix 436 436 444 444 446 446 446 446 446 451 451 453 453 454 455 456 456 456 467 468 468 470 470 472 473 473 474 474 474 484 485 485 486 486 486 487 488 488 488 488 488 497 498 498 499 499 501 501 501 501 502 502 515 515 6.33.1 USB device states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.2 USB terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.3 USB pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.4 USBD power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.5 USB pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.6 USB reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.7 USB suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.8 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.9 Control transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.10 Bulk and interrupt transactions . . . . . . . . . . . . . . . . . . . . . . . 6.33.11 Isochronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.12 USB register access limitations . . . . . . . . . . . . . . . . . . . . . . . 6.33.13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33.14 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.34 WDT — Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.34.1 Reload criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.34.2 Temporarily pausing the watchdog . . . . . . . . . . . . . . . . . . . . . . 6.34.3 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.34.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.34.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware and layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 aQFN73 ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 QFN40 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 WLCSP ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 aQFN73 7 x 7 mm package . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 QFN40 5 x 5 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 WLCSP 3.175 x 3.175 mm package . . . . . . . . . . . . . . . . . . . . . . 7.3 Reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Circuit configuration no. 1 for QIAA aQFN73 . . . . . . . . . . . . . . . . . . 7.3.2 Circuit configuration no. 2 for QIAA aQFN73 . . . . . . . . . . . . . . . . . . 7.3.3 Circuit configuration no. 3 for QIAA aQFN73 . . . . . . . . . . . . . . . . . . 7.3.4 Circuit configuration no. 4 for QIAA aQFN73 . . . . . . . . . . . . . . . . . . 7.3.5 Circuit configuration no. 5 for QIAA aQFN73 . . . . . . . . . . . . . . . . . . 7.3.6 Circuit configuration no. 6 for QIAA aQFN73 . . . . . . . . . . . . . . . . . . 7.3.7 Circuit configuration no. 1 for QDAA QFN40 . . . . . . . . . . . . . . . . . . . 7.3.8 Circuit configuration no. 2 for QDAA QFN40 . . . . . . . . . . . . . . . . . . . 7.3.9 Circuit configuration no. 3 for QDAA QFN40 . . . . . . . . . . . . . . . . . . . 7.3.10 Circuit configuration no. 4 for QDAA QFN40 . . . . . . . . . . . . . . . . . . 7.3.11 Circuit configuration no. 5 for QDAA QFN40 . . . . . . . . . . . . . . . . . . 7.3.12 Circuit configuration no. 6 for QDAA QFN40 . . . . . . . . . . . . . . . . . . 7.3.13 Circuit configuration no. 1 for CJAA WLCSP . . . . . . . . . . . . . . . . . . 7.3.14 Circuit configuration no. 2 for CJAA WLCSP . . . . . . . . . . . . . . . . . . 7.3.15 Circuit configuration no. 3 for CJAA WLCSP . . . . . . . . . . . . . . . . . . 7.3.16 Circuit configuration no. 4 for CJAA WLCSP . . . . . . . . . . . . . . . . . . 7.3.17 Circuit configuration no. 5 for CJAA WLCSP . . . . . . . . . . . . . . . . . . 7.3.18 Circuit configuration no. 6 for CJAA WLCSP . . . . . . . . . . . . . . . . . . 7.3.19 PCB guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.20 PCB layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Package Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 aQFN73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4452_021 v1.5 x 516 517 518 518 519 519 520 521 522 525 527 530 530 555 555 556 556 556 556 559 560 560 560 563 565 568 568 569 569 570 572 573 575 577 579 581 583 585 587 589 591 593 595 597 599 601 603 605 607 608 610 610 610 8 Recommended operating conditions. . . . . . . . . . . . . . . . . . . . 611 8.1 Extended Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 611 8.2 WLCSP light sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 9 Absolute maximum ratings. 10 Ordering information. 10.1 10.2 10.3 10.4 10.5 . . . . . . . . . . . . . . . . . . . . . . . . 612 . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Box labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code ranges and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal notices. 4452_021 v1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 614 614 615 616 617 619 1 Revision history Date Version Description November 2021 1.5 The following content has been added or updated: • Ordering information on page 614 - Build codes Axx not recommended for new designs • May 2021 1.4 Editorial changes The following content has been added or updated: • FICR — Factory information configuration registers on page 30 Added nRF52820 value to INFO.PART register and updated INFO.VARIANT device variants • Updated access port protection in Debug and trace on page 47 and UICR — User information configuration registers on page 40 • POWER — Power supply on page 61 - Added parameter RSOURCE,VBUSVDDH and changed the value of parameter RSOURCE,VBUSVDDH to 6Ω • CLOCK — Clock control on page 82 - Added parameter VAMP,IN,XO,LOW • CCM — AES CCM mode encryption on page 110 - Added HEADERMASK register • COMP — Comparator on page 122 - Added section Shared Resources • Mechanical specifications on page 568 - Added tolerances for D and E dimensions for WLCSP package • Ordering information on page 614 - Added new product options • Updated aQFN 73, QFN40, and WLCSP variants with note on DEC5 in ™ Reference circuitry on page 570 and Pin assignments on page 560 • RADIO — 2.4 GHz radio on page 280 - Corrected conversion formula for CCAEDTHRES, CCA, or EDLEVEL value to dBm • Reference circuitry on page 570 - Updated recommended value for USB serial resistor • August 2020 April 2020 1.3 1.2 Editorial changes The following content has been added or updated: • Added WLCSP package information • Editorial changes The following content has been added or updated since the last released version: • Added information for the QFN40 package variant in Pin assignments on page 560, Mechanical specifications on page 568, Reference circuitry on page 570, Package thermal characteristics on page 610, Absolute maximum ratings on page 612 and Ordering information on page 614. • Corrected minimum valid value for EasyDMA MAXCNT and AMOUNT registers in SPIM — Serial peripheral interface master with EasyDMA on page 391, SPIS — Serial peripheral interface slave with EasyDMA on page 408, TWIM — I2C compatible two-wire interface master with EasyDMA on page 451, TWIS — I2C compatible two-wire interface slave with EasyDMA on page 468 and UARTE — Universal asynchronous receiver/transmitter with EasyDMA on page 498. 4452_021 v1.5 12 Revision history Date Version Description • Current consumption on page 55 - Added missing compounded currents. • POWER — Power supply on page 61 - Clarified REG0 elspec parameters, by renaming and adding several parameters. • RADIO — 2.4 GHz radio on page 280 - Corrected Sensitivity plot. • SPIM — Serial peripheral interface master with EasyDMA on page 391 Corrected parameter tSPIM,CSK. • Reference circuitry on page 570 - Added optional 4.7 Ω resistor to USB supply in configuration 1 for QIAA package. • Recommended operating conditions on page 611 - Added parameter TJ (juntion temperature), moved from Absolute maximum ratings on page 612. • Absolute maximum ratings on page 612 - Increased aQFN73 CDM to 750 V. Removed parameter TJ (juntion temperature), moved to Recommended operating conditions on page 611. Added footnote regarding supply voltages used in HTOL. • Legal notices on page 619 - Updated copyright date. January 2020 1.1 Not released November 2019 1.0 First release 4452_021 v1.5 13 2 About this document This document is organized into chapters that are based on the modules and peripherals available in the IC. 2.1 Document status The document status reflects the level of maturity of the document. Document name Description Objective Product Specification (OPS) Applies to document versions up to 1.0. This document contains target specifications for product development. Product Specification (PS) Applies to document versions 1.0 and higher. This document contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Table 1: Defined document names 2.2 Peripheral chapters Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for identification and reference. This name is used in chapter headings and references, and it will appear in the ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify the peripheral. The peripheral instance name, which is different from the peripheral name, is constructed using the peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in the CMSIS to identify the peripheral instance. The chapters describing peripherals may include the following information: • A detailed functional description of the peripheral • Register configuration for the peripheral • Electrical specification tables, containing performance data which apply for the operating conditions described in Recommended operating conditions on page 611. 2.3 Register tables Individual registers are described using register tables. These tables are built up of two sections. The first three colored rows describe the position and size of the different fields in the register. The following rows describe the fields in more detail. 4452_021 v1.5 14 About this document 2.3.1 Fields and values The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has enumerated values, then every value will be identified with a unique value id in the Value Id column. A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to secure forward compatibility. If a register is divided into more than one field, a unique field name is specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/ off, and so on. Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal values have no prefix. The Value column can be populated in the following ways: • Individual enumerated values, for example 1, 3, 9. • Range of values, e.g. [0..4], indicating all values from and including 0 and 4. • Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or alternatively the field's translation and limitations are described in the text instead. If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the first field. Subsequent fields will indicate inheritance with '..'. A feature marked Deprecated should not be used for new designs. 2.3.2 Permissions Different fields in a register might have different access permissions enforced by hardware. The access permission for each register field is documented in the Access column in the following ways: Access Description Hardware behavior RO Read-only Field can only be read. A write will be ignored. WO Write-only Field can only be written. A read will return an undefined value. RW Read-write Field can be read and written multiple times. W1 Write-once Field can only be written once per reset. Any subsequent write will be ignored. A read will return an undefined value. RW1 Read-write-once Field can be read multiple times, but only written once per reset. Any subsequent write will be ignored. Table 2: Register field permission schemes 2.4 Registers Register Offset Description DUMMY 0x514 Example of a register controlling a dummy feature Table 3: Register overview 2.4.1 DUMMY Address offset: 0x514 Example of a register controlling a dummy feature 4452_021 v1.5 15 About this document Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D Reset 0x00050002 ID Access Field A RW FIELD_A C C C B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Example of a read-write field with several enumerated values Disabled 0 The example feature is disabled NormalMode 1 The example feature is enabled in normal mode ExtendedMode 2 The example feature is enabled along with extra functionality B RW FIELD_B C RW FIELD_C D RW FIELD_D Example of a deprecated read-write field Disabled 0 The override feature is disabled Enabled 1 The override feature is enabled Example of a read-write field with a valid range of values ValidRange [2..7] Example of allowed values for this field Example of a read-write field with no restriction on the values 4452_021 v1.5 16 Deprecated Block diagram This block diagram illustrates the overall system. Arrows with white heads indicate signals that share physical pins with other signals. RAM5 RAM6 slave slave slave slave RAM8 GPIO P0.0 – P0.31 P1.0 – P1.09 SW-DP slave slave slave master AHB-AP AHB TO APB BRIDGE FICR UICR ETM slave AHB multilayer CTRL-AP I-Cache CPU ARM CORTEX-M4 NVIC nRESET RAM7 slave RAM4 slave RAM3 slave RAM2 slave SWCLK SWDIO TPIU RAM1 slave TP RAM0 slave nRF52833 slave CODE NVMC SysTick RNG POWER RTC [0..2] TIMER [0..4] WDT TEMP PPI XC1 XC2 XL1 XL2 CLOCK ANT RADIO EasyDMA VBUS D+ D- P0.0 – P0.31 P1.0 – P1.09 EasyDMA master EasyDMA master EasyDMA CCM AAR master USBD EasyDMA NFC2 NFC1 ECB master NFCT EasyDMA master APB0 3 SPIM [0..3] master master GPIOTE COMP AIN0 – AIN7 OUT0 – OUT3 master EasyDMA master UARTE [0..1] I2S master EasyDMA master SPIS [0..2] PDM EasyDMA master master Figure 1: Block diagram 4452_021 v1.5 SCL SDA PWM [0..3] EasyDMA CLK DIN EasyDMA TWIM [0..1] master SCL SDA QDEC EasyDMA MCK LRCK SCL SDOUT SDIN master SAADC EasyDMA LED A B EasyDMA TWIS [0..1] LPCOMP SCK MOSI MISO 17 EasyDMA RTS CTS TXD RXD CSN MISO MOSI SCK 4 Core components 4.1 CPU The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance. This processor implements the following features that enable energy-efficient arithmetic and highperformance signal processing. • • • • • Digital signal processing (DSP) instructions Single-cycle multiply and accumulate (MAC) instructions Hardware divide 8- and 16-bit single instruction multiple data (SIMD) instructions Single-precision floating-point unit (FPU) The ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM®Cortex® processor series is implemented and available for the M4 CPU. Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC). Executing code from flash memory will have a wait state penalty on the nRF52 Series. An instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache on page 25. The Electrical specification on page 19 shows CPU performance parameters including wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark. The ARM system timer (SysTick) is present on nRF52833. The SysTick's clock will only tick when the CPU is running or when the system is in debug interface mode. 4.1.1 Floating point interrupt The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in turn will trigger the FPU interrupt. See Instantiation on page 22 for more information about the exceptions triggering the FPU interrupt. To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within the floating-point status and control register (FPSCR) needs to be cleared. For more information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide. 4.1.2 CPU and support module configuration The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the IC. 4452_021 v1.5 18 Core components Option / Module Description Implemented NVIC Nested vector interrupt controller 48 vectors PRIORITIES Priority bits 3 WIC Wakeup interrupt controller NO Endianness Memory system endianness Little endian Bit-banding Bit banded memory NO DWT Data watchpoint and trace YES SysTick System tick timer YES MPU Memory protection unit YES FPU Floating-point unit YES DAP Debug access port YES ETM Embedded trace macrocell YES ITM Instrumentation trace macrocell YES TPIU Trace port interface unit YES ETB Embedded trace buffer NO FPB Flash patch and breakpoint unit YES HTM AMBA AHB trace macrocell Core options Modules ™ NO 4.1.3 Electrical specification 4.1.3.1 CPU performance The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark® benchmark. It includes power regulator and clock base currents. All other blocks are IDLE. Symbol Description WFLASH CPU wait states, running CoreMark from flash, cache Min. Typ. Max. Units 2 disabled WFLASHCACHE CPU wait states, running CoreMark from flash, cache 3 enabled WRAM CPU wait states, running CoreMark from RAM CMFLASH CoreMark, running CoreMark from flash, cache enabled 217 0 CoreMark CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache 3.4 CoreMark/ enabled CMFLASH/mA MHz CoreMark per mA, running CoreMark from flash, cache 65.8 enabled, DCDC 3V CoreMark/ mA 4.2 Memory The nRF52833 contains 512 kB of flash memory and 128 kB of RAM that can be used for code and data storage. The CPU and peripherals with EasyDMA can access memory via the AHB multilayer interconnect. In additon, peripherals are accessed by the CPU via the AHB multilayer interconnect, as shown in the following figure. 4452_021 v1.5 19 Core components ICODE AHB DCODE AHB multilayer interconnect 0x2001 8000 0x0081 8000 Section 0 0x2001 0000 0x0081 0000 RAM7 AHB slave Section 1 Section 0 0x2000 F000 0x0080 F000 0x2000 E000 0x0080 E000 RAM6 AHB slave Section 1 0x2000 D000 0x0080 D000 Section 0 0x2000 C000 0x0080 C000 RAM5 AHB slave Section 1 0x2000 B000 0x0080 B000 Section 0 0x2000 A000 0x0080 A000 RAM4 AHB slave Section 1 0x2000 9000 0x0080 9000 Section 0 0x2000 8000 0x0080 8000 RAM3 AHB slave Section 1 0x2000 7000 0x0080 7000 0x2000 6000 0x0080 6000 RAM2 AHB slave Section 1 0x2000 5000 0x0080 5000 Section 0 0x2000 4000 0x0080 4000 RAM1 AHB slave Section 1 0x2000 3000 0x0080 3000 Section 0 0x2000 2000 0x0080 2000 RAM0 AHB slave Section 1 0x2000 1000 0x0080 1000 Section 0 0x2000 0000 0x0080 0000 I-Cache System bus ICODE EasyDMA DCODE EasyDMA DMA bus Peripheral DMA bus Peripheral Code RAM Section 1 Section 0 Page 127 NVMC CPU ARM Cortex-M4 Data RAM System RAM8 AHB slave AHB slave APB AHB slave AHB2APB ICODE / DCODE Flash ICODE/DCODE 0x0007 F000 Page 3..126 0x0000 3000 Page 2 0x0000 2000 Page 1 0x0000 1000 Page 0 0x0000 0000 Figure 2: Memory layout See AHB multilayer on page 46 and EasyDMA on page 44 for more information about the AHB multilayer interconnect and EasyDMA. The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the application to partition the RAM within these regions so that one does not corrupt the other. 4.2.1 RAM - Random access memory The RAM interface is divided into nine RAM AHB slaves. RAM AHB slaves 0 to 7 are connected to two 4 kB RAM sections each, while RAM AHB slave 8 is connected to two 32 kB sections, as shown in Memory layout on page 20. Each RAM section has separate power control for System ON and System OFF mode operation, which is configured via RAM register (see the POWER — Power supply on page 61). 4.2.2 Flash - Non-volatile memory The CPU can read from flash memory an unlimited number of times, but is restricted in how it writes to flash and the number of writes and erases it can perform. Writing to flash memory is managed by the non-volatile memory controller (NVMC), see NVMC — Nonvolatile memory controller on page 23. Flash memory is divided into 128 pages of 4 kB each that can be accessed by the CPU via the ICODE and DCODE buses as shown in Memory layout on page 20. 4.2.3 Memory map The complete memory map for the nRF52833 is shown in the following figure. As described in Memory on page 19, Code RAM and Data RAM are the same physical RAM. 4452_021 v1.5 20 Core components System address map Address map 0xFFFFFFFF Device Private peripheral bus 0xE0000000 0xE0000000 Device 0xC0000000 Device 0xA0000000 RAM 0x80000000 RAM 0x60000000 AHB peripherals Peripheral APB peripherals 0x40000000 0x50000000 0x40000000 SRAM Data RAM 0x20000000 Code UICR FICR Code RAM Flash 0x00000000 Figure 3: Memory map 4452_021 v1.5 21 0x20000000 0x10001000 0x10000000 0x00800000 0x00000000 Core components 4.2.4 Instantiation ID Base address Peripheral Instance Description 0 0x40000000 APPROTECT APPROTECT APPROTECT control 0 0x40000000 CLOCK CLOCK Clock control 0 0x40000000 POWER POWER Power control 0 0x50000000 GPIO GPIO General purpose input and output 0 0x50000000 GPIO P0 General purpose input and output, port 0 0 0x50000300 GPIO P1 General purpose input and output, port 1 1 0x40001000 RADIO RADIO 2.4 GHz radio 2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter 2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA, 3 0x40003000 SPI SPI0 SPI master 0 3 0x40003000 SPIM SPIM0 SPI master 0 3 0x40003000 SPIS SPIS0 SPI slave 0 3 0x40003000 TWI TWI0 Two-wire interface master 0 3 0x40003000 TWIM TWIM0 Two-wire interface master 0 3 0x40003000 TWIS TWIS0 Two-wire interface slave 0 4 0x40004000 SPI SPI1 SPI master 1 4 0x40004000 SPIM SPIM1 SPI master 1 4 0x40004000 SPIS SPIS1 SPI slave 1 4 0x40004000 TWI TWI1 Two-wire interface master 1 4 0x40004000 TWIM TWIM1 Two-wire interface master 1 4 0x40004000 TWIS TWIS1 Two-wire interface slave 1 5 0x40005000 NFCT NFCT Near field communication tag 6 0x40006000 GPIOTE GPIOTE GPIO tasks and events 7 0x40007000 SAADC SAADC Analog to digital converter 8 0x40008000 TIMER TIMER0 Timer 0 9 0x40009000 TIMER TIMER1 Timer 1 10 0x4000A000 TIMER TIMER2 Timer 2 11 0x4000B000 RTC RTC0 Real-time counter 0 12 0x4000C000 TEMP TEMP Temperature sensor 13 0x4000D000 RNG RNG Random number generator 14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption 15 0x4000F000 AAR AAR Accelerated address resolver 15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption 16 0x40010000 WDT WDT Watchdog timer 17 0x40011000 RTC RTC1 Real-time counter 1 18 0x40012000 QDEC QDEC Quadrature decoder 19 0x40013000 COMP COMP General purpose comparator 19 0x40013000 LPCOMP LPCOMP Low power comparator 20 0x40014000 EGU EGU0 Event generator unit 0 20 0x40014000 SWI SWI0 Software interrupt 0 21 0x40015000 EGU EGU1 Event generator unit 1 21 0x40015000 SWI SWI1 Software interrupt 1 22 0x40016000 EGU EGU2 Event generator unit 2 22 0x40016000 SWI SWI2 Software interrupt 2 23 0x40017000 EGU EGU3 Event generator unit 3 23 0x40017000 SWI SWI3 Software interrupt 3 24 0x40018000 EGU EGU4 Event generator unit 4 24 0x40018000 SWI SWI4 Software interrupt 4 25 0x40019000 EGU EGU5 Event generator unit 5 Deprecated Deprecated unit 0 4452_021 v1.5 22 Deprecated Deprecated Deprecated Deprecated Core components ID Base address Peripheral Instance Description 25 0x40019000 SWI SWI5 Software interrupt 5 26 0x4001A000 TIMER TIMER3 Timer 3 27 0x4001B000 TIMER TIMER4 Timer 4 28 0x4001C000 PWM PWM0 Pulse width modulation unit 0 29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface 30 0x4001E000 ACL ACL Access control lists 30 0x4001E000 NVMC NVMC Non-volatile memory controller 31 0x4001F000 PPI PPI Programmable peripheral interconnect 32 0x40020000 MWU MWU Memory watch unit 33 0x40021000 PWM PWM1 Pulse width modulation unit 1 34 0x40022000 PWM PWM2 Pulse width modulation unit 2 35 0x40023000 SPI SPI2 SPI master 2 35 0x40023000 SPIM SPIM2 SPI master 2 35 0x40023000 SPIS SPIS2 SPI slave 2 36 0x40024000 RTC RTC2 Real-time counter 2 37 0x40025000 I2S I2S Inter-IC sound interface 38 0x40026000 FPU FPU FPU interrupt 39 0x40027000 USBD USBD Universal serial bus device 40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA, Deprecated unit 1 45 0x4002D000 PWM PWM3 Pulse width modulation unit 3 47 0x4002F000 SPIM SPIM3 SPI master 3 N/A 0x10000000 FICR FICR Factory information configuration N/A 0x10001000 UICR UICR User information configuration Table 4: Instantiation table 4.3 NVMC — Non-volatile memory controller The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the UICR (user information configuration registers). The CONFIG on page 26 is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing (CONFIG.WEN = Een). The CPU must be halted before initiating a NVMC operation from the debug system. 4.3.1 Writing to flash When write is enabled, full 32-bit words can be written to word-aligned addresses in flash memory. As illustrated in Memory on page 19, the flash is divided into multiple pages. The same 32-bit word in flash memory can only be written n WRITE number of times before a page erase must be performed. The NVMC is only able to write 0 to bits in flash memory that are erased (set to 1). It cannot rewrite a bit back to 1. Only full 32-bit words can be written to flash memory using the NVMC interface. To write less than 32 bits, write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1. The restriction on the number of writes (nWRITE) still applies in this case. Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault. The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash. NVM writing time can be reduced by using READYNEXT. If this status bit is set to 1, code can perform the next data write to the flash. This write will be buffered and will be taken into account as soon as the ongoing write operation is completed. 4452_021 v1.5 23 Core components 4.3.2 Erasing a page in flash When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page 27. After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash. See Partial erase of a page in flash on page 25 for information on dividing the page erase time into shorter chunks. 4.3.3 Writing to user information configuration registers (UICR) User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset. UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on page 28 or ERASEALL on page 27. The time it takes to write a word to UICR is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR. 4.3.4 Erasing user information configuration registers (UICR) When erase is enabled, UICR can be erased using the ERASEUICR on page 28. After erasing UICR, all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation. 4.3.5 Erase all When erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALL on page 27. This operation will not erase the factory information configuration registers (FICR). The time it takes to perform an ERASEALL command is specified by tERASEALL. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation. 4.3.6 Access port protection behavior When access port protection is enabled, parts of the NVMC functionality will be blocked in order to prevent intentional or unintentional erase of UICR. CTRL-AP ERASEALL NVMC ERASEPAGE NVMC ERASEPAGE NVMC ERASEALL NVMC ERASEUICR PARTIAL APPROTECT Disabled Allowed Allowed Allowed Allowed Allowed Enabled Allowed Allowed Allowed Allowed Blocked Table 5: NVMC Protection 4.3.7 NVMC power failure protection NVMC power failure protection is possible through use of power-fail comparator that is monitoring power supply. If the power-fail comparator is enabled, and the power supply voltage is below VPOF threshold, the powerfail comparator will prevent the NVMC from performing erase or write operations in non-volatile memory (NVM). If a power failure warning is present at the start of an NVM erase operation, the NVMC operation will be ignored. 4452_021 v1.5 24 Core components If a power failure warning is present at the start of an NVM write operation, the CPU will hardfault. 4.3.8 Partial erase of a page in flash Partial erase is a feature in the NVMC to split a page erase time into shorter chunks to prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in flash memory and does not work with UICR. When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL on page 28. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page 28. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one erase cycle. After the erase is complete, all bits in the page are set to 1. The CPU is halted if the CPU executes code from the flash while the NVMC performs the partial erase operation. The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started but the total erase time is less than tERASEPAGE. 4.3.9 Cache An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC. A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of waitstates for a cache miss, where the instruction is not available in the cache and needs to be fetched from flash, is shown in CPU on page 18. Enabling the cache can increase CPU performance and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will decrease. When disabled, the cache does not use current and does not retain its content. It is possible to enable cache profiling to analyze the performance of the cache for your program using the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every instruction cache hit or miss, respectively. The hit and miss profiling registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers. 4.3.10 Registers Base address Peripheral Instance Description 0x4001E000 NVMC NVMC Non-volatile memory controller Configuration Table 6: Instances Register Offset Description READY 0x400 Ready flag READYNEXT 0x408 Ready flag CONFIG 0x504 Configuration register ERASEPAGE 0x508 Register for erasing a page in code area ERASEPCR1 0x508 Register for erasing a page in code area, equivalent to ERASEPAGE ERASEALL 0x50C Register for erasing all non-volatile user memory ERASEPCR0 0x510 Register for erasing a page in code area, equivalent to ERASEPAGE ERASEUICR 0x514 Register for erasing user information configuration registers 4452_021 v1.5 25 Deprecated Deprecated Core components Register Offset Description ERASEPAGEPARTIAL 0x518 Register for partial erase of a page in code area ERASEPAGEPARTIALCFG 0x51C Register for partial erase configuration ICACHECNF 0x540 I-code cache configuration register IHIT 0x548 I-code cache hit counter IMISS 0x54C I-code cache miss counter Table 7: Register overview 4.3.10.1 READY Address offset: 0x400 Ready flag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Busy 0 NVMC is busy (on-going write or erase operation) Ready 1 NVMC is ready READY NVMC is ready or busy 4.3.10.2 READYNEXT Address offset: 0x408 Ready flag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Busy 0 NVMC cannot accept any write operation Ready 1 NVMC is ready READYNEXT NVMC can accept a new write operation 4.3.10.3 CONFIG Address offset: 0x504 Configuration register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW WEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. 4452_021 v1.5 Ren 0 Read only access Wen 1 Write enabled Een 2 Erase enabled 26 Core components 4.3.10.4 ERASEPAGE Address offset: 0x508 Register for erasing a page in code area Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A W Value ID Value Description ERASEPAGE Register for starting erase of a page in code area The value is the address to the page to be erased. (Addresses of first word in page). The erase must be enabled using CONFIG.WEN before the page can be erased. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased. 4.3.10.5 ERASEPCR1 ( Deprecated ) Address offset: 0x508 Register for erasing a page in code area, equivalent to ERASEPAGE Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A W Value ID Value Description ERASEPCR1 Register for erasing a page in code area, equivalent to ERASEPAGE 4.3.10.6 ERASEALL Address offset: 0x50C Register for erasing all non-volatile user memory Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ERASEALL Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the nonvolatile memory can be erased. NoOperation 0 No operation Erase 1 Start chip erase 4.3.10.7 ERASEPCR0 ( Deprecated ) Address offset: 0x510 Register for erasing a page in code area, equivalent to ERASEPAGE 4452_021 v1.5 27 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A W Value ID Value Description ERASEPCR0 Register for starting erase of a page in code area, equivalent to ERASEPAGE 4.3.10.8 ERASEUICR Address offset: 0x514 Register for erasing user information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ERASEUICR Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. NoOperation 0 No operation Erase 1 Start erase of UICR 4.3.10.9 ERASEPAGEPARTIAL Address offset: 0x518 Register for partial erase of a page in code area Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ERASEPAGEPARTIAL Register for starting partial erase of a page in code area The value is the address to the page to be partially erased (address of the first word in page). The erase must be enabled using CONFIG.WEN before every erase page partial and disabled using CONFIG.WEN after every erase page partial. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased. 4.3.10.10 ERASEPAGEPARTIALCFG Address offset: 0x51C Register for partial erase configuration 4452_021 v1.5 28 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x0000000A ID Access Field A RW DURATION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Value ID Value Description Duration of the partial erase in milliseconds The user must ensure that the total erase time is long enough for a complete erase of the flash page. 4.3.10.11 ICACHECNF Address offset: 0x540 I-code cache configuration register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID Access Field A RW CACHEEN B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable cache. Invalidates all cache entries. Enabled 1 Enable cache Disabled 0 Disable cache profiling Enabled 1 Enable cache profiling Cache enable RW CACHEPROFEN Cache profiling enable 4.3.10.12 IHIT Address offset: 0x548 I-code cache hit counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW HITS Value ID Value Description Number of cache hits. Register is writable, but only to '0'. 4.3.10.13 IMISS Address offset: 0x54C I-code cache miss counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MISSES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Number of cache misses. Register is writable, but only to '0'. 4452_021 v1.5 29 Core components 4.3.11 Electrical specification 4.3.11.1 Flash programming Symbol Description nWRITE Number of times a 32-bit word can be written before erase Min. nENDURANCE Erase cycles per page tWRITE Time to write one 32-bit word tERASEPAGE Time to erase one page tERASEALL Time to erase all flash Typ. Max. Units 2 10000 42.51 87.5 173 tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total 1 1 µs ms ms 1.091 execution time for one partial page erase is defined as ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc. 4.3.11.2 Cache size Symbol Description SizeICODE I-Code cache size Min. Typ. 2048 Max. Units Bytes 4.4 FICR — Factory information configuration registers Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration. 4.4.1 Registers Base address Peripheral Instance Description 0x10000000 FICR FICR Factory information configuration Configuration Table 8: Instances Register Offset Description CODEPAGESIZE 0x010 Code memory page size CODESIZE 0x014 Code memory size DEVICEID[0] 0x060 Device identifier DEVICEID[1] 0x064 Device identifier ER[0] 0x080 Encryption root, word 0 ER[1] 0x084 Encryption root, word 1 ER[2] 0x088 Encryption root, word 2 ER[3] 0x08C Encryption root, word 3 IR[0] 0x090 Identity Root, word 0 IR[1] 0x094 Identity Root, word 1 IR[2] 0x098 Identity Root, word 2 IR[3] 0x09C Identity Root, word 3 DEVICEADDRTYPE 0x0A0 Device address type DEVICEADDR[0] 0x0A4 Device address 0 DEVICEADDR[1] 0x0A8 Device address 1 INFO.PART 0x100 Part code 1 Applies when HFXO is used. Timing varies according to HFINT accuracy when HFINT is used. 4452_021 v1.5 30 Core components Register Offset Description INFO.VARIANT 0x104 Build code (hardware version and production configuration) INFO.PACKAGE 0x108 Package option INFO.RAM 0x10C RAM variant INFO.FLASH 0x110 Flash variant INFO.UNUSED8[0] 0x114 Reserved INFO.UNUSED8[1] 0x118 Reserved INFO.UNUSED8[2] 0x11C PRODTEST[0] 0x350 Production test signature 0 PRODTEST[1] 0x354 Production test signature 1 PRODTEST[2] 0x358 Production test signature 2 TEMP.A0 0x404 Slope definition A0 TEMP.A1 0x408 Slope definition A1 TEMP.A2 0x40C Slope definition A2 TEMP.A3 0x410 Slope definition A3 TEMP.A4 0x414 Slope definition A4 TEMP.A5 0x418 Slope definition A5 TEMP.B0 0x41C Y-intercept B0 TEMP.B1 0x420 Y-intercept B1 TEMP.B2 0x424 Y-intercept B2 TEMP.B3 0x428 Y-intercept B3 TEMP.B4 0x42C Y-intercept B4 TEMP.B5 0x430 Y-intercept B5 TEMP.T0 0x434 Segment end T0 TEMP.T1 0x438 Segment end T1 TEMP.T2 0x43C Segment end T2 TEMP.T3 0x440 Segment end T3 TEMP.T4 0x444 Segment end T4 NFC.TAGHEADER0 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFC.TAGHEADER1 0x454 NFC.TAGHEADER2 0x458 NFC.TAGHEADER3 0x45C Reserved NFCID1_2ND_LAST, and NFCID1_LAST. Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Table 9: Register overview 4.4.1.1 CODEPAGESIZE Address offset: 0x010 Code memory page size Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description CODEPAGESIZE Code memory page size 4.4.1.2 CODESIZE Address offset: 0x014 Code memory size 4452_021 v1.5 31 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description CODESIZE Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE 4.4.1.3 DEVICEID[n] (n=0..1) Address offset: 0x060 + (n × 0x4) Device identifier Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description DEVICEID 64 bit unique device identifier DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier. 4.4.1.4 ER[n] (n=0..3) Address offset: 0x080 + (n × 0x4) Encryption root, word n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description ER Encryption root, word n 4.4.1.5 IR[n] (n=0..3) Address offset: 0x090 + (n × 0x4) Identity Root, word n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description IR Identity Root, word n 4.4.1.6 DEVICEADDRTYPE Address offset: 0x0A0 Device address type 4452_021 v1.5 32 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Public 0 Public address Random 1 Random address DEVICEADDRTYPE Device address type 4.4.1.7 DEVICEADDR[n] (n=0..1) Address offset: 0x0A4 + (n × 0x4) Device address n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description DEVICEADDR 48 bit device address DEVICEADDR[0] contains the least significant bits of the device address. DEVICEADDR[1] contains the most significant bits of the device address. Only bits [15:0] of DEVICEADDR[1] are used. 4.4.1.8 INFO.PART Address offset: 0x100 Part code Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00052833 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1 Value ID Value Description N52820 0x52820 nRF52820 N52833 0x52833 nRF52833 N52840 0x52840 nRF52840 Unspecified 0xFFFFFFFF Unspecified PART Part code 4.4.1.9 INFO.VARIANT Address offset: 0x104 Build code (hardware version and production configuration) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description VARIANT Build code (hardware version and production configuration). Encoded as ASCII. 4452_021 v1.5 AAAA 0x41414141 AAAA AAAB 0x41414142 AAAB 33 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description AAA0 0x41414130 AAA0 AAA1 0x41414131 AAA1 AAB0 0x41414230 AAB0 Unspecified 0xFFFFFFFF Unspecified 4.4.1.10 INFO.PACKAGE Address offset: 0x108 Package option Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description PACKAGE Package option QD 0x2007 QDxx - 5x5 40-pin QFN QI 0x2004 QIxx - 7x7 73-pin aQFN CJ 0x2008 CJxx - 3.175 x 3.175 WLCSP Unspecified 0xFFFFFFFF Unspecified 4.4.1.11 INFO.RAM Address offset: 0x10C RAM variant Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description K16 0x10 16 kByte RAM K32 0x20 32 kByte RAM K64 0x40 64 kByte RAM K128 0x80 128 kByte RAM K256 0x100 256 kByte RAM Unspecified 0xFFFFFFFF Unspecified RAM RAM variant 4.4.1.12 INFO.FLASH Address offset: 0x110 Flash variant 4452_021 v1.5 34 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description K128 0x80 128 kByte FLASH K256 0x100 256 kByte FLASH K512 0x200 512 kByte FLASH K1024 0x400 1 MByte FLASH K2048 0x800 2 MByte FLASH Unspecified 0xFFFFFFFF Unspecified FLASH Flash variant 4.4.1.13 PRODTEST[n] (n=0..2) Address offset: 0x350 + (n × 0x4) Production test signature n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description Done 0xBB42319F Production tests done NotDone 0xFFFFFFFF Production tests not done PRODTEST Production test signature n 4.4.1.14 TEMP.A0 Address offset: 0x404 Slope definition A0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description A A (slope definition) register. 4.4.1.15 TEMP.A1 Address offset: 0x408 Slope definition A1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description A A (slope definition) register. 4.4.1.16 TEMP.A2 Address offset: 0x40C Slope definition A2 4452_021 v1.5 35 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description A A (slope definition) register. 4.4.1.17 TEMP.A3 Address offset: 0x410 Slope definition A3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description A A (slope definition) register. 4.4.1.18 TEMP.A4 Address offset: 0x414 Slope definition A4 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description A A (slope definition) register. 4.4.1.19 TEMP.A5 Address offset: 0x418 Slope definition A5 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description A A (slope definition) register. 4.4.1.20 TEMP.B0 Address offset: 0x41C Y-intercept B0 4452_021 v1.5 36 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description B B (y-intercept) 4.4.1.21 TEMP.B1 Address offset: 0x420 Y-intercept B1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description B B (y-intercept) 4.4.1.22 TEMP.B2 Address offset: 0x424 Y-intercept B2 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description B B (y-intercept) 4.4.1.23 TEMP.B3 Address offset: 0x428 Y-intercept B3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description B B (y-intercept) 4.4.1.24 TEMP.B4 Address offset: 0x42C Y-intercept B4 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description B 4452_021 v1.5 B (y-intercept) 37 Core components 4.4.1.25 TEMP.B5 Address offset: 0x430 Y-intercept B5 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description B B (y-intercept) 4.4.1.26 TEMP.T0 Address offset: 0x434 Segment end T0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description T T (segment end) register 4.4.1.27 TEMP.T1 Address offset: 0x438 Segment end T1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description T T (segment end) register 4.4.1.28 TEMP.T2 Address offset: 0x43C Segment end T2 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description T T (segment end) register 4.4.1.29 TEMP.T3 Address offset: 0x440 Segment end T3 4452_021 v1.5 38 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description T T (segment end) register 4.4.1.30 TEMP.T4 Address offset: 0x444 Segment end T4 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description T T (segment end) register 4.4.1.31 NFC.TAGHEADER0 Address offset: 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0xFFFFFF5F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 ID Access Field A R MFGID Value ID Value Description B R UD1 Unique identifier byte 1 C R UD2 Unique identifier byte 2 D R UD3 Unique identifier byte 3 Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F 4.4.1.32 NFC.TAGHEADER1 Address offset: 0x454 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0xFFFFFFFF ID Access Field A-D R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description UD[i] (i=4..7) Unique identifier byte i 4.4.1.33 NFC.TAGHEADER2 Address offset: 0x458 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 4452_021 v1.5 39 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A-D R Value ID Value Description UD[i] (i=8..11) Unique identifier byte i 4.4.1.34 NFC.TAGHEADER3 Address offset: 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A-D R Value ID Value Description UD[i] (i=12..15) Unique identifier byte i 4.5 UICR — User information configuration registers The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user-specific settings. For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 23 and Memory on page 19 chapters. 4.5.1 Registers Base address Peripheral Instance Description 0x10001000 UICR UICR User information configuration Configuration Table 10: Instances Register Offset UNUSED0 0x000 Reserved UNUSED1 0x004 Reserved UNUSED2 0x008 Reserved UNUSED3 0x010 Reserved NRFFW[0] 0x014 Reserved for Nordic firmware design NRFFW[1] 0x018 Reserved for Nordic firmware design NRFFW[2] 0x01C Reserved for Nordic firmware design NRFFW[3] 0x020 Reserved for Nordic firmware design NRFFW[4] 0x024 Reserved for Nordic firmware design NRFFW[5] 0x028 Reserved for Nordic firmware design NRFFW[6] 0x02C Reserved for Nordic firmware design NRFFW[7] 0x030 Reserved for Nordic firmware design NRFFW[8] 0x034 Reserved for Nordic firmware design NRFFW[9] 0x038 Reserved for Nordic firmware design NRFFW[10] 0x03C Reserved for Nordic firmware design NRFFW[11] 0x040 Reserved for Nordic firmware design NRFFW[12] 0x044 Reserved for Nordic firmware design 4452_021 v1.5 Description 40 Core components Register Offset Description NRFHW[0] 0x050 Reserved for Nordic hardware design NRFHW[1] 0x054 Reserved for Nordic hardware design NRFHW[2] 0x058 Reserved for Nordic hardware design NRFHW[3] 0x05C Reserved for Nordic hardware design NRFHW[4] 0x060 Reserved for Nordic hardware design NRFHW[5] 0x064 Reserved for Nordic hardware design NRFHW[6] 0x068 Reserved for Nordic hardware design NRFHW[7] 0x06C Reserved for Nordic hardware design NRFHW[8] 0x070 Reserved for Nordic hardware design NRFHW[9] 0x074 Reserved for Nordic hardware design NRFHW[10] 0x078 Reserved for Nordic hardware design NRFHW[11] 0x07C Reserved for Nordic hardware design CUSTOMER[0] 0x080 Reserved for customer CUSTOMER[1] 0x084 Reserved for customer CUSTOMER[2] 0x088 Reserved for customer CUSTOMER[3] 0x08C Reserved for customer CUSTOMER[4] 0x090 Reserved for customer CUSTOMER[5] 0x094 Reserved for customer CUSTOMER[6] 0x098 Reserved for customer CUSTOMER[7] 0x09C Reserved for customer CUSTOMER[8] 0x0A0 Reserved for customer CUSTOMER[9] 0x0A4 Reserved for customer CUSTOMER[10] 0x0A8 Reserved for customer CUSTOMER[11] 0x0AC Reserved for customer CUSTOMER[12] 0x0B0 Reserved for customer CUSTOMER[13] 0x0B4 Reserved for customer CUSTOMER[14] 0x0B8 Reserved for customer CUSTOMER[15] 0x0BC Reserved for customer CUSTOMER[16] 0x0C0 Reserved for customer CUSTOMER[17] 0x0C4 Reserved for customer CUSTOMER[18] 0x0C8 Reserved for customer CUSTOMER[19] 0x0CC Reserved for customer CUSTOMER[20] 0x0D0 Reserved for customer CUSTOMER[21] 0x0D4 Reserved for customer CUSTOMER[22] 0x0D8 Reserved for customer CUSTOMER[23] 0x0DC Reserved for customer CUSTOMER[24] 0x0E0 Reserved for customer CUSTOMER[25] 0x0E4 Reserved for customer CUSTOMER[26] 0x0E8 Reserved for customer CUSTOMER[27] 0x0EC Reserved for customer CUSTOMER[28] 0x0F0 Reserved for customer CUSTOMER[29] 0x0F4 Reserved for customer CUSTOMER[30] 0x0F8 Reserved for customer CUSTOMER[31] 0x0FC Reserved for customer PSELRESET[0] 0x200 Mapping of the nRESET function (see POWER chapter for details) PSELRESET[1] 0x204 Mapping of the nRESET function (see POWER chapter for details) APPROTECT 0x208 Access port protection NFCPINS 0x20C Setting of pins dedicated to NFC functionality: NFC antenna or GPIO DEBUGCTRL 0x210 Processor debug control REGOUT0 0x304 Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. Table 11: Register overview 4452_021 v1.5 41 Core components 4.5.1.1 NRFFW[n] (n=0..12) Address offset: 0x014 + (n × 0x4) Reserved for Nordic firmware design Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A RW NRFFW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Reserved for Nordic firmware design 4.5.1.2 NRFHW[n] (n=0..11) Address offset: 0x050 + (n × 0x4) Reserved for Nordic hardware design Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A RW NRFHW Value ID Value Description Reserved for Nordic hardware design 4.5.1.3 CUSTOMER[n] (n=0..31) Address offset: 0x080 + (n × 0x4) Reserved for customer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID Access Field A RW CUSTOMER 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Reserved for customer 4.5.1.4 PSELRESET[n] (n=0..1) Address offset: 0x200 + (n × 0x4) Mapping of the nRESET function (see POWER chapter for details) All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start independently of the levels present on any of the GPIOs. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value Description A RW PIN 18 GPIO pin number onto which nRESET is exposed B RW PORT 0 Port number onto which nRESET is exposed C RW CONNECT 4452_021 v1.5 Value ID Connection Disconnected 1 Disconnect Connected 0 Connect 42 Core components 4.5.1.5 APPROTECT Address offset: 0x208 Access port protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A RW PALL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Enable or disable access port protection. See Debug and trace on page 47 for more information. Disabled 0xFF HwDisabled 0x5A Hardware disable of access port protection for devices where access port protection is controlled by hardware Hardware disable of access port protection for devices where access port protection is controlled by hardware and software Enabled 0x00 Enable 4.5.1.6 NFCPINS Address offset: 0x20C Setting of pins dedicated to NFC functionality: NFC antenna or GPIO Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0xFFFFFFFF ID Access Field A RW PROTECT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Setting of pins dedicated to NFC functionality Disabled 0 NFC 1 Operation as GPIO pins. Same protection as normal GPIO pins. Operation as NFC antenna pins. Configures the protection for NFC operation. 4.5.1.7 DEBUGCTRL Address offset: 0x210 Processor debug control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B A A A A A A A A Reset 0xFFFFFFFF ID Access Field A RW CPUNIDEN B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Enabled 0xFF Enable CPU ITM and ETM functionality (default behavior) Disabled 0x00 Disable CPU ITM and ETM functionality Configure CPU non-intrusive debug features RW CPUFPBEN Configure CPU flash patch and breakpoint (FPB) unit behavior Enabled 0xFF Enable CPU FPB unit (default behavior) Disabled 0x00 Disable CPU FPB unit. Writes into the FPB registers will be ignored. 4452_021 v1.5 43 Core components 4.5.1.8 REGOUT0 Address offset: 0x304 Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH V_VDDH-VDD. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0xFFFFFFFF ID Access Field A RW VOUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Output voltage from REG0 regulator stage. 1V8 0 1.8 V 2V1 1 2.1 V 2V4 2 2.4 V 2V7 3 2.7 V 3V0 4 3.0 V 3V3 5 3.3 V DEFAULT 7 Default voltage: 1.8 V 4.6 EasyDMA EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM. EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for direct access to Data RAM. EasyDMA is not able to access flash. A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example, for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA example on page 44. RAM AHB multilayer Peripheral READER RAM RAM AHB EasyDMA WRITER AHB EasyDMA Figure 4: EasyDMA example 4452_021 v1.5 44 Peripheral core Core components An EasyDMA channel is implemented in the following way, but some variations may occur: READERBUFFER_SIZE 5 WRITERBUFFER_SIZE 6 uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000; uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005; // Configuring the READER channel MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE; MYPERIPHERAL->READER.PTR = &readerBuffer; // Configure the WRITER channel MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE; MYPERIPHERAL->WRITER.PTR = &writerBuffer; This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed that the peripheral will perform the following tasks: • Read 5 bytes from the readerBuffer located in RAM at address 0x20000000 • Process the data • Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005 The memory layout of these buffers is illustrated in EasyDMA memory layout on page 45. 0x20000000 readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3] 0x20000004 readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2] 0x20000008 writerBuffer[3] writerBuffer[4] writerBuffer[5] Figure 5: EasyDMA memory layout The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer (writerBuffer). Otherwise, the channel would overflow the writerBuffer. Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how many bytes WRITER wrote to RAM. Note: The PTR register of a READER or WRITER must point to a valid memory region before use. The reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page 19 for more information about the different memory regions and EasyDMA connectivity. 4.6.1 EasyDMA error handling Some errors may occur during DMA handling. If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. 4452_021 v1.5 45 Core components If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall and wait for access to be granted, or lose data. 4.6.2 EasyDMA array list EasyDMA is able to operate in Array List mode. The Array List mode is implemented in channels where the LIST register is available. The array list does not provide a mechanism to explicitly specify where the next item in the list is located. Instead, it assumes that the list is organized as a linear array where items are located one after the other in RAM. The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in the code example below using a READER EasyDMA channel as an example: #define BUFFER_SIZE 4 typedef struct ArrayList { uint8_t buffer[BUFFER_SIZE]; } ArrayList_type; ArrayList_type ReaderList[3] __at__ 0x20000000; MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE; MYPERIPHERAL->READER.PTR = &ReaderList; MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList; The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA uses the READER.MAXCNT register to determine when the buffer is full. READER.PTR = &ReaderList 0x20000000 : ReaderList[0] buffer[0] buffer[1] buffer[2] buffer[3] 0x20000004 : ReaderList[1] buffer[0] buffer[1] buffer[2] buffer[3] 0x20000008 : ReaderList[2] buffer[0] buffer[1] buffer[2] buffer[3] Figure 6: EasyDMA array list 4.7 AHB multilayer AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is resolved using priorities. Each bus master is connected to all the slave devices using an interconnection matrix. The bus masters are assigned priorities, which are used to resolve access when two (or more) bus masters request access to the same slave device. When that occurs, the following rules apply: 4452_021 v1.5 46 Core components • If two (or more) bus masters request access to the same slave device, the master with the highest priority is granted the access first. • Bus masters with lower priority are stalled until the higher priority master has completed its transaction. • If the higher priority master pauses at any point during its transaction, the lower priority master in queue is temporarily granted access to the slave device until the higher priority master resumes its activity. • Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently. Some peripherals, such as RADIO, do not have a safe stalling mechanism (no internal data buffering, or opportunity to pause incoming data). Being a low priority bus master might cause loss of data for such peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, follow these guidelines: • Avoid situations where more than one bus master is accessing the same slave. • If more than one bus master is accessing the same slave, make sure that the bus bandwidth is not exhausted. Below is a list of bus masters in the system and their priorities. Bus master name Description CPU CTRL-AP USB SPIM1/SPIS1/TWIM1/TWIS1 Same priority and mutually exclusive RADIO CCM/ECB/AAR Same priority and mutually exclusive SAADC UARTE0 SPIM0/SPIS0/TWIM0/TWIS0 Same priority and mutually exclusive SPIM2/SPIS2 Same priority and mutually exclusive NFCT I2S PDM PWM0 PWM1 PWM2 PWM3 UARTE1 SPIM3 Table 12: AHB bus masters (listed from highest to lowest priority) Defined bus masters are the CPU and peripherals with implemented EasyDMA. The available slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix is illustrated in Memory on page 19. 4.8 Debug and trace The debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging. 4452_021 v1.5 47 Core components DAP SWDCLK External debugger CTRL-AP SW-DP SWDIO NVMC Access Port Protection Enable DAP bus interconnect & UICR APPROTECT AHB-AP AHB CxxxPWRUPREQ CxxxPWRUPRACK POWER RAM & flash CPU Power ARM Cortex-M4 TRACECLK Trace TRACEDATA[0] / SWO APB/AHB ETM Peripherals TRACEDATA[1] TRACEDATA[2] TPIU TRACEDATA[3] Trace ITM Figure 7: Debug and trace overview The main features of the debug and trace system are the following: • Two-pin serial wire debug (SWD) interface • Flash patch and breakpoint (FPB) unit that supports the following comparators: • • • • • Two literal comparators • Six instruction comparators Data watchpoint and trace (DWT) unit with four comparators Instrumentation trace macrocell (ITM) Embedded trace macrocell (ETM) Trace port interface unit (TPIU) • 4-bit parallel trace of ITM and ETM trace data • Serial wire output (SWO) trace of ITM data 4.8.1 DAP - Debug access port An external debugger can access the device via the DAP. The debug access port (DAP) implements a standard ARM® CoreSight™ serial wire debug port (SW-DP), which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK and SWDIO in Debug and trace overview on page 48. In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port (CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 51. Note: • The SWDIO line has an internal pull-up resistor. • The SWDCLK line has an internal pull-down resistor. 4.8.2 Access port protection Access port protection blocks the debugger from read and write access to all CPU registers and memorymapped addresses when enabled. Access port protection is enabled and disabled differently depending on the build code of the device. 4452_021 v1.5 48 Core components Access port protection controlled by hardware This information refers to build codes Axx and earlier. By default, access port protection is disabled. Access port protection is enabled by writing UICR.APPROTECT to Enabled and performing any reset. See Reset on page 69 for more information. Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will erase the flash, UICR, and RAM, including UICR.APPROTECT. Erasing UICR will set UICR.APPROTECT value to Disabled. CTRL-AP is described in more detail in CTRL-AP - Control access port on page 51. Access port protection controlled by hardware and software This information refers to build codes Bxx and later. By default, access port protection is enabled. Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. Read CTRLAP.APPROTECTSTATUS to ensure that access port protection is disabled, and repeat the ERASEALL command if needed. This command will erase the flash, UICR, and RAM. CTRL-AP is described in more detail in CTRL-AP - Control access port on page 51. Access port protection will remain disabled until one of the following occurs: • • • • Pin reset Power or brownout reset Watchdog reset if not in Debug Interface Mode, see Debug Interface mode on page 53 Wake from System OFF if not in Emulated System OFF To keep access port protection disabled, the following actions must be performed: • Program UICR.APPROTECT to HwDisabled. This disables the hardware part of the access port protection scheme after the first reset of any type. The hardware part of the access port protection will stay disabled as long as UICR.APPROTECT is not overwritten. • Firmware must write APPROTECT.DISABLE to SwDisable. This disables the software part of the access port protection scheme. Note: Register APPROTECT.DISABLE is reset after pin reset, power or brownout reset, watchdog reset, or wake from System OFF as mentioned above. The following figure is an example on how a device with access port protection enabled can be erased, programmed, and configured to allow debugging. Operations sent from debugger as well as registers written by firmware will affect the access port state. 4452_021 v1.5 49 Core components Debugger Pi CR = UI CT e d rit TE le W PRO isab AP wD H m ra e og ar Pr mw fir n t se re P -A L RL AL C T A SE ER Closed Open Closed Open Access port state Write APPROTECT.DISABLE = SwDisable Firmware Figure 8: Access port unlocking Access port protection is enabled when the disabling conditions are not present. For additional security, it is recommended to write Enabled to UICR.APPROTECT, and have firmware write Force to APPROTECT.FORCEPROTECT. This is illustrated in the following figure. Note: Register APPROTECT.FORCEPROTECT is reset after any reset. Debugger Pi CR = UI CT e rit TE d W PRO ble a AP En n t se re m ra e og ar Pr mw fir P -A L RL AL CT ASE ER Closed Open Closed Access port state Write APPROTECT.FORCEPROTECT = Force Firmware Figure 9: Force access port protection 4.8.2.1 Registers Base address Peripheral Instance Description 0x40000000 APPROTECT APPROTECT APPROTECT control Configuration Table 13: Instances Register Offset Description FORCEPROTECT 0x550 Software force enable APPROTECT mechanism until next reset. DISABLE 0x558 Software disable APPROTECT mechanism Table 14: Register overview 4452_021 v1.5 50 Core components 4.8.2.1.1 FORCEPROTECT Address offset: 0x550 Software force enable APPROTECT mechanism until next reset. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID Access Field A RW1 FORCEPROTECT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Write 0x0 to force enable APPROTECT mechanism Force 0x0 Software force enable APPROTECT mechanism 4.8.2.1.2 DISABLE Address offset: 0x558 Software disable APPROTECT mechanism Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A RW DISABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value SwDisable 0x5A Description Software disable APPROTECT mechanism Software disable APPROTECT mechanism 4.8.3 CTRL-AP - Control access port The control access port (CTRL-AP) is a custom access port that enables control of the device when other access ports in the DAP are disabled by the access port protection. Access port protection is described in more detail in Access port protection on page 48. Control access port has the following features: • Soft reset - see Reset on page 69 for more information • Disabling of access port protection - device control is allowed through CTRL-AP even when all other access ports in DAP are disabled by access port protection 4.8.3.1 Registers Register Offset Description RESET 0x000 Soft reset triggered through CTRL-AP ERASEALL 0x004 Erase all ERASEALLSTATUS 0x008 Status register for the ERASEALL operation APPROTECTSTATUS 0x00C Status register for access port protection IDR 0x0FC CTRL-AP identification register, IDR Table 15: Register overview 4.8.3.1.1 RESET Address offset: 0x000 Soft reset triggered through CTRL-AP 4452_021 v1.5 51 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Soft reset triggered through CTRL-AP. See Reset behavior in POWER chapter for more details. NoReset 0 Reset is not active Reset 1 Reset is active. Device is held in reset. 4.8.3.1.2 ERASEALL Address offset: 0x004 Erase all Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoOperation 0 No operation Erase 1 Erase all flash and RAM ERASEALL Erase all flash and RAM 4.8.3.1.3 ERASEALLSTATUS Address offset: 0x008 Status register for the ERASEALL operation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Ready 0 ERASEALL is ready Busy 1 ERASEALL is busy (on-going) ERASEALLSTATUS Status register for the ERASEALL operation 4.8.3.1.4 APPROTECTSTATUS Address offset: 0x00C Status register for access port protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description APPROTECTSTATUS Status register for access port protection Enabled 0 Access port protection enabled Disabled 1 Access port protection not enabled 4.8.3.1.5 IDR Address offset: 0x0FC CTRL-AP identification register, IDR 4452_021 v1.5 52 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E E E E D D D D C C C C C C C B B B B Reset 0x02880000 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A R APID Value ID Value AP identification B R CLASS Access port (AP) class A A A A A A A A Description NotDefined 0x0 No defined class MEMAP 0x8 Memory access port C R JEP106ID JEDEC JEP106 identity code D R JEP106CONT JEDEC JEP106 continuation code E R REVISION Revision 4.8.3.2 Electrical specification 4.8.3.2.1 Control access port Symbol Description Rpull Internal SWDIO and SWDCLK pull up/down resistance fSWDCLK SWDCLK frequency Min. Typ. Max. 13 0.125 Units kΩ 8 MHz 4.8.4 Debug Interface mode Before an external debugger can access either CPU's access port (AHB-AP) or the control access port (CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP. If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and the DIF flag in RESETREAS on page 75 will be set. The device is in the Debug Interface mode as long as the debugger is requesting power via CxxxPWRUPREQ. Once the debugger stops requesting power via CxxxPWRUPREQ, the device is back in normal mode. Some peripherals behave differently in Debug Interface mode compared to normal mode. These differences are described in more detail in the chapters of the peripherals that are affected. When a debug session is over, the external debugger must make sure to put the device back into normal mode since the overall power consumption is higher in Debug Interface mode than in normal mode. For details on how to use the debug capabilities, read the debug documentation of your IDE. 4.8.5 Real-time debug The nRF52833 supports real-time debugging. Real-time debugging allows interrupts to execute to completion in real time when breakpoints are set in Thread mode or lower priority interrupts. This enables developers to set breakpoints and single-step through the code without the risk of real-time event-driven threads running at higher priority failing. For example, this enables the device to continue to service the high-priority interrupts of an external controller or sensor without failure or loss of state synchronization while the developer steps through code in a low-priority thread. 4.8.6 Trace The device supports ETM and ITM trace. Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port interface unit (TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Debug and trace overview on page 48. 4452_021 v1.5 53 Core components In addition to parallel trace, the TPIU supports serial trace via the serial wire output (SWO) trace protocol. Parallel and serial trace cannot be used at the same time. ETM trace is only supported in Parallel Trace mode, while ITM trace is supported in both Parallel and Serial Trace modes. For details on how to use the trace capabilities, read the debug documentation of your IDE. TPIU's trace pins are multiplexed with GPIOs. SWO and TRACEDATA[0] use the same GPIO. See Pin assignments on page 560 for more information. Trace speed is configured in register TRACECONFIG on page 95. The speed of the trace pins depends on the DRIVE setting of the GPIOs that the trace pins are multiplexed with. Only S0S1 and H0H1 drives are suitable for debugging. S0S1 is the default DRIVE setting at reset. If parallel or serial trace port signals are not fast enough with the default settings, all GPIOs in use for tracing should be set to high drive (H0H1). The DRIVE setting for these GPIOs should not be overwritten by firmware during the debugging session. 4.8.6.1 Electrical specification 4.8.6.1.1 Trace port Symbol Description Min. Tcyc Clock period as defined by Arm in the Timing specifications 62.5 for Trace Port Physical Interface of the Embedded Trace Macrocell Architecture Specification 4452_021 v1.5 54 Typ. Max. Units 500 ns 5 Power and clock management 5.1 Power management unit (PMU) Power and clock management in nRF52833 is designed to automatically ensure maximum power efficiency. The core of the power and clock management system is the power management unit (PMU) illustrated in the following figure. MCU CPU External power sources Internal voltage regulators PMU Memory External crystals Internal oscillators Peripheral Figure 10: Power management unit The PMU automatically detects which power and clock resources are required by the different system components at any given time. The PMU will then automatically start/stop and choose operation modes in supply regulators and clock sources, to achieve the lowest power consumption possible. 5.2 Current consumption Because the system is continually being tuned by the Power management unit (PMU) on page 55, estimating an application's current consumption can be challenging when measurements cannot be directly performed on the hardware. To facilitate the estimation process, a set of current consumption scenarios are provided to show the typical current drawn from the VDD supply. Each scenario specifies a set of operations and conditions applying to the given scenario. The following table shows a set of common conditions used in all scenarios, unless otherwise stated in the description of a given scenario. All scenarios are listed in Electrical specification on page 56. 4452_021 v1.5 55 Power and clock management Condition Value Supply 3 V on VDD/VDDH (Normal voltage mode) Temperature 25°C CPU WFI (wait for interrupt)/WFE (wait for event) sleep Peripherals All idle Clock Not running Regulator LDO RAM In System ON, full 128 kB powered. In System OFF, full 128 kB retention. Compiler GCC v7.3.1 20180622 (release) [ARM/embedded-7-branch revision 261907] (GNU Tools for Arm Embedded Processors 7-2018-q3-update). • Compiler flags: -O0 -falign-functions=16 -fno-strictaliasing -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16. Compiler for CPU Running and Compounded ARMCC v6.13. Cache enabled2 Yes 32 MHz crystal3 SMD 2520, 32 MHz, 10 pF +/- 10 ppm • Compiler flags: -xc -std=gnu99 --target=arm-arm-noneeabi -mcpu=cortex-m4 -mfpu=none -mfloat-abi=soft -c -fno-rtti -funsigned-char -gdwarf-3 -fropi Ofast -ffunction-sections -Omax • Linker flags: --cpu=Cortex-M4 --fpu=SoftVFP --strict Omax Table 16: Current consumption scenarios, common conditions 5.2.1 Electrical specification 5.2.1.1 Sleep Symbol Description ION_RAMOFF_EVENT System ON, no RAM retention, wake on any event Min. Typ. 1.1 Max. Units µA ION_RAMON_EVENT System ON, full 128 kB RAM retention, wake on any event 1.8 µA ION_RAMON_POF System ON, full 128 kB RAM retention, wake on any event, 1.9 µA 7.4 µA 1.8 µA 1.5 µA 2.6 µA power-fail comparator enabled ION_RAMON_GPIOTE System ON, full 128 kB RAM retention, wake on GPIOTE input (event mode) ION_RAMON_GPIOTEPORTSystem ON, full 128 kB RAM retention, wake on GPIOTE PORT event ION_RAMOFF_RTC System ON, no RAM retention, wake on RTC (running from LFRC clock) ION_RAMON_RTC System ON, full 128 kB RAM retention, wake on RTC (running from LFRC clock) 2 3 Applies only when CPU is running from flash memory Applies only when HFXO is running 4452_021 v1.5 56 Power and clock management Symbol Description Min. IOFF_RAMOFF_RESET System OFF, no RAM retention, wake on reset Typ. Max. Units 0.6 µA IOFF_RAMOFF_LPCOMP System OFF, no RAM retention, wake on LPCOMP 0.9 µA IOFF_RAMON_RESET System OFF, full 128 kB RAM retention, wake on reset 1.3 µA ION_RAMOFF_EVENT_5V System ON, no RAM retention, wake on any event, 5 V 1.3 µA 1.0 µA supply on VDDH, REG0 output = 3.3 V IOFF_RAMOFF_RESET_5V System OFF, no RAM retention, wake on reset, 5 V supply on VDDH, REG0 output = 3.3 V 9 8 Current consumption [µA] 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 Temperature Range [ºC] 1.7 V 3V 3.6 V Figure 11: System OFF, no RAM retention, wake on reset (typical values) 4452_021 v1.5 57 120 Power and clock management 16 14 Current consumption [µA] 12 10 8 6 4 2 0 -40 -20 0 20 40 60 80 100 120 Temperature Range [ºC] 1.7 V 3V 3.6 V Figure 12: System ON, no RAM retention, wake on any event (typical values) 5.2.1.2 COMP active Symbol Description ICOMP,LP COMP enabled, low power mode Min. Typ. 22.7 Max. Units µA ICOMP,NORM COMP enabled, normal mode 26.4 µA ICOMP,HS COMP enabled, high-speed mode 33.0 µA 5.2.1.3 CPU running Symbol Description ICPU0 CPU running CoreMark @64 MHz from flash, Clock = HFXO, Min. Typ. Max. Units 3.3 mA Regulator = DC/DC ICPU1 CPU running CoreMark @64 MHz from flash, Clock = HFXO 5.6 mA ICPU2 CPU running CoreMark @64 MHz from RAM, Clock = HFXO, 2.4 mA Regulator = DC/DC ICPU3 CPU running CoreMark @64 MHz from RAM, Clock = HFXO 4.7 mA ICPU4 CPU running CoreMark @64 MHz from flash, Clock = HFINT, 3.1 mA Regulator = DC/DC 5.2.1.4 NFCT active Symbol Description Min. Isense Current in SENSE STATE Iactivated Current in ACTIVATED STATE 4 4 This current does not apply when in NFC field 4452_021 v1.5 58 Typ. Max. Units 100 nA 400 µA Power and clock management 5.2.1.5 Radio transmitting/receiving Symbol Description IRADIO_TX0 Radio transmitting @ 8 dBm output power, 1 Mbps Min. Typ. Max. Units 15.5 mA 6.0 mA 3.5 mA 11.0 mA 5.4 mA 6.0 mA 6.0 mA ® Bluetooth Low Energy (BLE) mode, Clock = HFXO, Regulator = DC/DC IRADIO_TX1 Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IRADIO_TX2 Radio transmitting @ -40 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IRADIO_TX3 Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO IRADIO_TX4 Radio transmitting @ -40 dBm output power, 1 Mbps BLE mode, Clock = HFXO IRADIO_TX5 Radio transmitting @ 0 dBm output power, 250 kbit/s IEE 802.15.4-2006 mode, Clock = HFXO, Regulator = DC/DC IRADIO_RX0 Radio receiving @ 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IRADIO_RX1 Radio receiving @ 1 Mbps BLE mode, Clock = HFXO 10.5 mA IRADIO_RX2 Radio receiving @ 250 kbit/s IEE 802.15.4-2006 mode, Clock 6.2 mA = HFXO, Regulator = DC/DC 28 26 Current consumption [mA] 24 22 20 18 16 14 12 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 Supply voltage [V] -40 ºC 25 ºC 85 ºC 105 ºC Figure 13: Radio transmitting @ 8 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC (typical values) 4452_021 v1.5 59 3.6 Power and clock management 9.5 9 Current consumption [mA] 8.5 8 7.5 7 6.5 6 5.5 5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Supply voltage [V] -40 ºC 25 ºC 85 ºC 105 ºC Figure 14: Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC (typical values) 5.2.1.6 RNG active Symbol Description IRNG0 RNG running Min. Typ. Max. 539 Units µA 5.2.1.7 SAADC active Symbol Description Min. ISAADC,RUN SAADC sampling @ 16 ksps, Acquisition time = 20 µs, Clock = Typ. Max. 1.37 Units mA HFXO, Regulator = DC/DC 5.2.1.8 TEMP active Symbol Description ITEMP0 TEMP started Min. Typ. Max. 0.92 Units mA 5.2.1.9 TIMER running Symbol Description ITIMER0 One TIMER instance running @ 1 MHz, Clock = HFINT 342 µA ITIMER1 Two TIMER instances running @ 1 MHz, Clock = HFINT 341 µA ITIMER2 One TIMER instance running @ 1 MHz, Clock = HFXO 573 µA ITIMER3 One TIMER instance running @ 16 MHz, Clock = HFINT 497 µA ITIMER4 One TIMER instance running @ 16 MHz, Clock = HFXO 729 µA 4452_021 v1.5 Min. 60 Typ. Max. Units Power and clock management 5.2.1.10 USBD running Symbol Description IUSB,ACTIVE,VBUS Current from VBUS supply, USB active Min. Typ. 2.4 Max. Units mA IUSB,SUSPEND,VBUS Current from VBUS supply, USB suspended, CPU sleeping 262 µA IUSB,ACTIVE,VDD Current from VDD supply (normal voltage mode), all RAM 7.73 mA 173 µA 7.46 mA 178 µA 7 µA retained, regulator=LDO, CPU running, USB active IUSB,SUSPEND,VDD Current from VDD supply (normal voltage mode), all RAM retained, regulator=LDO, CPU sleeping, USB suspended IUSB,ACTIVE,VDDH Current from VDDH supply (high voltage mode), VDD=3 V (REG0 output), all RAM retained, regulator=LDO, CPU running, USB active IUSB,SUSPEND,VDDH Current from VDDH supply (high voltage mode), VDD=3 V (REG0 output), all RAM retained, regulator=LDO, CPU sleeping, USB suspended IUSB,DISABLED,VDD Current from VDD supply, USB disabled, VBUS supply connected, all RAM retained, regulator=LDO, CPU sleeping 5.2.1.11 WDT active Symbol Description IWDT,STARTED WDT started Min. Typ. Max. 2.5 Units µA 5.2.1.12 Compounded Symbol Description IS0 CPU running CoreMark from flash, Radio transmitting @ 0 Min. Typ. Max. Units 8.5 mA 8.3 mA 16.7 mA 16.2 mA ® dBm output power, 1 Mbps Bluetooth Low Energy (BLE) mode, Clock = HFXO, Regulator = DC/DC IS1 CPU running CoreMark from flash, Radio receiving @ 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IS2 CPU running CoreMark from flash, Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO IS3 CPU running CoreMark from flash, Radio receiving @ 1 Mbps BLE mode, Clock = HFXO 5.3 POWER — Power supply The power supply consists of a number of LDO and DC/DC regulators that are utilized to maximize the system's power efficiency. This device has the following power supply features: • • • • • • • On-chip LDO and DC/DC regulators Global System ON/OFF modes Individual RAM section power control for all system modes Analog or digital pin wakeup from System OFF Supervisor hardware to manage power-on reset, brownout, and power failure Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency Separate USB supply 4452_021 v1.5 61 Power and clock management 5.3.1 Main supply The main supply voltage is connected to the VDD/VDDH pins. The system will enter one of two supply voltage modes, Normal or High Voltage mode, depending on how the supply voltage is connected to these pins. The system enters Normal Voltage mode when the supply voltage is connected to both the VDD and VDDH pins (pin VDD shorted to pin VDDH). For the supply voltage range to connect to both VDD and VDDH pins, see parameter VDD. The system enters High Voltage mode when the supply voltage is only connected to the VDDH pin and the VDD pin is not connected to any voltage supply. For the supply voltage range to connect to the VDDH pin, see parameter VDDH. The register MAINREGSTATUS on page 78 can be used to read the current supply voltage mode. 5.3.1.1 Main voltage regulators The system contains two main supply regulator stages, REG0 and REG1. REG1 regulator stage has the regulator type options of Low-droput regulator (LDO) and Buck regulator (DC/DC). REG0 regulator stage has only the option of Low-dropout regulator (LDO). In Normal Voltage mode, only the REG1 regulator stage is used, and the REG0 stage is automatically disabled. In High Voltage mode, both regulator stages (REG0 and REG1) are used. The output voltage of REG0 can be configured in register REGOUT0 on page 44. This output voltage is connected to VDD and is the input voltage to REG1. Note: In High Voltage mode, the configured output voltage for REG0 (REGOUT0 on page 44) must not be greater than REG0 input voltage minus the voltage drop in REG0 (VDDH - VVDDH-VDD). By default, the LDO regulators are enabled and the DC/DC regulator is disabled. Register DCDCEN on page 78 is used to enable the DC/DC regulator for REG1 stage. When the DC/DC converter is enabled, the corresponding LDO regulator is disabled. External LC filter must be connected for the DC/DC regulator if it is being used. The advantage of using a DC/DC regulator is that the overall power consumption is normally reduced as the efficiency of such a regulator is higher than that of a LDO. The efficiency gained by using a DC/DC regulator is best seen when the regulator voltage drop (difference between input and output voltage) is high. The efficiency of internal regulators vary with the supply voltage and the current drawn from the regulators. Note: Do not enable the DC/DC regulator without an external LC filter being connected as this will inhibit device operation, including debug access, until an LC filter is connected. 5.3.1.2 GPIO levels The GPIO high reference voltage is equal to the level on the VDD pin. In Normal Voltage mode, the GPIO high level equals the voltage supplied to the VDD pin. In High Voltage mode, it equals the level specified in register REGOUT0 on page 44. 5.3.1.3 Regulator configuration examples The voltage regulators can be configured in several ways, depending on the selected supply voltage mode (Normal/High) and the regulator type option for REG1 (LDO or DC/DC). Four configuration examples are illustrated in the following figures. 4452_021 v1.5 62 Power and clock management Main supply REGOUT0 DCDCEN REG0 Supply REG1 LDO VDDH 1.3V System power LDO DC/DC VDD DCC DEC4 GND Figure 15: Normal Voltage mode, REG1 LDO Main supply REGOUT0 DCDCEN REG0 REG1 Supply LDO VDDH 1.3V System power LDO DC/DC VDD DCC DEC4 Figure 16: Normal Voltage mode, REG1 DC/DC 4452_021 v1.5 63 GND Power and clock management Main supply REGOUT0 DCDCEN REG0 REG1 Supply LDO VDDH 1.3V System power LDO DC/DC VDD DCC DEC4 GND Figure 17: High Voltage mode, REG1 LDO Main supply REGOUT0 DCDCEN REG0 REG1 Supply LDO VDDH 1.3V System power LDO DC/DC VDD DCC DEC4 GND Figure 18: High Voltage mode, REG1 DC/DC 5.3.1.4 Power supply supervisor The power supply supervisor enables monitoring of the connected power supply. The power supply supervisor provides the following functionality: • Power-on reset - signals the circuit when a supply is connected • An optional power-fail comparator (POF) - signals the application when the supply voltages drop below a configured threshold • A fixed brownout reset detector - holds the system in reset when the voltage is too low for safe operation 4452_021 v1.5 64 Power and clock management The power supply supervisor is illustrated in the following figure. VDD Brownout reset VBOR C Power-on reset R POFCON.POF (VDDH>VDD) POFCON.THRESHOLDVDDH 4.2 V ........... 2.8 V VDDH MUX VPOFH 2.7 V POFWARN 2.8 V ........... 1.8 V VDD VPOF MUX 1.7 V POFCON.THRESHOLD POFCON.POF Figure 19: Power supply supervisor 5.3.1.5 Power-fail comparator Using the power-fail comparator (POF) is optional. When enabled, it can provide an early warning to the CPU of an impending power supply failure. To enable and configure the power-fail comparator, see the register POFCON on page 77. When the supply voltage falls below the defined threshold, the power-fail comparator generates an event (POFWARN) that can be used by an application to prepare for power failure. This event is also generated when the supply voltage is already below the threshold at the time the power-fail comparator is enabled, or if the threshold is re-configured to a level above the supply voltage. 4452_021 v1.5 65 Power and clock management If the power failure warning is enabled, and the supply voltage is below the threshold, the power-fail comparator will prevent the NVMC from performing write operations to the flash. The comparator features a hysteresis of VHYST, as illustrated in the following figure. Supply (VDD or VDDH) VPOF+VHYST VPOF 1.7V POFWARN MCU POFWARN t BOR Figure 20: Power-fail comparator (BOR = brownout reset) To save power, the power-fail comparator is not active in System OFF or System ON when HFCLK is not running. 5.3.2 USB supply When using the USB peripheral, a 5 V USB supply needs to be provided to the VBUS pin. The USB peripheral has a dedicated internal voltage regulator for converting the VBUS supply to 3.3 V used by the USB signalling interface (D+ and D- lines, and pull-up on D+). The remainder of the USB peripheral (USBD) is supplied through the main supply like other on-chip features. As a consequence, VBUS and either VDDH or VDD supplies are required for USB peripheral operation. When VBUS rises into its valid range, the software is notified through a USBDETECTED event. A USBREMOVED event is sent when VBUS goes below its valid range. Use these events to implement the USBD start-up sequence described in the USBD chapter. When VBUS rises into its valid range while the device is in System OFF, the device resets and transitions to System ON mode. The RESETREAS register will have the VBUS bit set to indicate the source of the wake-up. See VBUS detection specifications on page 82 for the levels at which the events are sent (VBUS,DETECT and VBUS,REMOVE) or at which the system is woken up from System OFF (VBUS,DETECT). When the USBD peripheral is enabled through the ENABLE register, and VBUS is detected, the regulator is turned on. A USBPWRRDY event is sent when the regulator's worst case settling time has elapsed, indicating to the software that it can enable the USB pull-up to signal a USB connection to the host. The software can read the state of the VBUS detection and regulator output readiness at any time through the USBREGSTATUS register. 4452_021 v1.5 66 Power and clock management USB supply 5 V USB supply VBUS 3.3 V USB power LDO DECUSB Figure 21: USB voltage regulator To ensure stability, the input and output of the USB regulator need to be decoupled with a suitable decoupling capacitor. See Reference circuitry on page 570 for the recommended values. 5.3.3 System OFF mode System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core functionality is powered down and all ongoing tasks are terminated. The device can be put into System OFF mode using the register SYSTEMOFF on page 76. When in System OFF mode, the device can be woken up through one of the following signals: • • • • • The DETECT signal, optionally generated by the GPIO peripheral. The ANADETECT signal, optionally generated by the LPCOMP module. The SENSE signal, optionally generated by the NFC module to wake-on-field. Detecting a valid USB voltage on the VBUS pin (VBUS,DETECT). A reset. The system is reset when it wakes up from System OFF mode. One or more RAM sections can be retained in System OFF mode, depending on the settings in the RAM[n].POWER registers. RAM[n].POWER are retained registers. These registers are usually overwritten by the start-up code provided with the nRF application examples. Before entering System OFF mode, all on-going EasyDMA transactions need to have completed. See peripheral specific chapters for more information about how to acquire the status of EasyDMA transactions. 5.3.3.1 Emulated System OFF mode If the device is in Debug Interface mode, System OFF will be emulated to secure that all required resources needed for debugging are available during System OFF. Required resources needed for debugging include the following key components: 4452_021 v1.5 67 Power and clock management • • • • • • • Debug and trace on page 47 CLOCK — Clock control on page 82 POWER — Power supply on page 61 NVMC — Non-volatile memory controller on page 23 CPU on page 18 Flash memory RAM See Debug and trace on page 47 for more information. Because the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be executed. 5.3.4 System ON mode System ON is the default state after power-on reset. In System ON mode, all functional blocks such as the CPU or peripherals can be in IDLE or RUN mode, depending on the configuration set by the software and the state of the application executing. Register RESETREAS on page 75 provides information about the source causing the wakeup or reset. The system can switch the appropriate internal power sources on and off, depending on the amount of power needed at any given time. The power requirement of a peripheral is directly related to its activity level, and the activity level of a peripheral fluctuates when specific tasks are triggered or events are generated. 5.3.4.1 Sub-power modes In System ON mode, when the CPU and all peripherals are in IDLE mode, the system can reside in one of the two sub-power modes. The sub-power modes are: • Constant Latency • Low-power In Constant Latency mode, the CPU wakeup latency and the PPI task response are constant and kept at a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. The cost of constant and predictable latency is increased power consumption. Constant Latency mode is selected by triggering the CONSTLAT task. In Low-power mode, the automatic power management system described in System ON mode on page 68 ensures that the most efficient supply option is chosen to save power. The cost of having the lowest possible power consumption is a varying CPU wakeup latency and PPI task response. Low-power mode is selected by triggering the LOWPWR task. When the system enters System ON mode, it is by default in the sub-power mode Low-power. 5.3.5 RAM power control The RAM power control registers are used for configuring the following: • The RAM sections to be retained during System OFF • The RAM sections to be retained and accessible during System ON In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding register RAM[n].POWER (n=0..8) on page 79. In System ON, retention and accessibility of a RAM section is configured in the RETENTION and POWER fields of the corresponding register RAM[n].POWER (n=0..8) on page 79. 4452_021 v1.5 68 Power and clock management The following table summarizes the behavior of these registers. Configuration RAM section status System on/off RAM[n].POWER.POWER RAM[n].POWER.RETENTION Accessible Retained Off x Off No No Off x On No Yes On Off Off No No No Yes Yes Yes On Off On On On x 5 Table 17: RAM section configuration The advantage of not retaining RAM contents is that the overall current consumption is reduced. See Memory on page 19 for more information on RAM sections. 5.3.6 Reset Several sources may trigger a reset. After a reset has occurred, register RESETREAS can be read to determine which source triggered the reset. 5.3.6.1 Power-on reset The power-on reset generator initializes the system at power-on. The system is held in reset state until the supply has reached the minimum operating voltage and the internal voltage regulators have started. 5.3.6.2 Pin reset A pin reset is generated when the physical reset pin on the device is asserted. Pin reset is configured via both registers PSELRESET[n] (n=0..1) on page 42. 5.3.6.3 Wakeup from System OFF mode reset The device is reset when it wakes up from System OFF mode. The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in Debug Interface mode. See chapter Debug and trace on page 47 for more information. 5.3.6.4 Soft reset A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR) in the ARM® core is set. See ARM documentation for more details. A soft reset can also be generated via the register RESET on page 51 in the CTRL-AP. 5.3.6.5 Watchdog reset A Watchdog reset is generated when the watchdog times out. See chapter WDT — Watchdog timer on page 555 for more information. 5 Not useful. RAM section power off gives negligible reduction in current consumption when retention is on. 4452_021 v1.5 69 Power and clock management 5.3.6.6 Brownout reset The brownout reset generator puts the system in a reset state if VDD drops below the brownout reset (BOR) threshold. See section Power fail comparator on page 81 for more information. 5.3.6.7 Retained registers A retained register is one that will retain its value in System OFF mode and through a reset, depending on the reset source. See the individual peripheral chapters for information on which of their registers are retained. 5.3.6.8 Reset behavior The various reset sources and their targets are summarized in the table below. Reset source Reset target CPU Peripherals GPIO x x x Soft reset x x x Wakeup from System OFF x x Watchdog reset 10 x x Pin reset x Brownout reset x Power-on reset x Debug6 SWJ-DP RAM WDT Retained RESETREAS registers CPU lockup 7 x8 x9 x x x x x x x x x x x x x x x x x x x x x x x x x x x x mode reset Note: The RAM is never reset, but depending on a reset source the content of RAM may be corrupted. 5.3.7 Registers Base address Peripheral Instance Description 0x40000000 POWER POWER Power control Configuration Table 18: Instances Register Offset Description TASKS_CONSTLAT 0x78 Enable Constant Latency mode TASKS_LOWPWR 0x7C Enable Low-power mode (variable latency) EVENTS_POFWARN 0x108 Power failure warning EVENTS_SLEEPENTER 0x114 CPU entered WFI/WFE sleep 6 7 8 9 10 All debug components excluding SWJ-DP. See Debug and trace on page 47 for more information about the different debug components. Reset from CPU lockup is disabled if the device is in Debug Interface mode. CPU lockup is not possible in System OFF. The debug components will not be reset if the device is in Debug Interface mode. RAM is not reset on wakeup from System OFF mode. RAM, or certain parts of RAM, may not be retained after the device has entered System OFF mode, depending on the settings in the RAM registers. Watchdog reset is not available in System OFF. 4452_021 v1.5 70 Power and clock management Register Offset Description EVENTS_SLEEPEXIT 0x118 CPU exited WFI/WFE sleep EVENTS_USBDETECTED 0x11C Voltage supply detected on VBUS EVENTS_USBREMOVED 0x120 Voltage supply removed from VBUS EVENTS_USBPWRRDY 0x124 USB 3.3 V supply ready INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt RESETREAS 0x400 Reset reason RAMSTATUS 0x428 RAM status register USBREGSTATUS 0x438 USB supply status SYSTEMOFF 0x500 System OFF register POFCON 0x510 Power-fail comparator configuration GPREGRET 0x51C General purpose retention register GPREGRET2 0x520 General purpose retention register DCDCEN 0x578 Enable DC/DC converter for REG1 stage MAINREGSTATUS 0x640 Main supply status RAM[0].POWER 0x900 RAM0 power control register RAM[0].POWERSET 0x904 RAM0 power control set register RAM[0].POWERCLR 0x908 RAM0 power control clear register RAM[1].POWER 0x910 RAM1 power control register RAM[1].POWERSET 0x914 RAM1 power control set register RAM[1].POWERCLR 0x918 RAM1 power control clear register RAM[2].POWER 0x920 RAM2 power control register RAM[2].POWERSET 0x924 RAM2 power control set register RAM[2].POWERCLR 0x928 RAM2 power control clear register RAM[3].POWER 0x930 RAM3 power control register RAM[3].POWERSET 0x934 RAM3 power control set register RAM[3].POWERCLR 0x938 RAM3 power control clear register RAM[4].POWER 0x940 RAM4 power control register RAM[4].POWERSET 0x944 RAM4 power control set register RAM[4].POWERCLR 0x948 RAM4 power control clear register RAM[5].POWER 0x950 RAM5 power control register RAM[5].POWERSET 0x954 RAM5 power control set register RAM[5].POWERCLR 0x958 RAM5 power control clear register RAM[6].POWER 0x960 RAM6 power control register RAM[6].POWERSET 0x964 RAM6 power control set register RAM[6].POWERCLR 0x968 RAM6 power control clear register RAM[7].POWER 0x970 RAM7 power control register RAM[7].POWERSET 0x974 RAM7 power control set register RAM[7].POWERCLR 0x978 RAM7 power control clear register RAM[8].POWER 0x980 RAM8 power control register RAM[8].POWERSET 0x984 RAM8 power control set register RAM[8].POWERCLR 0x988 RAM8 power control clear register Deprecated Table 19: Register overview 5.3.7.1 TASKS_CONSTLAT Address offset: 0x78 Enable Constant Latency mode 4452_021 v1.5 71 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_CONSTLAT Enable Constant Latency mode Trigger task 5.3.7.2 TASKS_LOWPWR Address offset: 0x7C Enable Low-power mode (variable latency) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_LOWPWR Enable Low-power mode (variable latency) Trigger task 5.3.7.3 EVENTS_POFWARN Address offset: 0x108 Power failure warning Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_POFWARN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Power failure warning 5.3.7.4 EVENTS_SLEEPENTER Address offset: 0x114 CPU entered WFI/WFE sleep Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_SLEEPENTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CPU entered WFI/WFE sleep 5.3.7.5 EVENTS_SLEEPEXIT Address offset: 0x118 CPU exited WFI/WFE sleep 4452_021 v1.5 72 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_SLEEPEXIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CPU exited WFI/WFE sleep 5.3.7.6 EVENTS_USBDETECTED Address offset: 0x11C Voltage supply detected on VBUS Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_USBDETECTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Voltage supply detected on VBUS 5.3.7.7 EVENTS_USBREMOVED Address offset: 0x120 Voltage supply removed from VBUS Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_USBREMOVED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Voltage supply removed from VBUS 5.3.7.8 EVENTS_USBPWRRDY Address offset: 0x124 USB 3.3 V supply ready Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_USBPWRRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated USB 3.3 V supply ready 5.3.7.9 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.5 73 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C B Reset 0x00000000 ID Access Field A RW POFWARN B C D E F A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event POFWARN RW SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER RW SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT RW USBDETECTED Write '1' to enable interrupt for event USBDETECTED RW USBREMOVED Write '1' to enable interrupt for event USBREMOVED RW USBPWRRDY Write '1' to enable interrupt for event USBPWRRDY 5.3.7.10 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C B Reset 0x00000000 ID Access Field A RW POFWARN B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event POFWARN Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW USBDETECTED 4452_021 v1.5 A Write '1' to disable interrupt for event USBDETECTED Clear 1 Disable Disabled 0 Read: Disabled 74 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C B Reset 0x00000000 ID E F Access Field A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Read: Enabled RW USBREMOVED Write '1' to disable interrupt for event USBREMOVED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW USBPWRRDY Write '1' to disable interrupt for event USBPWRRDY Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 5.3.7.11 RESETREAS Address offset: 0x400 Reset reason Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on-reset or a brownout reset. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I H G F E Reset 0x00000000 ID Access Field A RW RESETPIN B C D E Value ID Value Description NotDetected 0 Not detected Detected 1 Detected NotDetected 0 Not detected Detected 1 Detected Reset from pin-reset detected RW DOG Reset from watchdog detected RW SREQ Reset from soft reset detected NotDetected 0 Not detected Detected 1 Detected NotDetected 0 Not detected Detected 1 Detected RW LOCKUP Reset from CPU lock-up detected RW OFF Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO F NotDetected 0 Not detected Detected 1 Detected RW LPCOMP Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP G NotDetected 0 Not detected Detected 1 Detected RW DIF Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode H NotDetected 0 Not detected Detected 1 Detected RW NFC Reset due to wake up from System OFF mode by NFC field detect NotDetected 4452_021 v1.5 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not detected 75 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I H G F E Reset 0x00000000 ID I Access Field D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Detected 1 Detected RW VBUS Reset due to wake up from System OFF mode by VBUS rising into valid range NotDetected 0 Not detected Detected 1 Detected 5.3.7.12 RAMSTATUS ( Deprecated ) Address offset: 0x428 RAM status register Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to a block comprising RAM0.S0 and RAM1.S0. RAM block 1 is equivalent to a block comprising RAM2.S0 and RAM3.S0. RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0. RAM block 3 is equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any of the RAM sections associated with a block are on. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A-D R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RAMBLOCK[i] (i=0..3) RAM block i is on or off/powering up Off 0 Off On 1 On 5.3.7.13 USBREGSTATUS Address offset: 0x438 USB supply status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description VBUSDETECT VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) B R NoVbus 0 VBUS voltage below valid threshold VbusPresent 1 VBUS voltage above valid threshold NotReady 0 USBREG output settling time not elapsed Ready 1 USBREG output settling time elapsed (same information as OUTPUTRDY USB supply output settling time elapsed USBPWRRDY event) 5.3.7.14 SYSTEMOFF Address offset: 0x500 System OFF register 4452_021 v1.5 76 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Enter 1 Description SYSTEMOFF Enable System OFF mode Enable System OFF mode 5.3.7.15 POFCON Address offset: 0x510 Power-fail comparator configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D Reset 0x00000000 ID Access Field A RW POF B B B B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable power failure warning RW THRESHOLD Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. D V17 4 Set threshold to 1.7 V V18 5 Set threshold to 1.8 V V19 6 Set threshold to 1.9 V V20 7 Set threshold to 2.0 V V21 8 Set threshold to 2.1 V V22 9 Set threshold to 2.2 V V23 10 Set threshold to 2.3 V V24 11 Set threshold to 2.4 V V25 12 Set threshold to 2.5 V V26 13 Set threshold to 2.6 V V27 14 Set threshold to 2.7 V V28 15 Set threshold to 2.8 V RW THRESHOLDVDDH Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). 4452_021 v1.5 V27 0 Set threshold to 2.7 V V28 1 Set threshold to 2.8 V V29 2 Set threshold to 2.9 V V30 3 Set threshold to 3.0 V V31 4 Set threshold to 3.1 V V32 5 Set threshold to 3.2 V V33 6 Set threshold to 3.3 V V34 7 Set threshold to 3.4 V V35 8 Set threshold to 3.5 V V36 9 Set threshold to 3.6 V V37 10 Set threshold to 3.7 V V38 11 Set threshold to 3.8 V 77 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D Reset 0x00000000 ID Access Field B B B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description V39 12 Set threshold to 3.9 V V40 13 Set threshold to 4.0 V V41 14 Set threshold to 4.1 V V42 15 Set threshold to 4.2 V 5.3.7.16 GPREGRET Address offset: 0x51C General purpose retention register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A RW GPREGRET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description General purpose retention register This register is a retained register 5.3.7.17 GPREGRET2 Address offset: 0x520 General purpose retention register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A RW GPREGRET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description General purpose retention register This register is a retained register 5.3.7.18 DCDCEN Address offset: 0x578 Enable DC/DC converter for REG1 stage Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW DCDCEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable DC/DC converter for REG1 stage. 5.3.7.19 MAINREGSTATUS Address offset: 0x640 Main supply status 4452_021 v1.5 78 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Normal 0 Normal voltage mode. Voltage supplied on VDD. High 1 High voltage mode. Voltage supplied on VDDH. MAINREGSTATUS Main supply status 5.3.7.20 RAM[n].POWER (n=0..8) Address offset: 0x900 + (n × 0x10) RAMn power control register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A-P RW S[i]POWER (i=0..15) Value ID e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A Value Description Keep RAM section Si on or off in System ON mode. RAM sections are always retained when on, but can also be retained when off depending on the settings in SiRETENTION. All RAM sections will be off in System OFF mode. Q-f Off 0 Off On 1 On Off 0 Off On 1 On RW S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is off 5.3.7.21 RAM[n].POWERSET (n=0..8) Address offset: 0x904 + (n × 0x10) RAMn power control set register When read, this register will return the value of the POWER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x0000FFFF ID Access Field A-P W Q-f W e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value On 1 Description S[i]POWER (i=0..15) Keep RAM section Si of RAMn on or off in System ON mode On S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is switched off On 1 On 5.3.7.22 RAM[n].POWERCLR (n=0..8) Address offset: 0x908 + (n × 0x10) RAMn power control clear register When read, this register will return the value of the POWER register. 4452_021 v1.5 79 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A-P W Q-f W e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A Value ID Value Off 1 Description S[i]POWER (i=0..15) Keep RAM section Si of RAMn on or off in System ON mode Off S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is switched off Off 1 Off 5.3.8 Electrical specification 5.3.8.1 Regulator operating conditions Symbol Description Min. VDD,POR VDD supply voltage needed during power-on reset 1.75 Typ. Max. Units VDD Normal voltage mode operating voltage 1.7 3.0 3.6 V VDDH High voltage mode operating voltage 2.5 3.7 5.5 V CVDD Effective decoupling capacitance on the VDD pin 2.7 4.7 5.5 µF CDEC4 Effective decoupling capacitance on the DEC4 pin 0.7 1 1.3 µF Typ. Max. Units V 5.3.8.2 Regulator specifications, REG0 stage Symbol Description Min. VREG0OUT REG0 output voltage 1.8 3.3 V VREG0OUT,ERR REG0 output voltage error (deviation from setting in -10 5 % -10 7 % REGOUT0 on page 44) VREG0OUT,ERR,EXT REG0 output voltage error (deviation from setting in REGOUT0 on page 44), extended temperature range VVDDH-VDD Required difference between input voltage (VDDH) and 0.3 V output voltage (VDD, configured in REGOUT0 on page 44), VDDH > VDD 5.3.8.3 Device startup times Symbol Description tPOR Time in power-on reset after supply reaches minimum Min. Typ. Max. Units 1 10 ms operating voltage, depending on supply rise time tPOR,10µs VDD rise time 10 µs11 tPOR,10ms 9 VDD rise time 10 ms tPOR,60ms VDD rise time 60 ms11 tRISE,REG0OUT REG0 output (VDD) rise time after VDDH reaches minimum 11 ms 23 110 ms 0.22 1.55 ms VDDH supply voltage11 tRISE,REG0OUT,10µs VDDH rise time 10 µs11 tRISE,REG0OUT,10ms VDDH rise time 10 ms tRISE,REG0OUT,100ms VDDH rise time 100 ms11 tPINR Reset time when using pin reset, depending on pin 5 11 30 50 ms 80 ms 32.5 ms capacitance tPINR,500nF 11 500 nF capacitance at reset pin See Recommended operating conditions on page 611 for more information. 4452_021 v1.5 80 Power and clock management Symbol Description Min. Typ. Max. Units tPINR,10µF 10 µF capacitance at reset pin tR2ON Time from power-on reset to System ON 650 ms tR2ON,NOTCONF If reset pin not configured tPOR ms tR2ON,CONF If reset pin configured tPOR + ms tOFF2ON Time from OFF to CPU execute 16.5 µs tIDLE2CPU Time from IDLE to CPU execute 3.0 µs tEVTSET,CL1 Time from HW event to PPI event in Constant Latency 0.0625 µs 0.0625 µs tPINR System ON mode tEVTSET,CL0 Time from HW event to PPI event in Low Power System ON mode 5.3.8.4 Power fail comparator Symbol Description Min. VPOF,NV Nominal power level warning thresholds (falling supply Typ. Max. Units 1.7 2.8 V 2.7 4.2 V -5 5 % 60 mV 1.62 V voltage) in Normal voltage mode (supply on VDD). Levels are configurable between Min. and Max. in 100 mV increments VPOF,HV Nominal power level warning thresholds (falling supply voltage) in High voltage mode (supply on VDDH). Levels are configurable in 100 mV increments VPOFTOL Threshold voltage tolerance (applies in both Normal voltage mode and High voltage mode) VPOFHYST Threshold voltage hysteresis (applies in both Normal voltage 40 50 mode and High voltage mode) VBOR,OFF Brownout reset voltage range System OFF mode. Brownout 1.2 only applies to the voltage on VDD VBOR,ON Brownout reset voltage range System ON mode. Brownout 1.57 1.6 1.63 V only applies to the voltage on VDD 5.3.8.5 USB operating conditions Symbol Description Min. Typ. Max. Units VBUS Supply voltage on VBUS pin 4.35 5 5.5 V VDPDM Voltage on D+ and D- lines VSS - 0.3 VUSB33 V + 0.3 5.3.8.6 USB regulator specifications Symbol Description IUSB,QUIES USB regulator quiescent current drawn from VBUS (USBD Min. Typ. Max. Units 170 µA 1 ms enabled) tUSBPWRRDY Time from USB enabled to USBPWRRDY event triggered, VBUS supply provided VUSB33 On voltage at the USB regulator output (DECUSB pin) 3.0 RSOURCE,VBUS Maximum source resistance on VBUS, including cable, when 3.3 3.6 V 6 Ω 3.8 Ω 5.5 µF VDDH is not connected to VBUS RSOURCE,VBUSVDDH Maximum source resistance on VBUS, including cable, when VDDH is connected to VBUS CDECUSB 4452_021 v1.5 Decoupling capacitor on the DECUSB pin 2.35 81 4.7 Power and clock management 5.3.8.7 VBUS detection specifications Symbol Description Min. Typ. Max. Units VBUS,DETECT Voltage at which rising VBUS gets reported by USBDETECTED 3.4 4.0 4.3 V VBUS,REMOVE Voltage at which decreasing VBUS gets reported by 3.0 3.6 3.9 V USBREMOVED 5.4 CLOCK — Clock control The clock control system can source the system clocks from a range of internal or external high and low frequency oscillators and distribute them to modules based upon a module’s individual requirements. Clock distribution is automated and grouped independently by module to limit current consumption in unused branches of the clock tree. Listed here are the main features for CLOCK: • • • • • • • 64 MHz on-chip oscillator 64 MHz crystal oscillator, using external 32 MHz crystal 32.768 kHz +/-500 ppm RC oscillator 32.768 kHz crystal oscillator, using external 32.768 kHz crystal 32.768 kHz oscillator synthesized from 64 MHz oscillator Firmware (FW) override control of crystal oscillator activity for low latency start up Automatic internal oscillator and clock control, and distribution for ultra-low power HFCLKSTART HFCLKSTOP LFCLKSTART LFCLKSTOP CLOCK HFINT Internal oscillator PCLK1M PCLK16M XC1 PCLK32M HFCLK Clock control HFXO Crystal oscillator 32 MHz HCLK64M XC2 LFRC RC oscillator CAL SYNT XL1 LFXO Crystal oscillator 32.768 kHz LFCLK Clock control PCLK32KI XL2 HFCLKSTARTED LFCLKSTARTED Figure 22: Clock control 5.4.1 HFCLK controller The HFCLK controller provides several clock signals in the system. These are as follows: 4452_021 v1.5 82 Power and clock management • • • • HCLK64M: 64 MHz CPU clock PCLK1M: 1 MHz peripheral clock PCLK16M: 16 MHz peripheral clock PCLK32M: 32 MHz peripheral clock The HFCLK controller uses the following high frequency clock (HFCLK) sources: • 64 MHz internal oscillator (HFINT) • 64 MHz crystal oscillator (HFXO) For illustration, see Clock control on page 82. The HFCLK controller will automatically provide the clock(s) requested by the system. If the system does not request any clocks from the HFCLK controller, the controller will enter a power saving mode. The HFINT source will be used when HFCLK is requested and HFXO has not been started. The HFXO is started by triggering the HFCLKSTART task and stopped by triggering the HFCLKSTOP task. When the HFCLKSTART task is triggered, the HFCLKSTARTED event is generated once the HFXO startup time has elapsed. The HFXO startup time is given as the sum of the following: • HFXO power-up time, as specified in 64 MHz crystal oscillator (HFXO) on page 95. • HFXO debounce time, as specified in register HFXODEBOUNCE on page 94. The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz RC oscillator. 5.4.1.1 64 MHz crystal oscillator (HFXO) The 64 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal. The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Circuit diagram of the 64 MHz crystal oscillator on page 83 shows how the 32 MHz crystal is connected to the 64 MHz crystal oscillator. XC1 XC2 C1 C2 32 MHz crystal Figure 23: Circuit diagram of the 64 MHz crystal oscillator The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by: 4452_021 v1.5 83 Power and clock management C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. For more information, see Reference circuitry on page 570. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins. See table 64 MHz crystal oscillator (HFXO) on page 95. The load capacitors C1 and C2 should have the same value. For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance, and drive level must comply with the specifications in table 64 MHz crystal oscillator (HFXO) on page 95. It is recommended to use a crystal with lower than maximum load capacitance and/or shunt capacitance. A low load capacitance will reduce both start up time and current consumption. 5.4.2 LFCLK controller The system supports several low frequency clock sources. As illustrated in Clock control on page 82, the system supports the following low frequency clock sources: • 32.768 kHz RC oscillator (LFRC) • 32.768 kHz crystal oscillator (LFXO) • 32.768 kHz synthesized from HFCLK (LFSYNT) The LFCLK controller and all of the LFCLK clock sources are always switched off when in System OFF mode. The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page 93 and then triggering the LFCLKSTART task. If the LFXO is selected as the clock source, the LFCLK will initially start running from the 32.768 kHz LFRC while the LFXO is starting up and automatically switch to using the LFXO once this oscillator is running. The LFCLKSTARTED event will be generated when the LFXO has been started. The register LFXODEBOUNCE on page 94 is used to configure the LFXO debounce time. The register must be modified if operating in the Extended Operating Conditions temperature range, see Recommended operating conditions on page 611. The LFXO start up time will be increased as a result. The LFCLK clock is stopped by triggering the LFCLKSTOP task. Register LFCLKSRC on page 93 controls the clock source, and its allowed swing. The truth table for various situations is as follows: 4452_021 v1.5 84 Power and clock management SRC EXTERNAL BYPASS Comment 0 0 0 Normal operation, LFRC is source 0 0 1 DO NOT USE 0 1 X DO NOT USE 1 0 0 Normal XTAL operation 1 1 0 Apply external low swing signal to XL1, ground XL2 1 1 1 Apply external full swing signal to XL1, leave XL2 grounded or unconnected 1 0 1 DO NOT USE 2 0 0 Normal operation, LFSYNT is source 2 0 1 DO NOT USE 2 1 X DO NOT USE Table 20: LFCLKSRC configuration depending on clock source It is not allowed to write to register LFCLKSRC on page 93 when the LFCLK is running. A LFCLKSTOP task will stop the LFCLK oscillator. However, the LFCLKSTOP task can only be triggered after the STATE field in register LFCLKSTAT on page 93 indicates LFCLK running state. The synthesized 32.768 kHz clock depends on the HFCLK to run. If high accuracy is required for the LFCLK running off the synthesized 32.768 kHz clock, the HFCLK must running from the HFXO source. 5.4.2.1 32.768 kHz RC oscillator (LFRC) The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC). The LFRC oscillator does not require additional external components. The LFRC frequency will be affected by variation in temperature. The LFRC oscillator can be calibrated to improve accuracy by using the HFXO as a reference oscillator during calibration. 5.4.2.2 Calibrating the 32.768 kHz RC oscillator After the LFRC oscillator is started and running, it can be calibrated by triggering the CAL task. The LFRC oscillator will then temporarily request the HFCLK to be used as a reference for the calibration. A DONE event will be generated when calibration has finished. The HFCLK crystal oscillator has to be started (by triggering the HFCLKSTART task) in order for the calibration mechanism to work. It is not allowed to stop the LFRC during an ongoing calibration. 5.4.2.3 Calibration timer The calibration timer can be used to time the calibration interval of the 32.768 kHz RC oscillator. The calibration timer is started by triggering the CTSTART task and stopped by triggering the CTSTOP task. The calibration timer will always start counting down from the value specified in CTIV ( Retained ) on page 95 and generate a CTTO event when it reaches 0. The calibration timer will automatically stop when it reaches 0. CTSTART CTSTARTED CTSTOP CTSTOPPED Calibration timer CTIV CTTO Figure 24: Calibration timer After a CTSTART task has been triggered, the calibration timer will ignore further tasks until it has returned the CTSTARTED event. Likewise, after a CTSTOP task has been triggered, the calibration timer will ignore further tasks until it has returned a CTSTOPPED event. Triggering CTSTART while the calibration timer 4452_021 v1.5 85 Power and clock management is running will immediately return a CTSTARTED event. Triggering CTSTOP when the calibration timer is stopped will immediately return a CTSTOPPED event. 5.4.2.4 32.768 kHz crystal oscillator (LFXO) For higher LFCLK accuracy (when better than +/- 500 ppm accuracy is required), the low frequency crystal oscillator (LFXO) must be used. The following external clock sources are supported: • Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded. • Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Circuit diagram of the 32.768 kHz crystal oscillator on page 86 shows the LFXO circuitry. XL1 XL2 C1 C2 32.768 kHz crystal Figure 25: Circuit diagram of the 32.768 kHz crystal oscillator The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by: C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins (see Low frequency crystal oscillator (LFXO) on page 96). The load capacitors C1 and C2 should have the same value. For more information, see Reference circuitry on page 570. 5.4.2.5 32.768 kHz synthesized from HFCLK (LFSYNT) LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the accuracy of the HFCLK. Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power consumption as the HFCLK will need to be requested in the system. 4452_021 v1.5 86 Power and clock management 5.4.3 Registers Base address Peripheral Instance Description 0x40000000 CLOCK CLOCK Clock control Configuration Table 21: Instances Register Offset Description TASKS_HFCLKSTART 0x000 Start HFXO crystal oscillator TASKS_HFCLKSTOP 0x004 Stop HFXO crystal oscillator TASKS_LFCLKSTART 0x008 Start LFCLK TASKS_LFCLKSTOP 0x00C Stop LFCLK TASKS_CAL 0x010 Start calibration of LFRC TASKS_CTSTART 0x014 Start calibration timer TASKS_CTSTOP 0x018 Stop calibration timer EVENTS_HFCLKSTARTED 0x100 HFXO crystal oscillator started EVENTS_LFCLKSTARTED 0x104 LFCLK started EVENTS_DONE 0x10C Calibration of LFRC completed EVENTS_CTTO 0x110 Calibration timer timeout EVENTS_CTSTARTED 0x128 Calibration timer has been started and is ready to process new tasks EVENTS_CTSTOPPED 0x12C Calibration timer has been stopped and is ready to process new tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt HFCLKRUN 0x408 Status indicating that HFCLKSTART task has been triggered HFCLKSTAT 0x40C HFCLK status LFCLKRUN 0x414 Status indicating that LFCLKSTART task has been triggered LFCLKSTAT 0x418 LFCLK status LFCLKSRCCOPY 0x41C Copy of LFCLKSRC register, set when LFCLKSTART task was triggered LFCLKSRC 0x518 Clock source for the LFCLK HFXODEBOUNCE 0x528 HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. LFXODEBOUNCE 0x52C LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the CTIV 0x538 Calibration timer interval TRACECONFIG 0x55C Clocking options for the trace port debug interface LFCLKSRC register is configured for Xtal. Retained Table 22: Register overview 5.4.3.1 TASKS_HFCLKSTART Address offset: 0x000 Start HFXO crystal oscillator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_HFCLKSTART Start HFXO crystal oscillator Trigger 1 Trigger task 5.4.3.2 TASKS_HFCLKSTOP Address offset: 0x004 4452_021 v1.5 87 Power and clock management Stop HFXO crystal oscillator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_HFCLKSTOP Stop HFXO crystal oscillator Trigger 1 Trigger task 5.4.3.3 TASKS_LFCLKSTART Address offset: 0x008 Start LFCLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_LFCLKSTART Start LFCLK Trigger task 5.4.3.4 TASKS_LFCLKSTOP Address offset: 0x00C Stop LFCLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_LFCLKSTOP Stop LFCLK Trigger task 5.4.3.5 TASKS_CAL Address offset: 0x010 Start calibration of LFRC Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_CAL Start calibration of LFRC Trigger task 5.4.3.6 TASKS_CTSTART Address offset: 0x014 Start calibration timer 4452_021 v1.5 88 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_CTSTART Start calibration timer Trigger task 5.4.3.7 TASKS_CTSTOP Address offset: 0x018 Stop calibration timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_CTSTOP Stop calibration timer Trigger task 5.4.3.8 EVENTS_HFCLKSTARTED Address offset: 0x100 HFXO crystal oscillator started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_HFCLKSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated HFXO crystal oscillator started 5.4.3.9 EVENTS_LFCLKSTARTED Address offset: 0x104 LFCLK started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_LFCLKSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated LFCLK started 5.4.3.10 EVENTS_DONE Address offset: 0x10C Calibration of LFRC completed 4452_021 v1.5 89 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Calibration of LFRC completed 5.4.3.11 EVENTS_CTTO Address offset: 0x110 Calibration timer timeout Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CTTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Calibration timer timeout 5.4.3.12 EVENTS_CTSTARTED Address offset: 0x128 Calibration timer has been started and is ready to process new tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CTSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Calibration timer has been started and is ready to process new tasks NotGenerated 0 Event not generated Generated 1 Event generated 5.4.3.13 EVENTS_CTSTOPPED Address offset: 0x12C Calibration timer has been stopped and is ready to process new tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CTSTOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Calibration timer has been stopped and is ready to process new tasks NotGenerated 0 Event not generated Generated 1 Event generated 5.4.3.14 INTENSET Address offset: 0x304 4452_021 v1.5 90 Power and clock management Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E Reset 0x00000000 ID Access Field A RW HFCLKSTARTED B C D E F D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event HFCLKSTARTED Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW DONE Write '1' to enable interrupt for event DONE Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CTTO Write '1' to enable interrupt for event CTTO Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CTSTARTED Write '1' to enable interrupt for event CTSTARTED Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CTSTOPPED Write '1' to enable interrupt for event CTSTOPPED Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 5.4.3.15 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E Reset 0x00000000 ID Access Field A RW HFCLKSTARTED B C D B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event HFCLKSTARTED RW LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED RW DONE Write '1' to disable interrupt for event DONE RW CTTO 4452_021 v1.5 D C Write '1' to disable interrupt for event CTTO 91 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E Reset 0x00000000 ID E F Access Field D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CTSTARTED Write '1' to disable interrupt for event CTSTARTED RW CTSTOPPED Write '1' to disable interrupt for event CTSTOPPED 5.4.3.16 HFCLKRUN Address offset: 0x408 Status indicating that HFCLKSTART task has been triggered Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotTriggered 0 Task not triggered Triggered 1 Task triggered STATUS HFCLKSTART task triggered or not 5.4.3.17 HFCLKSTAT Address offset: 0x40C HFCLK status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID Access Field A R B R Value ID Value Description RC 0 64 MHz internal oscillator (HFINT) Xtal 1 64 MHz crystal oscillator (HFXO) NotRunning 0 HFCLK not running Running 1 HFCLK running SRC Source of HFCLK STATE HFCLK state 5.4.3.18 LFCLKRUN Address offset: 0x414 Status indicating that LFCLKSTART task has been triggered 4452_021 v1.5 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotTriggered 0 Task not triggered Triggered 1 Task triggered STATUS LFCLKSTART task triggered or not 5.4.3.19 LFCLKSTAT Address offset: 0x418 LFCLK status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID Access Field A R B R A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RC 0 32.768 kHz RC oscillator (LFRC) Xtal 1 32.768 kHz crystal oscillator (LFXO) Synth 2 32.768 kHz synthesized from HFCLK (LFSYNT) NotRunning 0 LFCLK not running Running 1 LFCLK running SRC Source of LFCLK STATE LFCLK state 5.4.3.20 LFCLKSRCCOPY Address offset: 0x41C Copy of LFCLKSRC register, set when LFCLKSTART task was triggered Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RC 0 32.768 kHz RC oscillator (LFRC) Xtal 1 32.768 kHz crystal oscillator (LFXO) Synth 2 32.768 kHz synthesized from HFCLK (LFSYNT) SRC Clock source 5.4.3.21 LFCLKSRC Address offset: 0x518 Clock source for the LFCLK 4452_021 v1.5 93 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B Reset 0x00000000 ID Access Field A RW SRC B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RC 0 32.768 kHz RC oscillator (LFRC) Xtal 1 32.768 kHz crystal oscillator (LFXO) Synth 2 32.768 kHz synthesized from HFCLK (LFSYNT) Clock source RW BYPASS Enable or disable bypass of LFCLK crystal oscillator with external clock source C Disabled 0 Disable (use with Xtal or low-swing external source) Enabled 1 Enable (use with rail-to-rail external source) Disabled 0 Disable external source (use with Xtal) Enabled 1 Enable use of external source instead of Xtal (SRC needs to RW EXTERNAL Enable or disable external source for LFCLK be set to Xtal) 5.4.3.22 HFXODEBOUNCE Address offset: 0x528 HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. The EVENTS_HFCLKSTARTED event is generated after the HFXO power up time + the HFXO debounce time has elapsed. It is not allowed to change the value of this register while the HFXO is starting. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000010 ID Access Field A RW HFXODEBOUNCE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Value ID Value Description 0x01..0xFF HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 µs. Db256us 0x10 Db1024us 0x40 256 µs debounce time. Recommended for 1.6 mm x 2.0 mm crystals and larger. 1024 µs debounce time. Recommended for 1.6 mm x 1.2 mm crystals and smaller. 5.4.3.23 LFXODEBOUNCE Address offset: 0x52C LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. The EVENTS_LFCLKSTARTED event is generated after the LFXO debounce time has elapsed. It is not allowed to change the value of this register while the LFXO is starting. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW LFXODEBOUNCE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Normal 0 Extended 1 Description LFXO debounce time. 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. 4452_021 v1.5 94 Power and clock management 5.4.3.24 CTIV ( Retained ) Address offset: 0x538 This register is a retained register Calibration timer interval Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000000 ID Access Field A RW CTIV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. 5.4.3.25 TRACECONFIG Address offset: 0x55C Clocking options for the trace port debug interface This register is a retained register. Reset behavior is the same as debug components. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B Reset 0x00000000 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW TRACEPORTSPEED Value ID Value Description Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. B 32MHz 0 32 MHz trace port clock (TRACECLK = 16 MHz) 16MHz 1 16 MHz trace port clock (TRACECLK = 8 MHz) 8MHz 2 8 MHz trace port clock (TRACECLK = 4 MHz) 4MHz 3 4 MHz trace port clock (TRACECLK = 2 MHz) RW TRACEMUX Pin multiplexing of trace signals. See pin assignment chapter for more details. GPIO 0 Serial 1 Parallel 2 No trace signals routed to pins. All pins can be used as regular GPIOs. SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. 5.4.4 Electrical specification 5.4.4.1 64 MHz internal oscillator (HFINT) Symbol Description fNOM_HFINT Nominal output frequency Min. 64 fTOL_HFINT Frequency tolerance ±1.5 fTOL_HFINT,EXT Frequency tolerance, extended temperature range 5.4.4.2 64 MHz crystal oscillator (HFXO) 4452_021 v1.5 95 Typ. Max. Units MHz ±8 % ±9 % Power and clock management Symbol Description Min. Typ. fNOM_HFXO Nominal output frequency 64 fXTAL_HFXO External crystal frequency 32 fTOL_HFXO Frequency tolerance requirement for 2.4 GHz proprietary Max. Units MHz MHz ±60 ppm ±40 ppm ±30 ppm radio applications fTOL_HFXO_BLE Frequency tolerance requirement, Bluetooth low energy applications, packet length ≤ 200 bytes fTOL_HFXO_BLE_LP Frequency tolerance requirement, Bluetooth low energy applications, packet length > 200 bytes CL_HFXO Load capacitance 12 pF C0_HFXO Shunt capacitance 7 pF RS_HFXO_7PF Equivalent series resistance 3 pF < C0 ≤ 7 pF 60 Ω RS_HFXO_3PF Equivalent series resistance C0 ≤ 3 pF 100 Ω PD_HFXO Drive level 100 µW CPIN_HFXO Input capacitance XC1 and XC2 ISTBY_X32M Core standby current for various crystals ISTBY_X32M_X0 Typical parameters for a given 2.5mm x 2.0mm crystal: 3 pF 65 µA 110 µA 360 µA 785 µA 60 µs 200 µs CL_HFXO = 8 pF, C0_HFXO = 1 pF, LM_HFXO = 7 mH, RS_HFXO = 20 Ω ISTBY_X32M_X1 Typical parameters for a given 1.6mm x 1.2mm crystal: CL_HFXO = 8 pF, C0_HFXO = 0.4 pF, LM_HFXO = 20 mH, RS_HFXO = 40 Ω ISTART_X32M Average startup current for various crystals, first 1 ms ISTART_X32M_X0 Typical parameters for a given 2.5mm x 2.0mm crystal: CL_HFXO = 8 pF, C0_HFXO = 1 pF, LM_HFXO = 7 mH, RS_HFXO = 20 Ω ISTART_X32M_X1 Typical parameters for a given 1.6mm x 1.2mm crystal: CL_HFXO = 8 pF, C0_HFXO = 0.4 pF, LM_HFXO = 20 mH, RS_HFXO = 40 Ω tPOWERUP_X32M Power-up time for various crystals tPOWERUP_X32M_X0 Typical parameters for a given 2.5mm x 2.0mm crystal: CL_HFXO = 8 pF, C0_HFXO = 1 pF, LM_HFXO = 7 mH, RS_HFXO = 20 Ω tPOWERUP_X32M_X1 Typical parameters for a given 1.6mm x 1.2mm crystal: CL_HFXO = 8 pF, C0_HFXO = 0.4 pF, LM_HFXO = 20 mH, RS_HFXO = 40 Ω 5.4.4.3 Low frequency crystal oscillator (LFXO) Symbol Description fNOM_LFXO Crystal frequency fTOL_LFXO_BLE Frequency tolerance requirement for BLE stack ±500 ppm fTOL_LFXO_ANT Frequency tolerance requirement for ANT stack ±50 ppm CL_LFXO Load capacitance 12.5 pF C0_LFXO Shunt capacitance 2 pF RS_LFXO Equivalent series resistance 100 kΩ PD_LFXO Drive level 0.5 μW Cpin Input capacitance on XL1 and XL2 pads 4 pF ILFXO Run current for 32.768 kHz crystal oscillator 0.23 µA tSTART_LFXO Startup time for 32.768 kHz crystal oscillator 0.25 s 4452_021 v1.5 Min. Typ. Max. 32.768 96 Units kHz Power and clock management Symbol Description Min. tSTART_LFXO_EXT Startup time for 32.768 kHz crystal oscillator when Typ. Max. 0.5 Units s CLOCK.LFXODEBOUNCE configured for Extended debounce time VAMP,IN,XO,LOW Peak to peak amplitude for external low swing clock. Input 200 1000 mV Max. Units signal must not swing outside supply rails. 5.4.4.4 Low frequency RC oscillator (LFRC) Symbol Description fNOM_LFRC Nominal frequency fTOL_LFRC Frequency tolerance, uncalibrated Min. Typ. 32.768 kHz ±5 % ±500 ppm fTOL_CAL_LFRC Frequency tolerance after calibration ILFRC Run current 0.7 µA tSTART_LFRC Startup time 1000 μs 12 5.4.4.5 Synthesized low frequency clock (LFSYNT) Symbol Description fNOM_LFSYNT Nominal frequency 12 Min. Typ. 32.768 Max. Units kHz Constant temperature within ±0.5 °C, calibration performed at least every 8 seconds, averaging interval > 7.5 ms, defined as 3 sigma 4452_021 v1.5 97 6 Peripherals 6.1 Peripheral interface Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral events are indicated to the CPU by event registers and interrupts if they are configured for a given event. Task signal from PPI Peripheral TASK write OR k SHORTS task Peripheral core event INTEN m EVENT m IRQ signal to NVIC Event signal to PPI Figure 26: Tasks, events, shortcuts, and interrupts 6.1.1 Peripheral ID Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit registers. See Instantiation on page 22 for more information about which peripherals are available and where they are located in the address map. There is a direct relationship between peripheral ID and base address. For example, a peripheral with base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a peripheral with base address 0x4001F000 is assigned ID=31. Peripherals may share the same ID, which may impose one or more of the following limitations: • Some peripherals share some registers or other common resources. • Operation is mutually exclusive. Only one of the peripherals can be used at a time. • Switching from one peripheral to another must follow a specific pattern (disable the first, then enable the second peripheral). 4452_021 v1.5 98 Peripherals 6.1.2 Peripherals with shared ID In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used simultaneously. The user can only enable one peripheral at the time on this specific ID. When switching between two peripherals sharing an ID, the user should do the following to prevent unwanted behavior: 1. Disable the previously used peripheral. 2. Remove any programmable peripheral interconnect (PPI) connections set up for the peripheral that is being disabled. 3. Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF. 4. Explicitly configure the peripheral that you are about to enable and do not rely on configuration values that may be inherited from the peripheral that was disabled. 5. Enable the now configured peripheral. See which peripherals are sharing ID in Instantiation on page 22. 6.1.3 Peripheral registers Most peripherals feature an ENABLE register. Unless otherwise specified in the relevant chapter, the peripheral registers (in particular the PSEL registers) must be configured before enabling the peripheral. The peripheral must be enabled before tasks and events can be used. 6.1.4 Bit set and clear Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables firmware to set and clear individual bits in a register without having to perform a read-modify-write operation on the main register. This pattern is implemented using three consecutive addresses in the register map, where the main register is followed by dedicated SET and CLR registers (in that exact order). The SET register is used to set individual bits in the main register while the CLR register is used to clear individual bits in the main register. Writing 1 to a bit in SET or CLR register will set or clear the same bit in the main register respectively. Writing 0 to a bit in SET or CLR register has no effect. Reading the SET or CLR register returns the value of the main register. Note: The main register may not be visible and hence not directly accessible in all cases. 6.1.5 Tasks Tasks are used to trigger actions in a peripheral, for example to start a particular behavior. A peripheral can implement multiple tasks with each task having a separate register in that peripheral's task register group. A task is triggered when firmware writes 1 to the task register, or when the peripheral itself or another peripheral toggles the corresponding task signal. See Tasks, events, shortcuts, and interrupts on page 98. 6.1.6 Events Events are used to notify peripherals and the CPU about events that have happened, for example a state change in a peripheral. A peripheral may generate multiple events with each event having a separate register in that peripheral’s event register group. An event is generated when the peripheral itself toggles the corresponding event signal, and the event register is updated to reflect that the event has been generated. See Tasks, events, shortcuts, and interrupts on page 98. An event register is only cleared when firmware writes 0 to it. 4452_021 v1.5 99 Peripherals Events can be generated by the peripheral even when the event register is set to 1. 6.1.7 Shortcuts A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is enabled, the associated task is automatically triggered when its associated event is generated. Using a shortcut is the equivalent to making the same connection outside the peripheral and through the PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay through the PPI. Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum of 32 shortcuts for each peripheral. 6.1.8 Interrupts All peripherals support interrupts. Interrupts are generated by events. A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example, the peripheral with ID=4 is connected to interrupt number 4 in the nested vectored interrupt controller (NVIC). Using the INTEN, INTENSET, and INTENCLR registers, every event generated by a peripheral can be configured to generate that peripheral's interrupt. Multiple events can be enabled to generate interrupts simultaneously. To resolve the correct interrupt source, the event registers in the event group of peripheral registers will indicate the source. Some peripherals implement only INTENSET and INTENCLR registers, and the INTEN register is not available on those peripherals. See the individual peripheral chapters for details. In all cases, reading back the INTENSET or INTENCLR register returns the same information as in INTEN. Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET, and INTENCLR registers. The relationship between tasks, events, shortcuts, and interrupts is shown in Tasks, events, shortcuts, and interrupts on page 98. Interrupt clearing Clearing an interrupt by writing 0 to an event register, or disabling an interrupt using the INTENCLR register, can take up to four CPU clock cycles to take effect. This means that an interrupt may reoccur immediately, even if a new event has not come, if the program exits an interrupt handler after the interrupt is cleared or disabled but before four clock cycles have passed. Note: To avoid an interrupt reoccurring before a new event has come, the program should perform a read from one of the peripheral registers. For example, the event register that has been cleared, or the INTENCLR register that has been used to disable the interrupt. This will cause a one to threecycle delay and ensure the interrupt is cleared before exiting the interrupt handler. Care should be taken to ensure the compiler does not remove the read operation as an optimization. If the program can guarantee a four-cycle delay after an event is cleared or an interrupt is disabled, then a read of a register is not required. 4452_021 v1.5 100 Peripherals 6.2 AAR — Accelerated address resolver Accelerated address resolver is a cryptographic support function for implementing the Resolvable Private Address Resolution procedure described in Bluetooth Core Specification v4.0. Resolvable Private Address generation should be achieved using ECB and is not supported by AAR. The procedure allows two devices that share a secret key to generate and resolve a hash based on their device address. The AAR block enables real-time address resolution on incoming packets when configured as described in this chapter. This allows real-time packet filtering (whitelisting) using a list of known shared keys (Identity Resolving Keys (IRK) in Bluetooth). 6.2.1 EasyDMA AAR implements EasyDMA for reading and writing to RAM. EasyDMA will have finished accessing RAM when the END, RESOLVED, and NOTRESOLVED events are generated. If the IRKPTR on page 106, ADDRPTR on page 106, and the SCRATCHPTR on page 106 is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. 6.2.2 Resolving a resolvable address A private resolvable address is composed of six bytes according to the Bluetooth Core Specification. LSB MSB random hash (24-bit) 10 prand (24-bit) Figure 27: Resolvable address To resolve an address, the register ADDRPTR on page 106 must point to the start of the packet. The resolver is started by triggering the START task. A RESOLVED event is generated when AAR manages to resolve the address using one of the Identity Resolving Keys (IRK) found in the IRK data structure. AAR will use the IRK specified in the register IRK0 to IRK15 starting from IRK0. The register NIRK on page 105 specifies how many IRKs should be used. The AAR module will generate a NOTRESOLVED event if it is not able to resolve the address using the specified list of IRKs. AAR will go through the list of available IRKs in the IRK data structure and for each IRK try to resolve the address according to the Resolvable Private Address Resolution Procedure described in the Bluetooth Core specification v4.0 [Vol 3] chapter 10.8.2.3. The time it takes to resolve an address varies due to the location in the list of the resolvable address. The resolution time will also be affected by RAM accesses performed by other peripherals and the CPU. See the Electrical specifications for more information about resolution time. AAR only compares the received address to those programmed in the module without checking the address type. AAR will stop as soon as it has managed to resolve the address, or after trying to resolve the address using NIRK number of IRKs from the IRK data structure. AAR will generate an END event after it has stopped. 4452_021 v1.5 101 Peripherals SCRATCHPTR ADDR: resolvable address START Scratch area ADDRPTR RESOLVED AAR S0 L S1 IRK data structure ADDR IRKPTR Figure 28: Address resolution with packet preloaded into RAM 6.2.3 Example The following example shows how to chain RADIO packet reception with address resolution using AAR. AAR may be started as soon as the 6 bytes required by AAR have been received by RADIO and stored in RAM. The ADDRPTR pointer must point to the start of packet. SCRATCHPTR S0: S0 field of RADIO (optional) L: Length field of RADIO (optional) S1: S1 field of RADIO (optional) ADDR: resolvable address START PACKETPTR ADDRPTR Scratch area RESOLVED AAR S0 L S1 IRK data structure ADDR IRKPTR From remote transmitter RADIO RXEN Figure 29: Address resolution with packet loaded into RAM by RADIO 6.2.4 IRK data structure The IRK data structure is located in RAM at the memory location specified by the IRKPTR register. Property Address offset Description IRK0 0 IRK number 0 (16 bytes) IRK1 16 IRK number 1 (16 bytes) .. .. .. IRK15 240 IRK number 15 (16 bytes) Table 23: IRK data structure overview 6.2.5 Registers Base address Peripheral Instance Description Configuration 0x4000F000 AAR AAR Accelerated address resolver Table 24: Instances Register Offset Description TASKS_START 0x000 Start resolving addresses based on IRKs specified in the IRK data structure TASKS_STOP 0x008 Stop resolving addresses EVENTS_END 0x100 Address resolution procedure complete 4452_021 v1.5 102 Peripherals Register Offset Description EVENTS_RESOLVED 0x104 Address resolved EVENTS_NOTRESOLVED 0x108 Address not resolved INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt STATUS 0x400 Resolution status ENABLE 0x500 Enable AAR NIRK 0x504 Number of IRKs IRKPTR 0x508 Pointer to IRK data structure ADDRPTR 0x510 Pointer to the resolvable address SCRATCHPTR 0x514 Pointer to data area used for temporary storage Table 25: Register overview 6.2.5.1 TASKS_START Address offset: 0x000 Start resolving addresses based on IRKs specified in the IRK data structure Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_START Start resolving addresses based on IRKs specified in the IRK data structure Trigger 1 Trigger task 6.2.5.2 TASKS_STOP Address offset: 0x008 Stop resolving addresses Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stop resolving addresses Trigger task 6.2.5.3 EVENTS_END Address offset: 0x100 Address resolution procedure complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_END 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Address resolution procedure complete 103 Peripherals 6.2.5.4 EVENTS_RESOLVED Address offset: 0x104 Address resolved Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RESOLVED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Address resolved 6.2.5.5 EVENTS_NOTRESOLVED Address offset: 0x108 Address not resolved Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_NOTRESOLVED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Address not resolved 6.2.5.6 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW END B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event END RW RESOLVED Write '1' to enable interrupt for event RESOLVED RW NOTRESOLVED Write '1' to enable interrupt for event NOTRESOLVED 6.2.5.7 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.5 104 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW END B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event END RW RESOLVED Write '1' to disable interrupt for event RESOLVED RW NOTRESOLVED Write '1' to disable interrupt for event NOTRESOLVED 6.2.5.8 STATUS Address offset: 0x400 Resolution status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID STATUS Value Description [0..15] The IRK that was used last time an address was resolved 6.2.5.9 ENABLE Address offset: 0x500 Enable AAR Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 3 Enable Enable or disable AAR 6.2.5.10 NIRK Address offset: 0x504 Number of IRKs Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A Reset 0x00000001 ID Access Field A RW NIRK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description [1..16] Number of Identity Root Keys available in the IRK data structure 4452_021 v1.5 105 Peripherals 6.2.5.11 IRKPTR Address offset: 0x508 Pointer to IRK data structure Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW IRKPTR Value ID Value Description Pointer to the IRK data structure 6.2.5.12 ADDRPTR Address offset: 0x510 Pointer to the resolvable address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID A RW ADDRPTR Value Description Pointer to the resolvable address (6-bytes) 6.2.5.13 SCRATCHPTR Address offset: 0x514 Pointer to data area used for temporary storage Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW SCRATCHPTR Value ID Value Description Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. 6.2.6 Electrical specification 6.2.6.1 AAR Electrical Specification Symbol Description Min. tAAR Address resolution time per IRK. Total time for several IRKs Typ. Max. Units 6 µs 49 µs is given as (1 µs + n * t_AAR), where n is the number of IRKs. (Given priority to the actual destination RAM block). tAAR,8 Time for address resolution of 8 IRKs. (Given priority to the actual destination RAM block). 6.3 ACL — Access control lists The Access control lists (ACL) peripheral is designed to assign and enforce access permission schemes for different regions of the on-chip flash memory map. 4452_021 v1.5 106 Peripherals Flash memory regions can be assigned individual ACL permission schemes. The following registers are involved: • PERM register - configures permission schemes • ADDR register - defines the flash page start address (word-aligned) • SIZE register - determines the size of the region where the permission schemes are applied Note: The size of the region is restricted to a multiple of the flash page size, measured in bytes. The maximum region is limited to half the size of the flash page. See Memory on page 19 for more information. On-chip flash memory ... l 31 0 ACL[7].ADDR Page N ACL[7].SIZE 0 0 1 l 31 Write protect 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 l 31 Page N+1 ACL[7].PERM 0 ... l 31 Page 3 ACL[0].ADDR 0 Page 2 Page 1 l0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 31 ACL[0].SIZE 0 1 1 l 31 Page 0 ACL[0].PERM 0 Figure 30: On-chip flash memory protected regions There are four defined ACL permission schemes, each with different combinations of read/write permissions, as shown in the following table. 4452_021 v1.5 107 Read/ Write protect Peripherals Read Write Protection description 0 0 No protection. Entire region can be executed, read, written to, or erased. 0 1 Region can be executed and read, but not written to or erased. 1 0 Region can be written to and erased, but not executed or read. 1 1 Region is locked for all access until next reset. Table 26: ACL permission schemes Note: If a permission violation to a protected region is detected by the ACL peripheral, the request is blocked and a Bus Fault exception is triggered. Access control to a configured region is enforced by the hardware. This goes into effect two CPU clock cycles after the ADDR, SIZE, and PERM registers for an ACL instance are written successfully. There are two dependencies for protection to be enforced. First, a valid start address for the flash page boundary must be written to the ADDR register. Second, the SIZE and PERM registers cannot be zero. The ADDR, SIZE, and PERM registers can only be written once. All ACL configuration registers are cleared on reset by resetting the device from a reset source. This is the only way of clearing the configuration registers. To ensure that the ACL peripheral always enforces the desired permission schemes, the device boot sequence must perform the necessary configuration. Debugger read access to a read-protected region will be Read-As-Zero (RAZ), while debugger write access to a write-protected region will be Write-Ignored (WI). 6.3.1 Registers Base address Peripheral Instance Description 0x4001E000 ACL ACL Access control lists Configuration Table 27: Instances Register Offset Description ACL[0].ADDR 0x800 Start address of region to protect. The start address must be word-aligned. ACL[0].SIZE 0x804 Size of region to protect counting from address ACL[0].ADDR. Writing a '0' has no effect. ACL[0].PERM 0x808 Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE ACL[0].UNUSED0 0x80C ACL[1].ADDR 0x810 Start address of region to protect. The start address must be word-aligned. ACL[1].SIZE 0x814 Size of region to protect counting from address ACL[1].ADDR. Writing a '0' has no effect. ACL[1].PERM 0x818 Access permissions for region 1 as defined by start address ACL[1].ADDR and size ACL[1].SIZE ACL[1].UNUSED0 0x81C ACL[2].ADDR 0x820 Start address of region to protect. The start address must be word-aligned. ACL[2].SIZE 0x824 Size of region to protect counting from address ACL[2].ADDR. Writing a '0' has no effect. ACL[2].PERM 0x828 Access permissions for region 2 as defined by start address ACL[2].ADDR and size ACL[2].SIZE ACL[2].UNUSED0 0x82C ACL[3].ADDR 0x830 Start address of region to protect. The start address must be word-aligned. ACL[3].SIZE 0x834 Size of region to protect counting from address ACL[3].ADDR. Writing a '0' has no effect. ACL[3].PERM 0x838 Access permissions for region 3 as defined by start address ACL[3].ADDR and size ACL[3].SIZE ACL[3].UNUSED0 0x83C ACL[4].ADDR 0x840 Start address of region to protect. The start address must be word-aligned. ACL[4].SIZE 0x844 Size of region to protect counting from address ACL[4].ADDR. Writing a '0' has no effect. ACL[4].PERM 0x848 Access permissions for region 4 as defined by start address ACL[4].ADDR and size ACL[4].SIZE ACL[4].UNUSED0 0x84C 4452_021 v1.5 Reserved Reserved Reserved Reserved Reserved 108 Peripherals Register Offset Description ACL[5].ADDR 0x850 Start address of region to protect. The start address must be word-aligned. ACL[5].SIZE 0x854 Size of region to protect counting from address ACL[5].ADDR. Writing a '0' has no effect. ACL[5].PERM 0x858 Access permissions for region 5 as defined by start address ACL[5].ADDR and size ACL[5].SIZE ACL[5].UNUSED0 0x85C ACL[6].ADDR 0x860 Start address of region to protect. The start address must be word-aligned. ACL[6].SIZE 0x864 Size of region to protect counting from address ACL[6].ADDR. Writing a '0' has no effect. ACL[6].PERM 0x868 Access permissions for region 6 as defined by start address ACL[6].ADDR and size ACL[6].SIZE ACL[6].UNUSED0 0x86C ACL[7].ADDR 0x870 Start address of region to protect. The start address must be word-aligned. ACL[7].SIZE 0x874 Size of region to protect counting from address ACL[7].ADDR. Writing a '0' has no effect. ACL[7].PERM 0x878 Access permissions for region 7 as defined by start address ACL[7].ADDR and size ACL[7].SIZE ACL[7].UNUSED0 0x87C Reserved Reserved Reserved Table 28: Register overview 6.3.1.1 ACL[n].ADDR (n=0..7) Address offset: 0x800 + (n × 0x10) Start address of region to protect. The start address must be word-aligned. This register can only be written once. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW1 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Start address of flash region n. The start address must point to a flash page boundary. 6.3.1.2 ACL[n].SIZE (n=0..7) Address offset: 0x804 + (n × 0x10) Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. This register can only be written once. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW1 SIZE Value ID Value Description Size of flash region n in bytes. Must be a multiple of the flash page size. 6.3.1.3 ACL[n].PERM (n=0..7) Address offset: 0x808 + (n × 0x10) Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE This register can only be written once. 4452_021 v1.5 109 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B Reset 0x00000000 ID Access Field B RW1 WRITE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Configure write and erase permissions for region n. Writing a '0' has no effect. C Enable 0 Allow write and erase instructions to region n. Disable 1 Block write and erase instructions to region n. RW1 READ Configure read permissions for region n. Writing a '0' has no effect. Enable 0 Allow read instructions to region n. Disable 1 Block read instructions to region n. 6.4 CCM — AES CCM mode encryption Cipher block chaining - message authentication code (CCM) mode is an authenticated encryption algorithm designed to provide both authentication and confidentiality during data transfer. CCM combines counter mode encryption and CBC-MAC authentication. The CCM terminology "Message authentication code (MAC)" is called the "Message integrity check (MIC)" in Bluetooth terminology and also in this document. The CCM block generates an encrypted keystream that is applied to input data using the XOR operation and generates the four byte MIC field in one operation. CCM and RADIO can be configured to work synchronously. CCM will encrypt in time for transmission and decrypt after receiving bytes into memory from the radio. All operations can complete within the packet RX or TX time. CCM on this device is implemented according to Bluetooth requirements and the algorithm as defined in IETF RFC3610, and depends on the AES-128 block cipher. A description of the CCM algorithm can also be found in NIST Special Publication 800-38C. The Bluetooth specification describes the configuration of counter mode blocks and encryption blocks to implement compliant encryption for Bluetooth Low Energy. The CCM block uses EasyDMA to load key counter mode blocks (including the nonce required), and to read/write plain text and cipher text. The AES CCM peripheral supports three operations: keystream generation, packet encryption, and packet decryption. These operations are performed in compliance with the Bluetooth AES CCM 128 bit block encryption, see Bluetooth Core specification Version 4.0. The following figure illustrates keystream generation followed by encryption or decryption. The shortcut is optional. keystream generation KSGEN encryption / decryption CRYPT ENDKSGEN ENDCRYPT SHORTCUT Figure 31: Keystream generation 6.4.1 Keystream generation A new keystream needs to be generated before a new packet encryption or packet decryption operation can start. A keystream is generated by triggering the KSGEN task. An ENDKSGEN event is generated after the keystream has been generated. 4452_021 v1.5 110 Peripherals Keystream generation, packet encryption, and packet decryption operations utilize the configuration specified in the data structure pointed to by CNFPTR on page 120. It is necessary to configure this pointer and its underlying data structure, and register MODE on page 120 before the KSGEN task is triggered. The keystream will be stored in the AES CCM peripheral’s temporary memory area, specified by the SCRATCHPTR on page 121, where it will be used in subsequent encryption and decryption operations. For default length packets (MODE.LENGTH = Default), the size of the generated keystream is 27 bytes. When using extended length packets (MODE.LENGTH = Extended), register MAXPACKETSIZE on page 121 specifies the length of the keystream to be generated. The length of the generated keystream must be greater or equal to the length of the subsequent packet payload to be encrypted or decrypted. The maximum length of the keystream in extended mode is 251 bytes, which means that the maximum packet payload size is 251. If a shortcut is used between the ENDKSGEN event and CRYPT task, pointer INPTR on page 120 and the pointers OUTPTR on page 121 must also be configured before the KSGEN task is triggered. 6.4.2 Encryption The AES CCM periheral is able to read an unencrypted packet, encrypt it, and append a four byte MIC field to the packet. During packet encryption, the AES CCM peripheral performs the following: • Reads the unencrypted packet located in RAM address specified in the INPTR pointer • Encrypts the packet • Appends a four byte long Message Integrity Check (MIC) field to the packet Encryption is started by triggering the CRYPT task with register MODE on page 120 set to ENCRYPTION. An ENDCRYPT event is generated when packet encryption is completed. The AES CCM peripheral will also modify the length field of the packet to adjust for the appended MIC field. It adds four bytes to the length and stores the resulting packet in RAM at the address specified in pointer OUTPTR on page 121, see Encryption on page 111. Empty packets (length field is set to 0) will not be encrypted but instead moved unmodified through the AES CCM peripheral. AES CCM supports different widths of the LENGTH field in the data structure for encrypted packets. This is configured in register MODE on page 120. SCRATCHPTR INPTR Unencrypted packet H L H L+4 OUTPTR RFU MODE = ENCRYPTION Encrypted packet RFU Scratch area PL EPL AES CCM H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload CCM data structure MIC CNFPTR Figure 32: Encryption 6.4.3 Decryption The AES CCM peripheral is able to read an encrypted packet, decrypt it, authenticate the MIC field, and generate an appropriate MIC status. During packet decryption, the AES CCM peripheral performs the following: • Reads the encrypted packet located in RAM at the address specified in the INPTR pointer • Decrypts the packet 4452_021 v1.5 111 Peripherals • Authenticates the packet's MIC field • Generates the appropriate MIC status The packet header (S0) and payload are included in the MIC authentication. Bits in the packet header can be masked away by configuring register HEADERMASK on page 122. Decryption is started by triggering the CRYPT task with register MODE on page 120 set to DECRYPTION. An ENDCRYPT event is generated when packet decryption is completed. The AES CCM peripheral modifies the length field of the packet to adjust for the MIC field. It subtracts four bytes from the length and stores the decrypted packet in RAM at the address specified in the pointer OUTPTR, see Decryption on page 112. CCM is only able to decrypt packet payloads that are at least five bytes long (one byte or more encrypted payload (EPL) and four bytes of MIC). CCM will therefore generate a MIC error for packets where the length field is set to 1, 2, 3, or 4. Empty packets (length field is set to 0) will not be decrypted but instead moved unmodified through the AES CCM peripheral. These packets will always pass the MIC check. CCM supports different widths of the LENGTH field in the data structure for decrypted packets. This is configured in register MODE on page 120. SCRATCHPTR OUTPTR Unencrypted packet H INPTR L RFU MODE = DECRYPTION Encrypted packet H L+4 RFU Scratch area PL EPL AES CCM H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload CCM data structure MIC CNFPTR Figure 33: Decryption 6.4.4 AES CCM and RADIO concurrent operation The CCM peripheral is able to encrypt/decrypt data synchronously to data being transmitted or received on the radio. In order for CCM to run synchronously with the radio, the data rate setting in register MODE on page 120 needs to match the radio data rate. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. The data rate setting of register MODE on page 120 can also be overridden on-the-fly during an ongoing encrypt/decrypt operation by the contents of register RATEOVERRIDE on page 122. The data rate setting in this register applies whenever the RATEOVERRIDE task is triggered. This feature can be useful in cases where the radio data rate is changed during an ongoing packet transaction. 6.4.5 Encrypting packets on-the-fly in radio transmit mode When the AES CCM peripheral encrypts a packet on-the-fly while RADIO is transmitting it, RADIO must read the encrypted packet from the same memory location that the AES CCM peripheral is writing to. The OUTPTR on page 121 pointer in the AES CCM must point to the same memory location as the PACKETPTR pointer in the radio, see Configuration of on-the-fly encryption on page 113. 4452_021 v1.5 112 Peripherals SCRATCHPTR INPTR Unencrypted packet OUTPTR & PACKETPTR H L H L+4 RFU Scratch area PL MODE = ENCRYPTION Encrypted packet RFU EPL AES CCM H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload CCM data structure MIC CNFPTR To remote receiver RADIO TXEN Figure 34: Configuration of on-the-fly encryption In order to match RADIO’s timing, the KSGEN task must be triggered early enough to allow the keystream generation to complete before packet encryption begins. For short packets (MODE.LENGTH = Default), the KSGEN task must be triggered before or at the same time as the START task in RADIO is triggered. In addition, the shortcut between the ENDKSGEN event and the CRYPT task must be enabled. This use-case is illustrated in On-the-fly encryption of short packets (MODE.LENGTH = Default) using a PPI connection on page 113. It uses a PPI connection between the READY event in RADIO and the KSGEN task in the AES CCM peripheral. For long packets (MODE.LENGTH = Extended), the keystream generation needs to start earlier, such as when the TXEN task in RADIO is triggered. Refer to Timing specification on page 122 for information about the time needed for generating a keystream. SHORTCUT ENDKSGEN CRYPT keystream generation AES CCM encryption KSGEN ENDCRYPT PPI READY RADIO RU P A H L RFU EPL MIC CRC TXEN END READY RU: Ramp-up of RADIO P: Preamble A: Address START SHORTCUT H: Header (S0) L: Length RFU: reserved for future use (S1) EPL: encrypted payload Figure 35: On-the-fly encryption of short packets (MODE.LENGTH = Default) using a PPI connection 6.4.6 Decrypting packets on-the-fly in RADIO receive mode When the AES CCM peripheral decrypts a packet on-the-fly while RADIO is receiving it, the AES CCM peripheral must read the encrypted packet from the same memory location that RADIO is writing to. The INPTR on page 120 pointer in the AES CCM must point to the same memory location as the PACKETPTR pointer in RADIO, see Configuration of on-the-fly decryption on page 114. 4452_021 v1.5 113 Peripherals SCRATCHPTR OUTPTR Unencrypted packet INPTR & PACKETPTR H L H L+4 RFU Scratch area PL RFU AES CCM MODE = DECRYPTION Encrypted packet EPL H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload CCM data structure MIC CNFPTR From remote transmitter RADIO RXEN Figure 36: Configuration of on-the-fly decryption In order to match RADIO’s timing, the KSGEN task must be triggered early enough to allow the keystream generation to complete before the decryption of the packet shall start. For short packets (MODE.LENGTH = Default) the KSGEN task must be triggered no later than when the START task in RADIO is triggered. In addition, the CRYPT task must be triggered no earlier than when the ADDRESS event is generated by RADIO. If the CRYPT task is triggered exactly at the same time as the ADDRESS event is generated by RADIO, the AES CCM peripheral will guarantee that the decryption is completed no later than when the END event in RADIO is generated. This use-case is illustrated in On-the-fly decryption of short packets (MODE.LENGTH = Default) using a PPI connection on page 114 using a PPI connection between the ADDRESS event in RADIO and the CRYPT task in the AES CCM peripheral. The KSGEN task is triggered from the READY event in RADIO through a PPI connection. For long packets (MODE.LENGTH = Extended) the keystream generation will need to start even earlier, such as when the RXEN task in RADIO is triggered. Refer to Timing specification on page 122 for information about the time needed for generating a keystream. keystream generation AES CCM KSGEN decryption ENDKSGEN CRYPT ENDCRYPT PPI PPI READY RADIO ADDRESS RU P A H L RFU EPL MIC RXEN CRC END READY RU: Ramp-up of RADIO P: Preamble A: Address START SHORTCUT H: Header (S0) L: Length RFU: reserved for future use (S1) EPL: encrypted payload : RADIO receiving noise Figure 37: On-the-fly decryption of short packets (MODE.LENGTH = Default) using a PPI connection 6.4.7 CCM data structure The CCM data structure is located in Data RAM at the memory location specified by the CNFPTR pointer register. 4452_021 v1.5 114 Peripherals Property Address offset Description KEY 0 16 byte AES key PKTCTR 16 Octet0 (LSO) of packet counter 17 Octet1 of packet counter 18 Octet2 of packet counter 19 Octet3 of packet counter 20 Bit 6 – Bit 0: Octet4 (7 most significant bits of packet counter, with Bit 6 being the most significant bit) Bit7: Ignored IV 21 Ignored 22 Ignored 23 Ignored 24 Bit 0: Direction bit Bit 7 – Bit 1: Zero padded 25 8 byte initialization vector (IV) Octet0 (LSO) of IV, Octet1 of IV, … , Octet7 (MSO) of IV Table 29: CCM data structure overview The NONCE vector (as specified by the Bluetooth Core Specification) will be generated by hardware based on the information specified in the CCM data structure from CCM data structure overview on page 115 . Property Address offset Description HEADER 0 Packet Header LENGTH 1 Number of bytes in unencrypted payload RFU 2 Reserved Future Use PAYLOAD 3 Unencrypted payload Table 30: Data structure for unencrypted packet Property Address offset Description HEADER 0 Packet Header LENGTH 1 Number of bytes in encrypted payload including length of MIC RFU 2 Reserved Future Use PAYLOAD 3 Encrypted payload MIC 3 + payload length ENCRYPT: 4 bytes encrypted MIC LENGTH will be 0 for empty packets since the MIC is not added to empty packets MIC is not added to empty packets Table 31: Data structure for encrypted packet 6.4.8 EasyDMA and ERROR event CCM implements an EasyDMA mechanism for reading and writing to RAM. When the CPU and EasyDMA enabled peripherals access the same RAM block at the same time, increased bus collisions might disrupt on-the-fly encryption. This will generate an ERROR event. EasyDMA stops accessing RAM when the ENDKSGEN and ENDCRYPT events are generated. If the CNFPTR, SCRATCHPTR, INPTR, and the OUTPTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. 4452_021 v1.5 115 Peripherals 6.4.9 Registers Base address Peripheral Instance Description Configuration 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption Table 32: Instances Register Offset Description TASKS_KSGEN 0x000 Start generation of keystream. This operation will stop by itself when completed. TASKS_CRYPT 0x004 Start encryption/decryption. This operation will stop by itself when completed. TASKS_STOP 0x008 Stop encryption/decryption TASKS_RATEOVERRIDE 0x00C Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register EVENTS_ENDKSGEN 0x100 Keystream generation complete EVENTS_ENDCRYPT 0x104 Encrypt/decrypt complete EVENTS_ERROR 0x108 CCM error event SHORTS 0x200 Shortcuts between local events and tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt MICSTATUS 0x400 MIC check result ENABLE 0x500 Enable MODE 0x504 Operation mode CNFPTR 0x508 Pointer to data structure holding the AES key and the NONCE vector INPTR 0x50C Input pointer OUTPTR 0x510 Output pointer SCRATCHPTR 0x514 Pointer to data area used for temporary storage MAXPACKETSIZE 0x518 Length of keystream generated when MODE.LENGTH = Extended RATEOVERRIDE 0x51C Data rate override setting. HEADERMASK 0x520 Header (S0) mask. for any ongoing encryption/decryption Deprecated Table 33: Register overview 6.4.9.1 TASKS_KSGEN Address offset: 0x000 Start generation of keystream. This operation will stop by itself when completed. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_KSGEN Start generation of keystream. This operation will stop by itself when completed. Trigger 1 Trigger task 6.4.9.2 TASKS_CRYPT Address offset: 0x004 Start encryption/decryption. This operation will stop by itself when completed. 4452_021 v1.5 116 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_CRYPT Start encryption/decryption. This operation will stop by itself when completed. Trigger 1 Trigger task 6.4.9.3 TASKS_STOP Address offset: 0x008 Stop encryption/decryption Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stop encryption/decryption Trigger task 6.4.9.4 TASKS_RATEOVERRIDE Address offset: 0x00C Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption Trigger 1 Trigger task 6.4.9.5 EVENTS_ENDKSGEN Address offset: 0x100 Keystream generation complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDKSGEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Keystream generation complete NotGenerated 0 Event not generated Generated 1 Event generated 6.4.9.6 EVENTS_ENDCRYPT Address offset: 0x104 Encrypt/decrypt complete 4452_021 v1.5 117 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDCRYPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Encrypt/decrypt complete 6.4.9.7 EVENTS_ERROR ( Deprecated ) Address offset: 0x108 CCM error event Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CCM error event Deprecated 6.4.9.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ENDKSGEN_CRYPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event ENDKSGEN and task CRYPT 6.4.9.9 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW ENDKSGEN B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event ENDKSGEN RW ENDCRYPT Write '1' to enable interrupt for event ENDCRYPT RW ERROR 4452_021 v1.5 Write '1' to enable interrupt for event ERROR 118 Deprecated Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.4.9.10 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW ENDKSGEN B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event ENDKSGEN RW ENDCRYPT Write '1' to disable interrupt for event ENDCRYPT RW ERROR Write '1' to disable interrupt for event ERROR Deprecated 6.4.9.11 MICSTATUS Address offset: 0x400 MIC check result Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description MICSTATUS The result of the MIC check performed during the previous decryption operation CheckFailed 0 MIC check failed CheckPassed 1 MIC check passed 6.4.9.12 ENABLE Address offset: 0x500 Enable 4452_021 v1.5 119 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 2 Enable Enable or disable CCM 6.4.9.13 MODE Address offset: 0x504 Operation mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0x00000001 ID Access Field A RW MODE B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. B C Encryption 0 AES CCM packet encryption mode Decryption 1 AES CCM packet decryption mode RW DATARATE Radio data rate that the CCM shall run synchronous with 1Mbit 0 1 Mbps 2Mbit 1 2 Mbps 125Kbps 2 125 kbps 500Kbps 3 500 kbps Default 0 RW LENGTH Packet length configuration Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. Extended 1 Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 6.4.9.14 CNFPTR Address offset: 0x508 Pointer to data structure holding the AES key and the NONCE vector Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW CNFPTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 6.4.9.15 INPTR Address offset: 0x50C Input pointer 4452_021 v1.5 120 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW INPTR Value ID Value Description Input pointer 6.4.9.16 OUTPTR Address offset: 0x510 Output pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW OUTPTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Output pointer 6.4.9.17 SCRATCHPTR Address offset: 0x514 Pointer to data area used for temporary storage Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW SCRATCHPTR Value ID Value Description Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. The scratch area is used for temporary storage of data during keystream generation and encryption. When MODE.LENGTH = Default, a space of 43 bytes is required for this temporary storage. When MODE.LENGTH = Extended, a space of (16 + MAXPACKETSIZE) bytes is required. 6.4.9.18 MAXPACKETSIZE Address offset: 0x518 Length of keystream generated when MODE.LENGTH = Extended Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x000000FB ID Access Field A RW MAXPACKETSIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 Value ID Value Description [0x001B..0x00FB] Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 4452_021 v1.5 121 Peripherals 6.4.9.19 RATEOVERRIDE Address offset: 0x51C Data rate override setting. Override value to be used instead of the setting of MODE.DATARATE. This override value applies when the RATEOVERRIDE task is triggered. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW RATEOVERRIDE Value ID Value Description 1Mbit 0 1 Mbps 2Mbit 1 2 Mbps 125Kbps 2 125 kbps 500Kbps 3 500 kbps Data rate override setting 6.4.9.20 HEADERMASK Address offset: 0x520 Header (S0) mask. Bitmask for packet header (S0) before MIC generation/authentication. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x000000E3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 ID Access Field Value ID A RW HEADERMASK Value Description Header (S0) mask 6.4.10 Electrical specification 6.4.10.1 Timing specification Symbol Description Min. tkgen Time needed for keystream generation (given priority access Typ. Max. Units 50 µs to destination RAM block) 6.5 COMP — Comparator The comparator (COMP) compares an input voltage (VIN+) against a second input voltage (VIN-). VIN+ can be derived from an analog input pin (AIN0-AIN7). VIN- can be derived from multiple sources depending on the operation mode of the comparator. The main features of COMP are the following: • Input range from 0 V to VDD • Single-ended mode • Fully flexible hysteresis using a 64-level reference ladder • Differential mode 4452_021 v1.5 122 Peripherals • Configurable hysteresis • Reference inputs (VREF): • VDD • External reference from AIN0 to AIN7 (between 0 V and VDD) • Internal references 1.2 V, 1.8 V, and 2.4 V • Three speed/power consumption modes: • Low-power • Normal • High-speed • Event generation on output changes AIN6 AIN7 AIN5 AIN4 AIN3 AIN2 AIN1 UP event on VIN- > VIN+ DOWN event on VIN- < VIN+ CROSS event on VIN+ and VIN- crossing READY event on core and internal reference (if used) ready AIN0 • • • • PSEL MUX SAMPLE STOP START VIN+ + Comparator core MODE VIN- HYST RESULT Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) READY DOWN CROSS UP Figure 38: Comparator overview Once enabled (using the ENABLE register), the comparator is started by triggering the START task and stopped by triggering the STOP task. The comparator will generate a READY event to indicate when it is ready for use and the output is correct. The delay between START and READY is tINT_REF,START if an internal reference is selected, or t COMP,START if an external reference is used. When the COMP module is started, events will be generated every time VIN+ crosses VIN-. Operation modes The comparator can be configured to operate in two main operation modes: differential mode and singleended mode. See the MODE register for more information. In both operation modes, the comparator can operate in different speed and power consumption modes (low-power, normal and high-speed). Highspeed mode will consume more power compared to low-power mode, and low-power mode will result in slower response time compared to high-speed mode. 4452_021 v1.5 123 Peripherals Use the PSEL register to select any of the AIN0-AIN7 pins as VIN+ input, regardless of the operation mode selected for the comparator. The source of VIN- depends on which of the following operation mode are used: • Differential mode - Derived directly from AIN0 to AIN7 • Single-ended mode - Derived from VREF. VREF can be derived from VDD, AIN0-AIN7 or internal 1.2 V, 1.8 V and 2.4 V references. The selected analog pins will be acquired by the comparator once it is enabled. An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode through the HYST register. In single-ended mode, VUP and VDOWN thresholds can be set to implement a hysteresis using the reference ladder (see Comparator in single-ended mode on page 126). This hysteresis is in the order of magnitude of VDIFFHYST, and shall prevent noise on the signal to create unwanted events. See Hysteresis example where VIN+ starts below VUP on page 126 for an illustration of the effect of an active hysteresis on a noisy input signal. An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The CROSS event will be generated every time there is a crossing, independent of direction. The immediate value of the comparator can be sampled to RESULT register by triggering the SAMPLE task. 6.5.1 Shared resources The COMP shares analog resources with other analog peripherals. While it is possible to use the SAADC at the same time as the COMP, selecting the same analog input pin for both peripherals is not supported. Additionally, COMP shares registers and other resources with other peripherals that have the same ID as the COMP. See Peripherals with shared ID on page 99 for more information. The COMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has been stopped. Failing to do so may result in unpredictable behavior. 6.5.2 Differential mode In differential mode, the reference input VIN- is derived directly from one of the AINx pins. Before enabling the comparator via the ENABLE register, the following registers must be configured for the differential mode: • PSEL • MODE • EXTREFSEL 4452_021 v1.5 124 PSEL MUX EXTREFSEL AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 AIN6 AIN7 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 Peripherals MUX SAMPLE STOP START VIN+ + VIN- Comparator core MODE RESULT Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) READY DOWN UP CROSS Figure 39: Comparator in differential mode Note: Depending on the device, not all the analog inputs may be available for each MUX. See definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a particular device. When the HYST register is turned on during this mode, the output of the comparator and associated events do the following: • Change from ABOVE to BELOW when VIN+ drops below VIN- - (VDIFFHYST/2) • Change from BELOW to ABOVE when VIN+ raises above VIN- + (VDIFFHYST/2) This behavior is illustrated in the following figure. VIN+ VIN- + (VDIFFHYST / 2) VIN- - (VDIFFHYST / 2) t Output ABOVE (VIN+ > (VIN- + VDIFFHYST /2)) BELOW (VIN+ < (VIN- - VDIFFHYST /2)) ABOVE (VIN+ > (VIN- + VDIFFHYST /2)) BELOW Figure 40: Hysteresis enabled in differential mode 6.5.3 Single-ended mode In single-ended mode, VIN- is derived from the reference ladder. Before enabling the comparator via the ENABLE register, the following registers must be configured for the single-ended mode: • • • • • PSEL MODE REFSEL EXTREFSEL TH 4452_021 v1.5 125 Peripherals PSEL MUX TH EXTREFSEL AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 MUX SAMPLE STOP START VIN+ + - VIN- 0 MUX 1 Comparator core MODE REFSEL AIN1 AIN0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 The reference ladder uses the reference voltage (VREF) to derive two new voltage references, VUP and VDOWN. VUP and VDOWN are configured using THUP and THDOWN respectively in the TH register. VREF can be derived from any of the available reference sources, configured using the EXTREFSEL and REFSEL registers as shown in the following figure. When AREF is selected in the REFSEL register, the EXTREFSEL register is used to select one of the AIN0-AIN7 analog input pins as reference input. The selected analog pins will be acquired by the comparator once it is enabled. VDD VUP AREF VDOWN Reference ladder HYST RESULT VREF MUX 1V2 1V8 2V4 Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) READY DOWN UP CROSS Figure 41: Comparator in single-ended mode Note: Depending on the device, not all the analog inputs may be available for each MUX. See definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a particular device. When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will switch to VDOWN. When VIN+ falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP larger than VDOWN, a hysteresis can be generated as illustrated in the following figures. Writing to HYST has no effect in single-ended mode, and the content of this register is ignored. VIN+ VUP VDOWN Output ABOVE (VIN+ > VIN-) BELOW VUP VDOWN VUP RESULT BELOW (VIN+ < VIN-) VIN- t DOWN SAMPLE START 3 2 SAMPLE 1 CPU ABOVE UP READY BELOW Figure 42: Hysteresis example where VIN+ starts below VUP 4452_021 v1.5 126 Peripherals VIN+ VUP VDOWN Output BELOW ( VIN+ < VIN-) ABOVE (VIN+ > VIN-) BELOW VDOWN VUP VDOWN VUP BELOW 3 2 SAMPLE START SAMPLE 1 CPU ABOVE UP DOWN READY ABOVE DOWN RESULT ABOVE (VIN+ > VIN-) VIN- t Figure 43: Hysteresis example where VIN+ starts above VUP 6.5.4 Registers Base address Peripheral Instance Description 0x40013000 COMP COMP General purpose comparator Configuration Table 34: Instances Register Offset Description TASKS_START 0x000 Start comparator TASKS_STOP 0x004 Stop comparator TASKS_SAMPLE 0x008 Sample comparator value EVENTS_READY 0x100 COMP is ready and output is valid EVENTS_DOWN 0x104 Downward crossing EVENTS_UP 0x108 Upward crossing EVENTS_CROSS 0x10C Downward or upward crossing SHORTS 0x200 Shortcuts between local events and tasks INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt RESULT 0x400 Compare result ENABLE 0x500 COMP enable PSEL 0x504 Pin select REFSEL 0x508 Reference source select for single-ended mode EXTREFSEL 0x50C External reference select TH 0x530 Threshold configuration for hysteresis unit MODE 0x534 Mode configuration HYST 0x538 Comparator hysteresis enable Table 35: Register overview 4452_021 v1.5 127 Peripherals 6.5.4.1 TASKS_START Address offset: 0x000 Start comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_START Start comparator Trigger task 6.5.4.2 TASKS_STOP Address offset: 0x004 Stop comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stop comparator Trigger task 6.5.4.3 TASKS_SAMPLE Address offset: 0x008 Sample comparator value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_SAMPLE Sample comparator value Trigger 1 Trigger task 6.5.4.4 EVENTS_READY Address offset: 0x100 COMP is ready and output is valid Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_READY 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated COMP is ready and output is valid 128 Peripherals 6.5.4.5 EVENTS_DOWN Address offset: 0x104 Downward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_DOWN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Downward crossing 6.5.4.6 EVENTS_UP Address offset: 0x108 Upward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_UP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Upward crossing 6.5.4.7 EVENTS_CROSS Address offset: 0x10C Downward or upward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CROSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Downward or upward crossing 6.5.4.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID Access Field A RW READY_SAMPLE 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event READY and task SAMPLE 129 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID Access Field B RW READY_STOP C D E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event READY and task STOP RW DOWN_STOP Shortcut between event DOWN and task STOP RW UP_STOP Shortcut between event UP and task STOP RW CROSS_STOP Shortcut between event CROSS and task STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut 6.5.4.9 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW READY B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event READY Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW DOWN Enable or disable interrupt for event DOWN RW UP Enable or disable interrupt for event UP RW CROSS Enable or disable interrupt for event CROSS 6.5.4.10 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW READY B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event READY Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW DOWN 4452_021 v1.5 Write '1' to enable interrupt for event DOWN 130 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID C D Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW UP Write '1' to enable interrupt for event UP RW CROSS Write '1' to enable interrupt for event CROSS 6.5.4.11 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW READY B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event READY RW DOWN Write '1' to disable interrupt for event DOWN RW UP Write '1' to disable interrupt for event UP RW CROSS Write '1' to disable interrupt for event CROSS 6.5.4.12 RESULT Address offset: 0x400 Compare result 4452_021 v1.5 131 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Below 0 Input voltage is below the threshold (VIN+ < VIN-) Above 1 Input voltage is above the threshold (VIN+ > VIN-) RESULT Result of last compare. Decision point SAMPLE task. 6.5.4.13 ENABLE Address offset: 0x500 COMP enable Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 2 Enable Enable or disable COMP 6.5.4.14 PSEL Address offset: 0x504 Pin select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID Access Field A RW PSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AnalogInput0 0 AIN0 selected as analog input AnalogInput1 1 AIN1 selected as analog input AnalogInput2 2 AIN2 selected as analog input AnalogInput3 3 AIN3 selected as analog input AnalogInput4 4 AIN4 selected as analog input AnalogInput5 5 AIN5 selected as analog input AnalogInput6 6 AIN6 selected as analog input AnalogInput7 7 AIN7 selected as analog input Analog pin select 6.5.4.15 REFSEL Address offset: 0x508 Reference source select for single-ended mode 4452_021 v1.5 132 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000004 ID Access Field A RW REFSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Value ID Value Description Int1V2 0 VREF = internal 1.2 V reference (VDD >= 1.7 V) Int1V8 1 VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) Int2V4 2 VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) VDD 4 VREF = VDD ARef 5 VREF = AREF Reference select 6.5.4.16 EXTREFSEL Address offset: 0x50C External reference select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID Access Field A RW EXTREFSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AnalogReference0 0 Use AIN0 as external analog reference AnalogReference1 1 Use AIN1 as external analog reference AnalogReference2 2 Use AIN2 as external analog reference AnalogReference3 3 Use AIN3 as external analog reference AnalogReference4 4 Use AIN4 as external analog reference AnalogReference5 5 Use AIN5 as external analog reference AnalogReference6 6 Use AIN6 as external analog reference AnalogReference7 7 Use AIN7 as external analog reference External analog reference select 6.5.4.17 TH Address offset: 0x530 Threshold configuration for hysteresis unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value Description A RW THDOWN [63:0] VDOWN = (THDOWN+1)/64*VREF B RW THUP [63:0] VUP = (THUP+1)/64*VREF Value ID 6.5.4.18 MODE Address offset: 0x534 Mode configuration 4452_021 v1.5 A A A A A A 133 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID Access Field A RW SP B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Low 0 Low-power mode Normal 1 Normal mode High 2 High-speed mode SE 0 Single-ended mode Diff 1 Differential mode Speed and power modes RW MAIN Main operation modes 6.5.4.19 HYST Address offset: 0x538 Comparator hysteresis enable Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW HYST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoHyst 0 Comparator hysteresis disabled Hyst50mV 1 Comparator hysteresis enabled Comparator hysteresis 6.5.5 Electrical specification 6.5.5.1 COMP Electrical Specification Symbol Description tPROPDLY,LP Propagation delay, Low-power mode13 tPROPDLY,N Propagation delay, Normal mode Min. 13 tPROPDLY,HS Propagation delay, High-speed mode VDIFFHYST Optional hysteresis applied to differential input 10 VVDD-VREF Required difference between VDD and a selected VREF, VDD 0.3 13 Typ. Max. Units 0.6 µs 0.2 µs 0.1 µs 30 90 mV V > VREF tINT_REF,START Startup time for the internal bandgap reference 80 µs EINT_REF Internal bandgap reference error -3 50 3 % VINPUTOFFSET Input offset -15 15 mV tCOMP,START Startup time for the comparator core 3 µs 6.6 ECB — AES electronic codebook mode encryption The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB encryption block supports 128 bit AES encryption (encryption only, not decryption). 13 Propagation delay is with 10 mV overdrive. 4452_021 v1.5 134 Peripherals AES ECB operates with EasyDMA access to system Data RAM for in-place operations on cleartext and ciphertext during encryption. ECB uses the same AES core as the CCM and AAR blocks, and is an asynchronous operation which may not complete if the AES core is busy. AES ECB features: • • • • 128 bit AES encryption Supports standard AES ECB block encryption Memory pointer support DMA data transfer AES ECB performs a 128 bit AES block encrypt. At the STARTECB task, data and key is loaded into the algorithm by EasyDMA. When output data has been written back to memory, the ENDECB event is triggered. AES ECB can be stopped by triggering the STOPECB task. 6.6.1 Shared resources The ECB, CCM, and AAR share the same AES module. The ECB will always have lowest priority, and if there is a sharing conflict during encryption, the ECB operation will be aborted and an ERRORECB event will be generated. 6.6.2 EasyDMA The ECB implements an EasyDMA mechanism for reading and writing to the Data RAM. This DMA cannot access the program memory or any other parts of the memory area except RAM. If the ECBDATAPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. The EasyDMA will have finished accessing the Data RAM when the ENDECB or ERRORECB is generated. 6.6.3 ECB data structure Block encrypt input and output is stored in the same data structure. ECBDATAPTR should point to this data structure before STARTECB is initiated. Property Address offset Description KEY 0 16 byte AES key CLEARTEXT 16 16 byte AES cleartext input block CIPHERTEXT 32 16 byte AES ciphertext output block Table 36: ECB data structure overview 6.6.4 Registers Base address Peripheral Instance Description 0x4000E000 ECB ECB AES electronic code book (ECB) mode Configuration block encryption Table 37: Instances 4452_021 v1.5 135 Peripherals Register Offset Description TASKS_STARTECB 0x000 Start ECB block encrypt TASKS_STOPECB 0x004 Abort a possible executing ECB operation EVENTS_ENDECB 0x100 ECB block encrypt complete EVENTS_ERRORECB 0x104 ECB block encrypt aborted because of a STOPECB task or due to an error INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ECBDATAPTR 0x504 ECB block encrypt memory pointers Table 38: Register overview 6.6.4.1 TASKS_STARTECB Address offset: 0x000 Start ECB block encrypt If a crypto operation is already running in the AES core, the STARTECB task will not start a new encryption and an ERRORECB event will be triggered. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STARTECB Start ECB block encrypt If a crypto operation is already running in the AES core, the STARTECB task will not start a new encryption and an ERRORECB event will be triggered. Trigger 1 Trigger task 6.6.4.2 TASKS_STOPECB Address offset: 0x004 Abort a possible executing ECB operation If a running ECB operation is aborted by STOPECB, the ERRORECB event is triggered. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STOPECB Abort a possible executing ECB operation If a running ECB operation is aborted by STOPECB, the ERRORECB event is triggered. Trigger 1 Trigger task 6.6.4.3 EVENTS_ENDECB Address offset: 0x100 ECB block encrypt complete 4452_021 v1.5 136 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDECB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated ECB block encrypt complete 6.6.4.4 EVENTS_ERRORECB Address offset: 0x104 ECB block encrypt aborted because of a STOPECB task or due to an error Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ERRORECB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ECB block encrypt aborted because of a STOPECB task or due to an error NotGenerated 0 Event not generated Generated 1 Event generated 6.6.4.5 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A RW ENDECB B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event ENDECB Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ERRORECB Write '1' to enable interrupt for event ERRORECB Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.6.4.6 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.5 137 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A RW ENDECB B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event ENDECB RW ERRORECB Write '1' to disable interrupt for event ERRORECB 6.6.4.7 ECBDATAPTR Address offset: 0x504 ECB block encrypt memory pointers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID A RW ECBDATAPTR Value Description Pointer to the ECB data structure (see Table 1 ECB data structure overview) 6.6.5 Electrical specification 6.6.5.1 ECB Electrical Specification Symbol Description tECB Run time per 16 byte block in all modes Min. Typ. Max. Units 7.2 µs 6.7 EGU — Event generator unit Event generator unit (EGU) provides support for interlayer signaling. This means providing support for atomic triggering of both CPU execution and hardware tasks, from both firmware (by CPU) and hardware (by PPI). This feature can be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's interrupt service routine (ISR) execution at a lower priority for some of its events. However, triggering any priority from any priority is possible. Listed here are the main EGU features: • Software-enabled interrupt triggering • Separate interrupt vectors for every EGU instance • Up to 16 separate event flags per interrupt for multiplexing Each instance of EGU implements a set of tasks which can individually be triggered to generate the corresponding event. For example, the corresponding event for TASKS_TRIGGER[n] is EVENTS_TRIGGERED[n]. See Instances on page 139 for a list of EGU instances. 4452_021 v1.5 138 Peripherals 6.7.1 Registers Base address Peripheral Instance Description Configuration 0x40014000 EGU EGU0 Event generator unit 0 0x40015000 EGU EGU1 Event generator unit 1 0x40016000 EGU EGU2 Event generator unit 2 0x40017000 EGU EGU3 Event generator unit 3 0x40018000 EGU EGU4 Event generator unit 4 0x40019000 EGU EGU5 Event generator unit 5 Table 39: Instances Register Offset Description TASKS_TRIGGER[0] 0x000 Trigger 0 for triggering the corresponding TRIGGERED[0] event TASKS_TRIGGER[1] 0x004 Trigger 1 for triggering the corresponding TRIGGERED[1] event TASKS_TRIGGER[2] 0x008 Trigger 2 for triggering the corresponding TRIGGERED[2] event TASKS_TRIGGER[3] 0x00C Trigger 3 for triggering the corresponding TRIGGERED[3] event TASKS_TRIGGER[4] 0x010 Trigger 4 for triggering the corresponding TRIGGERED[4] event TASKS_TRIGGER[5] 0x014 Trigger 5 for triggering the corresponding TRIGGERED[5] event TASKS_TRIGGER[6] 0x018 Trigger 6 for triggering the corresponding TRIGGERED[6] event TASKS_TRIGGER[7] 0x01C Trigger 7 for triggering the corresponding TRIGGERED[7] event TASKS_TRIGGER[8] 0x020 Trigger 8 for triggering the corresponding TRIGGERED[8] event TASKS_TRIGGER[9] 0x024 Trigger 9 for triggering the corresponding TRIGGERED[9] event TASKS_TRIGGER[10] 0x028 Trigger 10 for triggering the corresponding TRIGGERED[10] event TASKS_TRIGGER[11] 0x02C Trigger 11 for triggering the corresponding TRIGGERED[11] event TASKS_TRIGGER[12] 0x030 Trigger 12 for triggering the corresponding TRIGGERED[12] event TASKS_TRIGGER[13] 0x034 Trigger 13 for triggering the corresponding TRIGGERED[13] event TASKS_TRIGGER[14] 0x038 Trigger 14 for triggering the corresponding TRIGGERED[14] event TASKS_TRIGGER[15] 0x03C Trigger 15 for triggering the corresponding TRIGGERED[15] event EVENTS_TRIGGERED[0] 0x100 Event number 0 generated by triggering the corresponding TRIGGER[0] task EVENTS_TRIGGERED[1] 0x104 Event number 1 generated by triggering the corresponding TRIGGER[1] task EVENTS_TRIGGERED[2] 0x108 Event number 2 generated by triggering the corresponding TRIGGER[2] task EVENTS_TRIGGERED[3] 0x10C Event number 3 generated by triggering the corresponding TRIGGER[3] task EVENTS_TRIGGERED[4] 0x110 Event number 4 generated by triggering the corresponding TRIGGER[4] task EVENTS_TRIGGERED[5] 0x114 Event number 5 generated by triggering the corresponding TRIGGER[5] task EVENTS_TRIGGERED[6] 0x118 Event number 6 generated by triggering the corresponding TRIGGER[6] task EVENTS_TRIGGERED[7] 0x11C Event number 7 generated by triggering the corresponding TRIGGER[7] task EVENTS_TRIGGERED[8] 0x120 Event number 8 generated by triggering the corresponding TRIGGER[8] task EVENTS_TRIGGERED[9] 0x124 Event number 9 generated by triggering the corresponding TRIGGER[9] task EVENTS_TRIGGERED[10] 0x128 Event number 10 generated by triggering the corresponding TRIGGER[10] task EVENTS_TRIGGERED[11] 0x12C Event number 11 generated by triggering the corresponding TRIGGER[11] task EVENTS_TRIGGERED[12] 0x130 Event number 12 generated by triggering the corresponding TRIGGER[12] task EVENTS_TRIGGERED[13] 0x134 Event number 13 generated by triggering the corresponding TRIGGER[13] task EVENTS_TRIGGERED[14] 0x138 Event number 14 generated by triggering the corresponding TRIGGER[14] task EVENTS_TRIGGERED[15] 0x13C Event number 15 generated by triggering the corresponding TRIGGER[15] task INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt Table 40: Register overview 6.7.1.1 TASKS_TRIGGER[n] (n=0..15) Address offset: 0x000 + (n × 0x4) 4452_021 v1.5 139 Peripherals Trigger n for triggering the corresponding TRIGGERED[n] event Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_TRIGGER Trigger n for triggering the corresponding TRIGGERED[n] event Trigger 1 Trigger task 6.7.1.2 EVENTS_TRIGGERED[n] (n=0..15) Address offset: 0x100 + (n × 0x4) Event number n generated by triggering the corresponding TRIGGER[n] task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TRIGGERED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event number n generated by triggering the corresponding TRIGGER[n] task NotGenerated 0 Event not generated Generated 1 Event generated 6.7.1.3 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID P O N M L K J I H G F E D C B A Reset 0x00000000 ID Access Field A-P RW TRIGGERED[i] (i=0..15) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event TRIGGERED[i] 6.7.1.4 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID P O N M L K J I H G F E D C B A Reset 0x00000000 ID Access Field A-P RW TRIGGERED[i] (i=0..15) 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event TRIGGERED[i] 140 Peripherals 6.7.1.5 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID P O N M L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A-P RW TRIGGERED[i] (i=0..15) Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event TRIGGERED[i] 6.7.2 Electrical specification 6.7.2.1 EGU Electrical Specification Symbol Description tEGU,EVT Latency between setting an EGU event flag and the system Min. Typ. 1 Max. Units cycles setting an interrupt 6.8 GPIO — General purpose input/output The general purpose input/output pins (GPIOs) are grouped as one or more ports, with each port having up to 32 GPIOs. The number of ports and GPIOs per port varies with product variant and package. Refer to Registers on page 144 and Pin assignments on page 560 for more information about the number of GPIOs that are supported. GPIO has the following user-configurable features: • • • • • • • • • Up to 32 GPIO pins per GPIO port Output drive strength Internal pull-up and pull-down resistors Wake-up from high or low level triggers on all pins Trigger interrupt on state changes on any pin All pins can be used by the PPI task/event system One or more GPIO outputs can be controlled through the PPI and GPIOTE channels Any pin can be mapped to a peripheral for layout flexibility GPIO state changes captured on the SENSE signal can be stored by the LATCH register The GPIO port peripheral implements up to 32 pins, PIN0 through PIN31. Each of these pins can be individually configured in the PIN_CNF[n] registers (n=0..31). The following parameters can be configured through these registers: • • • • • Direction Drive strength Enabling of pull-up and pull-down resistors Pin sensing Input buffer disconnect 4452_021 v1.5 141 Peripherals • Analog input (for selected pins) The PIN_CNF registers are retained registers. See POWER — Power supply on page 61 for more information about retained registers. 6.8.1 Pin configuration Pins can be individually configured through the SENSE field in the PIN_CNF[n] register to detect either a high or low level input. When the correct level is detected on a configured pin, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register, combines all DETECT signals from the pins in the GPIO port into one common DETECT signal and routes it through the system to be utilized by other peripherals. This mechanism is functional in both System ON and System OFF mode. See GPIO port and the GPIO pin details on page 142. The following figure illustrates the GPIO port containing 32 individual pins, where PIN0 is shown in more detail for reference. All signals on the left side of the illustration are used by other peripherals in the system and therefore not directly available to the CPU. LDETECT PIN0 ANAEN GPIO port DIR_OVERRIDE DETECTMODE DETECT PIN[0].CNF.DRIVE OUT_OVERRIDE LATCH PIN0 OUT PIN[0].OUT PIN0.DETECT PIN[0].IN PIN[0].CNF PIN[0].CNF.DIR Sense PIN1.DETECT PIN[0].CNF.SENSE .. PIN[0].CNF.PULL PIN[0].CNF.INPUT PIN31.DETECT PIN[0].IN I PIN31 IN PIN[31].OUT PIN[31].IN PIN[31].CNF INPUT_OVERRIDE ANAIN O: output buffer I: input buffer Figure 44: GPIO port and the GPIO pin details Pins should be in a level that cannot trigger the sense mechanism before being enabled. If the SENSE condition configured in the PIN_CNF registers is met when the sense mechanism is enabled, the DETECT signal will immediately go high. A PORT event is triggered if the DETECT signal was low before enabling the sense mechanism. See GPIOTE — GPIO tasks and events on page 149. See the following peripherals for more information about how the DETECT signal is used: • POWER — Power supply on page 61 - uses the DETECT signal to exit from System OFF mode. • GPIOTE — GPIO tasks and events on page 149 - uses the DETECT signal to generate the PORT event. When a pin's PINx.DETECT signal goes high, a flag is set in the LATCH register. For example, when the PIN0.DETECT signal goes high, bit 0 in the LATCH register is set to 1. If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by writing a 1 to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low. The LDETECT signal will be set high when one or more bits in the LATCH register are 1. The LDETECT signal will be set low when all bits in the LATCH register are successfully cleared to 0. If one or more bits in the LATCH register are 1 after the CPU has performed a clear operation on the LATCH register, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior on page 143. 4452_021 v1.5 PIN0 PIN[0].OUT O 142 PIN31 Peripherals Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been met on any of the GPIO pins. This is still valid if that condition is no longer met at the time the CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the DETECT signal. The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE register. It is possible to change from default behavior to the DETECT signal that is derived directly from the LDETECT signal. See GPIO port and the GPIO pin details on page 142. The following figure illustrates the DETECT signal behavior for these two alternatives. PIN31.DETECT PIN1.DETECT PIN0.DETECT DETECT (Default mode) LATCH.31 LATCH.1 LATCH.0 3 4 LATCH = (1 EVENTS_RXPTRUPD = 0; 6.10.9 Pin configuration The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I2S module are mapped to physical pins according to the pin numbers specified in the PSEL.x registers. These pins are acquired whenever the I2S module is enabled through the register ENABLE on page 168. When a pin is acquired by the I2S module, the direction of the pin (input or output) will be configured automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for the various I2S pins are shown below in GPIO configuration before enabling peripheral (master mode) on page 164 and GPIO configuration before enabling peripheral (slave mode) on page 165. To secure correct signal levels on the pins when the system is in OFF mode, and when the I2S module is disabled, these pins must be configured in the GPIO peripheral directly. I2S signal I2S pin Direction Output value MCK As specified in PSEL.MCK Output 0 LRCK As specified in PSEL.LRCK Output 0 SCK As specified in PSEL.SCK Output 0 SDIN As specified in PSEL.SDIN Input Not applicable SDOUT As specified in PSEL.SDOUT Output 0 Comment Table 48: GPIO configuration before enabling peripheral (master mode) 4452_021 v1.5 164 Peripherals I2S signal I2S pin Direction Output value MCK As specified in PSEL.MCK Output 0 LRCK As specified in PSEL.LRCK Input Not applicable SCK As specified in PSEL.SCK Input Not applicable SDIN As specified in PSEL.SDIN Input Not applicable SDOUT As specified in PSEL.SDOUT Output 0 Comment Table 49: GPIO configuration before enabling peripheral (slave mode) 6.10.10 Registers Base address Peripheral Instance Description 0x40025000 I2S I2S Inter-IC sound interface Configuration Table 50: Instances Register Offset Description TASKS_START 0x000 Starts continuous I2S transfer. Also starts MCK generator when this is enabled. TASKS_STOP 0x004 Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event EVENTS_RXPTRUPD 0x104 to be generated. The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. EVENTS_STOPPED 0x108 I2S transfer stopped. EVENTS_TXPTRUPD 0x114 The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 Enable I2S module. CONFIG.MODE 0x504 I2S mode. CONFIG.RXEN 0x508 Reception (RX) enable. CONFIG.TXEN 0x50C Transmission (TX) enable. CONFIG.MCKEN 0x510 Master clock generator enable. CONFIG.MCKFREQ 0x514 Master clock generator frequency. CONFIG.RATIO 0x518 MCK / LRCK ratio. CONFIG.SWIDTH 0x51C Sample width. CONFIG.ALIGN 0x520 Alignment of sample within a frame. CONFIG.FORMAT 0x524 Frame format. CONFIG.CHANNELS 0x528 Enable channels. RXD.PTR 0x538 Receive buffer RAM start address. TXD.PTR 0x540 Transmit buffer RAM start address. RXTXD.MAXCNT 0x550 Size of RXD and TXD buffers. PSEL.MCK 0x560 Pin select for MCK signal. PSEL.SCK 0x564 Pin select for SCK signal. PSEL.LRCK 0x568 Pin select for LRCK signal. PSEL.SDIN 0x56C Pin select for SDIN signal. PSEL.SDOUT 0x570 Pin select for SDOUT signal. Table 51: Register overview 4452_021 v1.5 165 Peripherals 6.10.10.1 TASKS_START Address offset: 0x000 Starts continuous I2S transfer. Also starts MCK generator when this is enabled. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled. Trigger 1 Trigger task 6.10.10.2 TASKS_STOP Address offset: 0x004 Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. Trigger 1 Trigger task 6.10.10.3 EVENTS_RXPTRUPD Address offset: 0x104 The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXPTRUPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description The RXD.PTR register has been copied to internal doublebuffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. NotGenerated 0 Event not generated Generated 1 Event generated 6.10.10.4 EVENTS_STOPPED Address offset: 0x108 I2S transfer stopped. 4452_021 v1.5 166 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated I2S transfer stopped. 6.10.10.5 EVENTS_TXPTRUPD Address offset: 0x114 The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXPTRUPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description The TDX.PTR register has been copied to internal doublebuffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. NotGenerated 0 Event not generated Generated 1 Event generated 6.10.10.6 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID Access Field B RW RXPTRUPD C F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event RXPTRUPD RW STOPPED Enable or disable interrupt for event STOPPED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW TXPTRUPD Enable or disable interrupt for event TXPTRUPD 6.10.10.7 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.5 C B 167 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID Access Field B RW RXPTRUPD C F C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event RXPTRUPD RW STOPPED Write '1' to enable interrupt for event STOPPED RW TXPTRUPD Write '1' to enable interrupt for event TXPTRUPD 6.10.10.8 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID Access Field B RW RXPTRUPD C F C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event RXPTRUPD Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STOPPED Write '1' to disable interrupt for event STOPPED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TXPTRUPD Write '1' to disable interrupt for event TXPTRUPD Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.10.10.9 ENABLE Address offset: 0x500 Enable I2S module. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ENABLE 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable I2S module. 168 Peripherals 6.10.10.10 CONFIG.MODE Address offset: 0x504 I2S mode. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Master 0 Slave 1 Description I2S mode. Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 6.10.10.11 CONFIG.RXEN Address offset: 0x508 Reception (RX) enable. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW RXEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reception (RX) enable. Disabled 0 Enabled 1 Reception disabled and now data will be written to the RXD.PTR address. Reception enabled. 6.10.10.12 CONFIG.TXEN Address offset: 0x50C Transmission (TX) enable. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID Access Field A RW TXEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Disabled 0 Enabled 1 Description Transmission (TX) enable. Transmission disabled and now data will be read from the RXD.TXD address. Transmission enabled. 6.10.10.13 CONFIG.MCKEN Address offset: 0x510 Master clock generator enable. 4452_021 v1.5 169 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID Access Field A RW MCKEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Disabled 0 Enabled 1 Description Master clock generator enable. Master clock generator disabled and PSEL.MCK not connected(available as GPIO). Master clock generator running and MCK output on PSEL.MCK. 6.10.10.14 CONFIG.MCKFREQ Address offset: 0x514 Master clock generator frequency. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x20000000 ID Access Field A RW MCKFREQ 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description 32MDIV8 0x20000000 32 MHz / 8 = 4.0 MHz 32MDIV10 0x18000000 32 MHz / 10 = 3.2 MHz 32MDIV11 0x16000000 32 MHz / 11 = 2.9090909 MHz 32MDIV15 0x11000000 32 MHz / 15 = 2.1333333 MHz 32MDIV16 0x10000000 32 MHz / 16 = 2.0 MHz 32MDIV21 0x0C000000 32 MHz / 21 = 1.5238095 32MDIV23 0x0B000000 32 MHz / 23 = 1.3913043 MHz 32MDIV30 0x08800000 32 MHz / 30 = 1.0666667 MHz 32MDIV31 0x08400000 32 MHz / 31 = 1.0322581 MHz 32MDIV32 0x08000000 32 MHz / 32 = 1.0 MHz 32MDIV42 0x06000000 32 MHz / 42 = 0.7619048 MHz 32MDIV63 0x04100000 32 MHz / 63 = 0.5079365 MHz 32MDIV125 0x020C0000 32 MHz / 125 = 0.256 MHz Master clock generator frequency. 6.10.10.15 CONFIG.RATIO Address offset: 0x518 MCK / LRCK ratio. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000006 ID Access Field A RW RATIO 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Value ID Value Description MCK / LRCK ratio. 32X 0 LRCK = MCK / 32 48X 1 LRCK = MCK / 48 64X 2 LRCK = MCK / 64 96X 3 LRCK = MCK / 96 128X 4 LRCK = MCK / 128 192X 5 LRCK = MCK / 192 256X 6 LRCK = MCK / 256 384X 7 LRCK = MCK / 384 512X 8 LRCK = MCK / 512 170 Peripherals 6.10.10.16 CONFIG.SWIDTH Address offset: 0x51C Sample width. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000001 ID Access Field A RW SWIDTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description 8Bit 0 8 bit. 16Bit 1 16 bit. 24Bit 2 24 bit. Sample width. 6.10.10.17 CONFIG.ALIGN Address offset: 0x520 Alignment of sample within a frame. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ALIGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Left 0 Left-aligned. Right 1 Right-aligned. Alignment of sample within a frame. 6.10.10.18 CONFIG.FORMAT Address offset: 0x524 Frame format. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW FORMAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description I2S 0 Original I2S format. Aligned 1 Alternate (left- or right-aligned) format. Frame format. 6.10.10.19 CONFIG.CHANNELS Address offset: 0x528 Enable channels. 4452_021 v1.5 171 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW CHANNELS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Stereo 0 Stereo. Left 1 Left only. Right 2 Right only. Enable channels. 6.10.10.20 RXD.PTR Address offset: 0x538 Receive buffer RAM start address. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 6.10.10.21 TXD.PTR Address offset: 0x540 Transmit buffer RAM start address. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. 6.10.10.22 RXTXD.MAXCNT Address offset: 0x550 Size of RXD and TXD buffers. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Size of RXD and TXD buffers in number of 32 bit words. 6.10.10.23 PSEL.MCK Address offset: 0x560 Pin select for MCK signal. 4452_021 v1.5 172 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.10.10.24 PSEL.SCK Address offset: 0x564 Pin select for SCK signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID Access Field A B C RW CONNECT B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.10.10.25 PSEL.LRCK Address offset: 0x568 Pin select for LRCK signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.10.10.26 PSEL.SDIN Address offset: 0x56C Pin select for SDIN signal. 4452_021 v1.5 173 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.10.10.27 PSEL.SDOUT Address offset: 0x570 Pin select for SDOUT signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description A B RW PIN [0..31] Pin number RW PORT [0..1] C RW CONNECT Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.10.11 Electrical specification 6.10.11.1 I2S timing specification Symbol Description Min. tS_SDIN SDIN setup time before SCK rising 20 Typ. Max. Units ns tH_SDIN SDIN hold time after SCK rising 15 ns tS_SDOUT SDOUT setup time after SCK falling 40 ns tH_SDOUT SDOUT hold time before SCK falling 6 tSCK_LRCK SCLK falling to LRCK edge -5 fMCK ns 0 5 ns MCK frequency 4000 kHz fLRCK LRCK frequency 48 kHz fSCK SCK frequency 2000 kHz DCCK Clock duty cycle (MCK, LRCK, SCK) 55 % 45 tSCK_LRCK LRCK SCK tS_SDIN tH_SDIN SDIN tH_SDOUT SDOUT Figure 57: I2S timing diagram 4452_021 v1.5 174 tS_SDOUT Peripherals 6.11 LPCOMP — Low-power comparator Low-power comparator (LPCOMP) compares an input voltage against a reference voltage. Listed here are the main features of LPCOMP: • • • • 0 - VDD input range Ultra-low power Eight input options (AIN0 to AIN7) Reference voltage options: • Two external analog reference inputs, or • 15-level internal reference ladder (VDD/16) • Optional hysteresis enable on input • Can be used as a wakeup source from System OFF mode In System ON, the LPCOMP can generate separate events on rising and falling edges of a signal, or sample the current state of the pin as being above or below the selected reference. The block can be configured to use any of the analog inputs on the device. Additionally, the low-power comparator can be used as an analog wakeup source from System OFF or System ON. The comparator threshold can be programmed to a range of fractions of the supply voltage. Note: LPCOMP cannot be used (STARTed) at the same time as COMP. Only one comparator can be used at a time. EXTREFSEL REFSEL PSEL tasks HYST MUX AREF MUX VIN+ + Comparator core VIN- MUX ANADETECT (signal to POWER module) - READY DOWN CROSS UP VDD*1/16 VDD*1/8 VDD*3/16 VDD*2/8 VDD*5/16 VDD*3/8 VDD*7/16 VDD*4/8 VDD*9/16 VDD*5/8 VDD*11/16 VDD*6/8 VDD*13/16 VDD*7/8 VDD*15/16 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 SAMPLE AIN1 STOP START AIN0 RESULT events Figure 58: Low-power comparator The wakeup comparator (LPCOMP) compares an input voltage (VIN+), which comes from an analog input pin selected via the PSEL register, against a reference voltage (VIN-) selected via registers REFSEL on page 181 and EXTREFSEL. The PSEL, REFSEL, and EXTREFSEL registers must be configured before the LPCOMP is enabled through the ENABLE register. The HYST register allows enabling an optional hysteresis in the comparator core. This hysteresis shall prevent noise on the signal to create unwanted events. Figure below illustrates the effect of an active hysteresis on a noisy input signal. It is disabled by default, and shall be configured before enabling LPCOMP as well. 4452_021 v1.5 175 Peripherals VIN+ VIN- + VHYST/2 VIN- - VHYST/2 t Output ABOVE (VIN+ > (VIN- + VHYST/2)) BELOW (VIN+ < (VIN- - VHYST/2)) ABOVE (VIN+ > (VIN- + VHYST/2)) BELOW Figure 59: Effect of hysteresis on a noisy input signal The LPCOMP is started by triggering the START task. After a startup time of tLPCOMP,STARTUP, the LPCOMP will generate a READY event to indicate that the comparator is ready to use and the output of the LPCOMP is correct. The LPCOMP will generate events every time VIN+ crosses VIN-. More specifically, every time VIN+ rises above VIN- (upward crossing) an UP event is generated along with a CROSS event. Every time VIN+ falls below VIN- (downward crossing), a DOWN event is generated along with a CROSS event. When hysteresis is enabled, the upward crossing level becomes (VIN- + VHYST/2), and the downward crossing level becomes (VIN- - VHYST/2). The LPCOMP is stopped by triggering the STOP task. LPCOMP will be operational in both System ON and System OFF mode when it is enabled through the ENABLE register. See POWER — Power supply on page 61 for more information about power modes. Note that it is not allowed to go to System OFF when a READY event is pending to be generated. All LPCOMP registers, including ENABLE, are classified as retained registers when the LPCOMP is enabled. However, when the device wakes up from System OFF, all LPCOMP registers will be reset. The LPCOMP can wake up the system from System OFF by asserting the ANADETECT signal. The ANADETECT signal can be derived from any of the event sources that generate the UP, DOWN and CROSS events. In case of wakeup from System OFF, no events will be generated, only the ANADETECT signal. See the ANADETECT register (ANADETECT on page 182) for more information on how to configure the ANADETECT signal. The immediate value of the LPCOMP can be sampled to RESULT on page 180 by triggering the SAMPLE task. See RESETREAS on page 75 for more information on how to detect a wakeup from LPCOMP. 6.11.1 Shared resources The LPCOMP shares analog resources with SAADC. While it is possible to use the SAADC at the same time as the LPCOMP, selecting the same analog input pin for both modules is not supported. Additionally, LPCOMP shares registers and other resources with other peripherals that have the same ID as the LPCOMP. See Peripherals with shared ID on page 99 for more information. The LPCOMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has been stopped. Failing to do so may result in unpredictable behavior. 6.11.2 Pin configuration You can use the LPCOMP.PSEL register to select one of the analog input pins, AIN0 through AIN7, as the analog input pin for the LPCOMP. See GPIO — General purpose input/output on page 141 for more information about the pins. Similarly, you can use EXTREFSEL on page 182 to select one of the analog reference input pins, AIN0 and AIN1, 4452_021 v1.5 176 Peripherals as input for AREF in case AREF is selected in EXTREFSEL on page 182. The selected analog pins will be acquired by the LPCOMP when it is enabled through ENABLE on page 181. 6.11.3 Registers Base address Peripheral Instance Description 0x40013000 LPCOMP LPCOMP Low power comparator Configuration Table 52: Instances Register Offset Description TASKS_START 0x000 Start comparator TASKS_STOP 0x004 Stop comparator TASKS_SAMPLE 0x008 Sample comparator value EVENTS_READY 0x100 LPCOMP is ready and output is valid EVENTS_DOWN 0x104 Downward crossing EVENTS_UP 0x108 Upward crossing EVENTS_CROSS 0x10C Downward or upward crossing SHORTS 0x200 Shortcuts between local events and tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt RESULT 0x400 Compare result ENABLE 0x500 Enable LPCOMP PSEL 0x504 Input pin select REFSEL 0x508 Reference select EXTREFSEL 0x50C External reference select ANADETECT 0x520 Analog detect configuration HYST 0x538 Comparator hysteresis enable Table 53: Register overview 6.11.3.1 TASKS_START Address offset: 0x000 Start comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_START Start comparator Trigger task 6.11.3.2 TASKS_STOP Address offset: 0x004 Stop comparator 4452_021 v1.5 177 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stop comparator Trigger task 6.11.3.3 TASKS_SAMPLE Address offset: 0x008 Sample comparator value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_SAMPLE Sample comparator value Trigger task 6.11.3.4 EVENTS_READY Address offset: 0x100 LPCOMP is ready and output is valid Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_READY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated LPCOMP is ready and output is valid 6.11.3.5 EVENTS_DOWN Address offset: 0x104 Downward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_DOWN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Downward crossing 6.11.3.6 EVENTS_UP Address offset: 0x108 Upward crossing 4452_021 v1.5 178 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_UP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Upward crossing 6.11.3.7 EVENTS_CROSS Address offset: 0x10C Downward or upward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CROSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Downward or upward crossing 6.11.3.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID Access Field A RW READY_SAMPLE B C D E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event READY and task SAMPLE RW READY_STOP Shortcut between event READY and task STOP RW DOWN_STOP Shortcut between event DOWN and task STOP RW UP_STOP Shortcut between event UP and task STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW CROSS_STOP Shortcut between event CROSS and task STOP 6.11.3.9 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.5 179 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW READY B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event READY RW DOWN Write '1' to enable interrupt for event DOWN RW UP Write '1' to enable interrupt for event UP RW CROSS Write '1' to enable interrupt for event CROSS 6.11.3.10 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW READY B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event READY Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW DOWN Write '1' to disable interrupt for event DOWN Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW UP Write '1' to disable interrupt for event UP Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CROSS Write '1' to disable interrupt for event CROSS Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.11.3.11 RESULT Address offset: 0x400 Compare result 4452_021 v1.5 180 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Below 0 Input voltage is below the reference threshold (VIN+ < VIN-) Above 1 Input voltage is above the reference threshold (VIN+ > VIN-) RESULT Result of last compare. Decision point SAMPLE task. 6.11.3.12 ENABLE Address offset: 0x500 Enable LPCOMP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable LPCOMP 6.11.3.13 PSEL Address offset: 0x504 Input pin select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID Access Field A RW PSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AnalogInput0 0 AIN0 selected as analog input AnalogInput1 1 AIN1 selected as analog input AnalogInput2 2 AIN2 selected as analog input AnalogInput3 3 AIN3 selected as analog input AnalogInput4 4 AIN4 selected as analog input AnalogInput5 5 AIN5 selected as analog input AnalogInput6 6 AIN6 selected as analog input AnalogInput7 7 AIN7 selected as analog input Analog pin select 6.11.3.14 REFSEL Address offset: 0x508 Reference select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000004 ID Access Field A RW REFSEL 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Value ID Value Description Ref1_8Vdd 0 VDD * 1/8 selected as reference Ref2_8Vdd 1 VDD * 2/8 selected as reference Reference select 181 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000004 ID Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Value ID Value Description Ref3_8Vdd 2 VDD * 3/8 selected as reference Ref4_8Vdd 3 VDD * 4/8 selected as reference Ref5_8Vdd 4 VDD * 5/8 selected as reference Ref6_8Vdd 5 VDD * 6/8 selected as reference Ref7_8Vdd 6 VDD * 7/8 selected as reference ARef 7 External analog reference selected Ref1_16Vdd 8 VDD * 1/16 selected as reference Ref3_16Vdd 9 VDD * 3/16 selected as reference Ref5_16Vdd 10 VDD * 5/16 selected as reference Ref7_16Vdd 11 VDD * 7/16 selected as reference Ref9_16Vdd 12 VDD * 9/16 selected as reference Ref11_16Vdd 13 VDD * 11/16 selected as reference Ref13_16Vdd 14 VDD * 13/16 selected as reference Ref15_16Vdd 15 VDD * 15/16 selected as reference 6.11.3.15 EXTREFSEL Address offset: 0x50C External reference select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EXTREFSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AnalogReference0 0 Use AIN0 as external analog reference AnalogReference1 1 Use AIN1 as external analog reference External analog reference select 6.11.3.16 ANADETECT Address offset: 0x520 Analog detect configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW ANADETECT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Cross 0 Up 1 Generate ANADETECT on upward crossing only Down 2 Generate ANADETECT on downward crossing only Analog detect configuration Generate ANADETECT on crossing, both upward crossing and downward crossing 6.11.3.17 HYST Address offset: 0x538 Comparator hysteresis enable 4452_021 v1.5 182 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW HYST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Comparator hysteresis disabled Enabled 1 Comparator hysteresis enabled Comparator hysteresis enable 6.11.4 Electrical specification 6.11.4.1 LPCOMP Electrical Specification Symbol Description tLPCANADET Time from VIN crossing (>=50 mV above threshold) to Min. Typ. Max. 5 Units µs ANADETECT signal generated VINPOFFSET Input offset including reference ladder error -40 40 mV VHYST Optional hysteresis 35 mV tSTARTUP Startup time for LPCOMP 140 µs 6.12 MWU — Memory watch unit The Memory watch unit (MWU) can be used to generate events when a memory region is accessed by the CPU. The MWU can be configured to trigger events for access to Data RAM and Peripheral memory segments. The MWU allows an application developer to generate memory access events during development for debugging or during production execution for failure detection and recovery. Listed here are the main features for MWU: • Six memory regions, four user-configurable and two fixed regions in peripheral address space • Flexible configuration of regions with START and END addresses • Generate events on CPU read and/or write to a defined region of Data RAM or peripheral memory address space • Programmable maskable or non-maskable (NMI) interrupt on events • Peripheral interfaces can be watched for read and write access using subregions of the two fixed memory regions Memory region START address END address REGION[0..3] Configurable Configurable PREGION[0] 0x40000000 0x4001FFFF PREGION[1] 0x40020000 0x4003FFFF Table 54: Memory regions Each MWU region is defined by a start address and an end address, configured by the START and END registers respectively. These addresses are byte aligned and inclusive. The END register value has to be greater or equal to the START register value. Each region is associated with a pair of events that indicate that either a write access or a read access from the CPU has been detected inside the region. For regions containing subregions (see below), a set of status registers PERREGION[0..1].SUBSTATWA and PERREGION[0..1].SUBSTATRA indicate which subregion(s) caused the EVENT_PREGION[0..1].WA and EVENT_PREGION[0..1].RA respectively. The MWU is only able to detect memory accesses in the Data RAM and Peripheral memory segments from the CPU, see Memory on page 19 for more information about the different memory segments. EasyDMA 4452_021 v1.5 183 Peripherals accesses are not monitored by the MWU. The MWU requires two HCLK cycles to detect and generate the event. The peripheral regions, PREGION[0...1], are divided into 32 equally sized subregions, SR[0...31]. All subregions are excluded in the main region by default, and any can be included by specifying them in the SUBS register. When a subregion is excluded from the main region, the memory watch mechanism will not trigger any events when that subregion is accessed. Subregions in PREGION[0..1] cannot be individually configured for read or write access watch. Watch configuration is only possible for a region as a whole. The PRGNiRA and PRGNiWA (i=0..1) fields in the REGIONEN register control watching read and write access. REGION[0..3] can be individually enabled for read and/or write access watching through their respective RGNiRA and RGNiWA (i=0..3) fields in the REGIONEN register. REGIONENSET and REGIONENCLR allow respectively enabling and disabling one or multiple REGIONs or PREGIONs watching in a single write access. 6.12.1 Registers Base address Peripheral Instance Description 0x40020000 MWU MWU Memory watch unit Configuration Table 55: Instances Register Offset Description EVENTS_REGION[0].WA 0x100 Write access to region 0 detected EVENTS_REGION[0].RA 0x104 Read access to region 0 detected EVENTS_REGION[1].WA 0x108 Write access to region 1 detected EVENTS_REGION[1].RA 0x10C Read access to region 1 detected EVENTS_REGION[2].WA 0x110 Write access to region 2 detected EVENTS_REGION[2].RA 0x114 Read access to region 2 detected EVENTS_REGION[3].WA 0x118 Write access to region 3 detected EVENTS_REGION[3].RA 0x11C Read access to region 3 detected EVENTS_PREGION[0].WA 0x160 Write access to peripheral region 0 detected EVENTS_PREGION[0].RA 0x164 Read access to peripheral region 0 detected EVENTS_PREGION[1].WA 0x168 Write access to peripheral region 1 detected EVENTS_PREGION[1].RA 0x16C Read access to peripheral region 1 detected INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt NMIEN 0x320 Enable or disable interrupt NMIENSET 0x324 Enable interrupt NMIENCLR 0x328 Disable interrupt PERREGION[0].SUBSTATWA 0x400 Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching PERREGION[0].SUBSTATRA 0x404 PERREGION[1].SUBSTATWA 0x408 Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching Source of event/interrupt in region 1, write access detected while corresponding subregion was enabled for watching PERREGION[1].SUBSTATRA 0x40C Source of event/interrupt in region 1, read access detected while corresponding subregion was REGIONEN 0x510 Enable/disable regions watch REGIONENSET 0x514 Enable regions watch REGIONENCLR 0x518 Disable regions watch enabled for watching 4452_021 v1.5 184 Peripherals Register Offset Description REGION[0].START 0x600 Start address for region 0 REGION[0].END 0x604 End address of region 0 REGION[1].START 0x610 Start address for region 1 REGION[1].END 0x614 End address of region 1 REGION[2].START 0x620 Start address for region 2 REGION[2].END 0x624 End address of region 2 REGION[3].START 0x630 Start address for region 3 REGION[3].END 0x634 End address of region 3 PREGION[0].START 0x6C0 Reserved for future use PREGION[0].END 0x6C4 Reserved for future use PREGION[0].SUBS 0x6C8 Subregions of region 0 PREGION[1].START 0x6D0 Reserved for future use PREGION[1].END 0x6D4 Reserved for future use PREGION[1].SUBS 0x6D8 Subregions of region 1 Table 56: Register overview 6.12.1.1 EVENTS_REGION[n].WA (n=0..3) Address offset: 0x100 + (n × 0x8) Write access to region n detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW WA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Write access to region n detected 6.12.1.2 EVENTS_REGION[n].RA (n=0..3) Address offset: 0x104 + (n × 0x8) Read access to region n detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW RA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Read access to region n detected 6.12.1.3 EVENTS_PREGION[n].WA (n=0..1) Address offset: 0x160 + (n × 0x8) Write access to peripheral region n detected 4452_021 v1.5 185 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW WA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Write access to peripheral region n detected 6.12.1.4 EVENTS_PREGION[n].RA (n=0..1) Address offset: 0x164 + (n × 0x8) Read access to peripheral region n detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW RA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Read access to peripheral region n detected 6.12.1.5 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW REGION0WA B C D E F G H Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event REGION0WA RW REGION0RA Enable or disable interrupt for event REGION0RA RW REGION1WA Enable or disable interrupt for event REGION1WA RW REGION1RA Enable or disable interrupt for event REGION1RA Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW REGION2WA Enable or disable interrupt for event REGION2WA RW REGION2RA Enable or disable interrupt for event REGION2RA RW REGION3WA Enable or disable interrupt for event REGION3WA RW REGION3RA Enable or disable interrupt for event REGION3RA Disabled 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Disable 186 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Enable RW PREGION0WA Enable or disable interrupt for event PREGION0WA Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW PREGION0RA Enable or disable interrupt for event PREGION0RA RW PREGION1WA Enable or disable interrupt for event PREGION1WA RW PREGION1RA Enable or disable interrupt for event PREGION1RA 6.12.1.6 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW REGION0WA B C D E F G 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Write '1' to enable interrupt for event REGION0WA RW REGION0RA Write '1' to enable interrupt for event REGION0RA RW REGION1WA Write '1' to enable interrupt for event REGION1WA RW REGION1RA Write '1' to enable interrupt for event REGION1RA RW REGION2WA Write '1' to enable interrupt for event REGION2WA RW REGION2RA Write '1' to enable interrupt for event REGION2RA RW REGION3WA 4452_021 v1.5 H G F E D C B A Write '1' to enable interrupt for event REGION3WA Enable 187 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID H I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION3RA Write '1' to enable interrupt for event REGION3RA RW PREGION0WA Write '1' to enable interrupt for event PREGION0WA RW PREGION0RA Write '1' to enable interrupt for event PREGION0RA RW PREGION1WA Write '1' to enable interrupt for event PREGION1WA RW PREGION1RA Write '1' to enable interrupt for event PREGION1RA 6.12.1.7 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW REGION0WA B C D E Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event REGION0WA RW REGION0RA Write '1' to disable interrupt for event REGION0RA RW REGION1WA Write '1' to disable interrupt for event REGION1WA RW REGION1RA Write '1' to disable interrupt for event REGION1RA RW REGION2WA 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to disable interrupt for event REGION2WA 188 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID F G H I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION2RA Write '1' to disable interrupt for event REGION2RA RW REGION3WA Write '1' to disable interrupt for event REGION3WA RW REGION3RA Write '1' to disable interrupt for event REGION3RA RW PREGION0WA Write '1' to disable interrupt for event PREGION0WA RW PREGION0RA Write '1' to disable interrupt for event PREGION0RA RW PREGION1WA Write '1' to disable interrupt for event PREGION1WA RW PREGION1RA Write '1' to disable interrupt for event PREGION1RA 6.12.1.8 NMIEN Address offset: 0x320 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW REGION0WA B C Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Enable or disable interrupt for event REGION0WA RW REGION0RA Enable or disable interrupt for event REGION0RA RW REGION1WA 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable or disable interrupt for event REGION1WA Disable 189 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID D E F G H I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Enable RW REGION1RA Enable or disable interrupt for event REGION1RA Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW REGION2WA Enable or disable interrupt for event REGION2WA RW REGION2RA Enable or disable interrupt for event REGION2RA RW REGION3WA Enable or disable interrupt for event REGION3WA RW REGION3RA Enable or disable interrupt for event REGION3RA Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW PREGION0WA Enable or disable interrupt for event PREGION0WA RW PREGION0RA Enable or disable interrupt for event PREGION0RA RW PREGION1WA Enable or disable interrupt for event PREGION1WA RW PREGION1RA Enable or disable interrupt for event PREGION1RA Disabled 0 Disable Enabled 1 Enable 6.12.1.9 NMIENSET Address offset: 0x324 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW REGION0WA B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event REGION0WA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION0RA Write '1' to enable interrupt for event REGION0RA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION1WA 4452_021 v1.5 H G F E D C B A Write '1' to enable interrupt for event REGION1WA Set 1 Enable Disabled 0 Read: Disabled 190 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID D E F G H I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Read: Enabled RW REGION1RA Write '1' to enable interrupt for event REGION1RA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION2WA Write '1' to enable interrupt for event REGION2WA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION2RA Write '1' to enable interrupt for event REGION2RA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION3WA Write '1' to enable interrupt for event REGION3WA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION3RA Write '1' to enable interrupt for event REGION3RA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW PREGION0WA Write '1' to enable interrupt for event PREGION0WA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW PREGION0RA Write '1' to enable interrupt for event PREGION0RA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW PREGION1WA Write '1' to enable interrupt for event PREGION1WA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW PREGION1RA Write '1' to enable interrupt for event PREGION1RA Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.12.1.10 NMIENCLR Address offset: 0x328 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW REGION0WA 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Clear 1 Description Write '1' to disable interrupt for event REGION0WA Disable 191 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID B C D E F G H I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION0RA Write '1' to disable interrupt for event REGION0RA RW REGION1WA Write '1' to disable interrupt for event REGION1WA RW REGION1RA Write '1' to disable interrupt for event REGION1RA RW REGION2WA Write '1' to disable interrupt for event REGION2WA RW REGION2RA Write '1' to disable interrupt for event REGION2RA RW REGION3WA Write '1' to disable interrupt for event REGION3WA RW REGION3RA Write '1' to disable interrupt for event REGION3RA RW PREGION0WA Write '1' to disable interrupt for event PREGION0WA RW PREGION0RA Write '1' to disable interrupt for event PREGION0RA RW PREGION1WA Write '1' to disable interrupt for event PREGION1WA RW PREGION1RA Write '1' to disable interrupt for event PREGION1RA 6.12.1.11 PERREGION[n].SUBSTATWA (n=0..1) Address offset: 0x400 + (n × 0x8) 4452_021 v1.5 192 Peripherals Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 ID Access Field A-f RW SR[i] (i=0..31) e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoAccess 0 No write access occurred in this subregion Access 1 Write access(es) occurred in this subregion Subregion i in region n (write '1' to clear) 6.12.1.12 PERREGION[n].SUBSTATRA (n=0..1) Address offset: 0x404 + (n × 0x8) Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A-f RW SR[i] (i=0..31) e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A Value ID Value Description NoAccess 0 No read access occurred in this subregion Access 1 Read access(es) occurred in this subregion Subregion i in region n (write '1' to clear) 6.12.1.13 REGIONEN Address offset: 0x510 Enable/disable regions watch Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW RGN0WA B C D E F Value ID Value Description Disable 0 Disable write access watch in this region Enable 1 Enable write access watch in this region Disable 0 Disable read access watch in this region Enable 1 Enable read access watch in this region Enable/disable write access watch in region[0] RW RGN0RA Enable/disable read access watch in region[0] RW RGN1WA Enable/disable write access watch in region[1] Disable 0 Disable write access watch in this region Enable 1 Enable write access watch in this region Disable 0 Disable read access watch in this region Enable 1 Enable read access watch in this region Disable 0 Disable write access watch in this region Enable 1 Enable write access watch in this region Disable 0 Disable read access watch in this region Enable 1 Enable read access watch in this region RW RGN1RA Enable/disable read access watch in region[1] RW RGN2WA Enable/disable write access watch in region[2] RW RGN2RA 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable/disable read access watch in region[2] 193 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field G RW RGN3WA H I J K L H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disable 0 Disable write access watch in this region Enable 1 Enable write access watch in this region Disable 0 Disable read access watch in this region Enable 1 Enable read access watch in this region Disable 0 Disable write access watch in this PREGION Enable 1 Enable write access watch in this PREGION Enable/disable write access watch in region[3] RW RGN3RA Enable/disable read access watch in region[3] RW PRGN0WA Enable/disable write access watch in PREGION[0] RW PRGN0RA Enable/disable read access watch in PREGION[0] Disable 0 Disable read access watch in this PREGION Enable 1 Enable read access watch in this PREGION Disable 0 Disable write access watch in this PREGION Enable 1 Enable write access watch in this PREGION Disable 0 Disable read access watch in this PREGION Enable 1 Enable read access watch in this PREGION RW PRGN1WA Enable/disable write access watch in PREGION[1] RW PRGN1RA Enable/disable read access watch in PREGION[1] 6.12.1.14 REGIONENSET Address offset: 0x514 Enable regions watch Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW RGN0WA B C D E F Value ID Value Description Set 1 Enable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Set 1 Enable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Set 1 Enable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Set 1 Enable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Set 1 Enable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Enable write access watch in region[0] RW RGN0RA Enable read access watch in region[0] RW RGN1WA Enable write access watch in region[1] RW RGN1RA Enable read access watch in region[1] RW RGN2WA Enable write access watch in region[2] RW RGN2RA 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable read access watch in region[2] 194 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID G H I J K L Access Field H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Set 1 Enable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Set 1 Enable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Set 1 Enable write access watch in this PREGION Disabled 0 Write access watch in this PREGION is disabled Enabled 1 Write access watch in this PREGION is enabled Set 1 Enable read access watch in this PREGION Disabled 0 Read access watch in this PREGION is disabled Enabled 1 Read access watch in this PREGION is enabled Set 1 Enable write access watch in this PREGION Disabled 0 Write access watch in this PREGION is disabled Enabled 1 Write access watch in this PREGION is enabled Set 1 Enable read access watch in this PREGION Disabled 0 Read access watch in this PREGION is disabled Enabled 1 Read access watch in this PREGION is enabled RW RGN3WA Enable write access watch in region[3] RW RGN3RA Enable read access watch in region[3] RW PRGN0WA Enable write access watch in PREGION[0] RW PRGN0RA Enable read access watch in PREGION[0] RW PRGN1WA Enable write access watch in PREGION[1] RW PRGN1RA Enable read access watch in PREGION[1] 6.12.1.15 REGIONENCLR Address offset: 0x518 Disable regions watch Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field A RW RGN0WA B C Value ID Value Description Clear 1 Disable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Clear 1 Disable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Clear 1 Disable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Disable write access watch in region[0] RW RGN0RA Disable read access watch in region[0] RW RGN1WA 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Disable write access watch in region[1] 195 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L K J I Reset 0x00000000 ID Access Field D RW RGN1RA E F G H I J K L H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Clear 1 Disable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Clear 1 Disable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Clear 1 Disable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Clear 1 Disable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch in this region is enabled Clear 1 Disable write access watch in this PREGION Disabled 0 Write access watch in this PREGION is disabled Enabled 1 Write access watch in this PREGION is enabled Clear 1 Disable read access watch in this PREGION Disabled 0 Read access watch in this PREGION is disabled Enabled 1 Read access watch in this PREGION is enabled Clear 1 Disable write access watch in this PREGION Disabled 0 Write access watch in this PREGION is disabled Enabled 1 Write access watch in this PREGION is enabled Clear 1 Disable read access watch in this PREGION Disabled 0 Read access watch in this PREGION is disabled Enabled 1 Read access watch in this PREGION is enabled Disable read access watch in region[1] RW RGN2WA Disable write access watch in region[2] RW RGN2RA Disable read access watch in region[2] RW RGN3WA Disable write access watch in region[3] RW RGN3RA Disable read access watch in region[3] RW PRGN0WA Disable write access watch in PREGION[0] RW PRGN0RA Disable read access watch in PREGION[0] RW PRGN1WA Disable write access watch in PREGION[1] RW PRGN1RA Disable read access watch in PREGION[1] 6.12.1.16 REGION[n].START (n=0..3) Address offset: 0x600 + (n × 0x10) Start address for region n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW START 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Start address for region 196 Peripherals 6.12.1.17 REGION[n].END (n=0..3) Address offset: 0x604 + (n × 0x10) End address of region n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW END Value ID Value Description End address of region. 6.12.1.18 PREGION[n].START (n=0..1) Address offset: 0x6C0 + (n × 0x10) Reserved for future use Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A R Value ID Value Description START Reserved for future use 6.12.1.19 PREGION[n].END (n=0..1) Address offset: 0x6C4 + (n × 0x10) Reserved for future use Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A R Value ID Value Description END Reserved for future use 6.12.1.20 PREGION[n].SUBS (n=0..1) Address offset: 0x6C8 + (n × 0x10) Subregions of region n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 ID Access Field A-f RW SR[i] (i=0..31) e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Exclude 0 Exclude Include 1 Include Include or exclude subregion i in region 6.13 NFCT — Near field communication tag The NFCT peripheral is an implementation of an NFC Forum compliant listening device NFC-A. 4452_021 v1.5 197 Peripherals With appropriate software, the NFCT peripheral can be used as the listening device NFC-A as specified by the NFC Forum. Listed here are the main features for the NFCT peripheral: • NFC-A listen mode operation • • • • • 13.56 MHz input frequency • Bit rate 106 kbps Wake-on-field low power field detection (SENSE) mode Frame assemble and disassemble for the NFC-A frames specified by the NFC Forum Programmable frame timing controller Integrated automatic collision resolution, cyclic redundancy check (CRC), and parity functions GOSLEEP GOIDLE ENABLERXDATA STARTTX SENSE DISABLE ACTIVATE TASKS_ NFCT Frame assemble/ disassemble EasyDMA NFC1 NFC2 STARTED SELECTED COLLISION AUTOCOLRESSTARTED ENDTX ENDRX RXERROR ERROR RXFRAMEEND RXFRAMESTART TXFRAMEEND TXFRAMESTART FIELDLOST FIELDDETECTED READY EVENTS_ Modulator/ receiver Figure 60: NFCT block diagram 6.13.1 Overview The NFCT peripheral contains a 13.56 MHz AM receiver and a 13.56 MHz load modulator with 106 kbps data rate as defined by the NFC Forum. 4452_021 v1.5 198 Peripherals NFCT PACKETPTR MAXLEN TXD.FRAMECONFIG Frame assemble SoF/EoF/parity/CRC EasyDMA Collision resolution On-the-air symbol coder 13.56 MHz NFC-A load modulator FRAMEDELAYxxx Frame timing controller Clock recovery Frame disassemble SoF/EoF/parity/CRC On-the-air symbol decoder STARTTX ENABLERXDATA NFC1 NFC2 NFCID1_xxx SENSRES SELRES FRAMESTATUS.RX RXD.FRAMECONFIG 13.56 MHz NFC-A receiver Field detector Figure 61: NFCT overview When transmitting, the frame data will be transferred directly from RAM and transmitted with configurable frame type and delay timing. The system will be notified by an event whenever a complete frame is received or sent. The received frames will be automatically disassembled and the data part of the frame transferred to RAM. The NFCT peripheral also supports the collision detection and resolution ("anticollision") as defined by the NFC Forum. Wake-on-field is supported in SENSE mode while the device is either in System OFF or System ON mode. When the antenna enters an NFC field, an event will be triggered notifying the system to activate the NFCT functionality for incoming frames. In System ON, if the energy detected at the antenna increases beyond a threshold value, the module will generate a FIELDDETECTED event. When the strength of the field no longer supports NFC communication, the module will generate a FIELDLOST event. For the Low Power Field Detect threshold values, refer to NFCT Electrical Specification on page 227. In System OFF, the NFCT Low Power Field Detect function can wake the system up through a reset. See RESETREAS on page 75 for more information on how to detect a wakeup from NFCT. If the system is put into System OFF mode while a field is already present, the NFCT Low Power Field Detect function will wake the system up right away and generate a reset. Important: As a consequence of a reset, NFCT is disabled, and therefore the reset handler will have to activate NFCT again and set it up properly. The HFXO must be running before the NFCT peripheral goes into ACTIVATED state. Note that the NFCT peripheral calibration is automatically done on ACTIVATE task. The HFXO can be turned off when the NFCT peripheral goes into SENSE mode. The shortcut FIELDDETECTED_ACTIVATE can be used when the HFXO is already running while in SENSE mode. Outgoing data will be collected from RAM with the EasyDMA function and assembled according to theTXD.FRAMECONFIG on page 222 register. Incoming data will be disassembled according to the RXD.FRAMECONFIG register and the data section in the frame will be written to RAM via the EasyDMA function. 4452_021 v1.5 199 Peripherals The NFCT peripheral includes a frame timing controller that can be used to accurately control the interframe delay between the incoming frame and a corresponding outgoing frame. It also includes optional CRC functionality. 6.13.2 Operating states Tasks and events are used to control the operating state of the peripheral. The module can change state by triggering a task, or when specific operations are finalized. Events and tasks allow software to keep track of and change the current state. See NFCT block diagram on page 198 and NFCT state diagram, automatic collision resolution enabled on page 200 for more information. See NFC Forum, NFC Activity Technical Specification for description on NFCT operating states. Activated GOIDLE DISABLE DISABLE ACTIVATE NFC (ALL_REQ) / AUTOCOLRESSTARTED / READY IDLERU NFC (OTHER) / COLLISION IDLE READY_A / SELECTED NFC (SENS_REQ) / AUTOCOLRESSTARTED NFC (OTHER) / COLLISION GOSLEEP SENSE DISABLE SLEEP_A READY_A* NFC (ALL_REQ) / AUTOCOLRESSTARTED NFC (SLP_REQ) ACTIVE_A ENABLERXDATA STARTTX SENSE SENSE_FIELD STARTTX RECEIVE ACTIVATE / RXFRAMEEND TRANSMIT / TXFRAMEEND / RXERROR Figure 62: NFCT state diagram, automatic collision resolution enabled Activated DISABLE DISABLE ACTIVATE IDLERU / READY DISABLE SENSE ACTIVE_A ENABLERXDATA SENSE_FIELD STARTTX SENSE RECEIVE ACTIVATE /RXFRAMEEND STARTTX TRANSMIT /TXFRAMEEND / RXERROR Figure 63: NFCT state diagram, automatic collision resolution disabled 4452_021 v1.5 200 / SELECTED Peripherals Important: • FIELDLOST event is not generated in SENSE mode. • Sending SENSE task while field is still present does not generate FIELDDETECTED event. • If the FIELDDETECTED event is cleared before sending the ACTIVATE task, then the FIELDDETECTED event shows up again after sending the ACTIVATE task. The shortcut FIELDDETECTED_ACTIVATE can be used to avoid this condition. 6.13.3 Pin configuration NFCT uses two pins to connect the antenna and these pins are shared with GPIOs. The PROTECT field in the NFCPINS register in UICR defines the usage of these pins and their protection level against excessive voltages. The content of the NFCPINS register is reloaded at every reset. See Pin assignments on page 560 for the pins used by the NFCT peripheral. When NFCPINS.PROTECT=NFC, a protection circuit will be enabled on the dedicated pins, preventing the chip from being damaged in the presence of a strong NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2V. The GPIO function on those pins will also be disabled. When NFCPINS.PROTECT=Disabled, the device will not be protected against strong NFC field damages caught by a connected NFCT antenna, and the NFCT peripheral will not operate as expected, as it will never leave the DISABLE state. The pins dedicated to the NFCT antenna function will have some limitation when the pins are configured for normal GPIO operation. The pin capacitance will be higher on those (refer to CPAD_NFC in the Electrical Specification of GPIO — General purpose input/output on page 141), and some increased leakage current between the two pins is to be expected if they are used in GPIO mode, and are driven to different logical values. To save power, the two pins should always be set to the same logical value whenever entering one of the device power saving modes. For details, refer to INFC_LEAK in the Electrical Specification of GPIO — General purpose input/output on page 141. 6.13.4 EasyDMA The NFCT peripheral implements EasyDMA for reading and writing of data packets from and to the Data RAM. The NFCT EasyDMA utilizes a pointer called PACKETPTR on page 222 for receiving and transmitting packets. The NFCT peripheral uses EasyDMA to read or write RAM, but not both at the same time. The event RXFRAMESTART indicates that the EasyDMA has started writing to the RAM for a receive frame and the event RXFRAMEND indicates that the EasyDMA has completed writing to the RAM. Similarly, the event TXFRAMESTART indicates that the EasyDMA has started reading from the RAM for a transmit frame and the event TXFRAMEND indicates that the EasyDMA has completed reading from the RAM. If a transmit and a receive operation is issued at the same time, the transmit operation would be prioritized. Starting a transmit operation while the EasyDMA is writing a receive frame to the RAM will result in unpredictable behavior. Starting an EasyDMA operation when there is an ongoing EasyDMA operation may result in unpredictable behavior. It is recommended to wait for the TXFRAMEEND or RXFRAMEEND event for the ongoing transmit or receive before starting a new receive or transmit operation. The MAXLEN on page 222 register determines the maximum number of bytes that can be read from or written to the RAM. This feature can be used to ensure that the NFCT peripheral does not overwrite, or read beyond, the RAM assigned to a packet. Note that if the RXD.AMOUNT or TXD.AMOUNT register indicates longer data packets than set in MAXLEN, the frames sent to or received from the physical layer 4452_021 v1.5 201 Peripherals will be incomplete. In that situation, in RX, the OVERRUN bit in the FRAMESTATUS.RX register will be set and an RXERROR event will be triggered. Important: The RXD.AMOUNT and TXD.AMOUNT define a frame length in bytes and bits excluding start of frame (SoF), end of frame (EoF), and parity, but including CRC for RXD.AMOUNT only. Make sure to take potential additional bits into account when setting MAXLEN. Only sending task ENABLERXDATA ensures that a new value in PACKETPTR pointing to the RX buffer in Data RAM is taken into account. If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a hard fault or RAM corruption. For more information about the different memory regions, see Chapter Memory on page 19. The NFCT peripherals normally do alternative receive and transmit frames. Therefore, to prepare for the next frame, the PACKETPTR, MAXLEN, TXD.FRAMECONFIG and TXD.AMOUNT can be updated while the receive is in progress, and, similarly, the PACKETPTR, MAXLEN and RXD.FRAMECONFIG can be updated while the transmit is in progress. They can be updated and prepared for the next NFC frame immediately after the STARTED event of the current frame has been received. Updating the TXD.FRAMECONFIG and TXD.AMOUNT during the current transmit frame or updating RXD.FRAMECONFIG during current receive frame may cause unpredictable behaviour. In accordance with NFC Forum, NFC Digital Protocol Technical Specification, the least significant bit (LSB) from the least significant byte (LSByte) is sent on air first. The bytes are stored in increasing order, starting at the lowest address in the EasyDMA buffer in RAM. 6.13.5 Frame assembler The NFCT peripheral implements a frame assembler in hardware. When the NFCT peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For RX, see Frame disassembler on page 203. For TX, the software must indicate the address of the source buffer in Data RAM and its size through programming the PACKETPTR and MAXLEN registers respectively, then issuing a STARTTX task. MAXLEN must be set so that it matches the size of the frame to be sent. The STARTED event indicates that the PACKETPTR and MAXLEN registers have been captured by the frame assembler EasyDMA. When asserting the STARTTX task, the frame assembler module will start reading TXD.AMOUNT.TXDATABYTES bytes (plus one additional byte if TXD.AMOUNT.TXDATABITS > 0) from the RAM position set by the PACKETPTR. The NFCT peripheral transmits the data as read from RAM, adding framing and the CRC calculated on the fly if set in TXD.FRAMECONFIG. The NFCT peripheral will take (8*TXD.AMOUNT.TXDATABYTES + TXD.AMOUNT.TXDATABITS) bits and assemble a frame according to the settings in TXD.FRAMECONFIG. Both short frames, standard frames, and bit-oriented SDD frames as specified in the NFC Forum, NFC Digital Protocol Technical Specification can be assembled by the correct setting of the TXD.FRAMECONFIG register. The bytes will be transmitted on air in the same order as they are read from RAM with a rising bit order within each byte, least significant bit (LSB) first. That is, b0 will be transmitted on air before b1, and so on. The bits read from RAM will be coded into symbols as defined in the NFC Forum, NFC Digital Protocol Technical Specification. 4452_021 v1.5 202 Peripherals Important: Some NFC Forum documents, such as NFC Forum, NFC Digital Protocol Technical Specification, define bit numbering in a byte from b1 (LSB) to b8 (most significant bit (MSB)), while most other technical documents from the NFC Forum, and also the Nordic Semiconductor documentation, traditionally number them from b0 to b7. The present document uses the b0– b7 numbering scheme. Be aware of this when comparing the NFC Forum, NFC Digital Protocol Technical Specification to others. The frame assembler can be configured in TXD.FRAMECONFIG to add SoF symbol, calculate and add parity bits, and calculate and add CRC to the data read from RAM when assembling the frame. The total frame will then be longer than what is defined by TXD.AMOUNT.TXDATABYTES. TXDATABITS. DISCARDMODE will select if the first bits in the first byte read from RAM or the last bits in the last byte read from RAM will be discarded if TXD.AMOUNT.TXDATABITS are not equal to zero. Note that if TXD.FRAMECONFIG.PARITY = Parity and TXD.FRAMECONFIG.DISCARDMODE=DiscardStart, a parity bit will be included after the noncomplete first byte. No parity will be added after a non-complete last byte. The frame assemble operation is illustrated in Frame assemble illustration on page 203 for different settings in TXD.FRAMECONFIG. All shaded bit fields are added by the frame assembler. Some of these bits are optional and appearances are configured in TXD.FRAMECONFIG. Note that the frames illustrated do not necessarily comply with the NFC specification. The figure is only to illustrate the behavior of the NFCT peripheral. Data from RAM Byte 1: PACKETPTR + 0 b0 .. b7 Byte (TXDATABYTES) b0 .. b7 Byte 2: PACKETPTR + 1 b0 .. b7 Byte (TXDATABYTES + 1) b0 .. b7 (only if TXDATABITS > 0) Frame on air PARITY = Parity TXDATABITS = 0 CRCMODETX = CRC16TX Byte 1 b0 .. b7 SoF P Byte 2 b0 .. b7 Byte (TXDATABYTES) b0 .. b7 P P CRC 1 (8 bit) P CRC 2 (8 bit) P EoF PARITY = Parity TXDATABITS = 4 CRCMODETX = NoCRCTX DISCARDMODE = DiscardStart SoF Byte 1 b4 .. b7 P Byte 2 b0 .. b7 P Byte (TXDATABYTES) b0 .. b7 P Byte (TXDATABYTES + 1) b0 .. b7 P EoF PARITY = Parity TXDATABITS = 0 CRCMODETX = NoCRCTX SoF Byte 1 b0 .. b7 P Byte TXDATABYTES b0 .. b7 P EoF Figure 64: Frame assemble illustration The accurate timing for transmitting the frame on air is set using the frame timing controller settings. 6.13.6 Frame disassembler The NFCT peripheral implements a frame disassembler in hardware. When the NFCT peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For TX, see Frame assembler on page 202. For RX, the software must indicate the address and size of the destination buffer in Data RAM through programming the PACKETPTR and MAXLEN registers before issuing an ENABLERXDATA task. The STARTED event indicates that the PACKETPTR and MAXLEN registers have been captured by the frame disassembler EasyDMA. When an incoming frame starts, the RXFRAMESTART event will get issued and data will be written to the buffer in Data RAM. The frame disassembler will verify and remove any parity bits, start of frame (SoF) and 4452_021 v1.5 203 Peripherals end of frame (EoF) symbols on the fly based on RXD.FRAMECONFIG register configuration. It will, however, verify and transfer the CRC bytes into RAM, if the CRC is enabled through RXD.FRAMECONFIG. When an EoF symbol is detected, the NFCT peripheral will assert the RXFRAMEEND event and write the RXD.AMOUNT register to indicate numbers of received bytes and bits in the data packet. The module does not interpret the content of the data received from the remote NFC device, except for SoF, EoF, parity, and CRC checking, as described above. The frame disassemble operation is illustrated below. Frame on air PARITY = Parity RXDATABITS = 0 CRCMODERX = CRC16RX SoF Byte 1 b0 .. b7 P Byte 2 b0 .. b7 P b0 .. b7 P Byte 2 b0 .. b7 P Byte (RXDATABYTES) b0 .. b7 P CRC 1 (8 bit) Byte (RXDATABYTES) P CRC 2 (8 bit) P EoF PARITY = Parity CRCMODERX = NoCRCTR RXDATABITS = 4 SoF Byte 1 b0 .. b7 Byte (RXDATABYTES + 1) P b4 .. b7 EoF PARITY = NoParity CRCMODERX = NoCRCRX RXDATABITS = 0 SoF Byte 1 b0 .. b7 Byte 2 b0 .. b7 b0 .. b7 Byte RXDATABYTES b0 .. b7 EoF Data to RAM Byte 1: PACKETPTR + 0 b0 .. b7 Byte 2: PACKETPTR + 1 b0 .. b7 Byte (RXDATABYTES) b0 .. b7 Byte (RXDATABYTES + 1) b0 .. b7 (only if RXDATABITS > 0) Figure 65: Frame disassemble illustration Per NFC specification, the time between EoF to the next SoF can be as short as 86 μs, and thefore care must be taken that PACKETPTR and MAXLEN are ready and ENABLERXDATA is issued on time after the end of previous frame. The use of a PPI shortcut from TXFRAMEEND to ENABLERXDATA is recommended. 6.13.7 Frame timing controller The NFCT peripheral includes a frame timing controller that continuously keeps track of the number of the 13.56 MHz RF carrier clock periods since the end of the EoF of the last received frame. The NFCT peripheral can be programmed to send a responding frame within a time window or at an exact count of RF carrier periods. In case of FRAMEDELAYMODE = Window, a STARTTX task triggered before the frame timing controller counter is equal to FRAMEDELAYMIN will force the transmission to halt until the counter is equal to FRAMEDELAYMIN. If the counter is within FRAMEDELAYMIN and FRAMEDELAYMAX when the STARTTX task is triggered, the NFCT peripheral will start the transmission straight away. In case of FRAMEDELAYMODE = ExactVal, a STARTTX task triggered before the frame delay counter is equal to FRAMEDELAYMAX will halt the actual transmission start until the counter is equal to FRAMEDELAYMAX. In case of FRAMEDELAYMODE = WindowGrid, the behaviour is similar to the FRAMEDELAYMODE = Window, but the actual transmission between FRAMEDELAYMIN and FRAMEDELAYMAX starts on a bit grid as defined for NFC-A Listen frames (slot duration of 128 RF carrier periods). An ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) will be asserted if the frame timing controller counter reaches FRAMEDELAYMAX without any STARTTX task triggered. This may happen even when the response is not required as per NFC Forum, NFC Digital Protocol Technical Specification. Any commands handled by the automatic collision resolution that don't involve a response being generated may also result in an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS). The FRAMEDELAYMIN and FRAMEDELAYMAX values shall only be updated before the STARTTX task is triggered. Failing to do so may cause unpredictable behaviour. 4452_021 v1.5 204 Peripherals The frame timing controller operation is illustrated in Frame timing controller (FRAMEDELAYMODE=Window) on page 205. The frame timing controller automatically adjusts the frame timing counter based on the last received data bit according to NFC-A technology in the NFC Forum, NFC Digital Protocol Technical Specification. Receive Last data bit Transmit EoF Subcarrier continues in the 3 cases below Logic ‘0’ Logic ‘1’ 20/fc 84/fc Before Min FRAMEDELAYMAX FRAMEDELAYMIN STARTTX task SoF Subcarrier modulation Between Min and Max STARTTX task SoF Subcarrier modulation After Max (or missing) STARTTX task Subcarrier modulation ERROR event Figure 66: Frame timing controller (FRAMEDELAYMODE=Window) 6.13.8 Collision resolution The NFCT peripheral implements an automatic collision resolution function as defined by the NFC Forum. Automatic collision resolution is enabled by default, and it is recommended that the feature is used since it is power efficient and reduces the complexity of software handling the collision resolution sequence. This feature can be disabled through the MODE field in the AUTOCOLRESCONFIG register. When the automatic collision resolution is disabled, all commands will be sent over EasyDMA as defined in frame disassembler. The SENSRES and SELRES registers need to be programmed upfront in order for the collision resolution to behave correctly. Depending on the NFCIDSIZE field in SENSRES, the following registers also need to be programmed upfront: • NFCID1_LAST if NFCID1SIZE=NFCID1Single (ID = 4 bytes); • NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Double (ID = 7 bytes); • NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Triple (ID = 10 bytes); A pre-defined set of registers, NFC.TAGHEADER0..3, containing a valid NFCID1 value, is available in FICR and can be used by software to populate the NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST registers. NFCID1 byte allocation (top sent first on air) on page 206 explains the position of the ID bytes in NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST, depending on the ID size, and as compared to the definition used in the NFC Forum, NFC Digital Protocol Technical Specification. 4452_021 v1.5 205 Peripherals ID = 4 bytes ID = 7 bytes ID = 10 bytes NFCID1_Q nfcid10 NFCID1_R nfcid11 NFCID1_S nfcid12 NFCID1_T nfcid10 nfcid13 NFCID1_U nfcid11 nfcid14 NFCID1_V nfcid12 nfcid15 NFCID1_W nfcid10 nfcid13 nfcid16 NFCID1_X nfcid11 nfcid14 nfcid17 NFCID1_Y nfcid12 nfcid15 nfcid18 NFCID1_Z nfcid13 nfcid16 nfcid19 Table 57: NFCID1 byte allocation (top sent first on air) The hardware implementation can handle the states from IDLE to ACTIVE_A automatically as defined in the NFC Forum, NFC Activity Technical Specification, and the other states are to be handled by software. The software keeps track of the state through events. The collision resolution will trigger an AUTOCOLRESSTARTED event when it has started. Reaching the ACTIVE_A state is indicated by the SELECTED event. If collision resolution fails, a COLLISION event is triggered. Note that errors occurring during automatic collision resolution may also cause ERROR and/or RXERROR events to be generated. Other events may also get generated. It is recommended that the software ignores any event except COLLISION, SELECTED and FIELDLOST during automatic collision resolution. Software shall also make sure that any unwanted SHORT or PPI shortcut is disabled during automatic collision resolution. The automatic collision resolution will be restarted, if the packets are received with CRC or parity errors while in ACTIVE_A state. The automatic collision resolution feature can be disabled while in ACTIVE_A state to avoid this. The SLP_REQ is automatically handled by the NFCT peripheral when the automatic collision resolution is enabled. However, this results in an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) since the SLP_REQ has no response. This error must be ignored until the SELECTED event is triggered and this error should be cleared by the software when the SELECTED event is triggered. 6.13.9 Antenna interface In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that is within the Vswing limit. Refer to NFCT Electrical Specification on page 227. 6.13.10 NFCT antenna recommendations The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device. Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz. 4452_021 v1.5 206 Peripherals Ctune1 Cp1 Cint1 NFC1 ANTENNA Lant Rin NFC2 Cp2 Ctune2 Cint2 Figure 67: NFCT antenna recommendations The required tuning capacitor value is given by the below equations: An antenna inductance of Lant = 2 μH will give tuning capacitors in the range of 130 pF on each pin. The total capacitance on NFC1 and NFC2 must be matched. 6.13.11 Battery protection If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due to parasitic diodes and ESD structures. If the battery used does not tolerate return current, a series diode must be placed between the battery and the device in order to protect the battery. 6.13.12 Digital Modulation Signal Support for external analog frontends or antenna architectures is possible by optionally outputting the digital modulation signal to a GPIO. The NFCT peripheral is designed to connect directly to a loop antenna, receive a modulated signal from an NFC Reader with its internal analog frontend and transmit data back by changing the input resistance that is then seen as modulated load by the NFC Reader. In addition, the peripheral has an option to output the digital modulation signal to a GPIO. Reception still occurs through the internal analog frontend, whereas transmission can be done by one of the following: • The internal analog frontend through the loop antenna (default) • An external frontend using the digital modulation signal • The combination of both above 4452_021 v1.5 207 Peripherals There are two registers that allow configuration of the modulation signal (i.e. of the response from NFCT to the NFC Reader), MODULATIONCTRL and MODULATIONPSEL. The registers need to be programmed before NFCT sends a response to a request from a reader. Ideally, this configuration is performed during startup and whenever the NFCT peripheral is powered up. The selected GPIO needs to be configured as output in the corresponding GPIO configuration register. It is recommended to set an output value in the corresponding GPIO.OUT register – this value will be driven whenever the NFCT peripheral is disabled. NFCT drives the pin low when there is no modulation, and drives it with On-Off Keying (OOK) modulation of an 847 kHz subcarrier (derived from the carrier frequency) when it responds to commands from an NFC Reader. 6.13.13 References NFC Forum, NFC Analog Specification version 1.0, www.nfc-forum.org NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc-forum.org NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc-forum.org 6.13.14 Registers Base address Peripheral Instance Description Configuration 0x40005000 NFCT NFCT Near field communication tag Table 58: Instances Register Offset Description TASKS_ACTIVATE 0x000 Activate NFCT peripheral for incoming and outgoing frames, change state to activated TASKS_DISABLE 0x004 Disable NFCT peripheral TASKS_SENSE 0x008 Enable NFC sense field mode, change state to sense mode TASKS_STARTTX 0x00C Start transmission of an outgoing frame, change state to transmit TASKS_ENABLERXDATA 0x01C Initializes the EasyDMA for receive. TASKS_GOIDLE 0x024 Force state machine to IDLE state TASKS_GOSLEEP 0x028 Force state machine to SLEEP_A state EVENTS_READY 0x100 The NFCT peripheral is ready to receive and send frames EVENTS_FIELDDETECTED 0x104 Remote NFC field detected EVENTS_FIELDLOST 0x108 Remote NFC field lost EVENTS_TXFRAMESTART 0x10C Marks the start of the first symbol of a transmitted frame EVENTS_TXFRAMEEND 0x110 Marks the end of the last transmitted on-air symbol of a frame EVENTS_RXFRAMESTART 0x114 Marks the end of the first symbol of a received frame EVENTS_RXFRAMEEND 0x118 Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer EVENTS_ERROR 0x11C NFC error reported. The ERRORSTATUS register contains details on the source of the error. EVENTS_RXERROR 0x128 NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of EVENTS_ENDRX 0x12C RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. EVENTS_ENDTX 0x130 Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer the error. EVENTS_AUTOCOLRESSTARTED 0x138 Auto collision resolution process has started EVENTS_COLLISION 0x148 NFC auto collision resolution error reported. EVENTS_SELECTED 0x14C NFC auto collision resolution successfully completed EVENTS_STARTED 0x150 EasyDMA is ready to receive or send frames. SHORTS 0x200 Shortcuts between local events and tasks INTEN 0x300 Enable or disable interrupt 4452_021 v1.5 208 Peripherals Register Offset Description INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ERRORSTATUS 0x404 NFC Error Status register FRAMESTATUS.RX 0x40C Result of last incoming frame NFCTAGSTATE 0x410 NfcTag state register SLEEPSTATE 0x420 Sleep state during automatic collision resolution FIELDPRESENT 0x43C Indicates the presence or not of a valid field FRAMEDELAYMIN 0x504 Minimum frame delay FRAMEDELAYMAX 0x508 Maximum frame delay FRAMEDELAYMODE 0x50C Configuration register for the Frame Delay Timer PACKETPTR 0x510 Packet pointer for TXD and RXD data storage in Data RAM MAXLEN 0x514 Size of the RAM buffer allocated to TXD and RXD data storage each TXD.FRAMECONFIG 0x518 Configuration of outgoing frames TXD.AMOUNT 0x51C Size of outgoing frame RXD.FRAMECONFIG 0x520 Configuration of incoming frames RXD.AMOUNT 0x524 Size of last incoming frame MODULATIONCTRL 0x52C Enables the modulation output to a GPIO pin which can be connected to a second external MODULATIONPSEL 0x538 Pin select for Modulation control. NFCID1_LAST 0x590 Last NFCID1 part (4, 7 or 10 bytes ID) NFCID1_2ND_LAST 0x594 Second last NFCID1 part (7 or 10 bytes ID) NFCID1_3RD_LAST 0x598 Third last NFCID1 part (10 bytes ID) AUTOCOLRESCONFIG 0x59C Controls the auto collision resolution function. This setting must be done before the NFCT antenna. peripheral is activated. SENSRES 0x5A0 NFC-A SENS_RES auto-response settings SELRES 0x5A4 NFC-A SEL_RES auto-response settings Table 59: Register overview 6.13.14.1 TASKS_ACTIVATE Address offset: 0x000 Activate NFCT peripheral for incoming and outgoing frames, change state to activated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, change state to activated Trigger 1 Trigger task 6.13.14.2 TASKS_DISABLE Address offset: 0x004 Disable NFCT peripheral 4452_021 v1.5 209 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_DISABLE Disable NFCT peripheral Trigger task 6.13.14.3 TASKS_SENSE Address offset: 0x008 Enable NFC sense field mode, change state to sense mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_SENSE Enable NFC sense field mode, change state to sense mode Trigger task 6.13.14.4 TASKS_STARTTX Address offset: 0x00C Start transmission of an outgoing frame, change state to transmit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STARTTX Start transmission of an outgoing frame, change state to transmit Trigger 1 Trigger task 6.13.14.5 TASKS_ENABLERXDATA Address offset: 0x01C Initializes the EasyDMA for receive. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_ENABLERXDATA Initializes the EasyDMA for receive. Trigger task 6.13.14.6 TASKS_GOIDLE Address offset: 0x024 Force state machine to IDLE state 4452_021 v1.5 210 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_GOIDLE Force state machine to IDLE state Trigger task 6.13.14.7 TASKS_GOSLEEP Address offset: 0x028 Force state machine to SLEEP_A state Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_GOSLEEP Force state machine to SLEEP_A state Trigger task 6.13.14.8 EVENTS_READY Address offset: 0x100 The NFCT peripheral is ready to receive and send frames Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_READY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The NFCT peripheral is ready to receive and send frames 6.13.14.9 EVENTS_FIELDDETECTED Address offset: 0x104 Remote NFC field detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_FIELDDETECTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Remote NFC field detected 6.13.14.10 EVENTS_FIELDLOST Address offset: 0x108 Remote NFC field lost 4452_021 v1.5 211 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_FIELDLOST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Remote NFC field lost 6.13.14.11 EVENTS_TXFRAMESTART Address offset: 0x10C Marks the start of the first symbol of a transmitted frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXFRAMESTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Marks the start of the first symbol of a transmitted frame 6.13.14.12 EVENTS_TXFRAMEEND Address offset: 0x110 Marks the end of the last transmitted on-air symbol of a frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXFRAMEEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Marks the end of the last transmitted on-air symbol of a frame NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.13 EVENTS_RXFRAMESTART Address offset: 0x114 Marks the end of the first symbol of a received frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXFRAMESTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Marks the end of the first symbol of a received frame 6.13.14.14 EVENTS_RXFRAMEEND Address offset: 0x118 4452_021 v1.5 212 Peripherals Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXFRAMEEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.15 EVENTS_ERROR Address offset: 0x11C NFC error reported. The ERRORSTATUS register contains details on the source of the error. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NFC error reported. The ERRORSTATUS register contains details on the source of the error. NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.16 EVENTS_RXERROR Address offset: 0x128 NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.17 EVENTS_ENDRX Address offset: 0x12C RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 4452_021 v1.5 213 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDRX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.18 EVENTS_ENDTX Address offset: 0x130 Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDTX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.19 EVENTS_AUTOCOLRESSTARTED Address offset: 0x138 Auto collision resolution process has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW EVENTS_AUTOCOLRESSTARTED Value ID Value Description Auto collision resolution process has started NotGenerated 0 Event not generated Generated 1 Event generated 6.13.14.20 EVENTS_COLLISION Address offset: 0x148 NFC auto collision resolution error reported. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_COLLISION 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated NFC auto collision resolution error reported. 214 Peripherals 6.13.14.21 EVENTS_SELECTED Address offset: 0x14C NFC auto collision resolution successfully completed Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_SELECTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated NFC auto collision resolution successfully completed 6.13.14.22 EVENTS_STARTED Address offset: 0x150 EasyDMA is ready to receive or send frames. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated EasyDMA is ready to receive or send frames. 6.13.14.23 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID Access Field A RW FIELDDETECTED_ACTIVATE B F Value ID Value Description Shortcut between event FIELDDETECTED and task ACTIVATE Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW FIELDLOST_SENSE Shortcut between event FIELDLOST and task SENSE RW TXFRAMEEND_ENABLERXDATA Shortcut between event TXFRAMEEND and task ENABLERXDATA Disabled 0 Disable shortcut Enabled 1 Enable shortcut 6.13.14.24 INTEN Address offset: 0x300 Enable or disable interrupt 4452_021 v1.5 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 215 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID T S R Reset 0x00000000 ID Access Field A RW READY B C D E F G H K L M N R S T Value ID Value M L K H G F E D C B A Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event READY RW FIELDDETECTED Enable or disable interrupt for event FIELDDETECTED RW FIELDLOST Enable or disable interrupt for event FIELDLOST RW TXFRAMESTART Enable or disable interrupt for event TXFRAMESTART Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW TXFRAMEEND Enable or disable interrupt for event TXFRAMEEND RW RXFRAMESTART Enable or disable interrupt for event RXFRAMESTART RW RXFRAMEEND Enable or disable interrupt for event RXFRAMEEND RW ERROR Enable or disable interrupt for event ERROR Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW RXERROR Enable or disable interrupt for event RXERROR RW ENDRX Enable or disable interrupt for event ENDRX RW ENDTX Enable or disable interrupt for event ENDTX RW AUTOCOLRESSTARTED Enable or disable interrupt for event AUTOCOLRESSTARTED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW COLLISION Enable or disable interrupt for event COLLISION RW SELECTED Enable or disable interrupt for event SELECTED RW STARTED Enable or disable interrupt for event STARTED 6.13.14.25 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.5 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 216 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID T S R Reset 0x00000000 ID Access Field A RW READY B C D E F G H K L M N N M L K Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event READY RW FIELDDETECTED Write '1' to enable interrupt for event FIELDDETECTED RW FIELDLOST Write '1' to enable interrupt for event FIELDLOST RW TXFRAMESTART Write '1' to enable interrupt for event TXFRAMESTART RW TXFRAMEEND Write '1' to enable interrupt for event TXFRAMEEND RW RXFRAMESTART Write '1' to enable interrupt for event RXFRAMESTART RW RXFRAMEEND Write '1' to enable interrupt for event RXFRAMEEND RW ERROR Write '1' to enable interrupt for event ERROR RW RXERROR Write '1' to enable interrupt for event RXERROR RW ENDRX Write '1' to enable interrupt for event ENDRX RW ENDTX Write '1' to enable interrupt for event ENDTX RW AUTOCOLRESSTARTED Write '1' to enable interrupt for event AUTOCOLRESSTARTED R Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW COLLISION 4452_021 v1.5 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to enable interrupt for event COLLISION 217 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID T S R Reset 0x00000000 ID S T Access Field N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW SELECTED Write '1' to enable interrupt for event SELECTED RW STARTED Write '1' to enable interrupt for event STARTED 6.13.14.26 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID T S R Reset 0x00000000 ID Access Field A RW READY B C D E F G Value ID Value M L K H G F E D C B A Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event READY RW FIELDDETECTED Write '1' to disable interrupt for event FIELDDETECTED RW FIELDLOST Write '1' to disable interrupt for event FIELDLOST RW TXFRAMESTART Write '1' to disable interrupt for event TXFRAMESTART RW TXFRAMEEND Write '1' to disable interrupt for event TXFRAMEEND RW RXFRAMESTART Write '1' to disable interrupt for event RXFRAMESTART RW RXFRAMEEND 4452_021 v1.5 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to disable interrupt for event RXFRAMEEND 218 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID T S R Reset 0x00000000 ID Access Field H RW ERROR K L M N N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event ERROR RW RXERROR Write '1' to disable interrupt for event RXERROR RW ENDRX Write '1' to disable interrupt for event ENDRX RW ENDTX Write '1' to disable interrupt for event ENDTX RW AUTOCOLRESSTARTED Write '1' to disable interrupt for event AUTOCOLRESSTARTED R S T Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW COLLISION Write '1' to disable interrupt for event COLLISION Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW SELECTED Write '1' to disable interrupt for event SELECTED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STARTED Write '1' to disable interrupt for event STARTED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.13.14.27 ERRORSTATUS Address offset: 0x404 NFC Error Status register Write a bit to '1' to clear it. Writing '0' has no effect. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW FRAMEDELAYTIMEOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX 4452_021 v1.5 219 Peripherals 6.13.14.28 FRAMESTATUS.RX Address offset: 0x40C Result of last incoming frame Write a bit to '1' to clear it. Writing '0' has no effect. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B Reset 0x00000000 ID Access Field A RW CRCERROR B C A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description CRCCorrect 0 Valid CRC detected CRCError 1 CRC received does not match local check ParityOK 0 Frame received with parity OK ParityError 1 Frame received with parity error No valid end of frame (EoF) detected RW PARITYSTATUS Parity status of received frame RW OVERRUN Overrun detected NoOverrun 0 No overrun detected Overrun 1 Overrun error 6.13.14.29 NFCTAGSTATE Address offset: 0x410 NfcTag state register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NFCTAGSTATE NfcTag state Disabled 0 Disabled or sense RampUp 2 RampUp Idle 3 Idle Receive 4 Receive FrameDelay 5 FrameDelay Transmit 6 Transmit 6.13.14.30 SLEEPSTATE Address offset: 0x420 Sleep state during automatic collision resolution 4452_021 v1.5 220 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description SLEEPSTATE Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. Idle 0 State is IDLE. SleepA 1 State is SLEEP_A. 6.13.14.31 FIELDPRESENT Address offset: 0x43C Indicates the presence or not of a valid field Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description FIELDPRESENT Indicates if a valid field is present. Available only in the activated state. B R NoField 0 No valid field detected FieldPresent 1 Valid field detected NotLocked 0 Not locked to field Locked 1 Locked to field LOCKDETECT Indicates if the low level has locked to the field 6.13.14.32 FRAMEDELAYMIN Address offset: 0x504 Minimum frame delay Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000480 ID Access Field A RW FRAMEDELAYMIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 Value ID Value Description Minimum frame delay in number of 13.56 MHz clocks 6.13.14.33 FRAMEDELAYMAX Address offset: 0x508 Maximum frame delay Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A Reset 0x00001000 ID Access Field A RW FRAMEDELAYMAX 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Maximum frame delay in number of 13.56 MHz clocks 221 Peripherals 6.13.14.34 FRAMEDELAYMODE Address offset: 0x50C Configuration register for the Frame Delay Timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000001 ID Access Field A RW FRAMEDELAYMODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description FreeRun 0 Window 1 ExactVal 2 Frame is transmitted exactly at FRAMEDELAYMAX WindowGrid 3 Frame is transmitted on a bit grid between Configuration register for the Frame Delay Timer Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX FRAMEDELAYMIN and FRAMEDELAYMAX 6.13.14.35 PACKETPTR Address offset: 0x510 Packet pointer for TXD and RXD data storage in Data RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW PTR Value ID Value Description Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA. 6.13.14.36 MAXLEN Address offset: 0x514 Size of the RAM buffer allocated to TXD and RXD data storage each Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXLEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..257] Size of the RAM buffer allocated to TXD and RXD data storage each 6.13.14.37 TXD.FRAMECONFIG Address offset: 0x518 Configuration of outgoing frames 4452_021 v1.5 222 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D Reset 0x00000017 ID Access Field A RW PARITY B C D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 Value ID Value Description NoParity 0 Parity is not added to TX frames Parity 1 Parity is added to TX frames DiscardEnd 0 Unused bits are discarded at end of frame (EoF) DiscardStart 1 Unused bits are discarded at start of frame (SoF) NoSoF 0 SoF symbol not added SoF 1 SoF symbol added Indicates if parity is added to the frame RW DISCARDMODE Discarding unused bits at start or end of a frame RW SOF Adding SoF or not in TX frames RW CRCMODETX CRC mode for outgoing frames NoCRCTX 0 CRC is not added to the frame CRC16TX 1 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame 6.13.14.38 TXD.AMOUNT Address offset: 0x51C Size of outgoing frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B A A A Reset 0x00000000 ID Access Field A RW TXDATABITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..7] Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). The DISCARDMODE field in FRAMECONFIG.TX selects if unused bits is discarded at the start or at the end of a frame. A value of 0 data bytes and 0 data bits is invalid. B RW TXDATABYTES [0..257] Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing 6.13.14.39 RXD.FRAMECONFIG Address offset: 0x520 Configuration of incoming frames 4452_021 v1.5 223 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0x00000015 ID Access Field A RW PARITY B C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 Value ID Value Description NoParity 0 Parity is not expected in RX frames Parity 1 Parity is expected in RX frames NoSoF 0 SoF symbol is not expected in RX frames SoF 1 SoF symbol is expected in RX frames NoCRCRX 0 CRC is not expected in RX frames CRC16RX 1 Last 16 bits in RX frame is CRC, CRC is checked and Indicates if parity expected in RX frame RW SOF SoF expected or not in RX frames RW CRCMODERX CRC mode for incoming frames CRCSTATUS updated 6.13.14.40 RXD.AMOUNT Address offset: 0x524 Size of last incoming frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RXDATABITS Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). Frames with 0 data bytes and less than 7 data bits are invalid and are not received properly. B R RXDATABYTES Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) 6.13.14.41 MODULATIONCTRL Address offset: 0x52C Enables the modulation output to a GPIO pin which can be connected to a second external antenna. See MODULATIONPSEL for GPIO configuration. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000001 ID Access Field A RW MODULATIONCTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Configuration of modulation control. Invalid 0x0 Invalid, defaults to same behaviour as for Internal Internal 0x1 Use internal modulator only ModToGpio 0x2 Output digital modulation signal to a GPIO pin. InternalAndModToGpio 0x3 Use internal modulator and output digital modulation signal to a GPIO pin. 6.13.14.42 MODULATIONPSEL Address offset: 0x538 Pin select for Modulation control. 4452_021 v1.5 224 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.13.14.43 NFCID1_LAST Address offset: 0x590 Last NFCID1 part (4, 7 or 10 bytes ID) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0x00006363 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 ID Access Field Value ID Value Description A RW NFCID1_Z NFCID1 byte Z (very last byte sent) B RW NFCID1_Y NFCID1 byte Y C RW NFCID1_X NFCID1 byte X D RW NFCID1_W NFCID1 byte W 6.13.14.44 NFCID1_2ND_LAST Address offset: 0x594 Second last NFCID1 part (7 or 10 bytes ID) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C C C C C C C C B B B B B B B B A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A RW NFCID1_V NFCID1 byte V B RW NFCID1_U NFCID1 byte U C RW NFCID1_T NFCID1 byte T 6.13.14.45 NFCID1_3RD_LAST Address offset: 0x598 Third last NFCID1 part (10 bytes ID) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C C C C C C C C B B B B B B B B A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW NFCID1_S NFCID1 byte S B RW NFCID1_R NFCID1 byte R C RW NFCID1_Q NFCID1 byte Q 4452_021 v1.5 Value ID Value Description 225 Peripherals 6.13.14.46 AUTOCOLRESCONFIG Address offset: 0x59C Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. When modifiying this register bit 1 must be written to '1'. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000002 ID Access Field A RW MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Enabled 0 Auto collision resolution enabled Disabled 1 Auto collision resolution disabled Enables/disables auto collision resolution 6.13.14.47 SENSRES Address offset: 0x5A0 NFC-A SENS_RES auto-response settings Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E E E E D D D D C C B A A A A A Reset 0x00000001 ID Access Field A RW BITFRAMESDD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification SDD00000 0 SDD pattern 00000 SDD00001 1 SDD pattern 00001 SDD00010 2 SDD pattern 00010 SDD00100 4 SDD pattern 00100 SDD01000 8 SDD pattern 01000 SDD10000 16 SDD pattern 10000 B RW RFU5 Reserved for future use. Shall be 0. C RW NFCIDSIZE NFCID1 size. This value is used by the auto collision resolution engine. D NFCID1Single 0 NFCID1 size: single (4 bytes) NFCID1Double 1 NFCID1 size: double (7 bytes) NFCID1Triple 2 NFCID1 size: triple (10 bytes) RW PLATFCONFIG Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification E RW RFU74 Reserved for future use. Shall be 0. 6.13.14.48 SELRES Address offset: 0x5A4 NFC-A SEL_RES auto-response settings 4452_021 v1.5 226 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D D C C B A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW RFU10 Value ID Value Description Reserved for future use. Shall be 0. B RW CASCADE Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) C RW RFU43 Reserved for future use. Shall be 0. D RW PROTOCOL Protocol as defined by the b7:b6 of SEL_RES response in the E RW RFU7 NFC Forum, NFC Digital Protocol Technical Specification Reserved for future use. Shall be 0. 6.13.15 Electrical specification 6.13.15.1 NFCT Electrical Specification Symbol Description fc Frequency of operation Min. Typ. Max. CMI Carrier modulation index DR Data Rate 106 kbps Vsense Peak differential Field detect threshold level on NFC1- 1.2 Vp 13.56 Units MHz 95 % 15 NFC2 Imax Maximum input current on NFCT pins 80 mA Max. Units 500 µs 20 µs 6.13.15.2 NFCT Timing Parameters Symbol Description tactivate Time from task_ACTIVATE in SENSE or DISABLE state to Min. ACTIVATE_A or IDLE state tsense Typ. 16 Time from remote field is present in SENSE mode to FIELDDETECTED event is asserted DISABLE ACTIVATE SENSE TASKS tactivate tsense tsense RF-Carrier MODES DISABLE SENSE_FIELD IDLERU Activated DISABLE FIELDDETECTED FIELDLOST READY FIELDDETECTED EVENTS Figure 68: NFCT timing parameters (Shortcuts for FIELDDETECTED and FIELDLOST are disabled) 6.14 PDM — Pulse density modulation interface The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock 15 16 Input is high impedance in sense mode Does not account for voltage supply and oscillator startup times 4452_021 v1.5 227 Peripherals and supports single-channel or dual-channel (left and right) data input. Data is transferred directly to RAM buffers using EasyDMA. Listed here are the main features for PDM: • • • • • Up to two PDM microphones configured as a left/right pair using the same data input 16 kHz output sample rate, 16-bit samples EasyDMA support for sample buffering HW decimation filters Selectable ratio of 64 or 80 between PDM_CLK and output sample rate The PDM module illustrated below is interfacing up to two digital microphones with the PDM interface. EasyDMA is implemented to relieve the real-time requirements associated with controlling of the PDM slave from a low priority CPU execution context. It also includes all the necessary digital filter elements to produce pulse code modulation (PCM) samples. The PDM module allows continuous audio streaming. Bandpass and decimation (left) PDM to PCM Bandpass and decimation (right) RAM Sampling DIN PDM to PCM EasyDMA Master clock generator CLK Figure 69: PDM module 6.14.1 Master clock generator The master clock generator's PDMCLKCTRL register allows adjusting the PDM clock's frequency. The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but not mandatory) to use the Xtal as HFCLK source. 6.14.2 Module operation By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, and bits for the right are sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter which converts the PDM stream into 16-bit PCM samples, then filters and down-samples them to reach the appropriate sample rate. The EDGE field in the MODE register allows swapping left and right, so that left will be sampled on rising edge, and right on falling. The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM. Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono). To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination address pointer as the previous buffer is filled. The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes effective after the current frame has finished transferring, which will generate the STOPPED event. The STOPPED event indicates that all activity in the module is finished, and that the data is available in RAM (EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may result in unpredictable behavior. 4452_021 v1.5 228 Peripherals 6.14.3 Decimation filter In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in the PDM interface module. The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel on clock low). Depending on the RATIO selected, its output is 2 × 16-bit PCM samples at a sample rate either 64 times or 80 times (depending on the RATIO register) lower than the PDM clock rate. The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain is controlled by the GAINL and GAINR registers. As an example, if the goal is to achieve 2500 RMS output samples (16-bit) with a 1 kHz 90 dBA signal into a -26 dBFS sensitivity PDM microphone, do the following: • Sum the PDM module's default gain ( GPDM,default ) and the gain introduced by the microphone and acoustic path of his implementation (an attenuation would translate into a negative gain) • Adjust GAINL and GAINR by the above summed amount. Assuming that only the PDM module influences the gain, GAINL and GAINR must be set to -GPDM,default dB to achieve the requirement. With GPDM,default=3.2 dB, and as GAINL and GAINR are expressed in 0.5 dB steps, the closest value to program would be 3.0 dB, which can be calculated as: GAINL = GAINR = (DefaultGain - (2 * 3)) Remember to check that the resulting values programmed into GAINL and GAINR fall within MinGain and MaxGain. 6.14.4 EasyDMA Samples will be written directly to RAM, and EasyDMA must be configured accordingly. The address pointer for the EasyDMA channel is set in SAMPLE.PTR register. If the destination address set in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. DMA supports Stereo (Left+Right 16-bit samples) and Mono (Left only) data transfer, depending on the setting in the OPERATION field in the MODE register. The samples are stored little endian. MODE.OPERATION Bits per sample Result stored per RAM Physical RAM allocated Result boundary indexes Note word (32-bit words) in RAM Stereo 32 (2x16) L+R ceil(SAMPLE.MAXCNT/2) R0=[31:16]; L0=[15:0] Mono 16 2xL ceil(SAMPLE.MAXCNT/2) L1=[31:16]; L0=[15:0] Default Table 60: DMA sample storage The destination buffer in RAM consists of one block, the size of which is set in SAMPLE.MAXCNT register. Format is number of 16-bit samples. The physical RAM allocated is always: (RAM allocation, in bytes) = SAMPLE.MAXCNT * 2; (but the mapping of the samples depends on MODE.OPERATION. If OPERATION=Stereo, RAM will contain a succession of left and right samples. If OPERATION=Mono, RAM will contain a succession of left only samples. 4452_021 v1.5 229 Peripherals For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as compared to the mono sampling time. The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT registers have been written. When starting the module, it will take some time for the filters to start outputting valid data. Transients from the PDM microphone itself may also occur. The first few samples (typically around 50) might hence contain invalid values or transients. It is therefore advised to discard the first few samples after a PDM start. As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this register is double-buffered), to ensure continuous operation. When the buffer in RAM is filled with samples, an END event is triggered. The firmware can start processing the data in the buffer. Meanwhile, the PDM module starts acquiring data into the new buffer pointed to by SAMPLE.PTR, and sends a new STARTED event, so that the firmware can update SAMPLE.PTR to the next buffer address. 6.14.5 Hardware example PDM can be configured with a single microphone (mono), or with two microphones. When a single microphone is used, connect the microphone clock to CLK, and data to DIN. Vdd L/R nRFxxxxx CLK CLK DATA DIN CLK DIN Figure 70: Example of a single PDM microphone, wired as left Vdd L/R nRFxxxxx CLK CLK DATA DIN CLK DIN Figure 71: Example of a single PDM microphone, wired as right Note that in a single-microphone (mono) configuration, depending on the microphone’s implementation, either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable data. If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the same brand and type so that their timings in left and right operation match. Vdd L/R nRFxxxxx CLK CLK DATA DIN Vdd CLK L/R DATA CLK DIN Figure 72: Example of two PDM microphones 4452_021 v1.5 230 Peripherals 6.14.6 Pin configuration The CLK and DIN signals associated to the PDM module are mapped to physical pins according to the configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in any PSEL register is set to Disconnected, the associated PDM module signal will not be connected to the required physical pins, and will not operate properly. The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module is enabled, and retained only as long as the device is in System ON mode. See POWER — Power supply on page 61 for more information about power modes. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. To ensure correct behavior in the PDM module, the pins used by the PDM module must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 231 before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is supposed to be connected to an external PDM circuit. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. PDM signal PDM pin Direction Output value CLK As specified in PSEL.CLK Output 0 DIN As specified in PSEL.DIN Input Not applicable Comment Table 61: GPIO configuration before enabling peripheral 6.14.7 Registers Base address Peripheral Instance Description 0x4001D000 PDM PDM Pulse Density modulation (digital Configuration microphone) interface Table 62: Instances Register Offset Description TASKS_START 0x000 Starts continuous PDM transfer TASKS_STOP 0x004 Stops PDM transfer EVENTS_STARTED 0x100 PDM transfer has started EVENTS_STOPPED 0x104 PDM transfer has finished EVENTS_END 0x108 The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 PDM module enable register PDMCLKCTRL 0x504 PDM clock generator control MODE 0x508 Defines the routing of the connected PDM microphones' signals GAINL 0x518 Left output gain adjustment GAINR 0x51C Right output gain adjustment RATIO 0x520 Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. PSEL.CLK 0x540 Pin number configuration for PDM CLK signal PSEL.DIN 0x544 Pin number configuration for PDM DIN signal SAMPLE.PTR 0x560 RAM address pointer to write samples to with EasyDMA 4452_021 v1.5 231 Peripherals Register Offset Description SAMPLE.MAXCNT 0x564 Number of samples to allocate memory for in EasyDMA mode Table 63: Register overview 6.14.7.1 TASKS_START Address offset: 0x000 Starts continuous PDM transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_START Starts continuous PDM transfer Trigger task 6.14.7.2 TASKS_STOP Address offset: 0x004 Stops PDM transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stops PDM transfer Trigger task 6.14.7.3 EVENTS_STARTED Address offset: 0x100 PDM transfer has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated PDM transfer has started 6.14.7.4 EVENTS_STOPPED Address offset: 0x104 PDM transfer has finished 4452_021 v1.5 232 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated PDM transfer has finished 6.14.7.5 EVENTS_END Address offset: 0x108 The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_END 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM NotGenerated 0 Event not generated Generated 1 Event generated 6.14.7.6 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW STARTED B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event STARTED RW STOPPED Enable or disable interrupt for event STOPPED RW END Enable or disable interrupt for event END Disabled 0 Disable Enabled 1 Enable 6.14.7.7 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.5 233 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW STARTED B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event STARTED RW STOPPED Write '1' to enable interrupt for event STOPPED RW END Write '1' to enable interrupt for event END 6.14.7.8 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID Access Field A RW STARTED B C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STARTED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STOPPED Write '1' to disable interrupt for event STOPPED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW END Write '1' to disable interrupt for event END Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.14.7.9 ENABLE Address offset: 0x500 PDM module enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ENABLE 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable PDM module 234 Peripherals 6.14.7.10 PDMCLKCTRL Address offset: 0x504 PDM clock generator control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x08400000 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW FREQ Value ID Value Description 1000K 0x08000000 PDM_CLK = 32 MHz / 32 = 1.000 MHz Default 0x08400000 PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for 1067K 0x08800000 PDM_CLK = 32 MHz / 30 = 1.067 MHz 1231K 0x09800000 PDM_CLK = 32 MHz / 26 = 1.231 MHz 1280K 0x0A000000 PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for 1333K 0x0A800000 PDM_CLK frequency configuration RATIO=Ratio64. RATIO=Ratio80. PDM_CLK = 32 MHz / 24 = 1.333 MHz 6.14.7.11 MODE Address offset: 0x508 Defines the routing of the connected PDM microphones' signals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A RW OPERATION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Mono or stereo operation Stereo 0 Mono 1 Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] B RW EDGE Defines on which PDM_CLK edge left (or mono) is sampled LeftFalling 0 Left (or mono) is sampled on falling edge of PDM_CLK LeftRising 1 Left (or mono) is sampled on rising edge of PDM_CLK 6.14.7.12 GAINL Address offset: 0x518 Left output gain adjustment 4452_021 v1.5 235 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000028 ID Access Field A RW GAINL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value ID Value Description Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust MinGain 0x00 -20 dB gain adjustment (minimum) DefaultGain 0x28 0 dB gain adjustment MaxGain 0x50 +20 dB gain adjustment (maximum) 6.14.7.13 GAINR Address offset: 0x51C Right output gain adjustment Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000028 ID Access Field A RW GAINR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value ID Value Description Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) MinGain 0x00 -20 dB gain adjustment (minimum) DefaultGain 0x28 0 dB gain adjustment MaxGain 0x50 +20 dB gain adjustment (maximum) 6.14.7.14 RATIO Address offset: 0x520 Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW RATIO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Ratio64 0 Ratio of 64 Ratio80 1 Ratio of 80 Selects the ratio between PDM_CLK and output sample rate 6.14.7.15 PSEL.CLK Address offset: 0x540 4452_021 v1.5 236 Peripherals Pin number configuration for PDM CLK signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.14.7.16 PSEL.DIN Address offset: 0x544 Pin number configuration for PDM DIN signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.14.7.17 SAMPLE.PTR Address offset: 0x560 RAM address pointer to write samples to with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW SAMPLEPTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Address to write PDM samples to over DMA Note: See the memory chapter for details about which memories are available for EasyDMA. 6.14.7.18 SAMPLE.MAXCNT Address offset: 0x564 Number of samples to allocate memory for in EasyDMA mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW BUFFSIZE 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..32767] Length of DMA RAM allocation in number of samples 237 Peripherals 6.14.8 Electrical specification 6.14.8.1 PDM Electrical Specification Symbol Description fPDM,CLK,64 PDM clock speed. PDMCLKCTRL = Default (Setting needed Min. Typ. Max. Units 1.032 MHz 1.280 MHz for 16 MHz sample frequency @ RATIO = Ratio64) fPDM,CLK,80 PDM clock speed. PDMCLKCTRL = 1280K (Setting needed for 16 MHz sample frequency @ RATIO = Ratio80) tPDM,JITTER Jitter in PDM clock output TdPDM,CLK PDM clock duty cycle tPDM,DATA Decimation filter delay tPDM,cv Allowed clock edge to data valid tPDM,ci Allowed (other) clock edge to data invalid 0 ns tPDM,s Data setup time at fPDM,CLK=1.024 MHz or 1.280 MHz 65 ns tPDM,h Data hold time at fPDM,CLK=1.024 MHz or 1.280 MHz 0 GPDM,default Default (reset) absolute gain of the PDM module 40 50 20 ns 60 % 5 ms 125 ns ns 3.2 dB tPDM,CLK CLK tPDM,cv tPDM,s tPDM,h=tPDM,ci DIN (L) tPDM,cv tPDM,s tPDM,h=tPDM,ci DIN(R) Figure 73: PDM timing diagram 6.15 PPI — Programmable peripheral interconnect The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI. 4452_021 v1.5 238 Peripherals CH[1].EEP CH[0].EEP Peripheral 1 Peripheral 2 CH[n].EEP Event 1 Event 2 Event 1 Event 2 Event 3 0 0 0 1 1 1 n n n CHEN CHG[0] ... CHG[m] 16MHz Task 1 Task 1 Task 2 Task 3 CH[0].TEP Peripheral 1 Peripheral 2 FORK[0].TEP Figure 74: PPI block diagram The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way as ordinary PPI channels. Instance Channel Number of channels PPI 0-19 20 PPI (fixed) 20-31 12 Table 64: Configurable and fixed PPI channels The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel is composed of three end point registers, one EEP, and two TEPs. A peripheral task is connected to a TEP using the address of the task register associated with the task. Similarly, a peripheral event is connected to an EEP using the address of the event register associated with the event. On each PPI channel, the signals are synchronized to the 16 MHz clock to avoid any internal violation of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period. Note: Shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz synchronization, and are therefore not delayed. 4452_021 v1.5 239 Peripherals Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0]. There are two ways of enabling and disabling PPI channels: • Enable or disable PPI channels individually using the CHEN, CHENSET, and CHENCLR registers. • Enable or disable PPI channels in PPI channel groups through the groups’ ENABLE and DISABLE tasks. Prior to these tasks being triggered, the PPI channel group must be configured to define which PPI channels belong to which groups. Note: When a channel belongs to two groups m and n, and the tasks CHG[m].EN and CHG[n].DIS occur simultaneously (m and n can be equal or different), the CHG[m].EN on that channel has priority. PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they can be hooked to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels and one task can be triggered by multiple events in the same way. 6.15.1 Pre-programmed channels Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for these channels are still programmable and can be used by the application. For a list of pre-programmed PPI channels, see the following table. Channel EEP TEP 20 TIMER0->EVENTS_COMPARE[0] RADIO->TASKS_TXEN 21 TIMER0->EVENTS_COMPARE[0] RADIO->TASKS_RXEN 22 TIMER0->EVENTS_COMPARE[1] RADIO->TASKS_DISABLE 23 RADIO->EVENTS_BCMATCH AAR->TASKS_START 24 RADIO->EVENTS_READY CCM->TASKS_KSGEN 25 RADIO->EVENTS_ADDRESS CCM->TASKS_CRYPT 26 RADIO->EVENTS_ADDRESS TIMER0->TASKS_CAPTURE[1] 27 RADIO->EVENTS_END TIMER0->TASKS_CAPTURE[2] 28 RTC0->EVENTS_COMPARE[0] RADIO->TASKS_TXEN 29 RTC0->EVENTS_COMPARE[0] RADIO->TASKS_RXEN 30 RTC0->EVENTS_COMPARE[0] TIMER0->TASKS_CLEAR 31 RTC0->EVENTS_COMPARE[0] TIMER0->TASKS_START Table 65: Pre-programmed channels 6.15.2 Registers Base address Peripheral Instance Description 0x4001F000 PPI PPI Programmable peripheral interconnect Configuration Table 66: Instances Register Offset Description TASKS_CHG[0].EN 0x000 Enable channel group 0 TASKS_CHG[0].DIS 0x004 Disable channel group 0 TASKS_CHG[1].EN 0x008 Enable channel group 1 TASKS_CHG[1].DIS 0x00C Disable channel group 1 4452_021 v1.5 240 Peripherals Register Offset Description TASKS_CHG[2].EN 0x010 Enable channel group 2 TASKS_CHG[2].DIS 0x014 Disable channel group 2 TASKS_CHG[3].EN 0x018 Enable channel group 3 TASKS_CHG[3].DIS 0x01C Disable channel group 3 TASKS_CHG[4].EN 0x020 Enable channel group 4 TASKS_CHG[4].DIS 0x024 Disable channel group 4 TASKS_CHG[5].EN 0x028 Enable channel group 5 TASKS_CHG[5].DIS 0x02C Disable channel group 5 CHEN 0x500 Channel enable register CHENSET 0x504 Channel enable set register CHENCLR 0x508 Channel enable clear register CH[0].EEP 0x510 Channel 0 event endpoint CH[0].TEP 0x514 Channel 0 task endpoint CH[1].EEP 0x518 Channel 1 event endpoint CH[1].TEP 0x51C Channel 1 task endpoint CH[2].EEP 0x520 Channel 2 event endpoint CH[2].TEP 0x524 Channel 2 task endpoint CH[3].EEP 0x528 Channel 3 event endpoint CH[3].TEP 0x52C Channel 3 task endpoint CH[4].EEP 0x530 Channel 4 event endpoint CH[4].TEP 0x534 Channel 4 task endpoint CH[5].EEP 0x538 Channel 5 event endpoint CH[5].TEP 0x53C Channel 5 task endpoint CH[6].EEP 0x540 Channel 6 event endpoint CH[6].TEP 0x544 Channel 6 task endpoint CH[7].EEP 0x548 Channel 7 event endpoint CH[7].TEP 0x54C Channel 7 task endpoint CH[8].EEP 0x550 Channel 8 event endpoint CH[8].TEP 0x554 Channel 8 task endpoint CH[9].EEP 0x558 Channel 9 event endpoint CH[9].TEP 0x55C Channel 9 task endpoint CH[10].EEP 0x560 Channel 10 event endpoint CH[10].TEP 0x564 Channel 10 task endpoint CH[11].EEP 0x568 Channel 11 event endpoint CH[11].TEP 0x56C Channel 11 task endpoint CH[12].EEP 0x570 Channel 12 event endpoint CH[12].TEP 0x574 Channel 12 task endpoint CH[13].EEP 0x578 Channel 13 event endpoint CH[13].TEP 0x57C Channel 13 task endpoint CH[14].EEP 0x580 Channel 14 event endpoint CH[14].TEP 0x584 Channel 14 task endpoint CH[15].EEP 0x588 Channel 15 event endpoint CH[15].TEP 0x58C Channel 15 task endpoint CH[16].EEP 0x590 Channel 16 event endpoint CH[16].TEP 0x594 Channel 16 task endpoint CH[17].EEP 0x598 Channel 17 event endpoint CH[17].TEP 0x59C Channel 17 task endpoint CH[18].EEP 0x5A0 Channel 18 event endpoint CH[18].TEP 0x5A4 Channel 18 task endpoint CH[19].EEP 0x5A8 Channel 19 event endpoint CH[19].TEP 0x5AC Channel 19 task endpoint CHG[0] 0x800 Channel group 0 CHG[1] 0x804 Channel group 1 4452_021 v1.5 241 Peripherals Register Offset Description CHG[2] 0x808 Channel group 2 CHG[3] 0x80C Channel group 3 CHG[4] 0x810 Channel group 4 CHG[5] 0x814 Channel group 5 FORK[0].TEP 0x910 Channel 0 task endpoint FORK[1].TEP 0x914 Channel 1 task endpoint FORK[2].TEP 0x918 Channel 2 task endpoint FORK[3].TEP 0x91C Channel 3 task endpoint FORK[4].TEP 0x920 Channel 4 task endpoint FORK[5].TEP 0x924 Channel 5 task endpoint FORK[6].TEP 0x928 Channel 6 task endpoint FORK[7].TEP 0x92C Channel 7 task endpoint FORK[8].TEP 0x930 Channel 8 task endpoint FORK[9].TEP 0x934 Channel 9 task endpoint FORK[10].TEP 0x938 Channel 10 task endpoint FORK[11].TEP 0x93C Channel 11 task endpoint FORK[12].TEP 0x940 Channel 12 task endpoint FORK[13].TEP 0x944 Channel 13 task endpoint FORK[14].TEP 0x948 Channel 14 task endpoint FORK[15].TEP 0x94C Channel 15 task endpoint FORK[16].TEP 0x950 Channel 16 task endpoint FORK[17].TEP 0x954 Channel 17 task endpoint FORK[18].TEP 0x958 Channel 18 task endpoint FORK[19].TEP 0x95C Channel 19 task endpoint FORK[20].TEP 0x960 Channel 20 task endpoint FORK[21].TEP 0x964 Channel 21 task endpoint FORK[22].TEP 0x968 Channel 22 task endpoint FORK[23].TEP 0x96C Channel 23 task endpoint FORK[24].TEP 0x970 Channel 24 task endpoint FORK[25].TEP 0x974 Channel 25 task endpoint FORK[26].TEP 0x978 Channel 26 task endpoint FORK[27].TEP 0x97C Channel 27 task endpoint FORK[28].TEP 0x980 Channel 28 task endpoint FORK[29].TEP 0x984 Channel 29 task endpoint FORK[30].TEP 0x988 Channel 30 task endpoint FORK[31].TEP 0x98C Channel 31 task endpoint Table 67: Register overview 6.15.2.1 TASKS_CHG[n].EN (n=0..5) Address offset: 0x000 + (n × 0x8) Enable channel group n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description EN 4452_021 v1.5 Enable channel group n Trigger task 242 Peripherals 6.15.2.2 TASKS_CHG[n].DIS (n=0..5) Address offset: 0x004 + (n × 0x8) Disable channel group n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description DIS Disable channel group n Trigger task 6.15.2.3 CHEN Address offset: 0x500 Channel enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 ID Access Field A-T RW CH[i] (i=0..19) U-f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable channel Enabled 1 Enable channel Enable or disable channel i RW CH[i] (i=20..31) Enable or disable channel i Disabled 0 Disable channel Enabled 1 Enable channel 6.15.2.4 CHENSET Address offset: 0x504 Channel enable set register Read: reads value of CH{i} field in CHEN register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 ID Access Field A-T RW CH[i] (i=0..19) U-f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Channel i enable set register. Writing '0' has no effect. Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Set 1 Write: Enable channel RW CH[i] (i=20..31) Channel i enable set register. Writing '0' has no effect. Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Set 1 Write: Enable channel 6.15.2.5 CHENCLR Address offset: 0x508 Channel enable clear register 4452_021 v1.5 243 Peripherals Read: reads value of CH{i} field in CHEN register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 ID Access Field A-T RW CH[i] (i=0..19) U-f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Channel i enable clear register. Writing '0' has no effect. Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Clear 1 Write: disable channel RW CH[i] (i=20..31) Channel i enable clear register. Writing '0' has no effect. Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Clear 1 Write: disable channel 6.15.2.6 CH[n].EEP (n=0..19) Address offset: 0x510 + (n × 0x8) Channel n event endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW EEP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to event register. Accepts only addresses to registers from the Event group. 6.15.2.7 CH[n].TEP (n=0..19) Address offset: 0x514 + (n × 0x8) Channel n task endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW TEP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to task register. Accepts only addresses to registers from the Task group. 6.15.2.8 CHG[n] (n=0..5) Address offset: 0x800 + (n × 0x4) Channel group n 4452_021 v1.5 244 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A-T RW CH[i] (i=0..19) U-f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A Value ID Value Description Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Include or exclude channel i RW CH[i] (i=20..31) Include or exclude channel i 6.15.2.9 FORK[n].TEP (n=0..19, 20..31) Address offset: 0x910 + (n × 0x4) Channel n task endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW TEP Value ID Value Description Pointer to task register 6.16 PWM — Pulse width modulation The pulse with modulation (PWM) module enables the generation of pulse width modulated signals on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs. The following are the main features of a PWM module: • • • • • Programmable PWM frequency Up to four PWM channels with individual polarity and duty cycle values Edge or center-aligned pulses across PWM channels Multiple duty cycle arrays (sequences) defined in RAM Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA (no CPU involvement) • Change of polarity, duty cycle, and base frequency possibly on every PWM period • RAM sequences can be repeated or connected into loops 4452_021 v1.5 245 Peripherals Sequence 0 DATA RAM STARTED STOPPED EasyDMA START Sequence 1 PWM STOP SEQSTART[0] SEQSTART[1] SEQ[n].REFRESH SEQSTARTED[0] SEQSTARTED[1] SEQEND[0] SEQEND[1] Decoder NEXTSTEP Carry/Reload COMP0 PSEL.OUT[0] COMP1 PSEL.OUT[1] COMP2 PSEL.OUT[2] COMP3 PSEL.OUT[3] Wave Counter PWM_CLK COUNTERTOP PRESCALER Figure 75: PWM module 6.16.1 Wave counter The wave counter is responsible for generating the pulses at a duty cycle that depends on the compare values, and at a frequency that depends on COUNTERTOP. There is one common 15-bit counter with four compare channels. Thus, all four channels will share the same period (PWM frequency), but can have individual duty cycle and polarity. The polarity is set by a value read from RAM (see figure Decoder memory access modes on page 249). Whether the counter counts up, or up and down, is controlled by the MODE register. The timer top value is controlled by the COUNTERTOP register. This register value, in conjunction with the selected PRESCALER of the PWM_CLK, will result in a given PWM period. A COUNTERTOP value smaller than the compare setting will result in a state where no PWM edges are generated. OUT[n] is held high, given that the polarity is set to FallingEdge. All compare registers are internal and can only be configured through decoder presented later. COUNTERTOP can be safely written at any time. Sampling follows the START task. If DECODER.LOAD=WaveForm, the register value is ignored and taken from RAM instead (see section Decoder with EasyDMA on page 249 for more details). If DECODER.LOAD is anything else than the WaveForm, it is sampled following a STARTSEQ[n] task and when loading a new value from RAM during a sequence playback. The following figure shows the counter operating in up mode (MODE=PWM_MODE_Up), with three PWM channels with the same frequency but different duty cycle: 4452_021 v1.5 246 Peripherals COUNTERTOP COMP1 COMP0 OUT[0] OUT[1] Figure 76: PWM counter in up mode example - FallingEdge polarity The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert. OUT[n] is held low if the compare value is 0 and held high if set to COUNTERTOP, given that the polarity is set to FallingEdge. Counter running in up mode results in pulse widths that are edge-aligned. The following is the code for the counter in up mode example: uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY, PWM_CH3_DUTY}; NRF_PWM0->PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin DECODER = (PWM_LOOP_CNT_Disabled SEQ[0].PTR = (PWM_DECODER_LOAD_Common SEQ[0].CNT (PWM_DECODER_MODE_RefreshCount TASKS_SEQSTART[0] = 1; To completely stop the PWM generation and force the associated pins to a defined state, a STOP task can be triggered at any time. A STOPPED event is generated when the PWM generation has stopped at the end of currently running PWM period, and the pins go into their idle state as defined in GPIO OUT register. PWM generation can then only be restarted through a SEQSTART[n] task. SEQSTART[n] will resume PWM generation after having loaded the first value from the RAM buffer defined in the SEQ[n].PTR register. The table below indicates when specific registers get sampled by the hardware. Care should be taken when updating these registers to avoid that values are applied earlier than expected. 4452_021 v1.5 251 Peripherals Register Taken into account by hardware Recommended (safe) update SEQ[n].PTR When sending the SEQSTART[n] task After having received the SEQSTARTED[n] event SEQ[n].CNT When sending the SEQSTART[n] task After having received the SEQSTARTED[n] event SEQ[0].ENDDELAY When sending the SEQSTART[0] task Before starting sequence [0] through a SEQSTART[0] task Every time a new value from sequence [0] has been loaded from When no more value from sequence [0] gets loaded from RAM RAM and gets applied to the Wave Counter (indicated by the (indicated by the SEQEND[0] event) PWMPERIODEND event) At any time during sequence [1] (which starts when the SEQSTARTED[1] event is generated) SEQ[1].ENDDELAY When sending the SEQSTART[1] task Before starting sequence [1] through a SEQSTART[1] task Every time a new value from sequence [1] has been loaded from When no more value from sequence [1] gets loaded from RAM RAM and gets applied to the Wave Counter (indicated by the (indicated by the SEQEND[1] event) PWMPERIODEND event) At any time during sequence [0] (which starts when the SEQSTARTED[0] event is generated) SEQ[0].REFRESH When sending the SEQSTART[0] task Before starting sequence [0] through a SEQSTART[0] task Every time a new value from sequence [0] has been loaded from At any time during sequence [1] (which starts when the RAM and gets applied to the Wave Counter (indicated by the SEQSTARTED[1] event is generated) PWMPERIODEND event) SEQ[1].REFRESH When sending the SEQSTART[1] task Before starting sequence [1] through a SEQSTART[1] task Every time a new value from sequence [1] has been loaded from At any time during sequence [0] (which starts when the RAM and gets applied to the Wave Counter (indicated by the SEQSTARTED[0] event is generated) PWMPERIODEND event) COUNTERTOP MODE In DECODER.LOAD=WaveForm: this register is ignored. Before starting PWM generation through a SEQSTART[n] task In all other LOAD modes: at the end of current PWM period After a STOP task has been triggered, and the STOPPED event has (indicated by the PWMPERIODEND event) been received. Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. DECODER Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. PRESCALER Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. LOOP Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. PSEL.OUT[n] Immediately Before enabling the PWM instance through the ENABLE register Table 68: When to safely update PWM registers Note: SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored at the end of a complex sequence, indicated by a LOOPSDONE event. The reason for this is that the last value loaded from RAM is maintained until further action from software (restarting a new sequence, or stopping PWM generation). A more complex example, where LOOP.CNT>0, is shown in the following figure: 4452_021 v1.5 252 Peripherals SEQ[0].CNT=2, SEQ[1].CNT=3, SEQ[0].REFRESH=1, SEQ[1].REFRESH=0, SEQ[0].ENDDELAY=1, SEQ[1].ENDDELAY=0, LOOP.CNT=1 SEQ[0].PTR P O COMPARE L PWM clock period Event/Tasks SEQSTART[0] P O COMPARE L (continued below) SEQSTARTED[0] SEQEND[0] SEQ[1].PTR 1 PWM period SEQ[0].ENDDELAY=1 (continuation) P O COMPARE L P O COMPARE L PWM generation maintains last played value Event/Tasks SEQSTARTED[1] SEQEND[1] LOOPSDONE Figure 80: Example using two sequences In this case, an automated playback takes place, consisting of SEQ[0], delay 0, SEQ[1], delay 1, then again SEQ[0], etc. The user can choose to start a complex playback with SEQ[0] or SEQ[1] through sending the SEQSTART[0] or SEQSTART[1] task. The complex playback always ends with delay 1. The two sequences 0 and 1 are defined by the addresses of value tables in RAM (pointed to by SEQ[n].PTR) and the buffer size (SEQ[n].CNT). The rate at which a new value is loaded is defined individually for each sequence by SEQ[n].REFRESH. The chaining of sequence 1 following the sequence 0 is implicit, the LOOP.CNT register allows the chaining of sequence 1 to sequence 0 for a determined number of times. In other words, it allows to repeat a complex sequence a number of times in a fully automated way. In the following code example, sequence 0 is defined with SEQ[0].REFRESH set to 1, meaning that a new PWM duty cycle is pushed every second PWM period. This complex sequence is started with the SEQSTART[0] task, so SEQ[0] is played first. Since SEQ[0].ENDDELAY=1 there will be one PWM period delay between last period on sequence 0 and the first period on sequence 1. Since SEQ[1].ENDDELAY=0 there is no delay 1, so SEQ[0] would be started immediately after the end of SEQ[1]. However, as LOOP.CNT is 4452_021 v1.5 253 Peripherals 1, the playback stops after having played SEQ[1] only once, and both SEQEND[1] and LOOPSDONE are generated (their order is not guaranteed in this case). NRF_PWM0->PSEL.OUT[0] = (first_pin DECODER = (1 SEQ[0].PTR = (PWM_DECODER_LOAD_Common SEQ[0].CNT (PWM_DECODER_MODE_RefreshCount SEQ[1].PTR NRF_PWM0->SEQ[1].CNT = ((uint32_t)(seq1_ram) SEQ[1].ENDDELAY = 0; NRF_PWM0->TASKS_SEQSTART[0] = 1; The decoder can also be configured to asynchronously load new PWM duty cycle. If the DECODER.MODE register is set to NextStep, then the NEXTSTEP task will cause an update of internal compare registers on the next PWM period. The following figures provide an overview of each part of an arbitrary sequence, in various modes (LOOP.CNT=0 and LOOP.CNT>0). In particular, the following are represented: • • • • • Initial and final duty cycle on the PWM output(s) Chaining of SEQ[0] and SEQ[1] if LOOP.CNT>0 Influence of registers on the sequence Events generated during a sequence DMA activity (loading of next value and applying it to the output(s)) 4452_021 v1.5 254 4452_021 v1.5 255 Figure 82: Complex sequence (LOOP.CNT>0) starting with SEQ[0] SEQ[1].ENDDELA Y SEQ[1].CNT SEQ[0].ENDDELA Y SEQ[0].CNT SEQ[1].CNT (LOOP.CNT - 1) ... EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_LOOPSDONE EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] SEQ[0].ENDDELA Y SEQ[0].CNT SEQ[1].ENDDELA Y SEQ[1].CNT LOOP.CNT EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] SEQ[0].ENDDELA Y SEQ[0].CNT Loop counter EVENTS_SEQEND[0] TASKS_SEQSTART[0] EVENTS_SEQSTARTED[0] EVENTS_SEQEND[0] TASKS_SEQSTART[0] EVENTS_SEQSTARTED[0] SEQ[0].ENDDELA Y SEQ[0].CNT Peripherals 100% duty cycle last loaded duty cycle maintained Previously loaded duty cycle New value load 0% duty cycle Figure 81: Single shot (LOOP.CNT=0) Note: The single-shot example also applies to SEQ[1]. Only SEQ[0] is represented for simplicity. 1 100% duty cycle Previously loaded duty cycle last loaded duty cycle maintained New value load 0% duty cycle Peripherals SEQ[1].ENDDELA Y SEQ[1].CNT SEQ[0].ENDDELA Y 1 SEQ[0].CNT SEQ[1].CNT SEQ[0].ENDDELA Y (LOOP.CNT - 1) ... SEQ[0].CNT SEQ[1].CNT SEQ[1].ENDDELA Y LOOP.CNT Loop counter 100% duty cycle Previously loaded duty cycle last loaded duty cycle maintained 0% duty cycle EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_LOOPSDONE EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] TASKS_SEQSTART[1] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] New value load Figure 83: Complex sequence (LOOP.CNT>0) starting with SEQ[1] Note: If a sequence is in use in a simple or complex sequence, it must have a length of SEQ[n].CNT > 0. 6.16.3 Limitations Previous compare value is repeated if the PWM period is shorter than the time it takes for the EasyDMA to retrieve from RAM and update the internal compare registers. This is to ensure a glitch-free operation even for very short PWM periods. 6.16.4 Pin configuration The OUT[n] (n=0..3) signals associated with each PWM channel are mapped to physical pins according to the configuration of PSEL.OUT[n] registers. If PSEL.OUT[n].CONNECT is set to Disconnected, the associated PWM module signal will not be connected to any physical pins. The PSEL.OUT[n] registers and their configurations are used as long as the PWM module is enabled and the PWM generation active (wave counter started). They are retained only as long as the device is in System ON mode (see section POWER for more information about power modes). To ensure correct behavior in the PWM module, the pins that are used must be configured in the GPIO peripheral in the following way before the PWM module is enabled: PWM signal PWM pin Direction Output value Comment OUT[n] As specified in PSEL.OUT[n] Output 0 Idle state defined in GPIO OUT (n=0..3) register Table 69: Recommended GPIO configuration before starting PWM generation 4452_021 v1.5 256 Peripherals The idle state of a pin is defined by the OUT register in the GPIO module, to ensure that the pins used by the PWM module are driven correctly. If PWM generation is stopped by triggering a STOP task, the PWM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected pins (I/Os) for as long as the PWM module is supposed to be connected to an external PWM circuit. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. 6.16.5 Registers Base address Peripheral Instance Description 0x4001C000 PWM PWM0 Pulse width modulation unit 0 Configuration 0x40021000 PWM PWM1 Pulse width modulation unit 1 0x40022000 PWM PWM2 Pulse width modulation unit 2 0x4002D000 PWM PWM3 Pulse width modulation unit 3 Table 70: Instances Register Offset Description TASKS_STOP 0x004 Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback TASKS_SEQSTART[0] 0x008 Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. TASKS_SEQSTART[1] 0x00C Loads the first PWM value on all enabled channels from sequence 1, and starts playing that sequence at the rate defined in SEQ[1]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. TASKS_NEXTSTEP 0x010 Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. EVENTS_STOPPED 0x104 Response to STOP task, emitted when PWM pulses are no longer generated EVENTS_SEQSTARTED[0] 0x108 First PWM period started on sequence 0 EVENTS_SEQSTARTED[1] 0x10C First PWM period started on sequence 1 EVENTS_SEQEND[0] 0x110 Emitted at end of every sequence 0, when last value from RAM has been applied to wave EVENTS_SEQEND[1] 0x114 EVENTS_PWMPERIODEND 0x118 Emitted at the end of each PWM period EVENTS_LOOPSDONE 0x11C Concatenated sequences have been played the amount of times defined in LOOP.CNT SHORTS 0x200 Shortcuts between local events and tasks INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 PWM module enable register MODE 0x504 Selects operating mode of the wave counter COUNTERTOP 0x508 Value up to which the pulse generator counter counts PRESCALER 0x50C Configuration for PWM_CLK DECODER 0x510 Configuration of the decoder LOOP 0x514 Number of playbacks of a loop SEQ[0].PTR 0x520 Beginning address in RAM of this sequence SEQ[0].CNT 0x524 Number of values (duty cycles) in this sequence SEQ[0].REFRESH 0x528 Number of additional PWM periods between samples loaded into compare register SEQ[0].ENDDELAY 0x52C Time added after the sequence SEQ[1].PTR 0x540 Beginning address in RAM of this sequence counter Emitted at end of every sequence 1, when last value from RAM has been applied to wave counter 4452_021 v1.5 257 Peripherals Register Offset Description SEQ[1].CNT 0x544 Number of values (duty cycles) in this sequence SEQ[1].REFRESH 0x548 Number of additional PWM periods between samples loaded into compare register SEQ[1].ENDDELAY 0x54C Time added after the sequence PSEL.OUT[0] 0x560 Output pin select for PWM channel 0 PSEL.OUT[1] 0x564 Output pin select for PWM channel 1 PSEL.OUT[2] 0x568 Output pin select for PWM channel 2 PSEL.OUT[3] 0x56C Output pin select for PWM channel 3 Table 71: Register overview 6.16.5.1 TASKS_STOP Address offset: 0x004 Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback Trigger 1 Trigger task 6.16.5.2 TASKS_SEQSTART[n] (n=0..1) Address offset: 0x008 + (n × 0x4) Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_SEQSTART Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. Trigger 1 Trigger task 6.16.5.3 TASKS_NEXTSTEP Address offset: 0x010 Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 4452_021 v1.5 258 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. Trigger 1 Trigger task 6.16.5.4 EVENTS_STOPPED Address offset: 0x104 Response to STOP task, emitted when PWM pulses are no longer generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Response to STOP task, emitted when PWM pulses are no longer generated NotGenerated 0 Event not generated Generated 1 Event generated 6.16.5.5 EVENTS_SEQSTARTED[n] (n=0..1) Address offset: 0x108 + (n × 0x4) First PWM period started on sequence n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_SEQSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated First PWM period started on sequence n 6.16.5.6 EVENTS_SEQEND[n] (n=0..1) Address offset: 0x110 + (n × 0x4) Emitted at end of every sequence n, when last value from RAM has been applied to wave counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_SEQEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 4452_021 v1.5 NotGenerated 0 Event not generated Generated 1 Event generated 259 Peripherals 6.16.5.7 EVENTS_PWMPERIODEND Address offset: 0x118 Emitted at the end of each PWM period Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW EVENTS_PWMPERIODEND Value ID Value Description Emitted at the end of each PWM period NotGenerated 0 Event not generated Generated 1 Event generated 6.16.5.8 EVENTS_LOOPSDONE Address offset: 0x11C Concatenated sequences have been played the amount of times defined in LOOP.CNT Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_LOOPSDONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Concatenated sequences have been played the amount of times defined in LOOP.CNT NotGenerated 0 Event not generated Generated 1 Event generated 6.16.5.9 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID Access Field A RW SEQEND0_STOP B C D E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event SEQEND[0] and task STOP RW SEQEND1_STOP Shortcut between event SEQEND[1] and task STOP RW LOOPSDONE_SEQSTART0 Shortcut between event LOOPSDONE and task SEQSTART[0] RW LOOPSDONE_SEQSTART1 Shortcut between event LOOPSDONE and task SEQSTART[1] Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW LOOPSDONE_STOP 4452_021 v1.5 Shortcut between event LOOPSDONE and task STOP 260 Peripherals 6.16.5.10 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID Access Field B RW STOPPED C-D E-F G H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event STOPPED RW SEQSTARTED[i] (i=0..1) Enable or disable interrupt for event SEQSTARTED[i] RW SEQEND[i] (i=0..1) Enable or disable interrupt for event SEQEND[i] RW PWMPERIODEND Enable or disable interrupt for event PWMPERIODEND Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW LOOPSDONE Enable or disable interrupt for event LOOPSDONE 6.16.5.11 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID Access Field B RW STOPPED C-D E-F G H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Write '1' to enable interrupt for event STOPPED RW SEQSTARTED[i] (i=0..1) Write '1' to enable interrupt for event SEQSTARTED[i] RW SEQEND[i] (i=0..1) Write '1' to enable interrupt for event SEQEND[i] RW PWMPERIODEND Write '1' to enable interrupt for event PWMPERIODEND RW LOOPSDONE 4452_021 v1.5 Write '1' to enable interrupt for event LOOPSDONE 261 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Read: Enabled 6.16.5.12 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID Access Field B RW STOPPED C-D E-F G H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event STOPPED RW SEQSTARTED[i] (i=0..1) Write '1' to disable interrupt for event SEQSTARTED[i] RW SEQEND[i] (i=0..1) Write '1' to disable interrupt for event SEQEND[i] RW PWMPERIODEND Write '1' to disable interrupt for event PWMPERIODEND RW LOOPSDONE Write '1' to disable interrupt for event LOOPSDONE 6.16.5.13 ENABLE Address offset: 0x500 PWM module enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disabled Enabled 1 Enable Enable or disable PWM module 6.16.5.14 MODE Address offset: 0x504 Selects operating mode of the wave counter 4452_021 v1.5 262 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW UPDOWN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Up 0 Up counter, edge-aligned PWM duty cycle UpAndDown 1 Up and down counter, center-aligned PWM duty cycle Selects up mode or up-and-down mode for the counter 6.16.5.15 COUNTERTOP Address offset: 0x508 Value up to which the pulse generator counter counts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x000003FF ID Access Field A RW COUNTERTOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Value ID Value Description [3..32767] Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 6.16.5.16 PRESCALER Address offset: 0x50C Configuration for PWM_CLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID Access Field A RW PRESCALER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description DIV_1 0 Divide by 1 (16 MHz) DIV_2 1 Divide by 2 (8 MHz) DIV_4 2 Divide by 4 (4 MHz) DIV_8 3 Divide by 8 (2 MHz) DIV_16 4 Divide by 16 (1 MHz) DIV_32 5 Divide by 32 (500 kHz) DIV_64 6 Divide by 64 (250 kHz) DIV_128 7 Divide by 128 (125 kHz) Prescaler of PWM_CLK 6.16.5.17 DECODER Address offset: 0x510 Configuration of the decoder 4452_021 v1.5 263 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID Access Field A RW LOAD A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description How a sequence is read from RAM and spread to the compare register Common 0 1st half word (16-bit) used in all PWM channels 0..3 Grouped 1 1st half word (16-bit) used in channel 0..1; 2nd word in Individual 2 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 WaveForm 3 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in channel 2..3 COUNTERTOP B RW MODE Selects source for advancing the active sequence RefreshCount 0 NextStep 1 SEQ[n].REFRESH is used to determine loading internal compare registers NEXTSTEP task causes a new value to be loaded to internal compare registers 6.16.5.18 LOOP Address offset: 0x514 Number of playbacks of a loop Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled 0 Description Number of playbacks of pattern cycles Looping disabled (stop at the end of the sequence) 6.16.5.19 SEQ[n].PTR (n=0..1) Address offset: 0x520 + (n × 0x20) Beginning address in RAM of this sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Beginning address in RAM of this sequence Note: See the memory chapter for details about which memories are available for EasyDMA. 6.16.5.20 SEQ[n].CNT (n=0..1) Address offset: 0x524 + (n × 0x20) Number of values (duty cycles) in this sequence 4452_021 v1.5 264 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled 0 Description Number of values (duty cycles) in this sequence Sequence is disabled, and shall not be started as it is empty 6.16.5.21 SEQ[n].REFRESH (n=0..1) Address offset: 0x528 + (n × 0x20) Number of additional PWM periods between samples loaded into compare register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000001 ID Access Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) Continuous 0 Update every PWM period 6.16.5.22 SEQ[n].ENDDELAY (n=0..1) Address offset: 0x52C + (n × 0x20) Time added after the sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Time added after the sequence in PWM periods 6.16.5.23 PSEL.OUT[n] (n=0..3) Address offset: 0x560 + (n × 0x4) Output pin select for PWM channel n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID Access Field A B C RW CONNECT B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.17 QDEC — Quadrature decoder The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is suitable for mechanical and optical sensors. 4452_021 v1.5 265 Peripherals The sample period and accumulation are configurable to match application requirements. The QDEC provides the following: • • • • Digital waveform decoding from off-chip quadrature encoder Sample accumulation eliminating hard real-time requirements to be enforced on application Optional input de-bounce filters. Optional LED output signal for optical encoders ACCREAD ACCDBLREAD ACC ACCDBL + + SAMPLE Quadrature decoder IO router On-chip Off-chip Phase A Phase B LED Mechanical to electrical Mechanical device Quadrature Encoder Figure 84: Quadrature decoder configuration 6.17.1 Sampling and decoding The QDEC decodes the output from an incremental motion encoder by sampling the QDEC phase input pins (A and B). The off-chip quadrature encoder is an incremental motion encoder outputting two waveforms, phase A and phase B. The two output waveforms are always 90 degrees out of phase, meaning that one always changes level before the other. The direction of movement is indicated by the waveform that changes level first. Invalid transitions may occur, meaning the two waveforms simultaneously switch. This may occur if the wheel rotates too fast relative to the sample rate set for the decoder. The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B) at a fixed rate as specified in the SAMPLEPER register. If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task. SAMPLEPER can be then changed upon receiving the STOPPED event, and QDEC can be restarted using the START task. Failing to do so may result in unpredictable behavior. 4452_021 v1.5 266 Peripherals It is good practice to only change registers LEDPOL, REPORTPER, DBFEN, and LEDPRE when the QDEC is stopped. When started, the decoder continuously samples the two input waveforms and decodes these by comparing the current sample pair (n) with the previous sample pair (n-1). The decoding of the sample pairs is described in the table below. Previous Current SAMPLE sample pair(n samples register - 1) ACC operation ACCDBL Description operation pair(n) A B A B 0 0 0 0 0 No change No change No movement 0 0 0 1 1 Increment No change Movement in positive direction 0 0 1 0 -1 Decrement No change Movement in negative direction 0 0 1 1 2 No change Increment Error: Double transition 0 1 0 0 -1 Decrement No change Movement in negative direction 0 1 0 1 0 No change No change No movement 0 1 1 0 2 No change Increment Error: Double transition 0 1 1 1 1 Increment No change Movement in positive direction 1 0 0 0 1 Increment No change Movement in positive direction 1 0 0 1 2 No change Increment Error: Double transition 1 0 1 0 0 No change No change No movement 1 0 1 1 -1 Decrement No change Movement in negative direction 1 1 0 0 2 No change Increment Error: Double transition 1 1 0 1 -1 Decrement No change Movement in negative direction 1 1 1 0 1 Increment No change Movement in positive direction 1 1 1 1 0 No change No change No movement Table 72: Sampled value encoding 6.17.2 LED output The LED output follows the sample period. The LED is switched on for a set period before sampling and then switched off immediately after. The period the LED is switched on before sampling is given in the LEDPRE register. The LED output pin polarity is specified in the LEDPOL register. When using off-chip mechanical encoders not requiring an LED, the LED output can be disabled by writing value 'Disconnected' to the CONNECT field of the PSEL.LED register. In this case, the QDEC will not acquire access to a pin for the LED output. 6.17.3 Debounce filters Each of the two-phase inputs have digital debounce filters. When enabled through the DBFEN register, the filter inputs are sampled at a fixed 1 MHz frequency during the entire sample period (which is specified in the SAMPLEPER register). The filters require all of the samples within this sample period to equal before the input signal is accepted and transferred to the output of the filter. As a result, only input signal with a steady state longer than twice the period specified in SAMPLEPER are guaranteed to pass through the filter. Any signal with a steady state shorter than SAMPLEPER will always be suppressed by the filter. It is assumed that the frequency during the debounce period never exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency). The LED will always be ON when the debounce filters are enabled, as the inputs in this case will be sampled continuously. 4452_021 v1.5 267 Peripherals When the debounce filters are enabled, displacements reported by the QDEC peripheral are delayed by one SAMPLEPER period. 6.17.4 Accumulators The quadrature decoder contains two accumulator registers, ACC and ACCDBL. These registers accumulate valid motion sample values and the number of detected invalid samples (double transitions), respectively. The ACC register accumulates all valid values (1/-1) written to the SAMPLE register. This can be useful for preventing hard real-time requirements from being enforced on the application. When using the ACC register, the application can fetch data when necessary instead of reading all SAMPLE register output. The ACC register holds the relative movement of the external mechanical device from the previous clearing of the ACC register. Sample values indicating a double transition (2) will not be accumulated in the ACC register. An ACCOF event is generated if the ACC receives a SAMPLE value that would cause the register to overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be discarded, but any samples that do not cause the ACC to overflow or underflow will still be accepted. The accumulator ACCDBL accumulates the number of detected double transitions since the previous clearing of the ACCDBL register. The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the ACCREAD and ACCDBLREAD registers. The ACC register can be separately cleared by the RDCLRACC and subsequently read using the ACCREAD registers. The ACCDBL register can be separately cleared by the RDCLRDBL and subsequently read using the ACCDBLREAD registers. The REPORTPER register allows automated capture of multiple samples before sending an event. When a non-null displacement is captured and accumulated, a REPORTRDY event is sent. When one or more double-displacements are captured and accumulated, a DBLRDY event is sent. The REPORTPER field in this register determines how many samples must be accumulated before the contents are evaluated and a REPORTRDY or DBLRDY event is sent. Using the RDCLRACC task (manually sent upon receiving the event, or using the DBLRDY_RDCLRACC shortcut), ACCREAD can then be read. When a double transition has been captured and accumulated, a DBLRDY event is sent. Using the RDCLRDBL task (manually sent upon receiving the event, or using the DBLRDY_RDCLRDBL shortcut), ACCDBLREAD can then be read. 6.17.5 Output/input pins The QDEC uses a three-pin interface to the off-chip quadrature encoder. These pins are acquired when the QDEC is enabled in the ENABLE register. The pins acquired by the QDEC cannot be written by the CPU, but they can still be read by the CPU. The pin numbers used for the QDEC are selected using the PSEL.n registers. 6.17.6 Pin configuration The Phase A, Phase B, and LED signals are mapped to physical pins according to the configuration specified in the PSEL.A, PSEL.B, and PSEL.LED registers respectively. If the CONNECT field value 'Disconnected' is specified in any of these registers, the associated signal will not be connected to any physical pin. The PSEL.A, PSEL.B, and PSEL.LED registers and their configurations are only used as long as the QDEC is enabled, and retained only as long as the device is in ON mode. 4452_021 v1.5 268 Peripherals When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 269 before enabling the QDEC. This configuration must be retained in the GPIO for the selected I/Os as long as the QDEC is enabled. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. QDEC signal QDEC pin Direction Output value Phase A As specified in PSEL.A Input Not applicable Phase B As specified in PSEL.B Input Not applicable LED As specified in PSEL.LED Input Not applicable Comment Table 73: GPIO configuration before enabling peripheral 6.17.7 Registers Base address Peripheral Instance Description Configuration 0x40012000 QDEC QDEC Quadrature decoder Table 74: Instances Register Offset Description TASKS_START 0x000 Task starting the quadrature decoder TASKS_STOP 0x004 Task stopping the quadrature decoder TASKS_READCLRACC 0x008 Read and clear ACC and ACCDBL TASKS_RDCLRACC 0x00C Read and clear ACC TASKS_RDCLRDBL 0x010 Read and clear ACCDBL EVENTS_SAMPLERDY 0x100 Event being generated for every new sample value written to the SAMPLE register EVENTS_REPORTRDY 0x104 Non-null report ready EVENTS_ACCOF 0x108 ACC or ACCDBL register overflow EVENTS_DBLRDY 0x10C Double displacement(s) detected EVENTS_STOPPED 0x110 QDEC has been stopped SHORTS 0x200 Shortcuts between local events and tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 Enable the quadrature decoder LEDPOL 0x504 LED output pin polarity SAMPLEPER 0x508 Sample period SAMPLE 0x50C Motion sample value REPORTPER 0x510 Number of samples to be taken before REPORTRDY and DBLRDY events can be generated ACC 0x514 Register accumulating the valid transitions ACCREAD 0x518 Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task PSEL.LED 0x51C Pin select for LED signal PSEL.A 0x520 Pin select for A signal PSEL.B 0x524 Pin select for B signal DBFEN 0x528 Enable input debounce filters LEDPRE 0x540 Time period the LED is switched ON prior to sampling ACCDBL 0x544 Register accumulating the number of detected double transitions 4452_021 v1.5 269 Peripherals Register Offset Description ACCDBLREAD 0x548 Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task Table 75: Register overview 6.17.7.1 TASKS_START Address offset: 0x000 Task starting the quadrature decoder When started, the SAMPLE register will be continuously updated at the rate given in the SAMPLEPER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_START Task starting the quadrature decoder When started, the SAMPLE register will be continuously updated at the rate given in the SAMPLEPER register. Trigger 1 Trigger task 6.17.7.2 TASKS_STOP Address offset: 0x004 Task stopping the quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Task stopping the quadrature decoder Trigger task 6.17.7.3 TASKS_READCLRACC Address offset: 0x008 Read and clear ACC and ACCDBL Task transferring the content of ACC to ACCREAD and the content of ACCDBL to ACCDBLREAD, and then clearing the ACC and ACCDBL registers. These read-and-clear operations will be done atomically. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_READCLRACC Read and clear ACC and ACCDBL Task transferring the content of ACC to ACCREAD and the content of ACCDBL to ACCDBLREAD, and then clearing the ACC and ACCDBL registers. These read-and-clear operations will be done atomically. Trigger 4452_021 v1.5 1 Trigger task 270 Peripherals 6.17.7.4 TASKS_RDCLRACC Address offset: 0x00C Read and clear ACC Task transferring the content of ACC to ACCREAD, and then clearing the ACC register. This read-and-clear operation will be done atomically. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_RDCLRACC Read and clear ACC Task transferring the content of ACC to ACCREAD, and then clearing the ACC register. This read-and-clear operation will be done atomically. Trigger 1 Trigger task 6.17.7.5 TASKS_RDCLRDBL Address offset: 0x010 Read and clear ACCDBL Task transferring the content of ACCDBL to ACCDBLREAD, and then clearing the ACCDBL register. This readand-clear operation will be done atomically. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_RDCLRDBL Read and clear ACCDBL Task transferring the content of ACCDBL to ACCDBLREAD, and then clearing the ACCDBL register. This read-and-clear operation will be done atomically. Trigger 1 Trigger task 6.17.7.6 EVENTS_SAMPLERDY Address offset: 0x100 Event being generated for every new sample value written to the SAMPLE register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_SAMPLERDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event being generated for every new sample value written to the SAMPLE register NotGenerated 0 Event not generated Generated 1 Event generated 6.17.7.7 EVENTS_REPORTRDY Address offset: 0x104 4452_021 v1.5 271 Peripherals Non-null report ready Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing of the ACC register). Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_REPORTRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Non-null report ready Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing of the ACC register). NotGenerated 0 Event not generated Generated 1 Event generated 6.17.7.8 EVENTS_ACCOF Address offset: 0x108 ACC or ACCDBL register overflow Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ACCOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated ACC or ACCDBL register overflow 6.17.7.9 EVENTS_DBLRDY Address offset: 0x10C Double displacement(s) detected Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). 4452_021 v1.5 272 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_DBLRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Double displacement(s) detected Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). NotGenerated 0 Event not generated Generated 1 Event generated 6.17.7.10 EVENTS_STOPPED Address offset: 0x110 QDEC has been stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description QDEC has been stopped NotGenerated 0 Event not generated Generated 1 Event generated 6.17.7.11 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW REPORTRDY_READCLRACC B C D E F Value ID Value Description Shortcut between event REPORTRDY and task READCLRACC Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW SAMPLERDY_STOP Shortcut between event SAMPLERDY and task STOP RW REPORTRDY_RDCLRACC Shortcut between event REPORTRDY and task RDCLRACC RW REPORTRDY_STOP Shortcut between event REPORTRDY and task STOP RW DBLRDY_RDCLRDBL Shortcut between event DBLRDY and task RDCLRDBL Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 RW DBLRDY_STOP 4452_021 v1.5 Shortcut between event DBLRDY and task STOP Disable shortcut 273 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G F E D C B A Reset 0x00000000 ID G Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Enable shortcut RW SAMPLERDY_READCLRACC Shortcut between event SAMPLERDY and task READCLRACC Disabled 0 Disable shortcut Enabled 1 Enable shortcut 6.17.7.12 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID Access Field A RW SAMPLERDY B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event SAMPLERDY Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REPORTRDY Write '1' to enable interrupt for event REPORTRDY Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing of the ACC register). C D Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ACCOF Write '1' to enable interrupt for event ACCOF RW DBLRDY Write '1' to enable interrupt for event DBLRDY Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). E Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STOPPED Write '1' to enable interrupt for event STOPPED 6.17.7.13 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.5 274 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID Access Field A RW SAMPLERDY B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event SAMPLERDY RW REPORTRDY Write '1' to disable interrupt for event REPORTRDY Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing of the ACC register). C D Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ACCOF Write '1' to disable interrupt for event ACCOF Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW DBLRDY Write '1' to disable interrupt for event DBLRDY Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). E Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STOPPED Write '1' to disable interrupt for event STOPPED 6.17.7.14 ENABLE Address offset: 0x500 Enable the quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable the quadrature decoder When enabled the decoder pins will be active. When disabled the quadrature decoder pins are not active and can be used as GPIO . 4452_021 v1.5 Disabled 0 Disable Enabled 1 Enable 275 Peripherals 6.17.7.15 LEDPOL Address offset: 0x504 LED output pin polarity Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW LEDPOL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ActiveLow 0 Led active on output pin low ActiveHigh 1 Led active on output pin high LED output pin polarity 6.17.7.16 SAMPLEPER Address offset: 0x508 Sample period Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A RW SAMPLEPER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Sample period. The SAMPLE register will be updated for every new sample 128us 0 128 µs 256us 1 256 µs 512us 2 512 µs 1024us 3 1024 µs 2048us 4 2048 µs 4096us 5 4096 µs 8192us 6 8192 µs 16384us 7 16384 µs 32ms 8 32768 µs 65ms 9 65536 µs 131ms 10 131072 µs 6.17.7.17 SAMPLE Address offset: 0x50C Motion sample value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R SAMPLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [-1..2] Last motion sample The value is a 2's complement value, and the sign gives the direction of the motion. The value '2' indicates a double transition. 4452_021 v1.5 276 Peripherals 6.17.7.18 REPORTPER Address offset: 0x510 Number of samples to be taken before REPORTRDY and DBLRDY events can be generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A RW REPORTPER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. The report period in [µs] is given as: RPUS = SP * RP Where RPUS is the report period in [µs/report], SP is the sample period in [µs/sample] specified in SAMPLEPER, and RP is the report period in [samples/report] specified in REPORTPER . 10Smpl 0 10 samples/report 40Smpl 1 40 samples/report 80Smpl 2 80 samples/report 120Smpl 3 120 samples/report 160Smpl 4 160 samples/report 200Smpl 5 200 samples/report 240Smpl 6 240 samples/report 280Smpl 7 280 samples/report 1Smpl 8 1 sample/report 6.17.7.19 ACC Address offset: 0x514 Register accumulating the valid transitions Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID ACC Value Description [-1024..1023] Register accumulating all valid samples (not double transition) read from the SAMPLE register. Double transitions ( SAMPLE = 2 ) will not be accumulated in this register. The value is a 32 bit 2's complement value. If a sample that would cause this register to overflow or underflow is received, the sample will be ignored and an overflow event ( ACCOF ) will be generated. The ACC register is cleared by triggering the READCLRACC or the RDCLRACC task. 6.17.7.20 ACCREAD Address offset: 0x518 Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task 4452_021 v1.5 277 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A R Value ID ACCREAD Value Description [-1024..1023] Snapshot of the ACC register. The ACCREAD register is updated when the READCLRACC or RDCLRACC task is triggered. 6.17.7.21 PSEL.LED Address offset: 0x51C Pin select for LED signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.17.7.22 PSEL.A Address offset: 0x520 Pin select for A signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID Access Field A B C RW CONNECT B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.17.7.23 PSEL.B Address offset: 0x524 Pin select for B signal 4452_021 v1.5 278 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.17.7.24 DBFEN Address offset: 0x528 Enable input debounce filters Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW DBFEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Debounce input filters disabled Enabled 1 Debounce input filters enabled Enable input debounce filters 6.17.7.25 LEDPRE Address offset: 0x540 Time period the LED is switched ON prior to sampling Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A Reset 0x00000010 ID Access Field A RW LEDPRE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Value ID Value Description [1..511] Period in µs the LED is switched on prior to sampling 6.17.7.26 ACCDBL Address offset: 0x544 Register accumulating the number of detected double transitions Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A R ACCDBL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..15] Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). When this register has reached its maximum value, the accumulation of double/illegal transitions will stop. An overflow event (ACCOF) will be generated if any double or illegal transitions are detected after the maximum value was reached. This field is cleared by triggering the READCLRACC or RDCLRDBL task. 4452_021 v1.5 279 Peripherals 6.17.7.27 ACCDBLREAD Address offset: 0x548 Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID ACCDBLREAD Value Description [0..15] Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. 6.17.8 Electrical specification 6.17.8.1 QDEC Electrical Specification Symbol Description Min. tSAMPLE Time between sampling signals from quadrature decoder tLED Time from LED is turned on to signals are sampled Typ. Max. Units 128 131072 µs 0 511 µs 6.18 RADIO — 2.4 GHz radio The 2.4 GHz radio transceiver is compatible with multiple radio standards such as 1 Mbps and 2 Mbps Bluetooth® Low Energy modes, Long Range (125 kbps and 500 kbps) Bluetooth® Low Energy modes, IEEE 802.15.4 250 kbps mode, as well as Nordic's proprietary 1 Mbps and 2 Mbps modes. Listed here are main features for the RADIO: • Multidomain 2.4 GHz radio transceiver • 1 Mbps and 2 Mbps Bluetooth® Low Energy modes • Long Range (125 kbps and 500 kbps) Bluetooth® Low Energy modes • Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using Bluetooth® Low Energy • IEEE 802.15.4 250 kbps mode • 1 Mbps and 2 Mbps Nordic proprietary modes • Best in class link budget and low power operation • Efficient data interface with EasyDMA support • Automatic address filtering and pattern matching EasyDMA, in combination with an automated packet assembler, packet disassembler, automated CRC generator and CRC checker, makes it easy to configure and use the RADIO. See the following figure for details. 4452_021 v1.5 280 Peripherals RAM RADIO PACKETPTR Packet synch Device address match RSSI Address match S0 CRC Packet disassembler L Dewhitening 2.4 GHz receiver S1 EasyDMA Payload IFS control unit Bit counter S0 ANT1 L Packet assembler S1 Payload CRC Whitening 2.4 GHz transmitter MAXLEN Figure 85: RADIO block diagram The RADIO includes a device address match unit and an interframe spacing control unit that can be utilized to simplify address whitelisting and interframe spacing respectively in Bluetooth® low energy and similar applications. The RADIO also includes a received signal strength indicator (RSSI) and a bit counter. The bit counter generates events when a preconfigured number of bits are sent or received by the RADIO. 6.18.1 Packet configuration A RADIO packet contains the fields PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD, and CRC. For Long Range (125 kbps and 500 kbps) Bluetooth® Low Energy modes, fields CI, TERM1, and TERM2 are also included. The content of a RADIO packet is illustrated in the figures below. The RADIO sends the fields in the packet according to the order illustrated in the figures, starting on the left. BASE PREFIX S0 LENGTH S1 MSBit PREAMBLE LSBit LSBit LSBit 0x55 1 0 1 0 1 0 1 0 1 0xAA 0 1 0 1 0 1 0 1 0 PAYLOAD LSByte LSByte CRC MSByte ADDRESS PREFIX CI TERM1 S0 LENGTH S1 PAYLOAD LSByte CRC LSBit BASE LSByte MSBit PREAMBLE LSBit LSBit LSBit Figure 86: On-air packet layout TERM 2 MSByte ADDRESS Figure 87: On-air packet layout for Long Range (125 kbps and 500 kbps) Bluetooth® Low Energy modes Not shown in the figures is the static payload add-on (the length of which is defined in PCNF1.STATLEN, and which is 0 bytes in a standard BLE packet). The static payload add-on is sent between PAYLOAD and CRC fields. The RADIO sends the different fields in the packet in the order they are illustrated above, from left to right. PREAMBLE is sent with least significant bit first on air. The size of the PREAMBLE depends on the mode selected in the MODE register: • The PREAMBLE is one byte for MODE = Ble_1Mbit as well as all Nordic proprietary operating modes (MODE = Nrf_1Mbit and MODE = Nrf_2Mbit), and PCNF0.PLEN has to be set accordingly. If the first bit of the ADDRESS is 0, the preamble will be set to 0xAA. Otherwise the PREAMBLE will be set to 0x55. 4452_021 v1.5 281 Peripherals • For MODE = Ble_2Mbit, the PREAMBLE must be set to 2 bytes through PCNF0.PLEN. If the first bit of the ADDRESS is 0, the preamble will be set to 0xAAAA. Otherwise the PREAMBLE will be set to 0x5555. • For MODE = Ble_LR125Kbit and MODE = Ble_LR500Kbit, the PREAMBLE is 10 repetitions of 0x3C. • For MODE = Ieee802154_250Kbit, the PREAMBLE is 4 bytes and set to all zeros. Radio packets are stored in memory inside instances of a RADIO packet data structure as illustrated below. The PREAMBLE, ADDRESS, CI, TERM1, TERM2, and CRC fields are omitted in this data structure. Fields S0, LENGTH, and S1 are optional. S0 LENGTH 0 S1 PAYLOAD LSByte n Figure 88: Representation of a RADIO packet in RAM The byte ordering on air is always least significant byte first for the ADDRESS and PAYLOAD fields, and most significant byte first for the CRC field. The ADDRESS fields are always transmitted and received least significant bit first. The CRC field is always transmitted and received most significant bit first. The endianness, i.e. the order in which the bits are sent and received, of the S0, LENGTH, S1, and PAYLOAD fields can be configured via PCNF1.ENDIAN. The sizes of the S0, LENGTH, and S1 fields can be individually configured via S0LEN, LFLEN, and S1LEN in PCNF0 respectively. If any of these fields are configured to be less than 8 bits, the least significant bits of the fields are used. If S0, LENGTH, or S1 are specified with zero length, their fields will be omitted in memory. Otherwise each field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart. Independent of the configuration of PCNF1.MAXLEN, the combined length of S0, LENGTH, S1, and PAYLOAD cannot exceed 258 bytes. 6.18.2 Address configuration The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix field. The size of the base address field is configurable via PCNF1.BALEN. The base address is truncated from the least significant byte if the PCNF1.BALEN is less than 4. See Definition of logical addresses on page 282. The on-air addresses are defined in the BASE0/BASE1 and PREFIX0/PREFIX1 registers. It is only when writing these registers that the user must relate to the actual on-air addresses. For other radio address registers, such as the TXADDRESS, RXADDRESSES, and RXMATCH registers, logical radio addresses ranging from 0 to 7 are being used. The relationship between the on-air radio addresses and the logical addresses is described in the following table. Logical address Base address Prefix byte 0 BASE0 PREFIX0.AP0 1 BASE1 PREFIX0.AP1 2 BASE1 PREFIX0.AP2 3 BASE1 PREFIX0.AP3 4 BASE1 PREFIX1.AP4 5 BASE1 PREFIX1.AP5 6 BASE1 PREFIX1.AP6 7 BASE1 PREFIX1.AP7 Table 76: Definition of logical addresses 4452_021 v1.5 282 Peripherals 6.18.3 Data whitening The RADIO is able to do packet whitening and de-whitening, enabled in PCNF1.WHITEEN. When enabled, whitening and de-whitening will be handled by the RADIO automatically as packets are sent and received. The whitening word is generated using polynomial g(D) = D7+ D4 + 1, which then is XORed with the data packet that is to be whitened, or de-whitened. The linear feedback shift register is initialized via DATAWHITEIV. See the following figure. D0 D4 D7 + Position 0 1 2 Data out + 3 4 5 6 Data in Figure 89: Data whitening and de-whitening Whitening and de-whitening will be performed over the whole packet except for the preamble and the address fields. 6.18.4 CRC The CRC generator in RADIO calculates the CRC over the whole packet excluding the preamble. If desirable, the address field can be excluded from the CRC calculation as well. See CRCCNF register for more information. The CRC polynomial is configurable as illustrated in the following figure, where bit 0 in the CRCPOLY register corresponds to X0 and bit 1 corresponds to X1 etc. See CRCPOLY on page 328 for more information. Xn-1 Xn X2 X1 X0 Packet (Clocked in serially) + + + bn + + b0 Figure 90: CRC generation of an n bit CRC The figure shows that the CRC is calculated by feeding the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the CRC generator's latches b0 through bn will be initialized with a predefined value specified in the CRCINIT register. After the whole packet has been clocked through the CRC generator, b0 through bn will hold the resulting CRC. This value will be used by the RADIO during both transmission and reception. Latches b0 through bn are not available to be read by the CPU at any time. However, a received CRC can be read by the CPU via the RXCRC register. The length (n) of the CRC is configurable, see CRCCNF for more information. Once the entire packet, including the CRC, has been received and no errors were detected, RADIO generates a CRCOK event. If CRC errors were detected, a CRCERROR event is generated. The status of the CRC check can be read from the CRCSTATUS register after a packet has been received. 4452_021 v1.5 283 Peripherals 6.18.5 Radio states Tasks and events are used to control the operating state of RADIO. RADIO can enter the states described in the following table. State Description DISABLED No operations are going on inside the RADIO and the power consumption is at a minimum RXRU RADIO is ramping up and preparing for reception RXIDLE RADIO is ready for reception to start RX Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored TXRU RADIO is ramping up and preparing for transmission TXIDLE RADIO is ready for transmission to start TX RADIO is transmitting a packet RXDISABLE RADIO is disabling the receiver TXDISABLE RADIO is disabling the transmitter Table 77: RADIO state diagram A state diagram showing an overview of RADIO is shown in the following figure. DISABLE Address sent / ADDRESS START TXDISABLE TXRU / DISABLED Ramp-up complete / READY TXEN TXEN TX STOP Packet sent / END Payload sent [payload length >=0] / PAYLOAD Last bit sent / PHYEND DISABLED Last bit received / PHYEND RXEN / DISABLED RXDISABLE TXIDLE RXRU Ramp-up complete / READY Packet received / END START RXIDLE RX STOP DISABLE Address received [Address match] / ADDRESS Payload received [payload length >=0] / PAYLOAD Figure 91: Radio states This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state. If a task is triggered from the wrong state, for example if the RXEN task is triggered from the RXDISABLE state, this may lead to incorrect behavior. The PAYLOAD event is always generated even if the payload is zero. The END to START shortcut should not be used with IEEE 802.15.4 250 kbps mode. Use the PHYEND to START shortcut instead. The END to START shortcut should not be used with Long Range (125 kbps and 500 kbps) Bluetooth® Low Energy modes. Use the PHYEND to START shortcut instead. 6.18.6 Transmit sequence Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode. See TXRU in Radio states on page 284 and Transmit sequence on page 285. A TXRU ramp-up sequence is initiated when the TXEN task is triggered. After the RADIO has successfully ramped up it will generate the READY event 4452_021 v1.5 284 Peripherals indicating that a packet transmission can be initiated. A packet transmission is initiated by triggering the START task. The START task can first be triggered after the RADIO has entered into the TXIDLE state. TX CRC TXDISABLE (carrier) DISABLED PAYLOAD ADDRESS S0 L S1 2 DISABLE 3 START 1 TXEN Lifeline READY A END P (carrier) TXIDLE PHYEND TXIDLE Transmitter TXRU PAYLOAD State The following figure illustrates a single packet transmission where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. As illustrated in Transmit sequence on page 285 the RADIO will by default transmit 1s between READY and START, and between END and DISABLED. What is transmitted can be programmed through the DTX field in the MODECNF0 register. Figure 92: Transmit sequence PAYLOAD CRC (carrier) PHYEND S0 L S1 END A 1 DISABLE 2 START TXEN Lifeline READY P TXDISABLE DISABLED TX ADDRESS Transmitter TXRU PAYLOAD State The following figure shows a slightly modified version of the transmit sequence where RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced. Figure 93: Transmit sequence using shortcuts to avoid delays RADIO is able to send multiple packets one after the other without having to disable and re-enable the RADIO between packets, as illustrated in the following figure. 4452_021 v1.5 285 A S0 L S1 PAYLOAD CRC (carrier) DISABLE 3 START START 2 DISABLED P END (carrier) END PAYLOAD CRC PHYEND PAYLOAD TXDISABLE TX ADDRESS S0 L S1 ADDRESS A 1 TXEN Lifeline READY P TXIDLE PAYLOAD TX Transmitter TXRU PHYEND State Peripherals Figure 94: Transmission of multiple packets 6.18.7 Receive sequence Before RADIO is able to receive a packet, it must first ramp up in RX mode. See RXRU in Radio states on page 284 and Receive sequence on page 286 for more information. An RXRU ramp up sequence is initiated when the RXEN task is triggered. After RADIO has successfully ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet reception is initiated by triggering the START task. As illustrated in Radio states on page 284, the START task can first be triggered after RADIO has entered into the RXIDLE state. RX PAYLOAD 2 CRC DISABLED S0 L S1 RXDISABLE END A ADDRESS P DISABLE 3 START 1 RXEN Lifeline READY ’X’ RXIDLE PHYEND RXIDLE Reception RXRU PAYLOAD State The following figure shows a single packet reception where the CPU manually triggers the different tasks needed to control the flow of RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. RADIO will be listening and possibly receiving undefined data, represented with an 'X', from START and until a packet with valid preamble (P) is received. Figure 95: Receive sequence The following figure shows a modified version of the receive sequence, where RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced. 4452_021 v1.5 286 RX Lifeline PAYLOAD CRC ADDRESS S0 L S1 DISABLED A END P READY ’X’ RXDISABLE PAYLOAD Reception RXRU PHYEND State Peripherals 1 DISABLE RXEN START 2 Figure 96: Receive sequence using shortcuts to avoid delays S0 L S1 PAYLOAD CRC 3 DISABLE START START 2 DISABLED A END ’X’ P PHYEND CRC ADDRESS PAYLOAD RXDISABLE RX END S0 L S1 PHYEND A 1 RXEN Lifeline READY ’X’ P RXIDLE PAYLOAD RX ADDRESS Receiver RXRU PAYLOAD State RADIO is able to receive consecutive packets without having to disable and re-enable RADIO between packets, as illustrated in the following figure. Figure 97: Reception of multiple packets 6.18.8 Received signal strength indicator (RSSI) RADIO implements a mechanism for measuring the power in the received signal. This feature is called received signal strength indicator (RSSI). The RSSI is measured continuously and the value filtered using a single-pole IIR filter. After a signal level change, the RSSI will settle after approximately RSSISETTLE. Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read from the RSSISAMPLE register. The sample period of the RSSI is defined by RSSIPERIOD. The RSSISAMPLE will hold the filtered received signal strength after this sample period. For the RSSI sample to be valid, the RADIO has to be enabled in receive mode (RXEN task) and the reception has to be started (READY event followed by START task). 6.18.9 Interframe spacing (IFS) Interframe spacing (IFS) is defined as the time, in microseconds, between two consecutive packets, starting from when the end of the last bit of the previous packet is received, to the beginning of the first bit of the subsequent packet that is transmitted. The RADIO is able to enforce this interval, as specified in the TIFS register, as long as the TIFS is not specified to be shorter than the RADIO's turnaround time, i.e. 4452_021 v1.5 287 Peripherals the time needed to switch off the receiver, and then switch the transmitter back on. The TIFS register can be written any time before the last bit on air is received. This timing is illustrated in the figure below. Change to MODE OK TXRU TX P READY DISABLED CRC END A S0 L S1 PAYLOAD START DISABLE TIFS TXEN PAYLOAD RXDISABLE ADDRESS RX PAYLOAD Lifeline On air State Change to SHORTS and TIFS OK Figure 98: IFS timing detail The TIFS duration starts after the last bit on air (just before the END event), and elapses with first bit being transmitted on air (just after READY event). TIFS is only enforced if the shortcuts END to DISABLE and DISABLED to TXEN or END to DISABLE and DISABLED to RXEN are enabled. TIFS is qualified for use in IEEE 802.15.4 250kbps mode, Long Range (125 kbps and 500 kbps) Bluetooth® Low Energy modes, and 1 Mbps and 2 Mbps Bluetooth® Low Energy modes, using the default ramp-up mode. SHORTS and TIFS registers are not double-buffered, and can be updated at any point before the last bit on air is received. The MODE register is double-buffered and sampled at the TXEN or RXEN task. 6.18.10 Device address match The device address match feature is tailored for address whitelisting in Bluetooth® low energy and similar implementations. This feature enables on-the-fly device address matching while receiving a packet on air. This feature only works in receive mode and when the RADIO is configured for little endian, see PCNF1.ENDIAN. The device address match unit assumes that the first 48 bits of the payload are the device address and that bit number 6 in S0 is the TxAdd bit. See the Bluetooth® Core Specification for more information about device addresses, TxAdd, and whitelisting. The RADIO is able to listen for eight different device addresses at the same time. These addresses are specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP register specifies the 16 most significant bits of the device address. Each of the device addresses can be individually included or excluded from the matching mechanism. This is configured in the DACNF register. 4452_021 v1.5 288 Peripherals 6.18.11 Bit counter The RADIO implements a simple counter that can be configured to generate an event after a specific number of bits have been transmitted or received. By using shortcuts, this counter can be started from different events generated by the RADIO and count relative to these. The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the BCSTOP task is triggered. After a BCMATCH event, the CPU can reconfigure the BCC value for new BCMATCH events within the same packet. The bit counter can only be started after the RADIO has received the ADDRESS event. The bit counter will stop and reset on either the BCSTOP, STOP, or DISABLE task, or the END event. RX BCSTART END DISABLED CRC PAYLOAD BCMATCH BCMATCH READY START 2 PAYLOAD 2 BCC = 12 1 RXEN 1 S0 L S1 BCC = 12 + 16 Lifeline Assuming that the combined length of S0, length (L) and S1 is 12 bits. A ADDRESS Reception 0 ’X’ P RXDISABLE 3 DISABLE RXRU BCSTOP State The following figure shows how the bit counter can be used to generate a BCMATCH event in the beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the payload. Figure 99: Bit counter example 6.18.12 Direction finding The RADIO implements the Angle-of-Arrival (AoA) and Angle-of-Departure (AoD) Bluetooth Low Energy feature, which can be used to determine the direction of a peer device. The feature is available for the BLE 1 Mbps and BLE 2 Mbps modes. When using this feature, the transmitter sends a packet with a continuous tone extension (CTE) appended to the packet, after the CRC. During the CTE, the receiver can take IQ samples of the incoming signal. An antenna array is employed at the transmitter (AoD) or at the receiver (AoA). The AoD transmitter, or AoA receiver, switches between the antennas, in order to collect IQ samples from the different antenna pairs. The IQ samples can be used to calculate the relative path lengths between the antenna pairs, which can be used to estimate the direction of the transmitter. 6.18.12.1 CTE format The CTE is from 16 µs to 160 µs and consists of an unwhitened sequence of 1's, equivalent to a continuous tone nominally offset from the carrier by +250 kHz for the 1 Mbps PHY and +500 kHz for the 2 Mbps BLE PHYs. The format of the CTE, when switching and/or sampling, is shown in the following figure. 4452_021 v1.5 289 Peripherals GUARD PERIOD REFERENCE PERIOD SWITCH SLOT SAMPLE SLOT 4 µs 8 µs 1 or 2 µs 1 or 2 µs SWITCH SLOT SAMPLE SLOT SWITCH SLOT ... SAMPLE SLOT 16-160 µs Figure 100: Constant tone extension (CTE) structure Antenna switching is performed during switch slots and the guard period. The AoA/AoD feature requires that one IQ sample is taken for each microsecond within the reference period, and once for each sample slot. Oversampling is possible by changing the sample spacing as described in IQ sampling on page 293. The switch slot and sample slot durations are either 1 or 2 µs, but must be equal. The format of the CTE and switching and sampling procedures may be configured prior to, or during, packet transmission and reception. Alternatively, during packet reception, these operations can be configured by reading specific fields of the packet contents. 6.18.12.2 Mode Depending on the DFEMODE, the device performs the procedures shown in the following table. DFEMODE AOA TX Generating and transmitting CTE AoA/AoD Procedure AOD RX x TX RX x Receiving, interpreting, and sampling CTE x Antenna switching x x x Table 78: AoA/AoD Procedures performed as a function of DFEMODE and TX/RX mode 6.18.12.3 Inline configuration When inline configuration is enabled during RX, further configuration of the AoA/AoD procedures is performed based on the values of the CP bit and the CTEInfo octet within the packet. This is enabled by setting CTEINLINECONF.CTEINLINECTRLEN. The CTEInfo octet is present only if the CP bit is set. The position of the CP bit and CTEInfo octet depends on whether the packet has a Data Channel PDU (CTEINLINECONF.CTEINFOINS1=InS1), or an Advertising Channel PDU (CTEINLINECONF.CTEINFOINS1=NotInS1). Data channel PDU For Data Channel PDUs, PCNF0.S0LEN must be 1 byte, and PCNF0.LFLEN must be 8 bits. To determine if S1 is present, the registers CTEINLINECONF.S0MASK and CTEINLINECONF.S0CONF forms a bitwise mask-andtest for the S0 field. If the bitwise AND between S0 and S0MASK equals S0CONF, then S1 is determined to be present. When present, the value of PCNF0.S1LEN will be ignored, as this is decided by the CP bit in the the following figure. S0 LENGTH S1 ... CP ... Length CTEInfo 5 bits 1 bit 2 bits 8 bits 0 or 8 bits Figure 101: Data channel PDU header When encrypting and decrypting BLE packets using the CCM peripheral, it is also required to set PCNF0.S1INCL=1. The CCM mode must be configured to use an 8-bit length field. The value of the CP bit is included in the calculation of the MIC, while the S1 field is ignored by the CCM calculation. 4452_021 v1.5 290 Peripherals Advertising channel PDU For advertising channel PDUs, the CTEInfo Flag replaces the CP bit. The CTEInfo Flag is within the extended header flag field in some of the advertising PDUs that employ the common extended advertising payload format (i.e. AUX_SYNC_IND, AUX_CHAIN_IND). The format of such packets is shown in the following figure. S0 LENGTH PAYLOAD PDU Type ... Length Extended Header Length AdvMode ... CTEInfo flag ... AdvA TargetA CTEInfo ... 4 bits 4 bits 8 bits 6 bits 2 bits 2 bits 1 bit 5 bits 6 octets 6 octets 8 bits ... CRC CTE Extended Header Flags Figure 102: Advertising channel PDU header The CTEINLINECONF.S0CONF and CTEINLINECONF.S0MASK fields can be configured to accept only certain advertising PDU Types. If the extended header length is non-zero, the CTEInfo extended header flag is checked to determine whether CTEInfo is present. If a bit before the CTEInfo flag within the extended header flags is set, then the CTEInfo position is postponed 6 octets. CTEInfo parsing The CTEInfo field is shown in the following figure. CTETime RFU CTEType 5 bits 1 bit 2 bits Figure 103: CTEInfo field The CTETIME field defines the length of the CTE in 8 µs units. The valid upper bound of values can be adjusted using CTEINLINECONF.CTETIMEVALIDRANGE, including allowing use of the RFU bit within this field. If the CTETIME field is an invalid value of either 0 or 1, the CTE is assumed to be the minimum valid length of 16 µs. The slot duration is determined by the CTEType field. In RX this determines whether the sample spacing as defined in CTEINLINECONF.CTEINLINERXMODE1US or CTEINLINECONF.CTEINLINERXMODE2US is used. CTEType Description TX switch spacing RX sample spacing during Sample spacing RX during reference period reference period - TSAMPLESPACING1 TSAMPLESPACING2 0 AoA, no switching 1 AoD, 1 µs slots 2 µs TSAMPLESPACING1 CTEINLINERXMODE1US 2 AoD, 2 µs slots 4 µs TSAMPLESPACING1 CTEINLINERXMODE2US 3 Reserved for future use Table 79: Switching and sampling spacing based on CTEType 6.18.12.4 Manual configuration If CTEINLINECONF.CTEINLINECTRLEN is not set, then the packet is not parsed to determine the CTE parameters, and the antenna switching and sampling is controlled by other registers, see Antenna switching on page 292. The length of the CTE is given in 8 µs units by DFECTRL1.NUMBEROF8US. The start of the antenna switching and/or sampling (denoted as an AoA/AoD procedure), can be configured to start at some trigger with an additional offset. Using DFECTRL1.DFEINEXTENSION, the trigger can be configured to be the end of the CRC, or alternatively, the ADDRESS event. The additional offset for antenna switching is configured using DFECTRL2.TSWITCHOFFSET. Similarly, the additional offset for antenna sampling is configured using DFECTRL2.TSAMPLEOFFSET. 4452_021 v1.5 291 Peripherals 6.18.12.5 Receive- and transmit sequences PAYLOAD ADDRESS CTE (carrier) 2 3 TXEN START 1 CRC DISABLE Lifeline S0 L S1 TXDISABLE DISABLED A TXIDLE END P READY (carrier) TX PHYEND TXIDLE Transmitter TXRU PAYLOAD State The addition of the CTE to the transmitted packet is illustrated in the following figure. Figure 104: Transmit sequence with DFE RX CRC 2 CTE DISABLED PAYLOAD RXDISABLE PHYEND S0 L S1 PAYLOAD A ADDRESS P DISABLE 3 START 1 RXEN Lifeline READY ’X’ RXIDLE END RXIDLE Reception RXRU CTEPRESENT State The prescence of CTE within a received packet is signalled by the CTEPRESENT event illustrated in the figure below. Figure 105: Receive sequence with DFE 6.18.12.6 Antenna switching The RADIO can control up to 8 GPIO pins in order to control external antenna switches used in direction finding. Pin configuration The eight antenna selection signals are mapped to physical pins according to the pin numbers specified in the PSEL.DFEGPIO[n] registers. Only pins that have the PSEL.DFEGPIO[n].CONNECTED field set to Connected will be controlled by the RADIO. Pins that are Disconnected will be controlled by GPIO. During transmission in AoD TX mode or reception in AoA RX mode, the RADIO automatically acquires the pins as needed. At times when the RADIO does not use the pin, the pin is released to its default state and controlled by the GPIO configuration. Thus, the pin must be configured using the GPIO peripheral. 4452_021 v1.5 292 Peripherals Pin acquired by RADIO Direction Yes Output No Specified by GPIO Value Comment Specified in SWITCHPATTERN Pin acquired by RADIO, and in use for DFE. Specified by GPIO DFE not in progress. Pin has not been acquired by RADIO, but is available for DFE use. Table 80: Pin configuration matrix for a connected and enabled pin [n] Switch pattern configuration The values of the GPIOs while switching during the CTE are configured by writing successively to the SWITCHPATTERN register. The first write to SWITCHPATTERN is the GPIO pattern applied from the call of TASKS_TXEN or TASKS_RXEN until the first antenna switch is triggered. The second write sets the pattern for the reference period and is applied at the start of the guard period. The following writes set the pattern for the remaining switch slots and are applied at the start of each switch slot. If writing beyond the total number of antenna slots, the pattern will wrap to SWITCHPATTERN[2] and start over again. During operation, when the end of the SWITCHPATTERN buffer is reached, the RADIO cycles back to SWITCHPATTERN[2]. At the end of the AoA/AoD procedure, SWITCHPATTERN[0] is applied to DFECTRL1.TSWITCHSPACING after the previous antenna switch. The SWITCHPATTERN buffer can be erased/cleared using CLEARPATTERN. A minimum number of three patterns must be written to the SWITCHPATTERN register. If CTEINLINECONF.CTEINLINECTRLEN is not set, then the antenna switch spacing is determined by DFECTRL1.TSWITCHSPACING (otherwise described by Switching and sampling spacing based on CTEType on page 291). DFECTRL2.TSWITCHOFFSET determines the position of the first switch compared to the configurable start of CTE (see DFECTRL1.DFEINEXTENSION). 6.18.12.7 IQ sampling The RADIO uses DMA to write IQ samples recorded during the CTE to RAM. Alternatively, the magnitude and phase of the samples can be recorded using the DFECTRL1.SAMPLETYPE field. The samples are written to the location in RAM specified by DFEPACKET.PTR. The maximum number of samples to transfer are specified by DFEPACKET.MAXCNT and the number of samples transferred are given in DFEPACKET.AMOUNT. The IQ samples are recorded with respect to the RX carrier frequency. The format of the samples is provided in the following table. SAMPLETYPE Field Bits Description 0: I_Q (default) Q 31:16 12 bits signed, sign extended to 16 bits. Out of range samples are saturated at value -32768. I 15:0 reserved 31:29 Always zero magnitude 28:16 13 bits unsigned. Equals 1.646756*sqrt(I^2+Q^2). phase 15:0 9 bits signed, sign extended to 16 bits. Equals 64*atan2(Q, I) in the range [-201,201]. 1: MagPhase Table 81: Format of samples Oversampling is configured separately for the reference period and for the time after the reference period. During the reference period, the sample spacing is determined by DFECTRL1.TSAMPLESPACINGREF. DFECTRL2.TSAMPLEOFFSET determines the position of the first sample relative to the end of the last bit of the CRC. For the time after the reference period, if CTEINLINECONF.CTEINLINECTRLEN is disabled, the sample spacing is set in DFECTRL1.TSAMPLESPACING. However, when CTEINLINECONF.CTEINLINECTRLEN is enabled, the sample spacing is determined by two different registers, depending on whether the device is in AoA or AoD RX-mode. For AoD RX mode, the sample spacing after the reference period is determined by the CTEType in the packet, as listed in the following table. 4452_021 v1.5 293 Peripherals CTEType Sample spacing AoD 1 µs slots CTEINLINECONF.CTEINLINERXMODE1US AoD 2 µs slots CTEINLINECONF.CTEINLINERXMODE2US Other DFECTRL1.TSAMPLESPACING Table 82: Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoD RX mode For AoA RX mode, the sample spacing after the reference period is determined by DFECTRL1.TSWITCHSPACING, as listed in the following table. DFECTRL1.TSWITCHSPACING Sample spacing 2 µs CTEINLINECONF.CTEINLINERXMODE1US 4 µs CTEINLINECONF.CTEINLINERXMODE2US Other DFECTRL1.TSAMPLESPACING Table 83: Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoA RX mode For the reference and switching periods, DFECTRL1.TSAMPLESPACINGREF and DFECTRL1.TSAMPLESPACING can be used to achieve oversampling. 6.18.13 IEEE 802.15.4 operation With the MODE=Ieee802154_250kbit the RADIO will comply with the IEEE 802.15.4-2006 standard implementing its 250 kbps, 2450 MHz, O-QPSK PHY. The IEEE 802.15.4 standard differs from Nordic's proprietary and Bluetooth® low energy modes. Notable differences include modulation scheme, channel structure, packet structure, security, and medium access control. The main features of the IEEE 802.15.4 mode are: • • • • Ultra-low power 250 kbps, 2450 MHz, IEEE 802.15.4-2006 compliant link Clear channel assessment Energy detection scan CRC generation 6.18.13.1 Packet structure The IEEE 802.15.4 standard defines an on-the-air frame/packet that is different from what is used in BLE mode. The following figure provides an overview of the physical frame structure and its timing. 160 µs Preamble sequence 32 µs PHY protocol data unit (PPDU) SFD Length 5 octets synchronization header (SHR) 1 octet (PHR) 0 Include 1 Always include S1 field in RAM independent of S1LEN Length of code indicator - long range Length of preamble on air. Decision point: TASKS_START task 8bit 0 8-bit preamble 16bit 1 16-bit preamble 32bitZero 2 32-bit zero preamble - used for IEEE 802.15.4 LongRange 3 Preamble - used for BLE long range Exclude 0 LENGTH does not contain CRC Include 1 LENGTH includes CRC RW CRCINC Indicates if LENGTH field contains CRC or not RW TERMLEN Length of TERM field in Long Range operation 6.18.15.53 PCNF1 Address offset: 0x518 Packet configuration register 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D Reset 0x00000000 ID Access Field A RW MAXLEN C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..255] Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. B RW STATLEN [0..255] Static length in number of bytes The static length parameter is added to the total length of the payload when sending and receiving packets, e.g. if the static length is set to N the radio will receive or send N bytes more than what is defined in the LENGTH field of the packet. C RW BALEN [2..4] Base address length in number of bytes The address field is composed of the base address and the one byte long address prefix, e.g. set BALEN=2 to get a total address of 3 bytes. D RW ENDIAN On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. E Little 0 Least significant bit on air first Big 1 Most significant bit on air first Disabled 0 Disable Enabled 1 Enable RW WHITEEN 4452_021 v1.5 Enable or disable packet whitening 326 Peripherals 6.18.15.54 BASE0 Address offset: 0x51C Base address 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW BASE0 Value ID Value Description Base address 0 6.18.15.55 BASE1 Address offset: 0x520 Base address 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW BASE1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Base address 1 6.18.15.56 PREFIX0 Address offset: 0x524 Prefixes bytes for logical addresses 0-3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A-D RW AP[i] (i=0..3) Value ID Value Description Address prefix i. 6.18.15.57 PREFIX1 Address offset: 0x528 Prefixes bytes for logical addresses 4-7 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A Reset 0x00000000 ID Access Field A-D RW AP[i] (i=4..7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Address prefix i. 6.18.15.58 TXADDRESS Address offset: 0x52C Transmit address select 4452_021 v1.5 327 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID Access Field A RW TXADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Transmit address select Logical address to be used when transmitting a packet 6.18.15.59 RXADDRESSES Address offset: 0x530 Receive address select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 ID Access Field A-H RW ADDR[i] (i=0..7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable reception on logical address i. 6.18.15.60 CRCCNF Address offset: 0x534 CRC configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B Reset 0x00000000 ID Access Field A RW LEN Value ID Value Description [1..3] CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported B Disabled 0 CRC length is zero and CRC calculation is disabled One 1 CRC length is one byte and CRC calculation is enabled Two 2 CRC length is two bytes and CRC calculation is enabled Three 3 CRC length is three bytes and CRC calculation is enabled RW SKIPADDR Include or exclude packet address field out of CRC calculation. Include 0 CRC calculation includes address field Skip 1 CRC calculation does not include address field. The CRC Ieee802154 2 calculation will start at the first byte after the address. CRC calculation as per 802.15.4 standard. Starting at first byte after length field. 6.18.15.61 CRCPOLY Address offset: 0x538 CRC polynomial 4452_021 v1.5 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 328 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW CRCPOLY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description CRC polynomial Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/bit is hardwired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 . 6.18.15.62 CRCINIT Address offset: 0x53C CRC initial value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW CRCINIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description CRC initial value Initial value for CRC calculation 6.18.15.63 TIFS Address offset: 0x544 Interframe spacing in µs Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A Reset 0x00000000 ID Access Field A RW TIFS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Interframe spacing in µs. Interframe space is the time interval between two consecutive packets. It is defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet. 6.18.15.64 RSSISAMPLE Address offset: 0x548 RSSI sample 4452_021 v1.5 329 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID RSSISAMPLE Value Description [0..127] RSSI sample. RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm. 6.18.15.65 STATE Address offset: 0x550 Current radio state Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 RADIO is in the Disabled state RxRu 1 RADIO is in the RXRU state RxIdle 2 RADIO is in the RXIDLE state Rx 3 RADIO is in the RX state RxDisable 4 RADIO is in the RXDISABLED state TxRu 9 RADIO is in the TXRU state TxIdle 10 RADIO is in the TXIDLE state Tx 11 RADIO is in the TX state TxDisable 12 RADIO is in the TXDISABLED state STATE Current radio state 6.18.15.66 DATAWHITEIV Address offset: 0x554 Data whitening initial value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000040 ID Access Field A RW DATAWHITEIV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Value ID Value Description Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5, etc. 6.18.15.67 BCC Address offset: 0x560 Bit counter compare 4452_021 v1.5 330 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW BCC Value ID Value Description Bit counter compare Bit counter compare register 6.18.15.68 DAB[n] (n=0..7) Address offset: 0x600 + (n × 0x4) Device address base segment n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW DAB Value ID Value Description Device address base segment n 6.18.15.69 DAP[n] (n=0..7) Address offset: 0x620 + (n × 0x4) Device address prefix n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW DAP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Device address prefix n 6.18.15.70 DACNF Address offset: 0x640 Device address match configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID P O N M L K J I H G F E D C B A Reset 0x00000000 ID Access Field A-H RW ENA[i] (i=0..7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable device address matching using device address i I-P Disabled 0 Disabled Enabled 1 Enabled RW TXADD[i] (i=0..7) TxAdd for device address i 6.18.15.71 MHRMATCHCONF Address offset: 0x644 Search pattern configuration 4452_021 v1.5 331 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW MHRMATCHCONF Value ID Value Description Search pattern configuration 6.18.15.72 MHRMATCHMAS Address offset: 0x648 Pattern mask Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MHRMATCHMAS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pattern mask 6.18.15.73 MODECNF0 Address offset: 0x650 Radio mode configuration register 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C C Reset 0x00000200 ID Access Field A RW RU Value ID Value Default 0 Fast 1 Description Radio ramp-up time Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information When enabled, TIFS is not enforced by hardware and software needs to control when to turn on the Radio C RW DTX Default TX value Specifies what the RADIO will transmit when it is not started, i.e. between: RADIO.EVENTS_READY and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.EVENTS_DISABLED For IEEE 802.15.4 250 kbps mode only Center is a valid setting For Bluetooth Low Energy Long Range mode only Center is a valid setting B1 0 Transmit '1' B0 1 Transmit '0' Center 2 Transmit center frequency When tuning the crystal for center frequency, the RADIO must be set in DTX = Center mode to be able to achieve the expected accuracy 4452_021 v1.5 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 332 Peripherals 6.18.15.74 SFD Address offset: 0x660 IEEE 802.15.4 start of frame delimiter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x000000A7 ID Access Field A RW SFD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 Value ID Value Description IEEE 802.15.4 start of frame delimiter 6.18.15.75 EDCNT Address offset: 0x664 IEEE 802.15.4 energy detect loop count Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW EDCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description IEEE 802.15.4 energy detect loop count 6.18.15.76 EDSAMPLE Address offset: 0x668 IEEE 802.15.4 energy detect level Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID EDLVL Value Description [0..127] IEEE 802.15.4 energy detect level Register value must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by factor ED_RSSISCALE, as shown in the code example for ED sampling 6.18.15.77 CCACTRL Address offset: 0x66C IEEE 802.15.4 clear channel assessment control 4452_021 v1.5 333 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D D D D D C C C C C C C C B B B B B B B B Reset 0x052D0000 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW CCAMODE Value ID Value EdMode 0 A A A Description CCA mode of operation Energy above threshold Will report busy whenever energy is detected above CCAEDTHRES CarrierMode 1 Carrier seen Will report busy whenever compliant IEEE 802.15.4 signal is seen CarrierAndEdMode 2 Energy above threshold AND carrier seen CarrierOrEdMode 3 Energy above threshold OR carrier seen EdModeTest1 4 Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. B RW CCAEDTHRES CCA energy busy threshold. Used in all the CCA modes except CarrierMode. Must be converted from IEEE 802.15.4 range by dividing by factor ED_RSSISCALE - similar to EDSAMPLE register C RW CCACORRTHRES CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. D RW CCACORRCNT Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. 6.18.15.78 DFEMODE Address offset: 0x900 Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW DFEOPMODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Direction finding operation mode Disabled 0 Direction finding mode disabled AoD 2 Direction finding mode set to AoD AoA 3 Direction finding mode set to AoA 6.18.15.79 CTEINLINECONF Address offset: 0x904 Configuration for CTE inline mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I Reset 0x00002800 ID Access Field A RW CTEINLINECTRLEN I I I I I I I H H H H H H H H G G G F F F Value Description Enable parsing of CTEInfo from received packet in BLE Enabled 1 Parsing of CTEInfo is enabled Disabled 0 Parsing of CTEInfo is disabled RW CTEINFOINS1 4452_021 v1.5 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Value ID modes B E E CTEInfo is S1 byte or not 334 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I Reset 0x00002800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ID C E Access Field I I I I I I I H H H H H H H H G G G F F F E E Value ID Value Description InS1 1 CTEInfo is in S1 byte (data PDU) NotInS1 0 CTEInfo is NOT in S1 byte (advertising PDU) Yes 1 Sampling and antenna switching also when CRC is not OK No 0 No sampling and antenna switching when CRC is not OK RW CTEERRORHANDLING C B Sampling/switching if CRC is not OK RW CTETIMEVALIDRANGE Max range of CTETime Valid range is 2-20 in BLE core spec. If larger than 20, it can be an indication of an error in the received packet. 20 0 20 in 8 µs unit (default) Set to 20 if parsed CTETime is larger than 20 F 31 1 31 in 8 µs unit 63 2 63 in 8 µs unit RW CTEINLINERXMODE1US Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. When the device is in AoD mode, this is used when the received CTEType is "AoD 1 µs". When in AoA mode, this is used when TSWITCHSPACING is 2 µs. G 4us 1 4 µs 2us 2 2 µs 1us 3 1 µs 500ns 4 0.5 µs 250ns 5 0.25 µs 125ns 6 0.125 µs RW CTEINLINERXMODE2US Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. When the device is in AoD mode, this is used when the received CTEType is "AoD 2 µs". When in AoA mode, this is used when TSWITCHSPACING is 4 µs. H 4us 1 4 µs 2us 2 2 µs 1us 3 1 µs 500ns 4 0.5 µs 250ns 5 0.25 µs 125ns 6 0.125 µs RW S0CONF S0 bit pattern to match The least significant bit always corresponds to the first bit of S0 received. I RW S0MASK S0 bit mask to set which bit to match The least significant bit always corresponds to the first bit of S0 received. 6.18.15.80 DFECTRL1 Address offset: 0x910 Various configuration for Direction finding 4452_021 v1.5 335 A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I I I I H H H H Reset 0x00023282 ID Access Field A RW NUMBEROF8US G G G F E E E C C C B A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 Value ID Value Description Length of the AoA/AoD procedure in number of 8 µs units Always used in TX mode, but in RX mode only when CTEINLINECTRLEN is 0 B RW DFEINEXTENSION Add CTE extension and do antenna switching/sampling in this extension C CRC 1 AoA/AoD procedure triggered at end of CRC Payload 0 Antenna switching/sampling is done in the packet payload RW TSWITCHSPACING Interval between every time the antenna is changed in the SWITCHING state E F G 4us 1 4 µs 2us 2 2 µs 1us 3 1 µs 4us 1 4 µs 2us 2 2 µs 1us 3 1 µs 500ns 4 0.5 µs 250ns 5 0.25 µs 125ns 6 0.125 µs IQ 0 Complex samples in I and Q MagPhase 1 Complex samples as magnitude and phase RW TSAMPLESPACINGREF Interval between samples in the REFERENCE period RW SAMPLETYPE Whether to sample I/Q or magnitude/phase RW TSAMPLESPACING Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 Not used when CTEINLINECTRLEN is set. Then either CTEINLINERXMODE1US or CTEINLINERXMODE2US are used. H 4us 1 4 µs 2us 2 2 µs 1us 3 1 µs 500ns 4 0.5 µs 250ns 5 0.25 µs 125ns 6 0.125 µs RW REPEATPATTERN Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. NoRepeat I 0 Do not repeat (1 time in total) RW AGCBACKOFFGAIN Gain will be lowered by the specified number of gain steps at the start of CTE First LNAGAIN gain drops, then MIXGAIN, then AAFGAIN 6.18.15.81 DFECTRL2 Address offset: 0x914 Start offset for Direction finding 4452_021 v1.5 336 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B B B B Reset 0x00000000 ID Access Field A RW TSWITCHOFFSET A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Signed value offset after the end of the CRC before starting switching in number of 16M cycles Decreasing TSWITCHOFFSET beyond the trigger of the AoA/ AoD procedure will have no effect B RW TSAMPLEOFFSET Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 µs after switching start Decreasing TSAMPLEOFFSET beyond the trigger of the AoA/ AoD procedure will have no effect 6.18.15.82 SWITCHPATTERN Address offset: 0x928 GPIO patterns to be used for each antenna Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be configured in the GPIO peripheral as described in Pin configuration. If, during switching, the total number of antenna slots is bigger than the number of written patterns, the RADIO loops back to the pattern used after the reference pattern. A minimum number of three patterns must be written. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A RW SWITCHPATTERN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Fill array of GPIO patterns for antenna control. The GPIO pattern array size is 40 entries. When written, bit n corresponds to the GPIO configured in PSEL.DFEGPIO[n]. When read, returns the number of GPIO patterns written since the last time the array was cleared. Use CLEARPATTERN to clear the array. 6.18.15.83 CLEARPATTERN Address offset: 0x92C Clear the GPIO pattern array for antenna control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW CLEARPATTERN 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Clear 1 Description Clears GPIO pattern array for antenna control Clear the GPIO pattern 337 Peripherals 6.18.15.84 PSEL.DFEGPIO[n] (n=0..7) Address offset: 0x930 + (n × 0x4) Pin select for DFE pin n Must be set before enabling the radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A B C RW CONNECT Value ID B A A A A A Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.18.15.85 DFEPACKET.PTR Address offset: 0x950 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer See the memory chapter for details about which memories are available for EasyDMA. 6.18.15.86 DFEPACKET.MAXCNT Address offset: 0x954 Maximum number of buffer words to transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0x00001000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Maximum number of buffer words to transfer 6.18.15.87 DFEPACKET.AMOUNT Address offset: 0x958 Number of samples transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AMOUNT 4452_021 v1.5 Number of samples transferred in the last transaction 338 Peripherals 6.18.15.88 POWER Address offset: 0xFFC Peripheral power control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID Access Field A RW POWER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. Disabled 0 Peripheral is powered off Enabled 1 Peripheral is powered on 6.18.16 Electrical specification 6.18.16.1 General radio characteristics Symbol Description Min. fOP Operating frequencies 2360 Typ. Max. Units 2500 MHz fPLL,CH,SP PLL channel spacing 1 MHz fDELTA,1M Frequency deviation @ 1 Mbps ±170 kHz fDELTA,BLE,1M Frequency deviation @ BLE 1 Mbps ±250 kHz fDELTA,2M Frequency deviation @ 2 Mbps ±320 kHz fDELTA,BLE,2M Frequency deviation @ BLE 2 Mbps fskBPS On-the-air data rate fchip, IEEE 802.15.4 Chip rate in IEEE 802.15.4 mode ±500 125 kHz 2000 2000 kbps kchip/ s 6.18.16.2 Radio current consumption (transmitter) Symbol Description ITX,PLUS8dBM,DCDC TX only run current (DC/DC, 3 V) PRF = +8 dBm 14.2 mA ITX,PLUS8dBM TX only run current PRF = +8 dBm 30.4 mA ITX,PLUS4dBM,DCDC TX only run current (DC/DC, 3 V) PRF = +4 dBm 9.6 mA ITX,PLUS4dBM TX only run current PRF = +4 dBm 20.7 mA ITX,0dBM,DCDC TX only run current (DC/DC, 3 V)PRF = 0 dBm 4.9 mA ITX,0dBM TX only run current PRF = 0 dBm 10.3 mA ITX,MINUS4dBM,DCDC TX only run current DC/DC, 3 V PRF = -4 dBm 3.8 mA ITX,MINUS4dBM TX only run current PRF = -4 dBm 8.0 mA ITX,MINUS8dBM,DCDC TX only run current DC/DC, 3 V PRF = -8 dBm 3.4 mA ITX,MINUS8dBM TX only run current PRF = -8 dBm 7.1 mA ITX,MINUS12dBM,DCDC TX only run current DC/DC, 3 V PRF = -12 dBm 3.1 mA ITX,MINUS12dBM 6.4 mA ITX,MINUS16dBM,DCDC TX only run current DC/DC, 3 V PRF = -16 dBm 2.9 mA ITX,MINUS16dBM 5.9 mA ITX,MINUS20dBM,DCDC TX only run current DC/DC, 3 V PRF = -20 dBm 2.7 mA ITX,MINUS20dBM 5.5 mA ITX,MINUS40dBM,DCDC TX only run current DC/DC, 3 V PRF = -40 dBm 2.3 mA ITX,MINUS40dBM TX only run current PRF = -40 dBm 4.5 mA ISTART,TX,DCDC TX start-up current DC/DC, 3 V, PRF = 4 dBm 4.3 mA 4452_021 v1.5 Min. TX only run current PRF = -12 dBm TX only run current PRF = -16 dBm TX only run current PRF = -20 dBm 339 Typ. Max. Units Peripherals Symbol Description Min. ISTART,TX TX start-up current, PRF = 4 dBm Typ. Max. 8.9 Units mA 6.18.16.3 Radio current consumption (Receiver) Symbol Description IRX,1M,DCDC RX only run current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE Min. Typ. 4.6 Max. Units mA IRX,1M RX only run current (LDO, 3 V) 1 Mbps/1 Mbps BLE 9.6 mA IRX,2M,DCDC RX only run current (DC/DC, 3 V) 2 Mbps/2 Mbps BLE 5.2 mA IRX,2M RX only run current (LDO, 3 V) 2 Mbps/2 Mbps BLE 10.7 mA ISTART,RX,1M,DCDC RX start-up current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE 3.4 mA ISTART,RX,1M RX start-up current 1 Mbps/1 Mbps BLE 6.8 mA 6.18.16.4 Transmitter specification Symbol Description Min. Typ. Max. Units PRF Maximum output power 8 PRFC RF power control range 28 PRFCR RF power accuracy PRF1,1 1st Adjacent Channel Transmit Power 1 MHz (1 Mbps) -25 dBc PRF2,1 2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps) -54 dBc PRF1,2 1st Adjacent Channel Transmit Power 2 MHz (2 Mbps) -26 dBc PRF2,2 2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps) -54 dBc Evm Error vector magnitude in IEEE 802.15.4 mode dBm dB ±4 dB 9 %rms Pharm2nd, IEEE 802.15.4 2nd harmonics in IEEE 802.15.4 mode -51 dBm Pharm3rd, IEEE 802.15.4 3rd harmonics in IEEE 802.15.4 mode -51 dBm 8.4 8.2 Output power [dBm] 8 7.8 7.6 7.4 7.2 -40 -20 0 20 40 60 80 Temperature Range [°C] 1.7 V 3V 3.6 V Figure 115: Output power, 1 Mbps Bluetooth low energy mode, at maximum TXPOWER setting (typical values) 4452_021 v1.5 340 100 120 Peripherals 0.5 0 Output power [dBm] -0.5 -1 -1.5 -2 -2.5 -3 -40 -20 0 20 40 60 80 100 120 Temperature Range [°C] 1.7 V 3V 3.6 V Figure 116: Output power, 1 Mbps Bluetooth low energy mode, at 0 dBm TXPOWER setting (typical values) 6.18.16.5 Receiver operation Symbol Description PRX,MAX Maximum received signal strength at < 0.1% PER Min. Typ. Max. Units 0 dBm PSENS,IT,1M Sensitivity, 1 Mbps nRF mode ideal transmitter 17 -93 dBm PSENS,IT,2M Sensitivity, 2 Mbps nRF mode ideal transmitter 17 -89 dBm PSENS,IT,SP,1M,BLE Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≤ 37 -96 dBm -94 dBm -92 dBm 18 bytes BER=1E-3 PSENS,IT,LP,1M,BLE Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≥ 128 bytes BER=1E-4 PSENS,IT,SP,2M,BLE 19 Sensitivity, 2 Mbps BLE ideal transmitter, packet length ≤ 37 bytes PSENS,IT,BLE LE125k Sensitivity, 125 kbps BLE mode -103 dBm PSENS,IT,BLE LE500k Sensitivity, 500 kbps BLE mode -98 dBm PSENS,IEEE 802.15.4 Sensitivity in IEEE 802.15.4 mode -100 dBm 17 18 19 Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7] are used for receiver address correlation, the typical sensitivity for this mode is degraded by 3 dB. As defined in the Bluetooth Core Specification v4.0 Volume 6: Core System Package (Low Energy Controller Volume). Equivalent BER limit < 10E-04. 4452_021 v1.5 341 Peripherals -93.5 -94 Sensitivity [dBm] -94.5 -95 -95.5 -96 -96.5 -97 -40 -20 0 20 40 60 80 100 120 Temperature Range [°C] 1.7 V 3V 3.6 V Figure 117: Sensitivity, 1 Mbps Bluetooth low energy mode, Regulator = LDO (typical values) 6.18.16.6 RX selectivity RX selectivity with equal modulation on interfering signal20 Symbol Description C/I1M,co-channel 1Mbps mode, co-channel interference 10 dB C/I1M,-1MHz 1 Mbps mode, Adjacent (-1 MHz) interference -5 dB C/I1M,+1MHz 1 Mbps mode, Adjacent (+1 MHz) interference -14 dB C/I1M,-2MHz 1 Mbps mode, Adjacent (-2 MHz) interference -19 dB C/I1M,+2MHz 1 Mbps mode, Adjacent (+2 MHz) interference -42 dB C/I1M,-3MHz 1 Mbps mode, Adjacent (-3 MHz) interference -37 dB C/I1M,+3MHz 1 Mbps mode, Adjacent (+3 MHz) interference -47 dB C/I1M,±6MHz 1 Mbps mode, Adjacent (≥6 MHz) interference -52 dB C/I1MBLE,co-channel 1 Mbps BLE mode, co-channel interference 6 dB C/I1MBLE,-1MHz 1 Mbps BLE mode, Adjacent (-1 MHz) interference -2 dB C/I1MBLE,+1MHz 1 Mbps BLE mode, Adjacent (+1 MHz) interference -10 dB C/I1MBLE,-2MHz 1 Mbps BLE mode, Adjacent (-2 MHz) interference -23 dB C/I1MBLE,+2MHz 1 Mbps BLE mode, Adjacent (+2 MHz) interference -45 dB C/I1MBLE,>3MHz 1 Mbps BLE mode, Adjacent (≥3 MHz) interference -54 dB C/I1MBLE,image Image frequency interference -24 dB C/I1MBLE,image,1MHz Adjacent (1 MHz) interference to in-band image frequency -37 dB C/I2M,co-channel 2 Mbps mode, co-channel interference 10 dB C/I2M,-2MHz 2 Mbps mode, Adjacent (-2 MHz) interference -4 dB C/I2M,+2MHz 2 Mbps mode, Adjacent (+2 MHz) interference -16 dB C/I2M,-4MHz 2 Mbps mode, Adjacent (-4 MHz) interference -19 dB C/I2M,+4MHz 2 Mbps mode, Adjacent (+4 MHz) interference -46 dB 20 Min. Typ. Max. Units Desired signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the desired signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented. 4452_021 v1.5 342 Peripherals Symbol Description Min. Typ. Max. Units C/I2M,-6MHz 2 Mbps mode, Adjacent (-6 MHz) interference -41 dB C/I2M,+6MHz 2 Mbps mode, Adjacent (+6 MHz) interference -48 dB C/I2M,≥12MHz 2 Mbps mode, Adjacent (≥12 MHz) interference -52 dB C/I2MBLE,co-channel 2 Mbps BLE mode, co-channel interference 7 dB C/I2MBLE,-2MHz 2 Mbps BLE mode, Adjacent (-2 MHz) interference -2 dB C/I2MBLE,+2MHz 2 Mbps BLE mode, Adjacent (+2 MHz) interference -12 dB C/I2MBLE,-4MHz 2 Mbps BLE mode, Adjacent (-4 MHz) interference -22 dB C/I2MBLE,+4MHz 2 Mbps BLE mode, Adjacent (+4 MHz) interference -46 dB C/I2MBLE,≥6MHz 2 Mbps BLE mode, Adjacent (≥6 MHz) interference -52 dB C/I2MBLE,image Image frequency interference -22 dB C/I2MBLE,image, 2MHz Adjacent (2 MHz) interference to in-band image frequency -37 dB C/I125k BLE LR,co- 125 kbps BLE LR mode, co-channel interference 3 dB C/I125k BLE LR,-1MHz 125 kbps BLE LR mode, Adjacent (-1 MHz) interference -9 dB C/I125k BLE LR,+1MHz 125 kbps BLE LR mode, Adjacent (+1 MHz) interference -16 dB C/I125k BLE LR,-2MHz 125 kbps BLE LR mode, Adjacent (-2 MHz) interference -27 dB C/I125k BLE LR,+2MHz 125 kbps BLE LR mode, Adjacent (+2 MHz) interference -54 dB C/I125k BLE LR,>3MHz 125 kbps BLE LR mode, Adjacent (≥3 MHz) interference -60 dB C/I125k BLE LR,image Image frequency interference -27 dB C/IIEEE 802.15.4,-5MHz IEEE 802.15.4 mode, Adjacent (-5 MHz) rejection -33 dB C/IIEEE 802.15.4,+5MHz IEEE 802.15.4 mode, Adjacent (+5 MHz) rejection -38 dB C/IIEEE 802.15.4,±10MHz IEEE 802.15.4 mode, Alternate (±10 MHz) rejection -49 dB channel 6.18.16.7 RX intermodulation RX intermodulation. Desired signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer closest in frequency is not modulated, the other interferer is modulated equal with the desired signal. The input power of the interferers where the sensitivity equals BER = 0.1% is presented. Symbol Description Min. PIMD,5TH,1M IMD performance, 1 Mbps, 5th offset channel, packet length Typ. Max. Units -34 dBm -32 dBm -33 dBm -32 dBm ≤ 37 bytes PIMD,5TH,1M,BLE IMD performance, BLE 1 Mbps, 5th offset channel, packet length ≤ 37 bytes PIMD,5TH,2M IMD performance, 2 Mbps, 5th offset channel, packet length ≤ 37 bytes PIMD,5TH,2M,BLE IMD performance, BLE 2 Mbps, 5th offset channel, packet length ≤ 37 bytes 6.18.16.8 Radio timing Symbol Description Min. Max. Units tTXEN,BLE,1M Time between TXEN task and READY event after channel 140 Typ. 140 µs 40 40 µs 6 6 µs 140 140 µs 40 40 µs FREQUENCY configured (1 Mbps BLE and 150 µs TIFS) tTXEN,FAST,BLE,1M Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up and 150 µs TIFS) tTXDIS,BLE,1M When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit tRXEN,BLE,1M Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE) tRXEN,FAST,BLE,1M Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up) 4452_021 v1.5 343 Peripherals Symbol Description Min. tRXDIS,BLE,1M When in RX, delay between DISABLE task and DISABLED Typ. Max. Units 0 0 µs 4 4 µs 0 0 µs 130 130 µs 40 40 µs 21 21 µs 130 130 µs 40 40 µs 0.5 0.5 µs event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit tTXDIS,BLE,2M When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit tRXDIS,BLE,2M When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit tTXEN,IEEE 802.15.4 Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode) tTXEN,FAST,IEEE 802.15.4 Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode with fast rampup) tTXDIS,IEEE 802.15.4 When in TX, delay between DISABLE task and DISABLED event (IEEE 802.15.4 mode) tRXEN,IEEE 802.15.4 Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode) tRXEN,FAST,IEEE 802.15.4 Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode with fast rampup) tRXDIS,IEEE 802.15.4 When in RX, delay between DISABLE task and DISABLED event (IEEE 802.15.4 mode) tRX-to-TX turnaround Maximum TX-to-RX or RX-to-TX turnaround time in IEEE 40 µs 802.15.4 mode 6.18.16.9 Received signal strength indicator (RSSI) specifications Symbol Description RSSIACC RSSI accuracy RSSIRESOLUTION RSSIPERIOD RSSISETTLE Min. Typ. Max. Units ±2 dB RSSI resolution 1 dB RSSI sampling time from RSSI_START task 0.25 µs RSSI settling time after signal level change 15 µs 21 6.18.16.10 Jitter Symbol Description tDISABLEDJITTER Jitter on DISABLED event relative to END event when Min. Typ. Max. Units 0.25 µs 0.25 µs shortcut between END and DISABLE is enabled tREADYJITTER Jitter on READY event relative to TXEN and RXEN task 6.18.16.11 IEEE 802.15.4 mode energy detection constants Symbol Description ED_RSSISCALE Scaling value when converting between hardware-reported Min. Typ. 5 value and dBm ED_RSSIOFFS Offset value when converting between hardware-reported value and dBm 21 Valid range -90 to -30 dBm 4452_021 v1.5 344 -93 Max. Units Peripherals 6.19 RNG — Random number generator The Random number generator (RNG) generates true non-deterministic random numbers based on internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value. START Random number generator STOP VALRDY VALUE Figure 118: Random number generator The RNG is started by triggering the START task and stopped by triggering the STOP task. When started, new random numbers are generated continuously and written to the VALUE register when ready. A VALRDY event is generated for every new random number that is written to the VALUE register. This means that after a VALRDY event is generated, the CPU has the time until the next VALRDY event to read out the random number from the VALUE register before it is overwritten by a new random number. 6.19.1 Bias correction A bias correction algorithm is employed on the internal bit stream to remove any bias toward 1 or 0. The bits are then queued into an eight-bit register for parallel readout from the VALUE register. It is possible to enable bias correction in the CONFIG register. This will result in slower value generation, but will ensure a statistically uniform distribution of the random values. 6.19.2 Speed The time needed to generate one random byte of data is unpredictable, and may vary from one byte to the next. This is especially true when bias correction is enabled. 6.19.3 Registers Base address Peripheral Instance Description Configuration 0x4000D000 RNG RNG Random number generator Table 87: Instances Register Offset Description TASKS_START 0x000 Task starting the random number generator TASKS_STOP 0x004 Task stopping the random number generator EVENTS_VALRDY 0x100 Event being generated for every new random number written to the VALUE register SHORTS 0x200 Shortcuts between local events and tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt CONFIG 0x504 Configuration register VALUE 0x508 Output random number Table 88: Register overview 6.19.3.1 TASKS_START Address offset: 0x000 4452_021 v1.5 345 Peripherals Task starting the random number generator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_START Task starting the random number generator Trigger 1 Trigger task 6.19.3.2 TASKS_STOP Address offset: 0x004 Task stopping the random number generator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Task stopping the random number generator Trigger task 6.19.3.3 EVENTS_VALRDY Address offset: 0x100 Event being generated for every new random number written to the VALUE register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_VALRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event being generated for every new random number written to the VALUE register NotGenerated 0 Event not generated Generated 1 Event generated 6.19.3.4 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW VALRDY_STOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event VALRDY and task STOP 6.19.3.5 INTENSET Address offset: 0x304 4452_021 v1.5 346 Peripherals Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW VALRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event VALRDY Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.19.3.6 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW VALRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event VALRDY 6.19.3.7 CONFIG Address offset: 0x504 Configuration register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW DERCEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disabled Enabled 1 Enabled Bias correction 6.19.3.8 VALUE Address offset: 0x508 Output random number Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A R VALUE 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..255] Generated random number 347 Peripherals 6.19.4 Electrical specification 6.19.4.1 RNG Electrical Specification Symbol Description tRNG,START Time from setting the START task to generation begins. Min. Typ. Max. Units 128 µs 30 µs 120 µs This is a one-time delay on START signal and does not apply between samples. tRNG,RAW Run time per byte without bias correction. Uniform distribution of 0 and 1 is not guaranteed. tRNG,BC Run time per byte with bias correction. Uniform distribution of 0 and 1 is guaranteed. Time to generate a byte cannot be guaranteed. 6.20 RTC — Real-time counter The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock source (LFCLK). 32.768 kHz START STOP CLEAR TRIGOVRFLW task PRESCALER event TICK event OVRFLW event COMPARE[0..N] COUNTER task RTC task task CC[0:3] Figure 119: RTC block schematic The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick event generator for low power, tickless RTOS implementation. 6.20.1 Clock source The RTC runs off the LFCLK. The COUNTER resolution is 30.517 µs. Depending on the source, the RTC is able to run while the HFCLK is OFF and PCLK16M is not available. The software has to explicitly start LFCLK before using the RTC. See CLOCK — Clock control on page 82 for more information about clock sources. 6.20.2 Resolution versus overflow and the PRESCALER 4452_021 v1.5 348 Peripherals Counter increment frequency: fRTC [kHz] = 32.768 / (PRESCALER + 1 ) The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only once the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect. The PRESCALER is restarted on START, CLEAR, and TRIGOVRFLW, meaning the prescaler value is latched to an internal register () on these tasks. Examples of different frequency configurations are as following: • Desired COUNTER frequency 100 Hz (10 ms counter period) PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327 fRTC = 99.9 Hz 10009.576 μs counter period • Desired COUNTER frequency 8 Hz (125 ms counter period) PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095 fRTC = 8 Hz 125 ms counter period Prescaler Counter resolution Overflow 0 30.517 μs 512 seconds 28-1 7812.5 μs 131072 seconds 212-1 125 ms 582.542 hours Table 89: RTC resolution versus overflow 6.20.3 COUNTER register The COUNTER increments on LFCLK when the internal PRESCALER register () is 0x00. is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment of the COUNTER. The TICK event is disabled by default. SysClk LFClk TICK PRESC COUNTER 0x000 0x000 0x000 0x000 0x000 0x000000 0x000001 0x000002 0x000003 Figure 120: Timing diagram - COUNTER_PRESCALER_0 4452_021 v1.5 349 Peripherals SysClk LFClk TICK PRESC 0x001 0x000 COUNTER 0x001 0x000000 0x000 0x001 0x000001 Figure 121: Timing diagram - COUNTER_PRESCALER_1 6.20.4 Overflow features The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition. OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0. Note: The OVRFLW event is disabled by default. 6.20.5 TICK event The TICK event enables low power tickless RTOS implementation as it optionally provides a regular interrupt source for a RTOS without the need to use the ARM® SysTick feature. Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active. Note: The TICK event is disabled by default. 6.20.6 Event control feature To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK being requested when those events are triggered. This is managed using the EVTEN register. For example, if the TICK event is not required for an application, this event should be disabled as it is frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for long durations. This means that the RTC implements a slightly different task and event system compared to the standard system described in Peripheral interface on page 98. The RTC task and event system is illustrated in Tasks, events, and interrupts in the RTC on page 351. 4452_021 v1.5 350 Peripherals Task signal from PPI RTC write TASK OR task RTC core event EVTEN m INTEN m EVENT m IRQ signal to NVIC Event signal to PPI Figure 122: Tasks, events, and interrupts in the RTC 6.20.7 Compare feature There are a number of Compare registers. For more information, see Registers on page 356. When setting a compare register, the following behavior of the RTC compare event should be noted: • If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event. SysClk LFClk PRESC COUNTER 0x000 X 0x000000 CLEAR CC[0] 0x000000 COMPARE[0] 0 Figure 123: Timing diagram - COMPARE_CLEAR • If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event. 4452_021 v1.5 351 Peripherals SysClk LFClk PRESC 0x000 COUNTER N-1 N N+1 START CC[0] N COMPARE[0] 0 Figure 124: Timing diagram - COMPARE_START • COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N. SysClk LFClk PRESC COUNTER 0x000 N-2 N-1 CC[0] N N+1 N COMPARE[0] 0 1 Figure 125: Timing diagram - COMPARE • If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2. SysClk LFClk PRESC COUNTER 0x000 N-1 N N+1 N+2 > 62.5 ns CC[0] COMPARE[0] X N+2 0 1 Figure 126: Timing diagram - COMPARE_N+2 • If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event. 4452_021 v1.5 352 Peripherals SysClk LFClk PRESC COUNTER 0x000 N-2 N-1 N N+1 ≥0 CC[0] X N+1 COMPARE[0] 0 Figure 127: Timing diagram - COMPARE_N+1 • If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a match may trigger on the previous CC value before the new value takes effect. If the current CC value is greater than N+2 when the new value is written, there will be no event due to the old value. SysClk LFClk PRESC COUNTER CC[0] 0x000 N-2 N-1 N N+1 ≥0 N X COMPARE[0] 0 1 Figure 128: Timing diagram - COMPARE_N-1 6.20.8 TASK and EVENT jitter/delay Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not synchronous to the faster PCLK16M. Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register which is actually modified each time the RTC ticks. These registers must be synchronised between clock domains (PCLK16M and LFCLK). The following is a summary of the jitter introduced on tasks and events. Task Delay CLEAR, STOP, START, TRIGOVRFLOW +15 to 46 μs Table 90: RTC jitter magnitudes on tasks 4452_021 v1.5 353 Peripherals Operation/Function Jitter START to COUNTER increment COMPARE to COMPARE +/- 15 μs +/- 62.5 ns 22 Table 91: RTC jitter magnitudes on events Note: 32.768 kHz clock jitter is additional to the numbers provided above. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and rising of the LFCLK. This is between 15.2585 μs and 45.7755 μs – rounded to 15 μs and 46 μs for the remainder of the section. SysClk CLEAR LFClk PRESC COUNTER CLEARa 0x000 X X+1 0x000000 0x000001 0 or more SysClk after ≤ ~46 µs ≥ ~15 µs 1 or more SysClk before CLEARb Figure 129: Timing diagram - DELAY_CLEAR SysClk STOP LFClk PRESC COUNTER STOPa STOPb 0x000 X X+1 0 or more SysClk after ≤ ~46 µs ≥ ~15 µs 1 or more SysClk before Figure 130: Timing diagram - DELAY_STOP The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. In some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to ~250 μs. The software should therefore wait for the first TICK if it has to make sure the RTC is running. Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK, but the update will then be delayed by the same amount of time of up to ~250 μs. The figures show the shortest and longest delays on the START task which appears as a +/-15 μs jitter on the first COUNTER increment. 22 Assumes RTC runs continuously between these events. 4452_021 v1.5 354 Peripherals SysClk First tick LFClk PRESC 0x000 COUNTER X X+1 X+2 X+3 ≥ ~15 µs 0 or more SysClk before START Figure 131: Timing diagram - JITTER_STARTSysClk First tick LFClk PRESC 0x000 COUNTER X X+1 X+2 ≤ ~250 µs START Figure 132: Timing diagram - JITTER_START+ 6.20.9 Reading the COUNTER register To read the COUNTER register, the internal value is sampled. To ensure that the is safely sampled (considering an LFCLK transition may occur during a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five PCLK16M clock cycles. SysClk PREADY LFClk N-1 N COUNTER X N 375.2 ns COUNTER_READ Figure 133: Timing diagram - COUNTER_READ 4452_021 v1.5 355 Peripherals 6.20.10 Registers Base address Peripheral Instance Description Configuration 0x4000B000 RTC RTC0 Real-time counter 0 CC[0..2] implemented, CC[3] not 0x40011000 RTC RTC1 Real-time counter 1 CC[0..3] implemented 0x40024000 RTC RTC2 Real-time counter 2 CC[0..3] implemented implemented Table 92: Instances Register Offset Description TASKS_START 0x000 Start RTC COUNTER TASKS_STOP 0x004 Stop RTC COUNTER TASKS_CLEAR 0x008 Clear RTC COUNTER TASKS_TRIGOVRFLW 0x00C Set COUNTER to 0xFFFFF0 EVENTS_TICK 0x100 Event on COUNTER increment EVENTS_OVRFLW 0x104 Event on COUNTER overflow EVENTS_COMPARE[0] 0x140 Compare event on CC[0] match EVENTS_COMPARE[1] 0x144 Compare event on CC[1] match EVENTS_COMPARE[2] 0x148 Compare event on CC[2] match EVENTS_COMPARE[3] 0x14C Compare event on CC[3] match INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt EVTEN 0x340 Enable or disable event routing EVTENSET 0x344 Enable event routing EVTENCLR 0x348 Disable event routing COUNTER 0x504 Current COUNTER value PRESCALER 0x508 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is CC[0] 0x540 Compare register 0 CC[1] 0x544 Compare register 1 CC[2] 0x548 Compare register 2 CC[3] 0x54C Compare register 3 stopped. Table 93: Register overview 6.20.10.1 TASKS_START Address offset: 0x000 Start RTC COUNTER Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_START Start RTC COUNTER Trigger task 6.20.10.2 TASKS_STOP Address offset: 0x004 Stop RTC COUNTER 4452_021 v1.5 356 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stop RTC COUNTER Trigger task 6.20.10.3 TASKS_CLEAR Address offset: 0x008 Clear RTC COUNTER Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_CLEAR Clear RTC COUNTER Trigger task 6.20.10.4 TASKS_TRIGOVRFLW Address offset: 0x00C Set COUNTER to 0xFFFFF0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 Trigger task 6.20.10.5 EVENTS_TICK Address offset: 0x100 Event on COUNTER increment Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TICK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event on COUNTER increment NotGenerated 0 Event not generated Generated 1 Event generated 6.20.10.6 EVENTS_OVRFLW Address offset: 0x104 Event on COUNTER overflow 4452_021 v1.5 357 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_OVRFLW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Event on COUNTER overflow 6.20.10.7 EVENTS_COMPARE[n] (n=0..3) Address offset: 0x140 + (n × 0x4) Compare event on CC[n] match Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_COMPARE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Compare event on CC[n] match 6.20.10.8 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID Access Field A RW TICK B C-F Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event TICK RW OVRFLW Write '1' to enable interrupt for event OVRFLW RW COMPARE[i] (i=0..3) Write '1' to enable interrupt for event COMPARE[i] 6.20.10.9 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.5 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 358 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID Access Field A RW TICK B C-F B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event TICK RW OVRFLW Write '1' to disable interrupt for event OVRFLW RW COMPARE[i] (i=0..3) Write '1' to disable interrupt for event COMPARE[i] 6.20.10.10 EVTEN Address offset: 0x340 Enable or disable event routing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID Access Field A RW TICK B C-F B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable event routing for event TICK Disabled 0 Disable Enabled 1 Disable Disabled 0 Disable Enabled 1 Disable Disabled 0 Disable Enabled 1 Disable RW OVRFLW Enable or disable event routing for event OVRFLW RW COMPARE[i] (i=0..3) Enable or disable event routing for event COMPARE[i] 6.20.10.11 EVTENSET Address offset: 0x344 Enable event routing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID Access Field A RW TICK B Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Write '1' to enable event routing for event TICK RW OVRFLW 4452_021 v1.5 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to enable event routing for event OVRFLW 359 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID Access Field C-F RW COMPARE[i] (i=0..3) B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Write '1' to enable event routing for event COMPARE[i] 6.20.10.12 EVTENCLR Address offset: 0x348 Disable event routing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID Access Field A RW TICK B C-F B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable event routing for event TICK Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable RW OVRFLW Write '1' to disable event routing for event OVRFLW Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable RW COMPARE[i] (i=0..3) Write '1' to disable event routing for event COMPARE[i] Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable 6.20.10.13 COUNTER Address offset: 0x504 Current COUNTER value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description COUNTER Counter value 6.20.10.14 PRESCALER Address offset: 0x508 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PRESCALER 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Prescaler value 360 Peripherals 6.20.10.15 CC[n] (n=0..3) Address offset: 0x540 + (n × 0x4) Compare register n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW COMPARE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Compare value 6.20.11 Electrical specification 6.21 SAADC — Successive approximation analog-todigital converter The SAADC is a differential successive approximation register (SAR) analog-to-digital converter. It supports up to eight external analog input channels, depending on package variant. The following lists the main features of the SAADC: • Multiple input channels • Each channel can use pins AIN0 through AIN7, the VDD pin, or the VDDH pin as input • Eight channels for single-ended inputs and four channels for differential inputs • Full scale input range • Individual reference selection for each channel • • • • • VDD • Internal reference Continuous sampling Output samples are automatically written to RAM using EasyDMA Samples are stored as 16-bit 2's complement values 8/10/12-bit resolution, 14-bit resolution with oversampling 4452_021 v1.5 361 Peripherals PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].CONFIG PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].PSELP NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD VDDHDIV5 NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD VDDHDIV5 SAADC RAM MUX RESULT P RESP RESULT SAR core GAIN RESULT EasyDMA RESULT RESULT RESULT N RESN RESULT RESULT MUX RESULT.PTR START SAMPLE VDD Internal reference REFSEL STARTED END STOPPED STOP CH[X].PSELN PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A Figure 134: Block diagram An input channel is enabled and connected to an analog input pin using the registers CH[n].PSELP (n=0..7) on page 378 and CH[n].PSELN (n=0..7) on page 378. Before any sampling can take place, the length and the location of the memory buffer in RAM where output values shall be written need to be configured, and the START task has to be triggered to apply the configuration. See EasyDMA on page 364 for details on memory configuration and how the results are placed in memory. Sampling of all enabled channels is started by triggering the SAMPLE task, and the sample results are automatically written to memory using EasyDMA. When multiple channels are enabled, they are sampled successively in a sequence starting with the lowest channel number. The time it takes to sample all enabled channels is given as follows: Total time < Sum(CH[x].tACQ+tCONV), x is the number of enabled channels A DONE event is generated for every single completed conversion, and an END event is generated when multiple samples, as specified in RESULT.MAXCNT on page 381, have been written to memory. 6.21.1 Input configuration Each SAADC channel can be configured to use either single-ended or differential input mode. The configuration is done using the registers CH[n].CONFIG (n=0..7) on page 379. In single-ended mode, the negative channel input is shorted to ground internally and the setting in the corresponding register CH[n].PSELN (n=0..7) on page 378 will not apply. The assumption in single-ended mode is that the internal ground of the SAADC is the same as the external ground that the measured voltage is referred to. The SAADC is thus sensitive to ground bounce on the PCB in single-ended mode. If this is a concern, using differential measurement is recommended. In differential mode, both positive and negative input has to be configured in registersCH[n].PSELP (n=0..7) on page 378 and CH[n].PSELN (n=0..7) on page 378 respectively. 6.21.1.1 Acquisition time To sample input voltage, the SAADC connects a capacitor to the input. This is illustrated in the following figure: 4452_021 v1.5 362 Peripherals SAADC Rsource TACQ Figure 135: Simplified SAADC sample network The acquisition time indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required acquisition time depends on the source resistance (Rsource). For high source resistance the acquisition time should be increased: TACQ [µs] Maximum source resistance [kΩ] 3 10 5 40 10 100 15 200 20 400 40 800 Table 94: Acquisition time When using VDDHDIV5 as input, the acquisition time needs to be 10 µs or higher. 6.21.1.2 Internal resistor string (resistor ladder) The SAADC has an internal resistor string for positive and negative input. The resistors are controlled in registers CH[n].CONFIG.RESP and CH[n].CONFIG.RESN. The following figure illustrates the resistor ladder for positive (and negative) input: RESP = Pullup R Output Input R RESP = Pulldown Figure 136: Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP) 4452_021 v1.5 363 Peripherals 6.21.2 Reference voltage and gain settings Each SAADC channel can have individual reference and gain settings. This is configured in registers CH[n].CONFIG (n=0..7) on page 379. Available configuration options are: • VDD/4 or internal 0.6 V reference • Gain ranging from 1/6 to 4 The gain setting can be used to control the effective input range of the SAADC: Input range = (±0.6 V or ±VDD/4)/gain For example, selecting VDD as reference, single-ended input (grounded negative input), and a gain of 1/4 will result in the following input range: Input range = (VDD/4)/(1/4) = VDD With internal reference, single-ended input (grounded negative input) and a gain of 1/6, the input range will be: Input range = (0.6 V)/(1/6) = 3.6 V Inputs AIN0 through AIN7 cannot exceed VDD or be lower than VSS. 6.21.3 Digital output The digital output value from the SAADC is calculated using a formula. RESULT = (V(P) – V(N)) * (GAIN/REFERENCE) * 2(RESOLUTION - m) where V(P) is the voltage at input P V(N) is the voltage at input N GAIN is the selected gain REFERENCE is the selected reference voltage RESOLUTION is output resolution in bits, as configured in register RESOLUTION on page 380 m is 0 for single-ended channels is 1 for differential channels Results are sign extended to 16 bits and stored as little-endian byte order in RAM. 6.21.4 EasyDMA The SAADC resources are started by triggering the START task. The SAADC is using EasyDMA to store results in a result buffer in RAM. 4452_021 v1.5 364 Peripherals Registers RESULT.PTR on page 381 and RESULT.MAXCNT on page 381 must be configured before SAADC is started. The result buffer is located at the address specified in register RESULT.PTR on page 381. This register is double-buffered, and it can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the result buffer is specified in register RESULT.MAXCNT on page 381, and the SAADC will generate an END event when it has filled up the result buffer, as illustrated in the following figure: Data RAM Result 0 Result 1 Result 2 Result 3 0 RAM Sample and convert END 0x20000010 0x20000012 0x20000020 0x20000022 RAM SAMPLE SAMPLE RESULT.PTR = 0x20000020 START SAMPLE 3 SAMPLE RESULT.MAX CNT START RESULT.PTR = 0x20000000 2 RESULT.PTR = 0x20000010 Lifeline 1 Sample and convert RAM 0x20000002 END Sample and convert RAM STARTED Sample and convert STARTED SAADC 0 0x20000000 Figure 137: SAADC The following figure shows how results are placed in RAM when multiple channels are enabled, and value in RESULT.MAXCNT on page 381 is an even number: 31 16 15 0 RESULT.PTR CH[2] 1st result CH[1] 1st result RESULT.PTR + 4 CH[1] 2nd result CH[5] 1st result RESULT.PTR + 8 CH[5] 2nd result CH[2] 2nd result (…) RESULT.PTR + 2*RESULT.MAXCNT – 4 CH[5] last result CH[2] last result Figure 138: Example of RAM placement: RESULT.MAXCNT even number, channels 1, 2 and 5 enabled The following figure shows how results are placed in RAM when multiple channels are enabled and value in RESULT.MAXCNT on page 381 is an odd number: 31 16 15 0 RESULT.PTR CH[2] 1st result CH[1] 1st result RESULT.PTR + 4 CH[1] 2nd result CH[5] 1st result RESULT.PTR + 8 CH[5] 2nd result CH[2] 2nd result (…) CH[5] last result RESULT.PTR + 2*RESULT.MAXCNT – 2 Figure 139: Example of RAM placement: RESULT.MAXCNT odd number, channels 1, 2 and 5 enabled The last 32-bit word is populated only with one 16-bit result. In both examples, channels 1, 2 and 5 are enabled, and all others are disabled. See Memory on page 19 for more information about the different memory regions. 4452_021 v1.5 365 Peripherals EasyDMA is finished with accessing RAM when events END or STOPPED are generated. The register RESULT.AMOUNT on page 382 can then be read, to see how many results have been transferred to the result buffer in RAM since the START task was triggered. 6.21.5 Continuous sampling When using continuous sampling, new samples are automatically taken at a fixed sample rate. Continuous sampling of both single and multiple channels can be implemented using a general purpose timer connecting a timer event to SAADC's SAMPLE task via PPI. Alternatively, continuous sampling can be implemented by using the internal timer in the SAADC by setting the MODE field in register SAMPLERATE on page 381 to Timers. The sample rate (frequency at which the SAMPLE task is triggered) is configured in the same register. The internal timer and the continuous sampling are started by triggering the START task and stopped using the STOP task. Note: Note that the internal timer can only be used when a single input channel is enabled. For continuous sampling, ensure that the sample rate fullfills the following criteria: fSAMPLE < 1/[tACQ + tconv] 6.21.6 Oversampling An accumulator in the SAADC can be used to find the average of several analog input samples. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling does not improve the integral nonlinearity (INL) or differential non-linearity (DNL). The accumulator is controlled in the OVERSAMPLE register. When using oversampling, 2OVERSAMPLE input samples are averaged before the sample result is transferred to memory. Hence, the SAMPLE task must be triggered 2OVERSAMPLE times for each output value. The following events are relevant: • DONE event is generated for every input sample taken • RESULTDONE event is generated for every averaged value ready to be transferred into RAM • END event is generated when averaged values defined in RESULT.MAXCNT on page 381 have been written to memory. END event is generated every 2OVERSAMPLE time the DONE event is generated. If value in OVERSAMPLE is set to 0, the DONE and RESULTDONE events will be generated at the same rate. Note: Oversampling should only be used when a single input channel is enabled, as averaging is performed over all enabled channels. 6.21.7 Event monitoring using limits A channel can be event monitored by using limits. Limits are configured in CH[n].LIMIT register, with high limit and low limit. Note: High limit shall always be higher than or equal to low limit. Appropriate events are generated whenever the conversion results (sampled input signals) are outside of the two defined limits. It is not possible to generate an event when the input signal is inside a defined range by swapping high and low limits. An example of event montitoring using limits is illustrated in the following figure: 4452_021 v1.5 366 Peripherals VIN CH[n].LIMIT.HIGH CH[n].LIMIT.LOW t EVENTS_CH[n].LIMITL EVENTS_CH[n].LIMITH EVENTS_CH[n].LIMITH EVENTS_CH[n].LIMITH events Figure 140: Example: Event monitoring on channel n using limits The comparison to limits always takes place, it does not need to be specifically enabled. If comparison is not required on a channel, the software ignores the related events. In that situation, the value of the limits defined in register is irrelevant, i.e. it does not matter if the low limit is lower than the high limit or not. 6.21.8 Calibration The SAADC has a temperature dependent offset. Therefore, it is recommended to calibrate the SAADC at least once before use, and to re-run calibration every time the ambient temperature has changed by more than 10 °C. Offset calibration is started by triggering the CALIBRATEOFFSET task, and the CALIBRATEDONE event is generated when calibration is done. 6.21.9 Registers Base address Peripheral Instance Description Configuration 0x40007000 SAADC SAADC Analog to digital converter Table 95: Instances Register Offset Description TASKS_START 0x000 Starts the SAADC and prepares the result buffer in RAM TASKS_SAMPLE 0x004 Takes one SAADC sample TASKS_STOP 0x008 Stops the SAADC and terminates all on-going conversions TASKS_CALIBRATEOFFSET 0x00C Starts offset auto-calibration EVENTS_STARTED 0x100 The SAADC has started EVENTS_END 0x104 The SAADC has filled up the result buffer EVENTS_DONE 0x108 A conversion task has been completed. Depending on the configuration, multiple conversions EVENTS_RESULTDONE 0x10C might be needed for a result to be transferred to RAM. 4452_021 v1.5 Result ready for transfer to RAM 367 Peripherals Register Offset Description EVENTS_CALIBRATEDONE 0x110 Calibration is complete EVENTS_STOPPED 0x114 The SAADC has stopped EVENTS_CH[0].LIMITH 0x118 Last result is equal or above CH[0].LIMIT.HIGH EVENTS_CH[0].LIMITL 0x11C Last result is equal or below CH[0].LIMIT.LOW EVENTS_CH[1].LIMITH 0x120 Last result is equal or above CH[1].LIMIT.HIGH EVENTS_CH[1].LIMITL 0x124 Last result is equal or below CH[1].LIMIT.LOW EVENTS_CH[2].LIMITH 0x128 Last result is equal or above CH[2].LIMIT.HIGH EVENTS_CH[2].LIMITL 0x12C Last result is equal or below CH[2].LIMIT.LOW EVENTS_CH[3].LIMITH 0x130 Last result is equal or above CH[3].LIMIT.HIGH EVENTS_CH[3].LIMITL 0x134 Last result is equal or below CH[3].LIMIT.LOW EVENTS_CH[4].LIMITH 0x138 Last result is equal or above CH[4].LIMIT.HIGH EVENTS_CH[4].LIMITL 0x13C Last result is equal or below CH[4].LIMIT.LOW EVENTS_CH[5].LIMITH 0x140 Last result is equal or above CH[5].LIMIT.HIGH EVENTS_CH[5].LIMITL 0x144 Last result is equal or below CH[5].LIMIT.LOW EVENTS_CH[6].LIMITH 0x148 Last result is equal or above CH[6].LIMIT.HIGH EVENTS_CH[6].LIMITL 0x14C Last result is equal or below CH[6].LIMIT.LOW EVENTS_CH[7].LIMITH 0x150 Last result is equal or above CH[7].LIMIT.HIGH EVENTS_CH[7].LIMITL 0x154 Last result is equal or below CH[7].LIMIT.LOW INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt STATUS 0x400 Status ENABLE 0x500 Enable or disable SAADC CH[0].PSELP 0x510 Input positive pin selection for CH[0] CH[0].PSELN 0x514 Input negative pin selection for CH[0] CH[0].CONFIG 0x518 Input configuration for CH[0] CH[0].LIMIT 0x51C High/low limits for event monitoring of a channel CH[1].PSELP 0x520 Input positive pin selection for CH[1] CH[1].PSELN 0x524 Input negative pin selection for CH[1] CH[1].CONFIG 0x528 Input configuration for CH[1] CH[1].LIMIT 0x52C High/low limits for event monitoring of a channel CH[2].PSELP 0x530 Input positive pin selection for CH[2] CH[2].PSELN 0x534 Input negative pin selection for CH[2] CH[2].CONFIG 0x538 Input configuration for CH[2] CH[2].LIMIT 0x53C High/low limits for event monitoring of a channel CH[3].PSELP 0x540 Input positive pin selection for CH[3] CH[3].PSELN 0x544 Input negative pin selection for CH[3] CH[3].CONFIG 0x548 Input configuration for CH[3] CH[3].LIMIT 0x54C High/low limits for event monitoring of a channel CH[4].PSELP 0x550 Input positive pin selection for CH[4] CH[4].PSELN 0x554 Input negative pin selection for CH[4] CH[4].CONFIG 0x558 Input configuration for CH[4] CH[4].LIMIT 0x55C High/low limits for event monitoring of a channel CH[5].PSELP 0x560 Input positive pin selection for CH[5] CH[5].PSELN 0x564 Input negative pin selection for CH[5] CH[5].CONFIG 0x568 Input configuration for CH[5] CH[5].LIMIT 0x56C High/low limits for event monitoring of a channel CH[6].PSELP 0x570 Input positive pin selection for CH[6] CH[6].PSELN 0x574 Input negative pin selection for CH[6] CH[6].CONFIG 0x578 Input configuration for CH[6] CH[6].LIMIT 0x57C High/low limits for event monitoring of a channel CH[7].PSELP 0x580 Input positive pin selection for CH[7] CH[7].PSELN 0x584 Input negative pin selection for CH[7] 4452_021 v1.5 368 Peripherals Register Offset Description CH[7].CONFIG 0x588 Input configuration for CH[7] CH[7].LIMIT 0x58C High/low limits for event monitoring of a channel RESOLUTION 0x5F0 Resolution configuration OVERSAMPLE 0x5F4 Oversampling configuration. The RESOLUTION is applied before averaging, thus for high SAMPLERATE 0x5F8 Controls normal or continuous sample rate RESULT.PTR 0x62C Data pointer RESULT.MAXCNT 0x630 Maximum number of 16-bit samples to be written to output RAM buffer RESULT.AMOUNT 0x634 Number of 16-bit samples written to output RAM buffer since the previous START task OVERSAMPLE a higher RESOLUTION should be used. Table 96: Register overview 6.21.9.1 TASKS_START Address offset: 0x000 Starts the SAADC and prepares the result buffer in RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_START Starts the SAADC and prepares the result buffer in RAM Trigger task 6.21.9.2 TASKS_SAMPLE Address offset: 0x004 Takes one SAADC sample Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_SAMPLE Takes one SAADC sample Trigger task 6.21.9.3 TASKS_STOP Address offset: 0x008 Stops the SAADC and terminates all on-going conversions Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stops the SAADC and terminates all on-going conversions Trigger task 6.21.9.4 TASKS_CALIBRATEOFFSET Address offset: 0x00C 4452_021 v1.5 369 Peripherals Starts offset auto-calibration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_CALIBRATEOFFSET Starts offset auto-calibration Trigger 1 Trigger task 6.21.9.5 EVENTS_STARTED Address offset: 0x100 The SAADC has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The SAADC has started 6.21.9.6 EVENTS_END Address offset: 0x104 The SAADC has filled up the result buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_END 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The SAADC has filled up the result buffer 6.21.9.7 EVENTS_DONE Address offset: 0x108 A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 4452_021 v1.5 NotGenerated 0 Event not generated Generated 1 Event generated 370 Peripherals 6.21.9.8 EVENTS_RESULTDONE Address offset: 0x10C Result ready for transfer to RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RESULTDONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Result ready for transfer to RAM 6.21.9.9 EVENTS_CALIBRATEDONE Address offset: 0x110 Calibration is complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID A RW EVENTS_CALIBRATEDONE Value Description Calibration is complete NotGenerated 0 Event not generated Generated 1 Event generated 6.21.9.10 EVENTS_STOPPED Address offset: 0x114 The SAADC has stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The SAADC has stopped 6.21.9.11 EVENTS_CH[n].LIMITH (n=0..7) Address offset: 0x118 + (n × 0x8) Last result is equal or above CH[n].LIMIT.HIGH 4452_021 v1.5 371 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW LIMITH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Last result is equal or above CH[n].LIMIT.HIGH 6.21.9.12 EVENTS_CH[n].LIMITL (n=0..7) Address offset: 0x11C + (n × 0x8) Last result is equal or below CH[n].LIMIT.LOW Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW LIMITL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Last result is equal or below CH[n].LIMIT.LOW 6.21.9.13 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID Access Field A RW STARTED B C D E F G H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event STARTED RW END Enable or disable interrupt for event END RW DONE Enable or disable interrupt for event DONE RW RESULTDONE Enable or disable interrupt for event RESULTDONE Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE RW STOPPED Enable or disable interrupt for event STOPPED RW CH0LIMITH Enable or disable interrupt for event CH0LIMITH RW CH0LIMITL Enable or disable interrupt for event CH0LIMITL Disabled 4452_021 v1.5 0 Disable 372 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID I J K L M N O P Q R S T U V Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Enable RW CH1LIMITH Enable or disable interrupt for event CH1LIMITH Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW CH1LIMITL Enable or disable interrupt for event CH1LIMITL RW CH2LIMITH Enable or disable interrupt for event CH2LIMITH RW CH2LIMITL Enable or disable interrupt for event CH2LIMITL RW CH3LIMITH Enable or disable interrupt for event CH3LIMITH Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW CH3LIMITL Enable or disable interrupt for event CH3LIMITL RW CH4LIMITH Enable or disable interrupt for event CH4LIMITH RW CH4LIMITL Enable or disable interrupt for event CH4LIMITL RW CH5LIMITH Enable or disable interrupt for event CH5LIMITH Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW CH5LIMITL Enable or disable interrupt for event CH5LIMITL RW CH6LIMITH Enable or disable interrupt for event CH6LIMITH RW CH6LIMITL Enable or disable interrupt for event CH6LIMITL RW CH7LIMITH Enable or disable interrupt for event CH7LIMITH Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW CH7LIMITL Enable or disable interrupt for event CH7LIMITL 6.21.9.14 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.5 373 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID Access Field A RW STARTED B C D E F G H I J K L M 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Write '1' to enable interrupt for event STARTED RW END Write '1' to enable interrupt for event END RW DONE Write '1' to enable interrupt for event DONE RW RESULTDONE Write '1' to enable interrupt for event RESULTDONE RW CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE RW STOPPED Write '1' to enable interrupt for event STOPPED RW CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH RW CH0LIMITL Write '1' to enable interrupt for event CH0LIMITL RW CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH RW CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL RW CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH RW CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL RW CH3LIMITH 4452_021 v1.5 Write '1' to enable interrupt for event CH3LIMITH Enable 374 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID N O P Q R S T U V Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL RW CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH RW CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL RW CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH RW CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL RW CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH RW CH6LIMITL Write '1' to enable interrupt for event CH6LIMITL RW CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH RW CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL 6.21.9.15 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID Access Field A RW STARTED 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STARTED 375 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID B C D E F G H I J K L M Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled RW END Write '1' to disable interrupt for event END RW DONE Write '1' to disable interrupt for event DONE RW RESULTDONE Write '1' to disable interrupt for event RESULTDONE RW CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE RW STOPPED Write '1' to disable interrupt for event STOPPED RW CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH RW CH0LIMITL Write '1' to disable interrupt for event CH0LIMITL RW CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH RW CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL RW CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH RW CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL RW CH3LIMITH 4452_021 v1.5 Write '1' to disable interrupt for event CH3LIMITH 376 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID N O P Q R S T U V Access Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Read: Enabled RW CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH6LIMITL Write '1' to disable interrupt for event CH6LIMITL Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH7LIMITH Write '1' to disable interrupt for event CH7LIMITH Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.21.9.16 STATUS Address offset: 0x400 Status 4452_021 v1.5 377 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Ready 0 SAADC is ready. No on-going conversions. Busy 1 SAADC is busy. Conversion in progress. STATUS Status 6.21.9.17 ENABLE Address offset: 0x500 Enable or disable SAADC Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable SAADC Enabled 1 Enable SAADC Enable or disable SAADC When enabled, the SAADC will acquire access to analog input pins specified in registers CH[n].PSELP and CH[n].PSELN 6.21.9.18 CH[n].PSELP (n=0..7) Address offset: 0x510 + (n × 0x10) Input positive pin selection for CH[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A Reset 0x00000000 ID Access Field A RW PSELP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NC 0 Not connected AnalogInput0 1 AIN0 AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDD 9 VDD VDDHDIV5 0x0D VDDH/5 Analog positive input channel 6.21.9.19 CH[n].PSELN (n=0..7) Address offset: 0x514 + (n × 0x10) Input negative pin selection for CH[n] 4452_021 v1.5 378 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A Reset 0x00000000 ID Access Field A RW PSELN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NC 0 Not connected AnalogInput0 1 AIN0 AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDD 9 VDD VDDHDIV5 0x0D VDDH/5 Analog negative input, enables differential channel 6.21.9.20 CH[n].CONFIG (n=0..7) Address offset: 0x518 + (n × 0x10) Input configuration for CH[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G Reset 0x00020000 ID Access Field A RW RESP B C D E F D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Positive channel resistor control Bypass 0 Bypass resistor ladder Pulldown 1 Pull-down to GND Pullup 2 Pull-up to VDD VDD1_2 3 Set input at VDD/2 Bypass 0 Bypass resistor ladder Pulldown 1 Pull-down to GND Pullup 2 Pull-up to VDD VDD1_2 3 Set input at VDD/2 Gain1_6 0 1/6 Gain1_5 1 1/5 Gain1_4 2 1/4 Gain1_3 3 1/3 Gain1_2 4 1/2 Gain1 5 1 Gain2 6 2 Gain4 7 4 Internal 0 Internal reference (0.6 V) VDD1_4 1 VDD/4 as reference RW RESN Negative channel resistor control RW GAIN Gain control RW REFSEL Reference control RW TACQ Acquisition time, the time the SAADC uses to sample the input voltage 4452_021 v1.5 E E E 3us 0 3 µs 5us 1 5 µs 10us 2 10 µs 379 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G Reset 0x00020000 ID F Access Field F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description 15us 3 15 µs 20us 4 20 µs 40us 5 40 µs SE 0 RW MODE Enable differential mode Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND G Diff 1 Differential Disabled 0 Burst mode is disabled (normal operation) Enabled 1 Burst mode is enabled. SAADC takes 2^OVERSAMPLE RW BURST Enable burst mode number of samples as fast as it can, and sends the average to Data RAM. 6.21.9.21 CH[n].LIMIT (n=0..7) Address offset: 0x51C + (n × 0x10) High/low limits for event monitoring of a channel Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A Reset 0x7FFF8000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A RW LOW [-32768 to +32767] Low level limit B RW HIGH [-32768 to +32767] High level limit 6.21.9.22 RESOLUTION Address offset: 0x5F0 Resolution configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000001 ID Access Field A RW VAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Set the resolution 8bit 0 8 bits 10bit 1 10 bits 12bit 2 12 bits 14bit 3 14 bits 6.21.9.23 OVERSAMPLE Address offset: 0x5F4 Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 4452_021 v1.5 380 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A RW OVERSAMPLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bypass 0 Bypass oversampling Over2x 1 Oversample 2x Over4x 2 Oversample 4x Over8x 3 Oversample 8x Over16x 4 Oversample 16x Over32x 5 Oversample 32x Over64x 6 Oversample 64x Over128x 7 Oversample 128x Over256x 8 Oversample 256x Oversample control 6.21.9.24 SAMPLERATE Address offset: 0x5F8 Controls normal or continuous sample rate Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID Access Field A RW CC B RW MODE A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [80..2047] Capture and compare value. Sample rate is 16 MHz/CC Select mode for sample rate control Task 0 Rate is controlled from SAMPLE task Timers 1 Rate is controlled from local timer (use CC to control the rate) 6.21.9.25 RESULT.PTR Address offset: 0x62C Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer Note: See Memory on page 19 for details about memories available to EasyDMA. 6.21.9.26 RESULT.MAXCNT Address offset: 0x630 Maximum number of 16-bit samples to be written to output RAM buffer 4452_021 v1.5 381 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Maximum number of 16-bit samples to be written to output RAM buffer 6.21.9.27 RESULT.AMOUNT Address offset: 0x634 Number of 16-bit samples written to output RAM buffer since the previous START task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AMOUNT Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. 6.21.10 Electrical specification 6.21.10.1 SAADC electrical specification Symbol Description Min. Typ. DNL10 Differential non-linearity, 10-bit resolution -0.95 = M+1 1 RXD.PTR = 0x20000000 M-1 RXSTARTED TWI CPU Lifeline 2 STOP ACK Stretch ACK 1 ACK 0 ACK ACK ACK WRITE START ADDR Figure 172: The TWI slave responding to a write command 6.30.4 Master repeated start sequence An example of a repeated start sequence is one in which the TWI master writes two bytes to the slave followed by reading four bytes from the slave. This is illustrated in the following figure. In this example, the receiver does not know what the master wants to read in advance. This information is in the first two received bytes of the write in the repeated start sequence. To guarantee that the CPU is able to process the received data before the TWI slave starts to reply to the read command, the SUSPEND task is triggered via a shortcut from the READ event generated when the read command is received. When the CPU has processed the incoming data and prepared the correct data response, the CPU will resume the transaction by triggering the RESUME task. STOPPED 3 RESUME TXD.MAXCNT = 4 PREPARETX SUSPEND TXD.PTR = 0x20000010 PREPARERX RXD.MAXCNT = 2 RXD.PTR = 0x20000000 TXSTARTED READ WRITE RXSTARTED TWI CPU Lifeline STOP 3 NACK 2 2 ACK 1 1 ACK 0 ACK ADDR ACK READ 1 RESTART ACK 0 ACK ACK WRITE START ADDR Figure 173: Repeated start sequence 6.30.5 Terminating an ongoing TWI transaction In some situations, e.g. if the external TWI master is not responding correctly, it may be required to terminate an ongoing transaction. This can be achieved by triggering the STOP task. In this situation, a STOPPED event will be generated when the TWI has stopped independent of whether or not a STOP condition has been generated on the TWI bus. The TWI slave will release the bus when it has stopped and go back to its IDLE state. 4452_021 v1.5 473 Peripherals 6.30.6 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register. 6.30.7 Slave mode pin configuration The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the configuration specified in the PSEL.SCL and PSEL.SDA registers respectively. The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. PSEL.SCL and PSEL.SDA must only be configured when the TWI slave is disabled. To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in the following table. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. TWI slave signal TWI slave pin Direction Output value Drive strength SCL As specified in PSEL.SCL Input Not applicable S0D1 SDA As specified in PSEL.SDA Input Not applicable S0D1 Table 125: GPIO configuration before enabling peripheral 6.30.8 Registers Base address Peripheral Instance Description 0x40003000 TWIS TWIS0 Two-wire interface slave 0 Configuration 0x40004000 TWIS TWIS1 Two-wire interface slave 1 Table 126: Instances Register Offset Description TASKS_STOP 0x014 Stop TWI transaction TASKS_SUSPEND 0x01C Suspend TWI transaction TASKS_RESUME 0x020 Resume TWI transaction TASKS_PREPARERX 0x030 Prepare the TWI slave to respond to a write command TASKS_PREPARETX 0x034 Prepare the TWI slave to respond to a read command EVENTS_STOPPED 0x104 TWI stopped EVENTS_ERROR 0x124 TWI error EVENTS_RXSTARTED 0x14C Receive sequence started EVENTS_TXSTARTED 0x150 Transmit sequence started EVENTS_WRITE 0x164 Write command received EVENTS_READ 0x168 Read command received SHORTS 0x200 Shortcuts between local events and tasks INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt 4452_021 v1.5 474 Peripherals Register Offset Description ERRORSRC 0x4D0 Error source MATCH 0x4D4 Status register indicating which address had a match ENABLE 0x500 Enable TWIS PSEL.SCL 0x508 Pin select for SCL signal PSEL.SDA 0x50C Pin select for SDA signal RXD.PTR 0x534 RXD Data pointer RXD.MAXCNT 0x538 Maximum number of bytes in RXD buffer RXD.AMOUNT 0x53C Number of bytes transferred in the last RXD transaction RXD.LIST 0x540 EasyDMA list type TXD.PTR 0x544 TXD Data pointer TXD.MAXCNT 0x548 Maximum number of bytes in TXD buffer TXD.AMOUNT 0x54C Number of bytes transferred in the last TXD transaction TXD.LIST 0x550 EasyDMA list type ADDRESS[0] 0x588 TWI slave address 0 ADDRESS[1] 0x58C TWI slave address 1 CONFIG 0x594 Configuration register for the address match mechanism ORC 0x5C0 Over-read character. Character sent out in case of an over-read of the transmit buffer. Table 127: Register overview 6.30.8.1 TASKS_STOP Address offset: 0x014 Stop TWI transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOP Stop TWI transaction Trigger task 6.30.8.2 TASKS_SUSPEND Address offset: 0x01C Suspend TWI transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_SUSPEND Suspend TWI transaction Trigger task 6.30.8.3 TASKS_RESUME Address offset: 0x020 Resume TWI transaction 4452_021 v1.5 475 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_RESUME Resume TWI transaction Trigger task 6.30.8.4 TASKS_PREPARERX Address offset: 0x030 Prepare the TWI slave to respond to a write command Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_PREPARERX Prepare the TWI slave to respond to a write command Trigger task 6.30.8.5 TASKS_PREPARETX Address offset: 0x034 Prepare the TWI slave to respond to a read command Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_PREPARETX Prepare the TWI slave to respond to a read command Trigger task 6.30.8.6 EVENTS_STOPPED Address offset: 0x104 TWI stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TWI stopped NotGenerated 0 Event not generated Generated 1 Event generated 6.30.8.7 EVENTS_ERROR Address offset: 0x124 TWI error 4452_021 v1.5 476 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated TWI error 6.30.8.8 EVENTS_RXSTARTED Address offset: 0x14C Receive sequence started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Receive sequence started 6.30.8.9 EVENTS_TXSTARTED Address offset: 0x150 Transmit sequence started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Transmit sequence started 6.30.8.10 EVENTS_WRITE Address offset: 0x164 Write command received Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_WRITE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Write command received 6.30.8.11 EVENTS_READ Address offset: 0x168 Read command received 4452_021 v1.5 477 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_READ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Read command received 6.30.8.12 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A RW WRITE_SUSPEND B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event WRITE and task SUSPEND RW READ_SUSPEND Shortcut between event READ and task SUSPEND 6.30.8.13 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G Reset 0x00000000 ID Access Field A RW STOPPED B E F G H Value ID Value B Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event STOPPED RW ERROR Enable or disable interrupt for event ERROR RW RXSTARTED Enable or disable interrupt for event RXSTARTED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW TXSTARTED Enable or disable interrupt for event TXSTARTED RW WRITE Enable or disable interrupt for event WRITE RW READ 4452_021 v1.5 F E A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable or disable interrupt for event READ 478 Peripherals 6.30.8.14 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G Reset 0x00000000 ID Access Field A RW STOPPED B E F G H F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event STOPPED RW ERROR Write '1' to enable interrupt for event ERROR RW RXSTARTED Write '1' to enable interrupt for event RXSTARTED RW TXSTARTED Write '1' to enable interrupt for event TXSTARTED RW WRITE Write '1' to enable interrupt for event WRITE RW READ Write '1' to enable interrupt for event READ 6.30.8.15 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G Reset 0x00000000 ID Access Field A RW STOPPED B E Value ID Value B Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Write '1' to disable interrupt for event STOPPED RW ERROR Write '1' to disable interrupt for event ERROR RW RXSTARTED 4452_021 v1.5 F E A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to disable interrupt for event RXSTARTED Disable 479 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G Reset 0x00000000 ID F G H Access Field F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TXSTARTED Write '1' to disable interrupt for event TXSTARTED RW WRITE Write '1' to disable interrupt for event WRITE RW READ Write '1' to disable interrupt for event READ 6.30.8.16 ERRORSRC Address offset: 0x4D0 Error source Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B Reset 0x00000000 ID Access Field A RW OVERFLOW B C A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotDetected 0 Error did not occur Detected 1 Error occurred NotReceived 0 Error did not occur Received 1 Error occurred RX buffer overflow detected, and prevented RW DNACK NACK sent after receiving a data byte RW OVERREAD TX buffer over-read detected, and prevented NotDetected 0 Error did not occur Detected 1 Error occurred 6.30.8.17 MATCH Address offset: 0x4D4 Status register indicating which address had a match Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A R MATCH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..1] Indication of which address in {ADDRESS} that matched the incoming address 6.30.8.18 ENABLE Address offset: 0x500 4452_021 v1.5 480 Peripherals Enable TWIS Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable TWIS Disabled 0 Disable TWIS Enabled 9 Enable TWIS 6.30.8.19 PSEL.SCL Address offset: 0x508 Pin select for SCL signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.30.8.20 PSEL.SDA Address offset: 0x50C Pin select for SDA signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID Access Field A B C RW CONNECT Value ID B A A A A A Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.30.8.21 RXD.PTR Address offset: 0x534 RXD Data pointer 4452_021 v1.5 481 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW PTR Value ID Value Description RXD Data pointer See the memory chapter for details about which memories are available for EasyDMA. 6.30.8.22 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in RXD buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..0xFFFF] Maximum number of bytes in RXD buffer 6.30.8.23 RXD.AMOUNT Address offset: 0x53C Number of bytes transferred in the last RXD transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID AMOUNT Value Description [0..0xFFFF] Number of bytes transferred in the last RXD transaction 6.30.8.24 RXD.LIST Address offset: 0x540 EasyDMA list type Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW LIST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable EasyDMA list ArrayList 1 Use array list List type 6.30.8.25 TXD.PTR Address offset: 0x544 TXD Data pointer 4452_021 v1.5 482 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW PTR Value ID Value Description TXD Data pointer See the memory chapter for details about which memories are available for EasyDMA. 6.30.8.26 TXD.MAXCNT Address offset: 0x548 Maximum number of bytes in TXD buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..0xFFFF] Maximum number of bytes in TXD buffer 6.30.8.27 TXD.AMOUNT Address offset: 0x54C Number of bytes transferred in the last TXD transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID AMOUNT Value Description [0..0xFFFF] Number of bytes transferred in the last TXD transaction 6.30.8.28 TXD.LIST Address offset: 0x550 EasyDMA list type Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID Access Field A RW LIST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable EasyDMA list ArrayList 1 Use array list List type 6.30.8.29 ADDRESS[n] (n=0..1) Address offset: 0x588 + (n × 0x4) TWI slave address n 4452_021 v1.5 483 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW ADDRESS Value ID Value Description TWI slave address 6.30.8.30 CONFIG Address offset: 0x594 Configuration register for the address match mechanism Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ID Access Field A-B RW ADDRESS[i] (i=0..1) Value ID Value Description Disabled 0 Disabled Enabled 1 Enabled Enable or disable address matching on ADDRESS[i] 6.30.8.31 ORC Address offset: 0x5C0 Over-read character. Character sent out in case of an over-read of the transmit buffer. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A RW ORC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Over-read character. Character sent out in case of an overread of the transmit buffer. 6.30.9 Electrical specification 6.30.9.1 TWIS slave timing specifications Symbol Description Min. fTWIS,SCL Bit rates for TWIS tTWIS,START Time from PREPARERX/PREPARETX task to ready to receive/ Typ. 100 37 1.5 Max. Units 400 kbps µs transmit tTWIS,SU_DAT Data setup time before positive edge on SCL – all modes 300 ns tTWIS,HD_DAT Data hold time after negative edge on SCL – all modes 500 ns tTWIS,HD_STA,100kbps TWI slave hold time from for START condition (SDA low to 5200 ns 1300 ns 5200 ns SCL low), 100 kbps tTWIS,HD_STA,400kbps TWI slave hold time from for START condition (SDA low to SCL low), 400 kbps tTWIS,SU_STO,100kbps TWI slave setup time from SCL high to STOP condition, 100 kbps 37 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4452_021 v1.5 484 Peripherals Symbol Description Min. tTWIS,SU_STO,400kbps TWI slave setup time from SCL high to STOP condition, 400 1300 Typ. Max. Units ns kbps tTWIS,BUF,100kbps TWI slave bus free time between STOP and START 4700 ns 1300 ns conditions, 100 kbps tTWIS,BUF,400kbps TWI slave bus free time between STOP and START conditions, 400 kbps Figure 174: TWIS timing diagram, 1 byte transaction 6.31 UART — Universal asynchronous receiver/ transmitter PSEL.RXD PSEL.CTS PSEL.RTS PSEL.TXD STARTTX STARTRX STOPRX RXD (signal) RXD-5 TXD RXD-4 RXD-3 TXD (signal) STOPTX RXD-2 RXD-1 RXTO RXD RXDRDY TXDRDY Figure 175: UART configuration 6.31.1 Functional description Listed here are the main features of UART. The UART implements support for the following features: • Full-duplex operation • Automatic flow control • Parity checking and generation for the 9th data bit As illustrated in UART configuration on page 485, the UART uses the TXD and RXD registers directly to transmit and receive data. The UART uses one stop bit. Note: The external crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication. See CLOCK — Clock control on page 82 for more information. 4452_021 v1.5 485 Peripherals 6.31.2 Pin configuration The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD associated with the UART are mapped to physical pins according to the configuration specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated UART signal will not be connected to any physical pin. The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used as long as the UART is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD must only be configured when the UART is disabled. To secure correct signal levels on the pins by the UART when the system is in OFF mode, the pins must be configured in the GPIO peripheral as described in Pin configuration on page 486. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. UART pin Direction Output value RXD Input Not applicable CTS Input Not applicable RTS Output 1 TXD Output 1 Table 128: GPIO configuration 6.31.3 Shared resources The UART shares registers and resources with other peripherals that have the same ID as the UART. All peripherals with the same ID as the UART must be disabled before configuring and using the UART. Disabling a peripheral that has the same ID as the UART will not reset any of the registers that are shared with the UART. It is therefore important to configure all relevant UART registers explicitly to ensure that it operates correctly. See Instantiation on page 22 for details on peripherals and their IDs. 6.31.4 Transmission A UART transmission sequence is started by triggering the STARTTX task. Bytes are transmitted by writing to the TXD register. When a byte has been successfully transmitted, the UART will generate a TXDRDY event after which a new byte can be written to the TXD register. A UART transmission sequence is stopped immediately by triggering the STOPTX task. If flow control is enabled, a transmission will be automatically suspended when CTS is deactivated, and resumed when CTS is activated again, as shown in the following figure. A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is suspended. For more information, see Suspending the UART on page 488. 4452_021 v1.5 486 5 6 STOPTX TXD = 2 5 TXD = N 3 N TXDRDY N-1 TXDRDY N-2 TXD = N-1 2 TXD = 1 TXD = 0 STARTTX Lifeline 1 2 TXDRDY 1 TXDRDY 0 TXDRDY TXD CTS Peripherals Figure 176: UART transmission 6.31.5 Reception A UART reception sequence is started by triggering the STARTRX task. The UART receiver chain implements a FIFO capable of storing six incoming RXD bytes before data is overwritten. Bytes are extracted from this FIFO by reading the RXD register. When a byte is extracted from the FIFO, a new byte pending in the FIFO will be moved to the RXD register. The UART will generate an RXDRDY event every time a new byte is moved to the RXD register. When flow control is enabled, the UART will deactivate the RTS signal when there is only space for four more bytes in the receiver FIFO. The counterpart transmitter is therefore able to send up to four bytes after the RTS signal is deactivated before data is being overwritten. To prevent overwriting data in the FIFO, the counterpart UART transmitter must therefore make sure to stop transmitting data within four bytes after the RTS line is deactivated. The RTS signal will first be activated again when the FIFO has been emptied, that is, when all bytes in the FIFO have been read by the CPU, see UART reception on page 488. The RTS signal will also be deactivated when the receiver is stopped through the STOPRX task as illustrated in UART reception on page 488. The UART is able to receive four to five additional bytes if they are sent in succession immediately after the RTS signal has been deactivated. This is possible because the UART is, even after the STOPRX task is triggered, able to receive bytes for an extended period of time dependent on the configured baud rate. The UART will generate a receiver timeout event (RXTO) when this period has elapsed. To prevent loss of incoming data, the RXD register must only be read one time following every RXDRDY event. To secure that the CPU can detect all incoming RXDRDY events through the RXDRDY event register, the RXDRDY event register must be cleared before the RXD register is read. The reason for this is that the UART is allowed to write a new byte to the RXD register, and can generate a new event immediately after the RXD register is read (emptied) by the CPU. 4452_021 v1.5 487 RXTO RXDRDY 7 M = RXD RXDRDY 6 STOPRX M-2 = RXD F = RXD E = RXD D = RXD A = RXD 5 M M-1 = RXD RXDRDY M-1 2 3 4 5 6 7 B = RXD 1 STARTRX Lifeline M-2 RXDRDY F RXDRDY RXDRDY C RXDRDY RXDRDY B RXDRDY A C = RXD RXD RTS Peripherals Figure 177: UART reception As indicated in occurrence 2 in the figure, the RXDRDY event associated with byte B is generated first after byte A has been extracted from RXD. 6.31.6 Suspending the UART The UART can be suspended by triggering the SUSPEND task. SUSPEND will affect both the UART receiver and the UART transmitter, i.e. the transmitter will stop transmitting and the receiver will stop receiving. UART transmission and reception can be resumed, after being suspended, by triggering STARTTX and STARTRX respectively. Following a SUSPEND task, an ongoing TXD byte transmission will be completed before the UART is suspended. When the SUSPEND task is triggered, the UART receiver will behave in the same way as it does when the STOPRX task is triggered. 6.31.7 Error conditions An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. Effectively, a framing error is always generated before a break condition occurs. 6.31.8 Using the UART without flow control If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time. 6.31.9 Parity and stop bit configuration Automatic even parity generation for both transmission and reception can be configured using the register CONFIG on page 497. If odd parity is desired, it can be configured using the register CONFIG on page 497. See the register description for details. The amount of stop bits can also be configured through the register CONFIG on page 497. 6.31.10 Registers Base address Peripheral Instance Description 0x40002000 UART UART0 Universal asynchronous receiver/ Configuration transmitter Table 129: Instances 4452_021 v1.5 488 Deprecated Peripherals Register Offset Description TASKS_STARTRX 0x000 Start UART receiver TASKS_STOPRX 0x004 Stop UART receiver TASKS_STARTTX 0x008 Start UART transmitter TASKS_STOPTX 0x00C Stop UART transmitter TASKS_SUSPEND 0x01C Suspend UART EVENTS_CTS 0x100 CTS is activated (set low). Clear To Send. EVENTS_NCTS 0x104 CTS is deactivated (set high). Not Clear To Send. EVENTS_RXDRDY 0x108 Data received in RXD EVENTS_TXDRDY 0x11C Data sent from TXD EVENTS_ERROR 0x124 Error detected EVENTS_RXTO 0x144 Receiver timeout SHORTS 0x200 Shortcuts between local events and tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ERRORSRC 0x480 Error source ENABLE 0x500 Enable UART PSEL.RTS 0x508 Pin select for RTS PSEL.TXD 0x50C Pin select for TXD PSEL.CTS 0x510 Pin select for CTS PSEL.RXD 0x514 Pin select for RXD RXD 0x518 RXD register TXD 0x51C TXD register BAUDRATE 0x524 Baud rate. Accuracy depends on the HFCLK source selected. CONFIG 0x56C Configuration of parity and hardware flow control Table 130: Register overview 6.31.10.1 TASKS_STARTRX Address offset: 0x000 Start UART receiver Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STARTRX Start UART receiver Trigger task 6.31.10.2 TASKS_STOPRX Address offset: 0x004 Stop UART receiver Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STOPRX Stop UART receiver Trigger 4452_021 v1.5 1 Trigger task 489 Peripherals 6.31.10.3 TASKS_STARTTX Address offset: 0x008 Start UART transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STARTTX Start UART transmitter Trigger task 6.31.10.4 TASKS_STOPTX Address offset: 0x00C Stop UART transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOPTX Stop UART transmitter Trigger task 6.31.10.5 TASKS_SUSPEND Address offset: 0x01C Suspend UART Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_SUSPEND Suspend UART Trigger 1 Trigger task 6.31.10.6 EVENTS_CTS Address offset: 0x100 CTS is activated (set low). Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CTS 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CTS is activated (set low). Clear To Send. 490 Peripherals 6.31.10.7 EVENTS_NCTS Address offset: 0x104 CTS is deactivated (set high). Not Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_NCTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CTS is deactivated (set high). Not Clear To Send. 6.31.10.8 EVENTS_RXDRDY Address offset: 0x108 Data received in RXD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXDRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Data received in RXD 6.31.10.9 EVENTS_TXDRDY Address offset: 0x11C Data sent from TXD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXDRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Data sent from TXD 6.31.10.10 EVENTS_ERROR Address offset: 0x124 Error detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ERROR 4452_021 v1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Error detected 491 Peripherals 6.31.10.11 EVENTS_RXTO Address offset: 0x144 Receiver timeout Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Receiver timeout 6.31.10.12 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID Access Field A RW CTS_STARTRX B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event CTS and task STARTRX RW NCTS_STOPRX Shortcut between event NCTS and task STOPRX 6.31.10.13 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID Access Field A RW CTS B C D D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Write '1' to enable interrupt for event CTS RW NCTS Write '1' to enable interrupt for event NCTS RW RXDRDY Write '1' to enable interrupt for event RXDRDY RW TXDRDY 4452_021 v1.5 E Write '1' to enable interrupt for event TXDRDY Enable 492 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID E F Access Field E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ERROR Write '1' to enable interrupt for event ERROR RW RXTO Write '1' to enable interrupt for event RXTO 6.31.10.14 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID Access Field A RW CTS B C D E F Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event CTS RW NCTS Write '1' to disable interrupt for event NCTS RW RXDRDY Write '1' to disable interrupt for event RXDRDY RW TXDRDY Write '1' to disable interrupt for event TXDRDY RW ERROR Write '1' to disable interrupt for event ERROR RW RXTO Write '1' to disable interrupt for event RXTO 6.31.10.15 ERRORSRC Address offset: 0x480 Error source 4452_021 v1.5 E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 493 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW OVERRUN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Overrun error A start bit is received while the previous data still lies in RXD. (Previous data is lost.) B NotPresent 0 Read: error not present Present 1 Read: error present RW PARITY Parity error A character with bad parity is received, if HW parity check is enabled. C NotPresent 0 Read: error not present Present 1 Read: error present RW FRAMING Framing error occurred A valid stop bit is not detected on the serial data input after all bits in a character have been received. D NotPresent 0 Read: error not present Present 1 Read: error present RW BREAK Break condition The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). NotPresent 0 Read: error not present Present 1 Read: error present 6.31.10.16 ENABLE Address offset: 0x500 Enable UART Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable UART Enabled 4 Enable UART Enable or disable UART 6.31.10.17 PSEL.RTS Address offset: 0x508 Pin select for RTS 4452_021 v1.5 494 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.31.10.18 PSEL.TXD Address offset: 0x50C Pin select for TXD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID Access Field A B C RW CONNECT B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.31.10.19 PSEL.CTS Address offset: 0x510 Pin select for CTS Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.31.10.20 PSEL.RXD Address offset: 0x514 Pin select for RXD 4452_021 v1.5 495 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.31.10.21 RXD Address offset: 0x518 RXD register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RXD RX data received in previous transfers, double buffered 6.31.10.22 TXD Address offset: 0x51C TXD register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TXD TX data to be transferred 6.31.10.23 BAUDRATE Address offset: 0x524 Baud rate. Accuracy depends on the HFCLK source selected. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 ID Access Field A RW BAUDRATE 4452_021 v1.5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Baud1200 0x0004F000 1200 baud (actual rate: 1205) Baud2400 0x0009D000 2400 baud (actual rate: 2396) Baud4800 0x0013B000 4800 baud (actual rate: 4808) Baud9600 0x00275000 9600 baud (actual rate: 9598) Baud14400 0x003B0000 14400 baud (actual rate: 14414) Baud19200 0x004EA000 19200 baud (actual rate: 19208) Baud28800 0x0075F000 28800 baud (actual rate: 28829) Baud31250 0x00800000 31250 baud Baud38400 0x009D5000 38400 baud (actual rate: 38462) Baud56000 0x00E50000 56000 baud (actual rate: 55944) Baud rate 496 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description Baud57600 0x00EBF000 57600 baud (actual rate: 57762) Baud76800 0x013A9000 76800 baud (actual rate: 76923) Baud115200 0x01D7E000 115200 baud (actual rate: 115942) Baud230400 0x03AFB000 230400 baud (actual rate: 231884) Baud250000 0x04000000 250000 baud Baud460800 0x075F7000 460800 baud (actual rate: 470588) Baud921600 0x0EBED000 921600 baud (actual rate: 941176) Baud1M 0x10000000 1Mega baud 6.31.10.24 CONFIG Address offset: 0x56C Configuration of parity and hardware flow control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D Reset 0x00000000 ID Access Field A RW HWFC B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Hardware flow control Disabled 0 Disabled Enabled 1 Enabled Excluded 0x0 Exclude parity bit Included 0x7 Include parity bit One 0 One stop bit Two 1 Two stop bits Even 0 Even parity Odd 1 Odd parity RW PARITY C Parity RW STOP D C B B B A Stop bits RW PARITYTYPE Even or odd parity type 6.31.11 Electrical specification 6.31.11.1 UART electrical specification Symbol Description Min. fUART Baud rate for UART . tUART,CTSH CTS high time tUART,START Time from STARTRX/STARTTX task to transmission started 38 Typ. 38 Max. Units 1000 kbps 1 µs 1 High baud rates may require GPIOs to be set as High Drive, see GPIO for more details. 4452_021 v1.5 497 µs Peripherals 6.32 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to 1 Mbps, and EasyDMA data transfer from/to RAM. Listed here are the main features for UARTE: • • • • • • • • Full-duplex operation Automatic hardware flow control Optional even parity bit checking and generation EasyDMA Up to 1 Mbps baudrate Return to IDLE between transactions supported (when using HW flow control) One or two stop bit Least significant bit (LSB) first PSELRXD STARTRX PSELCTS RXD (signal) STOPRX PSELRTS RXD.PTR TXD.PTR PSELTXD TXD (signal) STARTTX STOPTX SUSPEND RESUME RX FIFO RXTO ENDTX EasyDMA EasyDMA ENDRX CTS NCTS RAM RXD TXD RXD+1 TXD+1 RXD+2 TXD+2 RXD+n TXD+n Figure 178: UARTE configuration The GPIOs used for each UART interface can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing. Note: The external crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication. See CLOCK — Clock control on page 82 for more information. 6.32.1 EasyDMA The UARTE implements EasyDMA for reading and writing to and from the RAM. If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/ TX transmission immediately after having received the RXSTARTED/TXSTARTED event. The ENDRX and ENDTX events indicate that the EasyDMA is finished accessing the RX or TX buffer in RAM. 4452_021 v1.5 498 Peripherals 6.32.2 Transmission The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task. After each byte has been sent over the TXD line, a TXDRDY event will be generated. When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the UARTE transmission will end automatically and an ENDTX event will be generated. A UARTE transmission sequence is stopped by triggering the STOPTX task. A TXSTOPPED event will be generated when the UARTE transmitter has stopped. If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have not been transmitted. N 2 ENDTX TXDRDY TXDRDY N-1 TXDRDY N-2 2 TXDRDY TXDRDY 1 STARTTX TXD.MAXCNT = N+1 1 TXSTARTED Lifeline 0 TXDRDY TXD CTS If flow control is enabled through the HWFC field in the CONFIG register, a transmission will be automatically suspended when CTS is deactivated and resumed when CTS is activated again, as shown in the following figure. A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is suspended. Figure 179: UARTE transmission The UARTE transmitter will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTTX or after it has been stopped via STOPTX and the TXSTOPPED event has been generated. See POWER — Power supply on page 61 for more information about power modes. 6.32.3 Reception The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is using EasyDMA to store incoming data in an RX buffer in RAM. The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is doublebuffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register. The UARTE generates an ENDRX event when it has filled up the RX buffer, as seen in the following figure. 4452_021 v1.5 499 Peripherals For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM. The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have been transferred to the RX buffer in RAM since the previous ENDRX event. Data RAM 1 2 3 4 5 6 7 8 9 10 11 12 - 10 11 RXSTARTED ENDRX RXDRDY 0x20000010 0x20000011 0x20000012 0x20000013 0x20000014 0x20000020 0x20000021 0x20000022 0x20000023 0x20000024 12 RXD.PTR = 0x20000020 RXD.PTR = 0x20000030 4 STARTRX 3 0x20000003 0x20000004 12 RXDRDY 11 10 0x20000001 0x20000002 RXDRDY 9 9 RXDRDY RXSTARTED 8 8 RXDRDY 7 ENDRX 6 7 RXDRDY 6 RXDRDY 5 RXDRDY 4 5 STARTRX STARTRX RXD.MAXCNT = 5 RXD.PTR = 0x20000000 ENDRX_STARTRX = 1 3 4 2 1 RXD.PTR = 0x20000010 Lifeline 3 RXDRDY 2 RXSTARTED RXDRDY 1 2 RXDRDY RXD 1 RXDRDY EasyDMA - 0x20000000 Figure 180: UARTE reception The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated before the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event will be generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after the RXTO event is generated. Note: If the ENDRX event has not been generated when the UARTE receiver stops, indicating that all pending content in the RX FIFO has been moved to the RX buffer, the UARTE will generate the ENDRX event explicitly even though the RX buffer is not full. In this scenario the ENDRX event will be generated before the RXTO event is generated. To determine the amount of bytes the RX buffer has received, the CPU can read the RXD.AMOUNT register following the ENDRX event or the RXTO event. The UARTE is able to receive up to four bytes after the STOPRX task has been triggered, as long as these are sent in succession immediately after the RTS signal is deactivated. After the RTS is deactivated, the UART is able to receive bytes for a period of time equal to the time needed to send four bytes on the configured baud rate. After the RXTO event is generated the internal RX FIFO may still contain data, and to move this data to RAM the FLUSHRX task must be triggered. To make sure that this data does not overwrite data in the RX buffer, the RX buffer should be emptied or the RXD.PTR should be updated before the FLUSHRX task is triggered. To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, as seen in the following figure. The UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not get filled up. 4452_021 v1.5 500 Peripherals 5 6 6 7 Lifeline 2 1 7 8 8 9 9 11, 12, 13, 14 10 10 11 12 13 3 14 ENDRX 4 5 RXTO 3 4 ENDRX 2 3 RXSTARTED 1 2 ENDRX RXD 1 RXSTARTED EasyDMA To be able to know how many bytes have actually been received into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event. 3 4 5 FLUSHRX STOPRX ENDRX_STARTRX = 0 RXD.PTR = C STARTRX STARTRX RXD.PTR = B RXD.PTR = A RXD.MAXCNT = 5 ENDRX_STARTRX = 1 Timeout Figure 181: UARTE reception with forced stop via STOPRX If HW flow control is enabled through the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped via the STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO. With flow control disabled, the UARTE will function in the same way as when the flow control is enabled except that the RTS line will not be used. This means that no signal will be generated when the UARTE has reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when the internal RX FIFO is filled up, will be lost. The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event has been generated. See POWER — Power supply on page 61 for more information about power modes. 6.32.4 Error conditions An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. Effectively, a framing error is always generated before a break condition occurs. An ERROR event will not stop reception. If the error was a parity error, the received byte will still be transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit), that specific byte will NOT be stored into Data RAM, but following incoming bytes will. 6.32.5 Using the UARTE without flow control If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time. 6.32.6 Parity and stop bit configuration Automatic even parity generation for both transmission and reception can be configured using the register CONFIG on page 515. If odd parity is desired, it can be configured using the register CONFIG on page 515. See the register description for details. The amount of stop bits can also be configured through the register CONFIG on page 515. 6.32.7 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. 4452_021 v1.5 501 Peripherals The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped), but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is received in response, before disabling the peripheral through the ENABLE register. 6.32.8 Pin configuration The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD associated with the UARTE are mapped to physical pins according to the configuration specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively. The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used as long as the UARTE is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD, PSEL.RTS, PSEL.RTS, and PSEL.TXD must only be configured when the UARTE is disabled. To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the pins must be configured in the GPIO peripheral as described in the following table. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. UARTE signal UARTE pin Direction Output value RXD As specified in PSEL.RXD Input Not applicable CTS As specified in PSEL.CTS Input Not applicable RTS As specified in PSEL.RTS Output 1 TXD As specified in PSEL.TXD Output 1 Table 131: GPIO configuration before enabling peripheral 6.32.9 Registers Base address Peripheral Instance Description 0x40002000 UARTE UARTE0 Universal asynchronous receiver/ Configuration transmitter with EasyDMA, unit 0 0x40028000 UARTE UARTE1 Universal asynchronous receiver/ transmitter with EasyDMA, unit 1 Table 132: Instances Register Offset Description TASKS_STARTRX 0x000 Start UART receiver TASKS_STOPRX 0x004 Stop UART receiver TASKS_STARTTX 0x008 Start UART transmitter TASKS_STOPTX 0x00C Stop UART transmitter TASKS_FLUSHRX 0x02C Flush RX FIFO into RX buffer EVENTS_CTS 0x100 CTS is activated (set low). Clear To Send. EVENTS_NCTS 0x104 CTS is deactivated (set high). Not Clear To Send. EVENTS_RXDRDY 0x108 Data received in RXD (but potentially not yet transferred to Data RAM) EVENTS_ENDRX 0x110 Receive buffer is filled up EVENTS_TXDRDY 0x11C Data sent from TXD EVENTS_ENDTX 0x120 Last TX byte transmitted EVENTS_ERROR 0x124 Error detected EVENTS_RXTO 0x144 Receiver timeout EVENTS_RXSTARTED 0x14C UART receiver has started EVENTS_TXSTARTED 0x150 UART transmitter has started EVENTS_TXSTOPPED 0x158 Transmitter stopped 4452_021 v1.5 502 Peripherals Register Offset Description SHORTS 0x200 Shortcuts between local events and tasks INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ERRORSRC 0x480 Error source ENABLE 0x500 Enable UART PSEL.RTS 0x508 Pin select for RTS signal PSEL.TXD 0x50C Pin select for TXD signal PSEL.CTS 0x510 Pin select for CTS signal PSEL.RXD 0x514 Pin select for RXD signal BAUDRATE 0x524 Baud rate. Accuracy depends on the HFCLK source selected. RXD.PTR 0x534 Data pointer RXD.MAXCNT 0x538 Maximum number of bytes in receive buffer RXD.AMOUNT 0x53C Number of bytes transferred in the last transaction TXD.PTR 0x544 Data pointer TXD.MAXCNT 0x548 Maximum number of bytes in transmit buffer TXD.AMOUNT 0x54C Number of bytes transferred in the last transaction CONFIG 0x56C Configuration of parity and hardware flow control This register is read/write one to clear. Table 133: Register overview 6.32.9.1 TASKS_STARTRX Address offset: 0x000 Start UART receiver Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TASKS_STARTRX Start UART receiver Trigger 1 Trigger task 6.32.9.2 TASKS_STOPRX Address offset: 0x004 Stop UART receiver Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOPRX Stop UART receiver Trigger task 6.32.9.3 TASKS_STARTTX Address offset: 0x008 Start UART transmitter 4452_021 v1.5 503 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STARTTX Start UART transmitter Trigger task 6.32.9.4 TASKS_STOPTX Address offset: 0x00C Stop UART transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_STOPTX Stop UART transmitter Trigger task 6.32.9.5 TASKS_FLUSHRX Address offset: 0x02C Flush RX FIFO into RX buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description TASKS_FLUSHRX Flush RX FIFO into RX buffer Trigger task 6.32.9.6 EVENTS_CTS Address offset: 0x100 CTS is activated (set low). Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_CTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description CTS is activated (set low). Clear To Send. NotGenerated 0 Event not generated Generated 1 Event generated 6.32.9.7 EVENTS_NCTS Address offset: 0x104 CTS is deactivated (set high). Not Clear To Send. 4452_021 v1.5 504 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_NCTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CTS is deactivated (set high). Not Clear To Send. 6.32.9.8 EVENTS_RXDRDY Address offset: 0x108 Data received in RXD (but potentially not yet transferred to Data RAM) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXDRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data received in RXD (but potentially not yet transferred to Data RAM) NotGenerated 0 Event not generated Generated 1 Event generated 6.32.9.9 EVENTS_ENDRX Address offset: 0x110 Receive buffer is filled up Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDRX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Receive buffer is filled up NotGenerated 0 Event not generated Generated 1 Event generated 6.32.9.10 EVENTS_TXDRDY Address offset: 0x11C Data sent from TXD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXDRDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data sent from TXD NotGenerated 0 Event not generated Generated 1 Event generated 6.32.9.11 EVENTS_ENDTX Address offset: 0x120 Last TX byte transmitted 4452_021 v1.5 505 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ENDTX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Last TX byte transmitted 6.32.9.12 EVENTS_ERROR Address offset: 0x124 Error detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_ERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Error detected 6.32.9.13 EVENTS_RXTO Address offset: 0x144 Receiver timeout Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Receiver timeout 6.32.9.14 EVENTS_RXSTARTED Address offset: 0x14C UART receiver has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_RXSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated UART receiver has started 6.32.9.15 EVENTS_TXSTARTED Address offset: 0x150 UART transmitter has started 4452_021 v1.5 506 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated UART transmitter has started 6.32.9.16 EVENTS_TXSTOPPED Address offset: 0x158 Transmitter stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID Access Field A RW EVENTS_TXSTOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Transmitter stopped 6.32.9.17 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C Reset 0x00000000 ID Access Field C RW ENDRX_STARTRX D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut Shortcut between event ENDRX and task STARTRX RW ENDRX_STOPRX Shortcut between event ENDRX and task STOPRX 6.32.9.18 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L Reset 0x00000000 ID Access Field A RW CTS B Value ID Value H Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event CTS RW NCTS 4452_021 v1.5 J I G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable or disable interrupt for event NCTS 507 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L Reset 0x00000000 ID Access Field C RW RXDRDY D E F G H I J L J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event RXDRDY RW ENDRX Enable or disable interrupt for event ENDRX RW TXDRDY Enable or disable interrupt for event TXDRDY RW ENDTX Enable or disable interrupt for event ENDTX Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW ERROR Enable or disable interrupt for event ERROR RW RXTO Enable or disable interrupt for event RXTO RW RXSTARTED Enable or disable interrupt for event RXSTARTED RW TXSTARTED Enable or disable interrupt for event TXSTARTED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable RW TXSTOPPED Enable or disable interrupt for event TXSTOPPED 6.32.9.19 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L Reset 0x00000000 ID Access Field A RW CTS B C Value ID Value H G F E Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event CTS RW NCTS Write '1' to enable interrupt for event NCTS RW RXDRDY 4452_021 v1.5 J I D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to enable interrupt for event RXDRDY 508 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L Reset 0x00000000 ID Access Field D RW ENDRX E F G H I J L J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event ENDRX RW TXDRDY Write '1' to enable interrupt for event TXDRDY RW ENDTX Write '1' to enable interrupt for event ENDTX RW ERROR Write '1' to enable interrupt for event ERROR RW RXTO Write '1' to enable interrupt for event RXTO RW RXSTARTED Write '1' to enable interrupt for event RXSTARTED RW TXSTARTED Write '1' to enable interrupt for event TXSTARTED RW TXSTOPPED Write '1' to enable interrupt for event TXSTOPPED 6.32.9.20 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L Reset 0x00000000 ID Access Field A RW CTS B H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event CTS Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW NCTS 4452_021 v1.5 J I Write '1' to disable interrupt for event NCTS Clear 1 Disable Disabled 0 Read: Disabled 509 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID L Reset 0x00000000 ID C D E F G H I J L Access Field Value ID Value Description Enabled 1 Read: Enabled RW RXDRDY H G F E Write '1' to disable interrupt for event RXDRDY Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ENDRX Write '1' to disable interrupt for event ENDRX Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TXDRDY Write '1' to disable interrupt for event TXDRDY Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ENDTX Write '1' to disable interrupt for event ENDTX Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ERROR Write '1' to disable interrupt for event ERROR Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW RXTO Write '1' to disable interrupt for event RXTO Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW RXSTARTED Write '1' to disable interrupt for event RXSTARTED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TXSTARTED Write '1' to disable interrupt for event TXSTARTED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TXSTOPPED Write '1' to disable interrupt for event TXSTOPPED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.32.9.21 ERRORSRC Address offset: 0x480 Error source This register is read/write one to clear. 4452_021 v1.5 J I D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 510 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D C B A Reset 0x00000000 ID Access Field A RW OVERRUN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Overrun error A start bit is received while the previous data still lies in RXD. (Previous data is lost.) B NotPresent 0 Read: error not present Present 1 Read: error present RW PARITY Parity error A character with bad parity is received, if HW parity check is enabled. C NotPresent 0 Read: error not present Present 1 Read: error present RW FRAMING Framing error occurred A valid stop bit is not detected on the serial data input after all bits in a character have been received. D NotPresent 0 Read: error not present Present 1 Read: error present RW BREAK Break condition The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit). NotPresent 0 Read: error not present Present 1 Read: error present 6.32.9.22 ENABLE Address offset: 0x500 Enable UART Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID Access Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable UARTE Enabled 8 Enable UARTE Enable or disable UARTE 6.32.9.23 PSEL.RTS Address offset: 0x508 Pin select for RTS signal 4452_021 v1.5 511 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.32.9.24 PSEL.TXD Address offset: 0x50C Pin select for TXD signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID Access Field A B C RW CONNECT B A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description RW PIN [0..31] Pin number RW PORT [0..1] Port number Connection Disconnected 1 Disconnect Connected 0 Connect 6.32.9.25 PSEL.CTS Address offset: 0x510 Pin select for CTS signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.32.9.26 PSEL.RXD Address offset: 0x514 Pin select for RXD signal 4452_021 v1.5 512 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID B A A A A A ID Access Field Value Description A RW PIN [0..31] Pin number B RW PORT [0..1] Port number C RW CONNECT Connection Disconnected 1 Disconnect Connected 0 Connect 6.32.9.27 BAUDRATE Address offset: 0x524 Baud rate. Accuracy depends on the HFCLK source selected. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 ID Access Field A RW BAUDRATE 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Baud1200 0x0004F000 1200 baud (actual rate: 1205) Baud2400 0x0009D000 2400 baud (actual rate: 2396) Baud4800 0x0013B000 4800 baud (actual rate: 4808) Baud9600 0x00275000 9600 baud (actual rate: 9598) Baud14400 0x003AF000 14400 baud (actual rate: 14401) Baud19200 0x004EA000 19200 baud (actual rate: 19208) Baud28800 0x0075C000 28800 baud (actual rate: 28777) Baud31250 0x00800000 31250 baud Baud38400 0x009D0000 38400 baud (actual rate: 38369) Baud56000 0x00E50000 56000 baud (actual rate: 55944) Baud57600 0x00EB0000 57600 baud (actual rate: 57554) Baud76800 0x013A9000 76800 baud (actual rate: 76923) Baud115200 0x01D60000 115200 baud (actual rate: 115108) Baud230400 0x03B00000 230400 baud (actual rate: 231884) Baud250000 0x04000000 250000 baud Baud460800 0x07400000 460800 baud (actual rate: 457143) Baud921600 0x0F000000 921600 baud (actual rate: 941176) Baud1M 0x10000000 1 megabaud Baud rate 6.32.9.28 RXD.PTR Address offset: 0x534 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer See the memory chapter for details about which memories are available for EasyDMA. 4452_021 v1.5 513 Peripherals 6.32.9.29 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in receive buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..0xFFFF] Maximum number of bytes in receive buffer 6.32.9.30 RXD.AMOUNT Address offset: 0x53C Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID AMOUNT Value Description [0..0xFFFF] Number of bytes transferred in the last transaction 6.32.9.31 TXD.PTR Address offset: 0x544 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field A RW PTR Value ID Value Description Data pointer See the memory chapter for details about which memories are available for EasyDMA. 6.32.9.32 TXD.MAXCNT Address offset: 0x548 Maximum number of bytes in transmit buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [0..0xFFFF] Maximum number of bytes in transmit buffer 6.32.9.33 TXD.AMOUNT Address offset: 0x54C Number of bytes transferred in the last transaction 4452_021 v1.5 514 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID Access Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID AMOUNT Value Description [0..0xFFFF] Number of bytes transferred in the last transaction 6.32.9.34 CONFIG Address offset: 0x56C Configuration of parity and hardware flow control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D Reset 0x00000000 ID Access Field A RW HWFC B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disabled Enabled 1 Enabled Hardware flow control RW PARITY C Parity Excluded 0x0 Exclude parity bit Included 0x7 Include even parity bit One 0 One stop bit Two 1 Two stop bits Even 0 Even parity Odd 1 Odd parity RW STOP D C B B B A Stop bits RW PARITYTYPE Even or odd parity type 6.32.10 Electrical specification 6.32.10.1 UARTE electrical specification Symbol Description Min. fUARTE Baud rate for UARTE . tUARTE,CTSH CTS high time tUARTE,START Time from STARTRX/STARTTX task to transmission started Typ. 39 1 Max. Units 1000 kbps µs 1 µs 6.33 USBD — Universal serial bus device The USB device (USBD) controller implements a full speed USB device function that meets 2.0 revision of the USB specification. 39 High baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4452_021 v1.5 515 Peripherals POWER USBDETECTED USBREMOVED USBPWRRDY Event generator LDO tasks events ref VBUS DECUSB Registers USBD MAC APB Data RAM AHB Flash HFXO Serial interface engine (SIE) PLL Physcial layer (PHY)/ Transceiver D+ D- EasyDMA EasyDMA EasyDMA for each endpoint Local buffers Figure 182: USB device block diagram Listed here are the main features for USBD: • Full-speed (12 Mbps) device fully compliant to Universal Serial Bus Specification Revision 2.0, including following engineering change notices (ECNs) issued by USB Implementers Forum: • • • • • Pull-up/pull-down Resistors ECN • 5V Short Circuit Withstand Requirement Change ECN USB device stack available in the Nordic SDK Integrated (on-chip) USB transceiver (PHY) Software controlled on-chip pull-up on D+ Endpoints: • • • • • • Two control (1 IN, 1 OUT) • 14 bulk/interrupt (7 IN, 7 OUT) • Two isochronous (1 IN, 1 OUT) Double buffering for isochronous (ISO) endpoints (IN/OUT) support USB suspend, resume, and remote wake-up support 64 bytes buffer size for each bulk/interrupt endpoint Up to 1023 bytes buffer size for ISO endpoints EasyDMA for all data transfers 6.33.1 USB device states The behavior of a USB device can be modelled through a state diagram. The USB 2.0 Specification (see Chapter 9 USB Device Framework) defines a number of states for a USB device, as shown in the following figure. 4452_021 v1.5 516 Peripherals Attached USB power applied USB power lost Bus inactive Powered Momentary power interruption Bus activity Suspended USB reset Bus inactive Default Bus activity Suspended USB reset Address assigned Bus inactive Address Bus activity Suspended Device configured Device deconfigured Bus inactive Configured Bus activity Suspended Figure 183: Device state diagram The device must change state according to host-initiated traffic and USB bus states. It is up to the software to implement a state machine that matches the above definition. To detect the presence or absence of USB supply (VBUS), two events USBDETECTED and USBREMOVED can be used to implement the state machine. For more details on these events, see USB supply on page 66. As a general rule when implementing the software, the host behavior shall never be assumed to be predictable. In particular the sequence of commands received during an enumeration. The software shall always react to the current bus conditions or commands sent by the host. 6.33.2 USB terminology The USB specification defines bus states, rather than logic levels on the D+ and D- lines. For a full speed device, the bus state where the D+ line is high and the D- line is low is defined as the J state. The bus state where D+ is low and D- high is called the K state. An idle bus, where D+ and D- lines are only polarized through the pull-up on D+ and pull-downs on the host side, will be in J state. Both lines low are called SE0 (single-ended 0), and both lines high SE1 (single-ended 1). 4452_021 v1.5 517 Peripherals 6.33.3 USB pins The USBD peripheral features a number of dedicated pins. The dedicated USB pins can be grouped in two categories, signal and power. The signal pins consist of the D+ and D- pins, which are to be connected to the USB host. They are dedicated pins, and not available as standard GPIOs. The USBD peripheral is implemented according to the USB specification revision 2.0, 5V Short Circuit Withstand ECN Requirement Change, meaning these two pins are not 5 V tolerant. The signal pins and the pull-up will operate only while VBUS is in its valid voltage range, and USBD is enabled through the ENABLE register. For details on the USB power supply and VBUS detection, see USB supply on page 66. For more information about the pinout, see Pin assignments on page 560. 6.33.4 USBD power-up sequence The physical layer interface (PHY)/USB transceiver is powered separately from the rest of the device (VBUS pin), which has some implications on the USBD power-up sequence. The device is not able to properly signal its presence to the USB host and handle traffic from the host, unless the PHY's power supply is enabled and stable. Turning the PHY's power supply on/off is directly linked to register ENABLE. The device provides events that help synchronizing software to the various steps during the power-up sequence. To make sure that all resources in USBD are available and the dedicated USB voltage regulator stabilized, the following is recommended: • Enable USBD only after VBUS has been detected • Turn the USB pull-up on after the following events have occurred: • USBPWRRDY • USBEVENT, with the READY condition flagged in EVENTCAUSE The following sequence chart illustrates a typical handling of VBUS power-up: VBUS POWER CLOCK Software USBD VBUS in valid range USBDETECTED ENABLE=Enabled HFCLKSTART HFCLK Crystal oscillator now starting USBEVENT EVENTCAUSE=READY USBD has been initialized, but PHY has not powered up USBPWRRDY PHY is now powered HFCLKSTARTED USBPULLUP=Enabled Enumeration starts Figure 184: VBUS power-up sequence Upon detecting VBUS removal, it is recommended to wait for ongoing EasyDMA transfers to finish before disabling USBD (relevant ENDEPIN[n], ENDISOIN, ENDEPOUT[n], or ENDISOOUT events, see EasyDMA on page 521). The USBREMOVED event, described in USB supply on page 66, signals when the VBUS is removed. Reading the ENABLE register will return Enabled until USBD is completely disabled. 4452_021 v1.5 518 Peripherals 6.33.5 USB pull-up The USB pull-up serves two purposes: it indicates to the host that the device is connected to the USB bus, and it indicates the device's speed capability. When no pull-up is connected to the USB bus, the host sees both D+ and D- lines low, as they are pulled down on the host side by 15 kΩ resistors. The device is not detected by the host, putting it in a detached state even if it is physically connected to the host. In this situation, the device is not allowed to draw current from VBUS, according to USB 2.0 Specification. When a full-speed device connects its 1.5 kΩ pull-up to D+, the host sees the corresponding line high. The device is then in the attached state. During the enumeration process, the host attempts to determine if the full-speed device also supports higher speeds and initiates communication with the device to further identify it. The USBD peripheral implemented in this device supports only full-speed operation (12 Mbps), and thus ignores the negotiation for higher speeds in accordance with USB 2.0 Specification. Register USBPULLUP enables software to connect or disconnect the pull-up on D+. This allows the software to control when USB enumeration takes place. It also allows to emulate a physical disconnect from the USB bus, for instance when re-enumeration is required. USBPULLUP has to be enabled to allow the USBD to handle USB traffic and generate appropriate events. This forbids the use of an external pullup. Note that disconnecting the pull-up through register USBPULLUP while connected to a host, will result in both D+ and D- lines to be pulled low by the host's pull-down resistors. However, as mentioned above, this will also inhibit the generation of the USBRESET event. The pull-up is disabled by default after a chip reset. The pull-up shall only get connected after USBD has been enabled through register ENABLE. The USB pull-up value is automatically changed depending on the bus activity, as specified in Resistor ECN which amends the original USB 2.0 Specification. The user does not have access to this function as it is handled in hardware. While they should never be used in normal traffic activity, lines D+ and D- may at any time be forced into state specified in register DPDMVALUE by the task DPDMDRIVE. The DPDMNODRIVE task stops driving them, and PHY returns to normal operation. 6.33.6 USB reset The USB specification defines a USB reset, which is not be confused with a chip reset. The USB reset is a normal USB bus condition, and is used as part of the enumeration sequence, it does not reset the chip. The USB reset results from a single-ended low state (SE0) on lines D+/D- for a tUSB,DETRST amount of time. Only the host is allowed to drive a USB reset condition on the bus. The UBSD peripheral automatically interprets a SE0 longer than tUSB,DETRST as a USB reset. When the device detects a USB reset and generates a USBRESET event, the device USB stack and related parts of the application shall re-initialize themselves, and go back to the default state. Some of the registers in the USBD peripheral get automatically reset to a known state, in particular all data endpoints are disabled and the USBADDR reset to 0. After the device has connected to the USB bus (i.e. after VBUS is applied), the device shall not respond to any traffic from the time the pull-up is enabled until it has seen a USB reset condition. This is automatically ensured by the USBD. After a USB reset, the device shall be fully responsive after at most TRSTRCY (according to chapter 7 in the USB specification). Software shall take into account this time that takes the hardware to recover from a USB reset condition. 4452_021 v1.5 519 Peripherals 6.33.7 USB suspend and resume Normally, the host will maintain activity on the USB at least every millisecond according to USB specification. A USB device will enter suspend when there is no activity on the bus (idle) for a given time. The device will resume operation when it receives any non idle signalling. To signal that the device shall go into low power mode (suspend), the host stops activity on the USB bus, which becomes idle. Only the device pull-up and host pull-downs act on D+ and D-, and the bus is thus kept at a constant J state. It is up to the device to detect this lack of activity, and enter the low power mode (suspend) within a specified time. The USB host can decide to suspend or resume USB activity at any time. If remote wake-up is enabled, the device may signal to the host to resume from suspend. 6.33.7.1 Entering suspend The USBD peripheral automatically detects lack of activity for more than a defined amount of time, and performs steps needed to enter suspend. When no activity has been detected for longer than tUSB,SUSPEND, the USBD generates the USBEVENT event with SUSPEND bit set in register EVENTCAUSE. The software shall ensure that the current drawn from the USB supply line VBUS is within the specified limits before T2SUSP, as defined in chapter 7 of the USB specification. In order to reduce idle current of USBD, the software must explicitly place the USBD in low power mode through writing LowPower to register LOWPOWER. In order to save power, and provided that no other peripheral needs it, the crystal oscillator (HFXO) in CLOCK may be disabled by software during the USB suspend, while the USB pull-up is disconnected, or when VBUS is not present. Software must explicitly enable it at any other time. The USBD will not be able to respond to USB traffic unless HFXO is enabled and stable. 6.33.7.2 Host-initiated resume Once the host resumes the bus activity, it has to be responsive to incoming requests on the USB bus within the time TRSMRCY (as defined in chapter 7 of the USB specification) and revert to normal power consumption mode. If the host resumes bus activity with or without a RESUME condition (in other words: bus activity is defined as any non-J state), the USBD peripheral will generate a USBEVENT event, with RESUME bit set in register EVENTCAUSE. If the host resumes bus activity simply by restarting sending frames, the USBD peripheral will generate SOF events. 6.33.7.3 Device-initiated remote wake-up Assuming the remote wake-up is supported by the device and enabled by the host, the device can request the host to resume from suspend if wake-up condition is met. To do so, the HFXO needs to be enabled first. After waking up the HFXO, the software must bring USBD out of the low power mode and into the normal power consumption mode through writing ForceNormal in register LOWPOWER. It can then instruct the USBD peripheral to drive a RESUME condition (K state) on the USB bus by triggering the DPDMDRIVE task, and hence attempt to wake up the host. By choosing Resume in DPDMVALUE, the duration of the RESUME state is under hardware control (tUSB,DRIVEK). By choosing J or K, the duration of that state is under software control (the J or K state is maintained until a DPDMNODRIVE task is triggered) and has to meet TDRSMUP as specified in USB specification chapter 7. Upon writing the ForceNormal in register LOWPOWER, a USBEVENT event is generated with the USBWUALLOWED bit set in register EVENTCAUSE. The value in register DPDMVALUE on page 549 will only be captured and used when the DPDMDRIVE task is triggered. This value defines the state the bus will be forced into after the DPDMDRIVE task. 4452_021 v1.5 520 Peripherals The device shall ensure that it does not initiate a remote wake-up request before TWTRSM (according to USB specification chapter 7) after the bus has entered idle state. Using the recommended resume value in DPDMVALUE (rather than K) takes care of this, and postpones the RESUME state accordingly. 6.33.8 EasyDMA The USBD peripheral implements EasyDMA for accessing memory without CPU involvement. Each endpoint has an associated set of registers, tasks and events. EasyDMA and traffic on USB are tightly related. A number of events provide insight of what is happening on the USB bus with a number of tasks allowing an automated response to the traffic. Note: Endpoint 0 (IN and OUT) are implemented as control endpoint. For more information, see Control transfers on page 522. Registers Enabling endpoints is controlled through the EPINEN and EPOUTEN registers. The following registers define the memory address of the buffer for a specific IN or OUT endpoint: • • • • EPIN[n].PTR, (n=0..7) EPOUT[n].PTR, (n=0..7) ISOIN.PTR ISOOUT.PTR The following registers define the amount of bytes to be sent on USB for next transaction: • EPIN[n].MAXCNT, (n=0..7) • ISOIN.MAXCNT The following registers define the length of the buffer (in bytes) for next transfer of incoming data: • EPOUT[n].MAXCNT, (n=1..7) • ISOOUT.MAXCNT Since the host decides how many bytes are sent over USB, the MAXCNT value can be copied from register SIZE.EPOUT[n] (n=1..7) or register SIZE.ISOOUT. Register EPOUT[0].MAXCNT defines the length of the OUT buffer (in bytes) for the control endpoint 0. Register SIZE.EPOUT[0] shall indicate the same value as MaxPacketSize from the device descriptor or wLength from the SETUP command, whichever is the least. The .AMOUNT registers indicate how many bytes actually have been transferred over EasyDMA during the last transfer. Stalling bulk/interrupt endpoints is controlled through the EPSTALL register. Note: Due to USB specification requirements, the effect of the stalling control endpoint 0 may be overridden by hardware, in particular when a new SETUP token is received. EasyDMA will not copy the SETUP data to memory (it will only transfer data from the data stage). The following are separate registers in the USBD peripheral that have setup data. • • • • • • BMREQUESTTYPE BREQUEST WVALUEL WVALUEH WINDEXL WINDEXH 4452_021 v1.5 521 Peripherals • WLENGTHL • WLENGTHH The EVENTCAUSE register provides details on what caused a given USBEVENT event, for instance if a CRC error is detected during a transaction, or if bus activity stops or resumes. Tasks Tasks STARTEPIN[n], STARTEPOUT[n] (n=0..7), STARTISOIN, and STARTISOOUT capture the values for .PTR and .MAXCNT registers. For IN endpoints, a transaction over USB gets automatically triggered when the EasyDMA transfer is complete. For OUT endpoints, it is up to software to allow the next transaction over USB. See the examples in Control transfers on page 522, Bulk and interrupt transactions on page 525, and Isochronous transactions on page 527. For the control endpoint 0, OUT transactions are allowed through the EP0RCVOUT task. The EP0STATUS task allows a status stage to be initiated, and the EP0STALL task allows stalling further traffic (data or status stage) on the control endpoint. Events The STARTED event confirms that the values of the .PTR and .MAXCNT registers of the endpoints flagged in register EPSTATUS have been captured. Those can then be modified by software for the next transfer. Events ENDEPIN[n], ENDEPOUT[n] (n=0..7), ENDISOIN, and ENDISOOUT events indicate that the entire buffer has been consumed. The buffer can be accessed safely by the software. Only a single EasyDMA transfer can take place in USBD at any time. Software must ensure that tasks STARTEPIN[n] (n=0..7), STARTISOIN , STARTEPOUT[n] (n=0..7), or STARTISOOUT are not triggered before events ENDEPIN[n] (n=0..7), ENDISOIN, ENDEPOUT[n] (n=0..7), or ENDISOOUT are received from an ongoing transfer. The EPDATA event indicates that a successful (acknowledged) data transaction has occurred on the data endpoint(s) flagged in register EPDATASTATUS. A successful (acknowledged) data transaction on endpoint 0 is signalled by the EP0DATADONE event. At any time a USBEVENT event may be sent, with details provided in EVENTCAUSE register. The EP0SETUP event indicates that a SETUP token has been received on the control endpoint 0, and that the setup data is available in the setup data registers. 6.33.9 Control transfers The USB specification mandates every USB device to implement endpoint 0 IN and OUT as control endpoints. A control transfer consists of two or three stages: • Setup stage • Data stage (optional) • Status stage Each control transfer can be one of following types: • • • • Control read Control read no data Control write Control write no data An EP0SETUP event indicates that the data in the setup stage (following the SETUP token) is available in registers. 4452_021 v1.5 522 Peripherals The data in the data stage (following the IN or OUT token) is transferred from or to the desired location using EasyDMA. The control endpoint buffer can be of any size. After receiving the SETUP token, the USB controller will not accept (NAK) any incoming IN or OUT tokens until the software has finished decoding the command, determined the type of transfer, and prepared for the next stage (data or status) appropriately. The software can stall a command when in the data and status stages, through the EP0STALL task, when the command is not supported or if its wValue, wIndex or wLength parameters are wrong. The following shows a stalled control read transfer, but the same mechanism (tasks) applies to stalling a control write transfer. Setup stage USB host SETUP USB device Data stage 8 bytes IN ACK NAK STALL EP0STALL EP0SETUP Events & tasks IN Software EP0STALL=1 (Command not supported) Decode setup Figure 185: Control read gets stalled See the USB 2.0 Specification and relevant class specifications for rules on stalling commands. Note: The USBD peripheral handles the SetAddress transfer by itself. As a consequence, the software shall not process this command other than updating its state machine (see Device state diagram), nor initiate a status stage. If necessary, the address assigned by the host can be read out from the USBADDR register after the command has been processed. 6.33.9.1 Control read transfer This section describes how the software behaves when responding to a control read transfer. As mentioned earlier, the USB controller will not accept (NAK) any incoming IN tokens until software has finished decoding the command, determining the type of transfer, and preparing for the next stage (data or status) appropriately. For a control read, transferring the data from memory into USBD will trigger a valid, acknowledged (ACK) IN transaction on USB. The software has to prepare EasyDMA by pointing to the buffer containing the data to be transferred. If no other EasyDMA transfers are on-going with USBD, the software can send the STARTEPIN0 task, which will initiate the data transfer and transaction on USB. A STARTED event (with EPIN0 bit set in the EPSTATUS register) will be generated as soon as the EPIN[0].PTR and .MAXCNT registers have been captured. Software may then prepare them for the next data transaction. 4452_021 v1.5 523 Peripherals An ENDEPIN[0] event will be generated when the data has been transferred from memory to the USBD peripheral. Finally, an EP0DATADONE event will be generated when the data has been transmitted over USB and acknowledged by the host. The software can then either prepare and transmit the next data transaction by repeating the above sequence, or initiate the status stage through the EP0STATUS task. Setup stage USB host SETUP Data stage 8 bytes IN Status stage IN IN DATA (n) NAK IN NAK ACK OUT DATA (0) DATA (n+1) ACK EP0STATUS EP0DATADONE ENDEPIN[0] STARTED STARTEPIN[0] EP0DATADONE EP0SETUP NAK ACK ENDEPIN[0] Events & tasks NAK IN STARTED ACK STARTEPIN[0] USB device IN Software EP0STATUS=1 Allow status stage (enable EP0DATADONE to EP0STATUS) STARTEPIN[0]=1 EPIN[0].MAXCNT =