UM805/811/812
4-Pin μP Voltage Monitors with Manual Reset Input
UM805/811/812 SOT143
General Description
The UM805/811/812 are low-power microprocessor (μP) supervisory circuits used to monitor power
supplies in μP and digital systems. They provide excellent circuit reliability and low cost by
eliminating external components and adjustments when used with 5V-powered or 3V-powered
circuits. The UM805/811/812 also provide a debounced manual reset input.
These devices perform a single function: They assert a reset signal whenever the VCC supply voltage
falls below a preset threshold, keeping it asserted for at least 140ms after VCC has risen above the
reset threshold. Reset thresholds are available for operation with a variety of supply voltages.
The UM805 has an open-drain
output stage, while the UM811/812 have push-pull outputs. The
_____________
resistor that can be connected to a voltage
UM805’s open-drain RESET output requires a pull-up _____________
higher than VCC. The UM805/811 have an active-low RESET output, while the UM812 has an
active-high RESET output. The reset comparator is designed to ignore fast transients on VCC, and
the outputs are guaranteed to be in the correct logic state for VCC down to 1V.
Low supply current makes the UM805/811/812 ideal for use in portable equipments. The devices
come in a 4-pin SOT143 package.
Applications
Features
z
z
z
z
z
z
z
z
z
Computers
Controllers
Portable/Battery-Powered Equipments
Intelligent Instruments
Critical μP and μC Power Monitoring
z
z
z
z
z
z
No External Components
VCC Transient Immunity
Correct Logic Output Guaranteed to VCC=1.0V
Precision VCC Monitoring of 3.0V, 3.3V and 5.0V
Supplies
2μA Supply Current
140ms Minimum Power-On Reset Pulse Width
Guaranteed Over Temperature
Available in 3 Output Configurations:
__________
Output (UM805)
Open-Drain Active-Low_ _ _RESET
_______
Push-Pull Active-Low RESET Output (UM811)
Push-Pull Active-High RESET Output (UM812)
4-Pin SOT143 Package
Wide Operation Temperature: -40°C to +85°C
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UM805/811/812
Pin Configurations
GND
1
RESET
2
(RESET)
Top View
4
VCC
3
MR
( ) are for UM812
M: Month Code
UM805/811/812
SOT143
Ordering Information
UM8 XX Z P
XX: Output Type
=05 Open-Drain Active Low
=11 Push-Pull Active Low
=12 Push-Pull Active High
Z: Reset Threshold (V)
=L
4.63
=M 4.38
=J
4.00
=T 3.08
=S 2.93
=R 2.63
=Z 2.32
P: Package Type
=E SOT143
Typical Operating Circuit
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UM805/811/812
Pin Description
Pin
Number
1
Pin Name
Function
GND
Ground
_____________
Active-Low Reset Output. RESET
remains low while VCC is below
_______
the reset threshold or while MR is held low. It remains low for the
Reset Active Timeout Period (tRP) after the reset conditions are
terminated. See Figure 1.
UM811:
CMOS push-pull output (sources and sinks current).
UM805:
Open-drain, active low,
NMOS output (sinks current only). Connect a
______________
pull-up resistor from RESET to any supply voltage up to 6V.
Active-High Reset Output. RESET
remains high while VCC is below
_______
the reset threshold or while MR is held low. RESET remains high for
Reset Active Timeout Period (tRP) after the reset conditions are
terminated.
______________
RESET
(UM805/811)
2
RESET
(UM812)
_______
3
_______
MR
Manual Reset Input._______
A logic low on MR asserts reset.
_______Reset remains
asserted as long as MR is low and for 240ms after MR returns high.
This active-low input has an internal 20kΩ pull-up resistor. It can be
driven from a TTL or CMOS-logic line, or shorted to ground with a
switch. Leave open if unused. See Figure 2.
4
VCC
+5V, +3.3V or +3V Supply Voltage
Absolute Maximum Ratings (Note 1)
Symbol
VCC
Parameter
Supply Voltage
RESET, RESET (Push-Pull)
_____________
RESET (Open-Drain)
IO
PD
TA
TSTG
Unit
-0.3 to +6.0
_____________
ICC
Value
-0.3 to (VCC+0.3)
V
-0.3 to +6.0
_______
Input Current, VCC, MR
_____________
20
mA
20
mA
Output Current, RESET, RESET
Continuous Power Dissipation
(Derate 4mW/°C above 70°C)
Operating Temperature Range
320
mW
-40 to +105
°C
Storage Temperature Range
-65 to +160
°C
Lead Temperature (Soldering, 10s)
+300
°C
Note 1: Stresses beyond those listed under “Absolute maximum Ratings” may cause permanent
damage to the device. These are stress ratings only and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications are not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
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UM805/811/812
Electrical Characteristics
(VCC=5V for L/M/J versions, VCC=3.3V for T/S versions, VCC=3V for R version, and VCC=2.5V for
Z version, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA=+25°C.) (Note 2)
Symbol
Parameter
Conditions
Min
VCC
Supply Voltage
Range
TA=0°C to +70°C
1.0
ICC
Supply Current
L Version
M Version
J Version
VTH+
Reset Threshold
T Version
S Version
R Version
Z Version
tRP
TA=+25°C
4.56
TA=-40°C to +85°C
4.50
TA=+25°C
4.31
TA=-40°C to +85°C
4.25
TA=+25°C
3.93
TA=-40°C to +85°C
3.89
TA=+25°C
3.04
TA=-40°C to +85°C
3.00
TA=+25°C
2.89
TA=-40°C to +85°C
2.85
TA=+25°C
2.59
TA=-40°C to +85°C
2.55
TA=+25°C
2.28
TA=-40°C to +85°C
2.25
Reset Threshold
Tempco
VCC to Reset Delay
(Note 3)
Reset Active
Timeout Period
140
Typ
Max
Unit
5.5
V
2.0
5.0
μA
4.63
4.70
4.75
4.38
4.45
4.50
4.00
4.06
4.10
3.08
3.11
V
3.15
2.93
2.96
3.00
2.63
2.66
2.70
2.32
2.35
2.38
150
ppm/°C
10
μs
240
560
ms
______
tMR
MR Minimum
μs
10
Pulse Width
______
MR Glitch
Immunity
(Note 4)
100
ns
0.5
μs
______
tMD
MR to Reset
Propagation Delay
VIH
VIL
VIH
______
MR Input
Threshold
VIL
VCC>VTH(MAX)
UM805/811/812LE/ME/JE
2.3
VCC>VTH(MAX)
UM805/811/812TE/SE/RE/ZE
0.7×VCC
0.8
V
0.25×VCC
______
MR Pull-Up
Resistance
10
20
30
kΩ
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UM805/811/812
Electrical Characteristics (Continued)
(VCC=5V for L/M/J versions, VCC=3.3V for T/S versions, VCC=3V for R version, and VCC=2.5V for
Z version, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA=+25°C.) (Note 2)
Symbol
Parameter
VOH
VOL
RESET Output
Voltage
VOH
____________
RESET Output
Voltage
VOL
Conditions
ISOURCE=150μA, 1.8VVTH(MAX)
UM811LE/ME/JE
ISINK=1.2mA, VCC=VTH(MIN)
UM805/811TE/SE/RE/ZE
ISINK=3.2mA, VCC=VTH(MIN)
UM805/811LE/ME/JE
ISINK=50μA, VCC>1.0V
Min
Typ
Max
Unit
0.3
V
0.8×VCC
0.4
0.8×VCC
VCC-1.5
0.3
V
0.4
0.3
Note 2: Production
testing done at TA=+25°C; limits over temperature guaranteed by design only.
_____________
Note 3: RESET output for UM805/811; RESET output for UM812.
Note 4: “Glitches” of 100ns or less typically will not generate a reset pulse.
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UM805/811/812
Typical Operating Characteristics
(TA=+25°C, unless otherwise noted.)
Supply Current vs. Temperature
(UM811RE)
Power-down RESET Delay vs. Temperature
(UM811RE)
VCC=3.3V
Power-up RESET Timeout vs. Temperature
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UM805/811/812
Detailed Description
RESET Timing
The reset signal is asserted LOW for the UM811 and HIGH for the UM812 when the power supply
voltage falls below the threshold trip voltage and remains asserted for at least 140ms after the power
supply voltage has risen above the threshold.
Figure 1. RESET vs. VCC Timing Diagram
_______
The reset signal is asserted LOW for the _______
UM811 and HIGH for the UM812 when MR is low and
remains asserted for at least 140ms after MR is high.
HIGH
tMR
MR
LOW
tRP
tMD
VCC
RESET
0V
VCC
RESET
0V
_______
Figure 2. RESET vs. MR Timing Diagram
Reset Output
A microprocessor’s (µP’s) reset input starts the µP in a known state. These μP supervisory circuits
assert
reset to prevent code execution errors during power-up, power-down, or brownout conditions.
_____________
RESET is guaranteed_____________
to be a logic low for VCC>1V. Once VCC exceeds the reset _____________
threshold, an
internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes
high.
_____________
If a brownout condition occurs (VCC dips below the reset threshold), RESET goes low. Any time
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UM805/811/812
_____________
VCC goes below the reset threshold, the internal timer resets to zero,_____________
and RESET goes low. The
internal timer starts after VCC returns above the reset threshold, and RESET remains low for the
reset timeout period.
_______
The manual reset input (MR ) can also initiate a reset. See the Manual Reset Input section. _____________
The UM812 has an active-high RESET output that is the inverse of the UM805/811’s RESET
output. The UM805 uses an open-drain output,
and the UM811/812 have a push-pull output stage.
_____________
Connect a pull-up resistor on the UM805’s RESET output to any supply between 0 and 6V.
Manual Reset Input
Many μP-based products require manual reset capability, allowing
the operator, a test technician, or
_______
reset. Reset remains asserted
external_______
logic circuitry to initiate a reset. A logic low on MR asserts _______
returns high. This input
while MR is low, and for the Reset Active Timeout Period (tRP) after MR _______
has an internal 20kΩ pull-up resistor, so it can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels,
_______ or with open-drain/collector outputs. Connect a normally open
to GND to create a manual-reset function; external debounce
momentary switch from MR
_______
cables or if the device is used in a noisy
circuitry is not required. If MR is driven from long_______
environment, connecting a 0.1μF capacitor from MR to ground provides additional noise
immunity.
Reset Threshold Accuracy
The UM805/811/812 are ideal for systems using a 5V±5% or 3V±5% power supply with ICs
specified for 5V±10% or 3V±10%, respectively. They are designed to meet worst-case
specifications over temperature. The reset is guaranteed to assert after the power supply falls out of
regulation, but before power drops below the minimum specified operating voltage range for the
system ICs. The thresholds are pre-trimmed and exhibit tight distribution, reducing the range over
which an undesirable reset may occur.
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UM805/811/812
Applications Information
Negative-Going VCC Transients
In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the
UM805/811/812 are relatively immune to short-duration negative-going VCC transients (glitches).
Figure 3 shows typical transient duration vs. reset comparator overdrive, for which the
UM805/811/812 do not generate a reset pulse. The graph was generated using a negative-going
pulse applied to VCC, starting above the actual reset threshold and ending below it by the magnitude
indicated (reset comparator overdrive). The graph indicates the typical maximum pulse width a
negative-going VCC transient may have without causing a reset pulse to be issued. As the magnitude
of the transient increases (goes farther below the reset threshold), the maximum allowable pulse
width decreases. Typically, for the UM8_ _LE/ME/JE, a VCC transient that goes 125mV below the
reset threshold and lasts 40µs or less will not cause a reset pulse to be issued. A 0.1µF capacitor
mounted as close as possible to the VCC provides additional transient immunity.
UM8_ _LE/ME/JE
UM8
TE/SE/RE/ZE
Figure 3. Maximum Transient Duration without Causing a Reset Pulse
vs. Reset Comparator Overdrive
______________
Ensuring a Valid RESET Output Down to VCC=0V
_____________
When VCC falls below 1V, the UM811 RESET output no longer sinks current—it
becomes an open
_____________
circuit. Therefore, high-impedance CMOS-logic inputs connected to RESET can drift to
undetermined voltages. This presents no problem in most applications since
most µP and other
_____________
circuitry is inoperative with VCC below 1V. However,
_____________ in applications where RESET must be valid
down to 0V, adding a pull-down
_____________ resistor to RESET pin will causes any stray leakage currents to
4). R1’s value is not critical; 100kΩ is large enough
flow to ground,
holding RESET low (Figure _____________
_____________
not to load RESET and small enough to pull RESET to ground.
A 100kΩ pull-up resistor to VCC is also recommended for the UM812 if RESET is required to
remain valid for VCC
