PMC271/PMS271 Series
8-bit ADC
Field Programmable Processor Array
(FPPATM) 8-bit Controller
Data Sheet
Version 0.04– June 11, 2015
Copyright 2015 by PADAUK Technology Co., Ltd., all rights reserved
10F-2, No. 1, Sec. 2, Dong-Da Road, Hsin-Chu 300, Taiwan, R.O.C.
TEL: 886-3-532-7598 www.padauk.com.tw
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those that may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2015, PADAUK Technology Co. Ltd
Page 2 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Table of Contents
1. Features ............................................................................................................................... 8
1.1.
1.2.
1.3.
1.4.
Special Features ..................................................................................................................... 8
System Features ..................................................................................................................... 8
CPU Features ......................................................................................................................... 8
Package Information ............................................................................................................... 9
2. General Description and Block Diagram ........................................................................ 10
3. Pin Assignment and Description..................................................................................... 11
4. Device Characteristics ..................................................................................................... 16
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
4.10.
4.11.
4.12.
4.13.
4.14.
4.15.
4.16.
DC/AC Characteristics .......................................................................................................... 16
Absolute Maximum Ratings .................................................................................................. 18
Typical IHRC Frequency vs. VDD (calibrated to 16MHz) ..................................................... 18
Typical ILRC Frequency vs. VDD ......................................................................................... 18
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz) ........................................ 19
Typical ILRC Frequency vs. Temperature ............................................................................ 19
Typical Operating Current vs. VDD and CLK=IHRC/n .......................................................... 20
Typical Operating Current vs. VDD and CLK=ILRC/n .......................................................... 20
Typical Lowest Operating Current vs. VDD and CLK=ILRC/n .............................................. 21
Typical Operating Current vs. VDD @CLK=32KHz EOSC/n ................................................ 22
Typical Operating Current vs. VDD @CLK=1MHz EOSC/n ................................................. 23
Typical Operating Current vs. VDD @CLK=4MHz EOSC/n ................................................. 24
Typical IO pull high resistance .............................................................................................. 25
Typical IO driving current (IOH) and sink current (IOL) ............................................................ 25
Typical IO input high / low threshold voltage (VIH/VIL) ........................................................... 25
Typical (VDD/2) Bias output voltage ..................................................................................... 25
5. Functional Description ..................................................................................................... 26
5.1.
5.2.
5.3.
5.4.
Processing Units ................................................................................................................... 26
5.1.1. Program Counter ........................................................................................................ 27
5.1.2. Stack Pointer .............................................................................................................. 27
5.1.3. Single FPP mode........................................................................................................ 28
Program Memory – OTP ....................................................................................................... 29
5.2.1. Program Memory Assignment .................................................................................... 29
5.2.2. Example of Using Program Memory for Two FPP mode ............................................ 29
5.2.3. Example of Using Program Memory for Single FPP mode ........................................ 30
Program Structure................................................................................................................. 31
5.3.1. Program structure of two FPP units mode.................................................................. 31
5.3.2. Program structure of single FPP mode ...................................................................... 31
Boot Procedure ..................................................................................................................... 32
©Copyright 2015, PADAUK Technology Co. Ltd
Page 3 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
5.11.
5.12.
5.13.
5.14.
5.15.
6.
Data Memory – SRAM .......................................................................................................... 33
Arithmetic and Logic Unit ...................................................................................................... 33
Oscillator and clock ............................................................................................................... 34
5.7.1. Internal High RC oscillator and Internal Low RC oscillator ......................................... 34
5.7.2. Chip calibration ........................................................................................................... 34
5.7.3. IHRC Frequency Calibration and System Clock ......................................................... 34
5.7.4. External Crystal Oscillator .......................................................................................... 36
5.7.5. System Clock and LVR levels .................................................................................... 37
5.7.6. System Clock Switching ............................................................................................. 38
16-bit Timer (Timer16) .......................................................................................................... 39
Watchdog Timer.................................................................................................................... 40
Interrupt................................................................................................................................. 41
Power-Save and Power-Down .............................................................................................. 42
5.11.1. Power-Save mode (“stopexe”).................................................................................. 43
5.11.2. Power-Down mode (“stopsys”) ................................................................................. 44
5.11.3. Wake-up ................................................................................................................... 45
IO Pins .................................................................................................................................. 46
Reset and LVR...................................................................................................................... 47
5.13.1. Reset ........................................................................................................................ 47
5.13.2. LVR reset.................................................................................................................. 47
LCD Half VDD Bias Voltage.................................................................................................. 47
Analog-to-Digital Conversion (ADC) module ........................................................................ 48
5.15.1 The input requirement for AD conversion .................................................................. 49
5.15.2 ADC clock selection................................................................................................... 50
5.15.3 AD conversion ........................................................................................................... 50
5.15.4 Configuring the analog pins ....................................................................................... 50
IO Registers....................................................................................................................... 51
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.12.
6.13.
6.14.
6.15.
ACC Status Flag Register (flag), IO address = 0x00 ............................................................ 51
FPP unit Enable Register (fppen), IO address = 0x01 .......................................................... 51
Stack Pointer Register (sp), IO address = 0x02 ................................................................... 51
Clock Mode Register (clkmd), IO address = 0x03 ................................................................ 52
Interrupt Enable Register (inten), IO address = 0x04 ........................................................... 52
Interrupt Request Register (intrq), IO address = 0x05 .......................................................... 52
Timer 16 mode Register (t16m), IO address = 0x06............................................................. 53
General Data register for IO (gdio), IO address = 0x07 ........................................................ 53
External Oscillator setting Register (eoscr, write only), IO address = 0x0a .......................... 53
IHRC oscillator control Register (ihrcr, write only), IO address = 0x0b ................................. 54
Interrupt Edge Select Register (integs), IO address = 0x0c.................................................. 54
Port A Digital Input Enable Register (padier), IO address = 0x0d......................................... 55
Port B Digital Input Enable Register (pbdier), IO address = 0x0e......................................... 56
Port A Data Registers (pa), IO address = 0x10 .................................................................... 57
Port A Control Registers (pac), IO address = 0x11 .............................................................. 57
©Copyright 2015, PADAUK Technology Co. Ltd
Page 4 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.16. Port A Pull-High Registers (paph), IO address = 0x12 ......................................................... 57
6.17. Port B Data Registers (pb), IO address = 0x14 .................................................................... 57
6.18. Port B Control Registers (pbc), IO address = 0x15 .............................................................. 57
6.19. Port B Pull-High Registers (pbph), IO address = 0x16 ......................................................... 57
6.20. ADC Control Register (adcc), IO address = 0x20 ................................................................. 58
6.21. ADC Mode Register (adcm, write only), IO address = 0x21 ................................................. 58
6.22. ADC Result Register (adcr, read only), IO address = 0x22 .................................................. 59
6.23. ADC Reference High Control Register (adcrhc), IO address = 0x1c .................................... 59
6.24 RESET Status Register (rstst), IO address = 0x25 ................................................................ 59
6.23. MISC Register (misc), IO address = 0x3b ............................................................................ 60
7. Instructions ....................................................................................................................... 61
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Data Transfer Instructions..................................................................................................... 62
Arithmetic Operation Instructions .......................................................................................... 67
Shift Operation Instructions................................................................................................... 69
Logic Operation Instructions ................................................................................................. 70
Bit Operation Instructions...................................................................................................... 73
Conditional Operation Instructions ........................................................................................ 74
System control Instructions ................................................................................................... 76
Summary of Instructions Execution Cycle ............................................................................ 78
Summary of affected flags by Instructions ............................................................................ 79
8. Special Notes .................................................................................................................... 80
8.1.
8.2.
Using IC ................................................................................................................................ 80
8.1.1.
IO pin usage and setting ................................................................................... 80
8.1.2.
Interrupt ............................................................................................................. 81
8.1.3.
System clock switching ..................................................................................... 81
8.1.4.
Power down mode, wakeup and watchdog ....................................................... 82
8.1.5.
TIMER time out ................................................................................................. 82
8.1.6.
Using ADC ......................................................................................................... 83
8.1.7.
LVR ................................................................................................................... 83
8.1.8.
Differences in command timing between single / double FPPA mode .............. 83
8.1.9.
Program writing ................................................................................................. 83
Using ICE .............................................................................................................................. 84
8.2.1.
Emulating PMC271/PMS271 series IC on ICE PDK3S-I-001/002/003 ............. 84
8.2.2.
Important Notice for ICE operation .................................................................... 85
©Copyright 2015, PADAUK Technology Co. Ltd
Page 5 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Revision History:
Revision
Date
Description
ST
0.01
2013/12/10
1
version
0.02
2014/2/19
Add chapter 8 Special Notes
0.03
2014/12/22
0.04
2015/6/11
Amend PMS271 operating temperature
1. Amend page 7: PMC271/PMS271 Band-gap mV
2. Amend 1.1 PMS271 series operating temperature range to -20°C ~ 70°C
3. Amend 4.1 Band-gap reference voltage
©Copyright 2015, PADAUK Technology Co. Ltd
Page 6 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Major Differences between PDK22C and PMC271/PMS271
There are many differences between PDK22C and PMC271/PMS271. The table below only shows the major
differences between them.
Item
Function
PDK22C
PMC271/PMS271
1
IO Pin
15 IO + 1 input
16 IO
2
IO capability
15mA@5.0V
10mA@5.0V
3
Band-gap
N/A
4
LVR
5 levels LVR setting
8 levels LVR setting
5
Fast wake up
N/A
Yes
6
Single FPPA mode
N/A
Yes
7
ADC channel
4 channels
8 channels
Yes
No
External RC and external
8
clock source mode
+/- 60mV(@1.20V)
after calibration
9
T16 clock source
Support external RC oscillator
Not support
10
LCD VDD/2 bias voltage
Enabled by code option
Controlled by misc.4
11
misc register
N/A
Yes
adcdi register
padier and pbdier
12
Port digital input
configure registers
13
IHRC option command
.ADJUST_OTP_IHRCR
.ADJUST_IC
14
WDT timeout period
1024 ILRC cycles
4 selectable periods
Procedure for converting code from PDK22C to PMC271/PMS271
Please follow the below steps for converting codes from PDK22C to PMC271/PMS271:
1.
Go through the PMC271/PMS271 datasheet and user guide;
2.
Modify the source code engineering file “.pre”; change “.chip PDK22CXXX” to “.chip PMC271” or “.chip
PMS271”
3.
Press “Build” and then IDE will show some errors and warnings.
4.
Modify the source code correspondingly until all errors have been solved.
5.
Save and build the project files again.
6.
Write to a real chip and test its functions in detail.
7.
Back to the step 3 if necessary.
8.
Contact our FAE at fae@padauk.com.tw if you still have any problems.
©Copyright 2015, PADAUK Technology Co. Ltd
Page 7 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
1. Features
1.1. Special Features
PMC271 series:
High EFT series
Operating temperature range: -40°C ~ 85°C
PMS271 series:
General purpose series
Please don’t apply to AC RC step-down powered, high power ripple or high EFT requirement
application
Operating temperature range: -20°C ~ 70°C
1.2. System Features
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator
Internal High RC Oscillator (IHRC) frequency
Band-gap circuit to provide 1.20V reference voltage
One hardware 16-bit timer
Total 8-channel 8-bit ADC, including one channel for band-gap reference voltage input
Built-in half VDD bias voltage generator for LCD application
Support fast wake-up
Eight levels of LVR reset ~ 4.1V, 3.6V, 3.1V, 2.8V, 2.5V, 2.2V, 2.0V, 1.8V
16 IO pins with 10mA capability and optional pull-high resistor
Two external interrupt pins
Every IO pin can be configured to enable wake-up function
Operating frequency range:
DC ~ 8MHz@VDD≧3.3V; DC ~ 4MHz@VDD≧2.5V; DC ~ 2MHz@VDD≧2.2V
Operating voltage range: 2.2V ~ 5.5V
Low power consumption
Ioperating ~ 1.7mA@1MIPS, VDD=5.0V
Ioperating ~ 8uA@ILRC=12KHz, VDD=3.3V
Ipowerdown ~ 0.7uA@VDD=5.0V
Ipowerdown
~ 0.4uA@VDD=3.3V
1.3. CPU Features
Operating modes: Two processing units FPPATM mode or Traditional one processing unit mode
1KW OTP program memory
64 Bytes data RAM
101 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer and adjustable stack level
All data memories are available for use as an index pointer
Separated IO space and memory space
©Copyright 2015, PADAUK Technology Co. Ltd
Page 8 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
1.4. Package Information
PMC271 series
PMC271 - S14: SOP14 (150mil);
PMC271 - S16: SOP16 (150mil) ;
PMC271 - S18: SOP18 (300mil) ;
PMC271 - Y16: SSOP16 (150mil);
PMC271 - Y20: SSOP20 (150mil);
PMC271 - D14: DIP14 (300mil);
PMS271 series
PMS271 - S14: SOP14 (150mil);
PMS271 - S16: SOP16 (150mil) ;
PMS271 - S18: SOP18 (300mil) ;
PMS271 - Y16: SSOP16 (150mil);
PMS271 - Y20: SSOP20 (150mil);
PMS271 - D14: DIP14 (300mil);
©Copyright 2015, PADAUK Technology Co. Ltd
Page 9 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
2. General Description and Block Diagram
The PMC271/PMS271 series is an ADC-Type of PADAUK’s parallel processing, fully static, OTP-based CMOS
two 8 bit processor array that can execute two peripheral functions in parallel. Besides operated in two
processing units, PMC271/PMS271 can act as traditional MCU in one processing unit. The PMC271/PMS271
employs RISC architecture based on patented FPPA™ (Field Programmable Processor Array) technology and
most the instructions are executed in one cycle except that few instructions are two cycles that handle indirect
memory access.
1KW bits OTP program memory and 64 bytes data SRAM are inside for two FPP units using, PMC271/PMS271
provides one hardware 16-bit timer, one 8 channels 8-bit ADC and hardware circuit to generate half VDD bias
voltage for LCD application. The functions for peripheral devices like UART and PWM can be easily
implemented by using FPPA™ unique architecture.
FPP0
Internal Processor Bus
PWM
Function
Internal Processor Bus
1KW OTP
&
Task
Control
I2C
Function
SPI
Function
Interrupt
controller
16-bit Timer
IO Ports
64 Bytes
SRAM
FPP1
8-Bit ADC
UART
Function
POR / LVD
Key scan
Function
Watchdog
Timer
LCD
Function
Power
management
©Copyright 2015, PADAUK Technology Co. Ltd
Page 10 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
3. Pin Assignment and Description
PMC271 series
PA2/COM2
1
14
PA1/COM1
PA2/COM2
1
16
PA1/COM1
PA3/AD5/COM3
2
13
PA0/INT0
PA3/AD5//COM3
2
15
PA0/INT0
PA4/AD6/COM4
3
12
PA7/X1
PA4/AD6/COM4
3
14
PA7/X1
PA5/PRST#
4
11
PA6/X2
PA5/PRST#
4
13
PA6/X2
GND
5
10
VDD
PB0/INT1/AD0
6
9
PB7/AD4
PB1/AD1
7
8
PB6
PMC271 (SOP14-150mil)
PMC271 (DIP14-300mil)
GND
5
12
VDD
PB0/INT1/AD0
6
11
PB7/AD4
PB1/AD1
7
10
PB6
PB2/AD2
8
9
PB5
PMC271 (SSOP16-150mil)
PMC271 (SOP16-150mil)
PA2/COM2
1
18
PA1/COM1
PA2/COM2
1
20
PA1/COM1
PA3/AD5/COM3
2
17
PA0/INT0
PA3/AD5/COM3
2
19
PA0/INT0
3
18
PA7/X1
PA4/AD6/COM4
3
16
PA7/X1
PA4/AD6/COM4
PA5/PRST#
4
15
PA6/X2
PA5/PRST#
4
17
PA6/X2
GND
5
16
VDD
GND
5
14
VDD
PB0/INT1/AD0
6
13
PB7/AD4
NC
6
15
NC
12
PB6
PB0/INT1//AD0
7
14
PB7/AD4
PB1/AD1
7
PB2/AD2
8
11
PB5
PB1/AD1
8
13
PB6
PB3/AD3
9
10
PB4
PB2/AD2
9
12
PB5
PB3/AD3
10
11
PB4
PMC271 (SOP18-300mil)
PMC271 (SSOP20-150mil)
©Copyright 2015, PADAUK Technology Co. Ltd
Page 11 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
PMS271 series
PA2/COM2
1
14
PA1/COM1
PA2/COM2
1
16
PA1/COM1
PA3/AD5/COM3
2
13
PA0/INT0
PA3/AD5//COM3
2
15
PA0/INT0
PA4/AD6/COM4
3
12
PA7/X1
PA4/AD6/COM4
3
14
PA7/X1
PA5/PRST#
4
11
PA6/X2
PA5/PRST#
4
13
PA6/X2
GND
5
10
VDD
GND
5
12
VDD
PB0/INT1/AD0
6
9
PB7/AD4
PB0/INT1/AD0
6
11
PB7/AD4
PB1/AD1
7
8
PB6
PB1/AD1
7
10
PB6
PB2/AD2
8
9
PB5
PMS271 (SOP14-150mil)
PMS271 (DIP14-300mil)
PMS271 (SSOP16-150mil)
PMS271 (SOP16-300mil)
PA2/COM2
1
20
PA1/COM1
PA0/INT0
PA3/AD5/COM3
2
19
PA0/INT0
PA7/X1
PA4/AD6/COM4
3
18
PA7/X1
PA5/PRST#
4
17
PA6/X2
GND
5
16
VDD
NC
6
15
NC
PA2/COM2
1
18
PA1/COM1
PA3/AD5/COM3
2
17
PA4/AD6/COM4
3
16
PA5/PRST#
4
15
PA6/X2
GND
5
14
VDD
PB0/INT1/AD0
6
13
PB7/AD4
PB1/AD1
7
12
PB6
PB0/INT1//AD0
7
14
PB7/AD4
PB2/AD2
8
11
PB5
PB1/AD1
8
13
PB6
PB3/AD3
9
10
PB4
PB2/AD2
9
12
PB5
PB3/AD3
10
11
PB4
PMS271 (SOP18-300mil)
PMS271 (SSOP20-150mil)
©Copyright 2015, PADAUK Technology Co. Ltd
Page 12 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Pin Description
Pin Name
Pin & Buffer
Type
Description
The functions of this pin can be:
IO
PA7/X1
ST / CMOS
/ Analog
(1) Bit 7 of port A. It can be configured as input or output with pull-up resistor.
(2) X1 (input) when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed
“0” to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
IO
PA6/X2
ST / CMOS
/ Analog
(1) Bit 6 of port A. It can be configured as input or output with pull-up resistor.
(2) X2 (output) when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed
“0” to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as input or open-drain output pin. Please
notice that there is no pull-up resistor in this pin.
PA5/PRST#
IO
(2) Hardware reset.
ST / CMOS This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”.
Please put 33Ω resistor in series to have high noise immunity when this pin is in
input mode.
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as input or output with pull-up resistor.
IO
PA4/AD6/COM4 ST / CMOS /
Analog
(2) Channel 6 input of ADC.
(3) COM4 for LCD to provide (1/2 VDD) for LCD bias voltage.
If this pin acts as analog input, bit 4 of padier register must be programmed “0” to
avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 4 of
padier register is “0”
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as input or output with pull-up resistor.
IO
PA3/AD5/COM3 ST / CMOS /
Analog
(2) Channel 5 input of ADC.
(3) COM3 for LCD to provide (1/2 VDD) for LCD bias voltage.
If this pin acts as analog input, bit 3 of padier register must be programmed “0” to
avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 3 of
padier register is “0”.
©Copyright 2015, PADAUK Technology Co. Ltd
Page 13 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
PA2/COM2
IO
ST / CMOS
(1) Bit 2 of port A. It can be configured as input or output with pull-up resistor.
(2) COM2 for LCD to provide (1/2 VDD) for LCD bias voltage.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 2 of padier register is “0”.
The functions of this pin can be:
PA1/COM1
IO
ST / CMOS
(1) Bit 1 of port A. It can be configured as input or output with pull-up resistor.
(2) COM1 for LCD to provide (1/2 VDD) for LCD bias voltage.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 1 of padier register is “0”.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as input or output with pull-up resistor.
PA0/INT0
IO
ST / CMOS
(2) External interrupt line 0. Both rising edge and falling edge are accepted to
request interrupt service.
This pin can be used to wake-up system during sleep mode, however, wake-up
function from this pin is also disabled when bit 0 of padier register is “0”. Both
rising edge and falling edge are accepted to request interrupt service.
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as input or output with pull-up resistor.
IO
PB7/AD4
(2) Channel 4 input of ADC.
ST / CMOS / If this pin acts as analog input, bit 7 of pbdier register must be programmed “0”
Analog
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 7 of
pbdier register is “0”.
The function of this pin is Bit 6 of port B. It can be configured as input or output
PB6
IO
ST / CMOS
with pull-up resistor.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 6 of pbdier register is “0”.
The function of this pin is Bit 5 of port B. It can be configured as input or output
PB5
IO
ST / CMOS
with pull-up resistor.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 5 of pbdier register is “0”.
The function of this pin is Bit 4 of port B. It can be configured as input or output
PB4
IO
ST / CMOS
with pull-up resistor.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 4 of pbdier register is “0”.
©Copyright 2015, PADAUK Technology Co. Ltd
Page 14 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as input or output with pull-up resistor.
IO
PB3/AD3
(2) Channel 3 input of ADC.
ST / CMOS / If this pin acts as analog input, bit 3 of pbdier register must be programmed “0”
Analog
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 3 of
pbdier register is “0”.
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as input or output with pull-up resistor.
IO
PB2/AD2
(2) Channel 2 input of ADC.
ST / CMOS / If this pin acts as analog input, bit 2 of pbdier register must be programmed “0”
Analog
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 2 of
pbdier register is “0”.
The functions of this pin can be:
(1) Bit 1 of port B. It can be configured as input or output with pull-up resistor.
IO
PB1/AD1
(2) Channel 1 input of ADC.
ST / CMOS / If this pin acts as analog input, bit 1 of pbdier register must be programmed “0”
Analog
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 1 of
pbdier register is “0”.
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as input or output with pull-up resistor.
(2) External interrupt line 1. Both rising edge and falling edge are accepted to
IO
PB0/INT1/AD0
request interrupt service.
ST / CMOS / (3) Channel 0 input of ADC.
Analog
If this pin acts as analog input, bit 0 of pbdier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 0 of
pbdier register is “0”.
VDD
Positive power
GND
Ground
Notes: IO: Input/Output; ST: Schmitt Trigger input; Analog: Analog input pin; CMOS: CMOS voltage level
©Copyright 2015, PADAUK Technology Co. Ltd
Page 15 of 85
PDK-DS-PMX271-EN_V004 – June 11, 2015
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4. Device Characteristics
4.1. DC/AC Characteristics
All data are acquired under the conditions of Ta = - 40 oC ~ 85 oC, Vdd=5.0V, fSYS=2MHz unless noted.
Symbol
Description
Min
Typ
Max
Unit
Conditions
VDD
fSYS
Operating Voltage
System clock* =
IHRC/2
IHRC/4 & crystal oscillator
IHRC/8 & crystal oscillator
ILRC
2.2
5.0
0
0
0
5.5
8M
4M
2M
V
fSYS = 2MHz
Hz
Under_20ms_Vdd_ok**=Y/N
VDD≧3.0V / VDD≧3.3V
VDD≧2.5V / VDD≧2.8V
VDD≧2.2V / VDD≧2.2V
VDD = 5.0V
24K
IOP
Operating Current
1.7
8
mA
uA
fSYS=1MIPS@5.0V
fSYS=ILRC=12KHz@3.3V
IPD
Power Down Current
(by stopsys command)
0.7
0.4
uA
uA
fSYS= 0Hz,VDD=5.0V
fSYS= 0Hz,VDD=3.3V
IPS
Power Save Current
(by stopexe command)
0.4
mA
VDD=5.0V;
Band-gap, LVR, IHRC, ILRC,
Timer16 modules are ON.
VIL
Input low voltage for IO lines
0
0.3VDD
V
VIH
Input high voltage for IO lines
0.7 VDD
VDD
V
IOL
IO lines sink current
13
mA
VDD=5.0V, VOL=0.5V
VDD=5.0V, VOH=4.5V
IOH
IO lines drive current
VIN
Input voltage
IINJ (PIN)
RPH
VBRD
10
-5
-7
-0.3
Injected current on pin
Low Voltage Detect Voltage *
(Brown-out voltage)
Band-gap Reference Voltage *
(after calibration)
©Copyright 2015, PADAUK Technology Co. Ltd
-9
mA
VDD+0.3
V
1
mA
VDD+0.3≧VIN≧ -0.3
KΩ
VDD=5.0V
VDD=3.3V
VDD=2.2V
62
100
210
Pull-high Resistance
Band-gap Reference Voltage
(before calibration)
VBG
7
3.86
3.35
2.84
2.61
2.37
2.04
1.86
1.67
4.15
3.60
3.05
2.80
2.55
2.20
2.00
1.80
4.44
3.85
3.26
3.00
2.73
2.35
2.14
1.93
1.104*
1.109*
1.200*
1.200*
1.296*
1.291*
1.140*
1.145*
1.200*
1.200*
1.260*
1.255*
Page 16 of 85
V
V
VDD=2.2V ~ 5.5V
-40oC
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