FM25F01
1M-BIT SERIAL FLASH MEMORY
Datasheet
Oct. 2016
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
1
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FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
2
1. Description
The FM25F01 is a 1M-bit (128K-byte) Serial Flash
memory,
with
advanced
write
protection
mechanisms. The FM25F01 supports the standard
Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Dual I/O.
The FM25F01 can be programmed 1 to 256 bytes at
a time, using the Page Program instruction. It is
designed to allow either single Sector/Block at a
time or full chip erase operation. The FM25F01
can be configured to protect part of the memory as
the software protected mode. The device can
sustain a minimum of 100K program/erase cycles on
each sector or block.
2. Features
1Mbit of Flash memory
– 32 uniform sectors with 4K-byte each
– 2 uniform blocks with 64K-byte each
– 4 uniform blocks with 32K-byte each
– 256 bytes per programmable page
Wide Operation Range
– 2.3V~3.6V single voltage supply
– Industrial temperature range
Serial Interface
– Standard SPI: CLK, CS#, DI, DO, WP#
– Dual SPI: CLK, CS#, DQ0, DQ1, WP#
– Continuous READ mode support
High Performance
– Max FAST_READ clock frequency: 100MHz
– Max READ clock frequency: 50MHz
– Typical page program time: 1.5ms
– Typical sector erase time: 90ms
– Typical block erase time: 500ms
– Typical chip erase time: 1.5s
Low Power Consumption
– Typical standby current: 1µA
Security
– Software and hardware write protection
– Lockable 256-Byte OTP security sectors
– Low Voltage Write Inhibit
– 64-Bit Unique ID for each device
High Reliability
– Endurance: 100,000 program/erase cycles
– Data retention: 20 years
Green Package
– 8-pin SOP (150mil)
– 8-pin TSSOP
– 8-pin TDFN (2x3mm)
– All Packages are RoHS Compliant and Halogenfree
3. Packaging Type
SOP 8 (150mil)
CS#
DO(DQ1)
1
2
8
7
VCC
WP#
VSS
3
4
6
5
CLK
DI(DQ0)
HOLD#
TSSOP8
CS#
DO(DQ1)
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
CLK
DI(DQ0)
TDFN8 (2x3mm)
CS#
DO(DQ1)
WP#
VSS
1
2
3
4
8 VCC
7 HOLD#
6 CLK
5 DI(DQ0)
4. Pin Configurations
PIN PIN
I/O
FUNCTION
NO. NAME
1
CS#
I Chip Select Input
DO
Data Output (Data Input Output
2
I/O (1)
(DQ1)
1)
3
WP#
I Write Protect Input
4
VSS
Ground
DI
Data Input (Data Input Output
5
I/O (1)
(DQ0)
0)
6
CLK
I Serial Clock Input
7 HOLD# I Hold Input
8
VCC
Power Supply
Note:
1 DQ0 and DQ1 are used for Dual SPI instructions.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
3
5.
Block Diagram
Figure 1 FM25F01 Serial Flash Memory Block Diagram
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
4
6.
Pin Descriptions
Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and
output operations.
Serial Data Input, Output and I/Os (DI, DO and DQ0, DQ1): The FM25F01 supports standard
SPI and Dual SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to
serially write instructions, addresses or data to the device on the rising edge of the Serial Clock
(CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status
from the device on the falling edge of CLK.
Dual SPI instructions use the bidirectional DQ pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the
falling edge of CLK.
Chip Select (CS#): The SPI Chip Select (CS#) pin enables and disables device operation.
When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ0, DQ1) pins
are at high impedance. When deselected, the devices power consumption will be at standby
levels unless an internal erase, program or write status register cycle is in progress. When CS#
is brought low, the device will be selected, power consumption will increase to active levels and
instructions can be written to and data read from the device. After power-up, CS# must transition
from high to low before a new instruction will be accepted. The CS# input must track the VCC
supply level at power-up (see “9 Write Protection” and Figure 25). If needed a pull-up resister on
CS# can be used to accomplish this.
HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected.
When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device
operation can resume. The HOLD# function can be useful when multiple devices are sharing the
same SPI signals. The HOLD# pin is active low.
Write Protect (WP#): The Write Protect (WP#) pin can be used to prevent the Status Registers
from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1 and
BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire
memory array can be hardware protected. The WP# pin is active low.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
5
7.
Memory Organization
The FM25F01 array is organized into 512 programmable pages of 256-bytes each. Up to 256
bytes can be programmed (bits are programmed from 1 to 0) at a time. Pages can be erased in
groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block
erase) or the entire chip (chip erase). The FM25F01 has 32 erasable sectors , 4 erasable 32-k
byte blocks and 2 erasable 64-k byte blocks respectively. The small 4KB sectors allow for
greater flexibility in applications that require data and parameter storage.
Table 1
Block
(64KB)
1
0
Block
(32KB)
3
2
1
0
Sector
(4KB)
31
:
16
15
:
3
2
1
0
Sector
(4KB)
31
:
25
24
23
:
17
16
15
:
9
8
7
:
1
0
FM25F01 1M-BIT SERIAL FLASH MEMORY
Memory Organization
Address Range
01F000h
:
010000h
00F000h
:
003000h
002000h
001000h
000000h
01FFFFh
:
010FFFh
00FFFFh
:
003FFFh
002FFFh
001FFFh
000FFFh
Address Range
01F000h
:
019000h
018000h
017000h
:
011000h
010000h
00F000h
:
009000h
008000h
007000h
:
001000h
000000h
Ver. 1.5
01FFFFh
:
019FFFh
018FFFh
017FFFh
:
011FFFh
010FFFh
00FFFFh
:
009FFFh
008FFFh
007FFFh
:
001FFFh
000FFFh
Datasheet
6
8.
Device Operations
8.1.
Standard SPI
The FM25F01 is accessed through an SPI compatible bus consisting of four signals: Serial
Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write instructions, addresses or data to the device
on the rising edge of CLK. The DO output pin is used to read data or status from the device on
the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between
Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in
standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is
normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high
on the falling and rising edges of CS#.
Figure 2 The difference between Mode 0 and Mode 3
8.2.
Dual SPI
The FM25F01 supports Dual SPI operation when using instructions such as “Fast Read Dual
Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to
or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI
Read instructions are ideal for quickly downloading code to RAM upon power-up (codeshadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using
Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: DQ0 and DQ1.
8.3.
Hold
For Standard SPI and Dual SPI operations, the HOLD# signal allows the FM25F01 operation to
be paused while it is actively selected (when CS# is low). The HOLD# function may be useful in
cases where the SPI data and clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a priority interrupt requires use of the
SPI bus. In this case the HOLD# function can save the state of the instruction and the data in the
buffer so programming can resume where it left off once the bus is available again.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition
will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is
not already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD#
condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If
the CLK is not already low the HOLD# condition will terminate after the next falling edge of CLK.
During a HOLD# condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
7
active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic state
of the device.
Figure 3 Hold Condition Waveform
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
8
9.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise
and other adverse system conditions that may compromise data integrity. To address this
concern, the FM25F01 provides several means to protect the data from inadvertent writes.
Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (WP# pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Sectors using Status
Register.
Upon power-up or at power-down, the FM25F01 will maintain a reset condition while VCC is
below the threshold value of VWI, (See “12.3 Power-up Timing” and Figure 25). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time
delay of tPUW . This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip
Erase and the Write Status Register instructions. Note that the chip select pin (CS#) must track
the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If
needed a pull-up resister on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status
Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will
be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL)
is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and
setting the Status Register Protect (SRP) and Block Protect (BP2, BP1 and BP0) bits. These
settings allow a portion as small as a 4KB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register
can be enabled or disabled under hardware control. See Status Register section for further
information. Additionally, the Power-down instruction offers an extra level of write protection as
all instructions are ignored except for the Release Power-down instruction.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
9
10.
Status Register
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, the state of write protection, Security
Sector lock status. The Write Status Register instruction can be used to configure the device write
protection features and Security Sector OTP lock. Write access to the Status Register is
controlled by the state of the non-volatile Status Register Protect bit (SRP), the Write Enable
instruction, and the WP# pin.
Factory default for all Status Register bits are 0.
Figure 4 Status Register
10.1.
WIP Bit
WIP is a read only bit in the status register (S0) that is set to a 1 state when the device is
executing a Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register.
During this time the device will ignore further instructions except for the Read Status Register
(see tW, tPP, tSE, tBE, and tCE in “12.6 AC Electrical Characteristics”). When the program, erase or
write status register (or security sector) instruction has completed, the WIP bit will be cleared to a
0 state indicating the device is ready for further instructions.
10.2.
Write Enable Latch bit (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after
executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write
disabled. A write disable state occurs upon power-up or after any of the following instructions:
Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register.
10.3.
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
10
the Write Status Register Instruction (see tW in “12.6 AC Electrical Characteristics”). All, none or
a portion of the memory array can be protected from Program and Erase instructions (see Table
2 Status Register Memory Protection). The factory default setting for the Block Protection Bits is
0, none of the array protected.
10.4.
Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect
from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Table 2 Status Register
Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the
Write Status Register Instruction depending on the state of the SRP and WEL bits.
10.5.
Status Register Protect bit / Lock_bit (SRP/LB)
The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is
set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status
Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR)
instruction is no longer accepted for execution.
In OTP mode, this bit is served as Lock_bit (LB), user can read/program/erase security sector as
normal sector while LB value is equal 0, after LB is programmed with 1 by WRSR command, the
security sector is protected from program and erase operation. The LB can only be programmed
once.
Note : In OTP mode, the WRSR command will ignore any input data and program LB to 1, user
must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the Security sector before leaving OTP mode.
10.6.
Status Register Memory Protection
Table 2
Status Register Memory Protection
Status Register Content
TB
bit
X
0
1
X
BP2
bit
X
X
X
X
BP1
bit
0
0
0
1
BP0
bit
0
1
1
X
FM25F01 1M-BIT SERIAL FLASH MEMORY
Memory Content
Address
None
010000h-01FFFFh
000000h-00FFFFh
000000h-01FFFFh
Ver. 1.5
Density (KB)
None
64KB
64KB
128KB
Portion
None
Upper 1/2
Lower 1/2
All
Datasheet
11
11.
Instructions
The Standard/Dual SPI instruction set of the FM25F01 consists of 17 basic instructions that are
fully controlled through the SPI bus (see Table 4~Table 5 Instruction Set). Instructions are
initiated with the falling edge of Chip Select (CS#). The first byte of data clocked into the DI input
provides the instruction code. Data on the DI input is sampled on the rising edge of clock with
most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address
bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are
completed with the rising edge of edge CS#. Clock relative timing diagrams for each instruction
are included in Figure 5 through Figure 29. All read instructions can be completed after any
clocked bit. However, all instructions that Write, Program or Erase must complete on a byte
boundary (CS# driven high after a full 8-bits have been clocked) otherwise the instruction will be
ignored. This feature further protects the device from inadvertent writes. Additionally, while the
memory is being programmed or erased, or when the Status Register is being written, all
instructions except for Read Status Register will be ignored until the program or erase cycle has
completed.
11.1.
Manufacturer and Device Identification
Table 3
Manufacturer and Device Identification
OP Code
MF7-MF0
ABh
90h
9Fh
11.2.
ID15-ID0
ID7-ID0
10h
10h
A1h
A1h
3111h
Standard SPI Instructions Set
Table 4
INSTRUCTION
BYTE 1
NAME
CLOCK NUMBER
(0-7)
Write Enable
06h
Write Disable
04h
Read Status
05h
Register
Write Status Register 01h
Page Program
02h
Sector Erase (4KB)
20h
Block Erase (32KB)
52h
Block Erase (64KB)
D8h
Chip Erase
C7h/60h
Power-down
B9h
Read Data
03h
Fast Read
0Bh
Release Powerdown
ABh
/ ID(4)
FM25F01 1M-BIT SERIAL FLASH MEMORY
Standard SPI Instructions Set (1)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(8-15)
(16-23)
(24-31)
(32-39)
(40-47)
(S7-S0)
A23-A16
A23-A16
A23-A16
A23-A16
(S15-S8)
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0(3)
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(S7-S0)(2)
dummy
dummy
Ver. 1.5
dummy
(D7-D0)
(2)
(ID7-ID0)
Datasheet
12
INSTRUCTION
BYTE 1
NAME
Read Unique ID
4Bh
Manufacturer/Device
90h
ID(4)
11.3.
JEDEC ID(4)
9Fh
Enter OTP mode
3Ah
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
dummy
dummy
dummy
dummy
(UID63-UID0)
(MF7-MF0)
(ID7-ID0)
dummy
dummy
(MF7-MF0)
Manufacturer
00h
(ID15-ID8)
(ID7-ID0)
Memory
Capacity
Type
Dual SPI Instructions Set
Table 5
INSTRUCTION
NAME
CLOCK NUMBER
Fast Read Dual
Output
Fast Read Dual I/O
Dual SPI Instructions Set
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(0-7)
(8-15)
(16-23)
(24-31)
(32-39)
(40-47)
3Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, R)(6)
BBh
A23-A8(5)
A7-A0, M7M0 (5)
(D7D0, R)(6)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )”
indicate data output from the device on 1 or 2 DQ pins.
2. The Status Register contents and Device ID will repeat continuously until CS# terminates the
instruction.
3. At least one byte of data input is required for Page Program and Program Security Sectors,
up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the
addressing will wrap to the beginning of the page and overwrite previously sent data.
4. See Table 3 Manufacturer and Device Identification table for device ID information.
5. Dual SPI address input format:
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
6. Dual SPI data output format:
DQ0 = (D6, D4, D2, D0)
DQ1 = (D7, D5, D3, D1)
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
13
11.4.
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the
Status Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase,
Block Erase, Chip Erase, Write Status Register instruction. The Write Enable (WREN) instruction
is entered by driving CS# low, shifting the instruction code “06h” into the Data Input (DI) pin on
the rising edge of CLK, and then driving CS# high.
Figure 5 Write Enable Instruction
11.5.
Write Disable (WRDI) (04h)
The Write Disable (WRDI) instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the
Status Register to a 0. The Write Disable (WRDI) instruction is entered by driving CS# low,
shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL
bit is automatically reset after Power-up and upon completion of the Write Status Register, Page
Program, Sector Erase, Block Erase, Chip Erase instructions.
Figure 6 Write Disable Instruction
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
14
11.6.
Read Status Register (RDSR) (05h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction
is entered by driving CS# low and shifting the instruction code “05h” into the DI pin on the rising
edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of
CLK with most significant bit (MSB) first as shown in Figure 7. The Status Register bits are
shown in Figure 4 and include the WIP, WEL, BP2-BP0 and SRP bits.
The Read Status Register instruction may be used at any time, even while a Program, Erase or
Write Status Register cycle is in progress. This allows the WIP status bit to be checked to
determine when the cycle is complete and if the device can accept another instruction. The
Status Register can be read continuously. The instruction is completed by driving CS# high.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (05h)
DI
(DQ0)
Status Register out
Status Register out
High Impedance
D0
(DQ1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
=MSB
Figure 7 Read Status Register Instruction
11.7.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows the Status Register to be written. Only nonvolatile Status Register bits SRP, BP2, BP1, BP0 can be written to. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register (WRSR) instruction.
The Status Register bits are shown in Figure 4, and described in 10 Status Register.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must
previously have been executed for the device to accept the Write Status Register (WRSR)
instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered
by driving CS# low, sending the instruction code “01h”, and then writing the status register data
byte as illustrated in Figure 8.
To complete the Write Status Register (WRSR) instruction, the CS# pin must be driven high after
the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register
(WRSR) instruction will not be executed.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See
“12.6 AC Electrical Characteristics”). While the Write Status Register cycle is in progress, the
Read Status Register instruction may still be accessed to check the status of the WIP bit. The
WIP bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and
ready to accept other instructions again. After the Write Status Register cycle has finished, the
Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
15
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
1
0
Mode 0
Instruction (01h)
DI
(DQ0)
Status Register in
7
6
5
4
3
2
High Impedance
D0
(DQ1)
=MSB
Figure 8 Write Status Register Instruction
11.8.
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the
memory. The instruction is initiated by driving the CS# pin low and then shifting the instruction
code “03h” followed by a 24-bit address A23-A0 into the DI pin. The code and address bits are
latched on the rising edge of the CLK pin. After the address is received, the data byte of the
addressed memory location will be shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first. The address is automatically incremented to the next higher
address after each byte of data is shifted out allowing for a continuous stream of data. This
means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in Figure 9. If a Read Data instruction is issued
while an Erase, Program or Write cycle is in process (WIP =1) the instruction is ignored and will
not have any effect on the current cycle. The Read Data instruction allows clock rates from D.C.
to a maximum of fR (see “12.6 AC Electrical Characteristics”).
The Read Data (03h) instruction is only supported in Standard SPI mode.
Figure 9 Read Data Instruction
11.9.
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see “12.6 AC Electrical Characteristics”). This is accomplished
by adding eight “dummy” clocks after the 24-bit address as shown in Figure 10. The dummy
clocks allow the devices internal circuits additional time for setting up the initial address. During
the dummy clocks the data value on the DI pin is a “don’t care”.
FM25F01 1M-BIT SERIAL FLASH MEMORY
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16
Figure 10 Fast Read Instruction
11.10. Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh)
instruction except that data is output on two pins; DQ0 and DQ1. This allows data to be
transferred from the FM25F01 at twice the rate of standard SPI devices. The Fast Read Dual
Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for
applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the
highest possible frequency of FR (see “12.6 AC Electrical Characteristics”). This is accomplished
by adding eight “dummy” clocks after the 24-bit address as shown in Figure 11. The dummy
clocks allow the device's internal circuits additional time for setting up the initial address. The
input data during the dummy clocks is “don’t care”. However, the DQ0 pin should be highimpedance prior to the falling edge of the first data out clock.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
17
Figure 11
Fast Read Dual Output Instruction
11.11. Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining
two I/O pins, DQ0 and DQ1. It is similar to the Fast Read Dual Output (3Bh) instruction but with
the capability to input the Address bits A23-A0 two bits per clock. This reduced instruction
overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 12.
The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction
through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the
(M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling
edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction
(after CS# is raised and then lowered) does not require the BBh instruction code, as shown in
Figure 13. This reduces the instruction sequence by eight clocks and allows the Read address to
be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (1,0), the next instruction (after CS# is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on
DQ0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal
operation.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
18
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (BBh)
A23-16
DI
(DQ0)
D0
(DQ1)
A15-8
A7-0
M7-0
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
23
21
19
17
15
13
11
9
7
5
3
1
7
5
3
1
33
34
35
36
37
38
39
=MSB
CS#
23
24
25
26
27
28
29
30
31
32
CLK
IOs switch from
Input to Output
DI
(DQ0)
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
D0
(DQ1)
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte 1
Byte 2
Byte 3
Byte 4
Figure 12 Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10)
Figure 13 Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10)
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
19
11.12. Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be
programmed at previously erased (FFh) memory locations. A Write Enable instruction must be
executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1).
The instruction is initiated by driving the CS# pin low then shifting the instruction code “02h”
followed by a 24-bit address A23-A0 and at least one data byte, into the DI pin. The CS# pin must
be held low for the entire length of the instruction while data is being sent to the device. The Page
Program instruction sequence is shown in Figure 14.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant
address bits) should be set to 0. If the last address byte is not zero, and the number of clocks
exceeds the remaining page length, the addressing will wrap to the beginning of the page. In
some cases, less than 256 bytes (a partial page) can be programmed without having any effect
on other bytes within the same page. One condition to perform a partial page program is that the
number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to
the device the addressing will wrap to the beginning of the page and overwrite previously sent
data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the
last byte has been latched. If this is not done the Page Program instruction will not be executed.
After CS# is driven high, the self-timed Page Program instruction will commence for a time
duration of tPP (See “12.6 AC Electrical Characteristics”). While the Page Program cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of
the WIP bit. The WIP bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Page Program cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page
Program instruction will not be executed if the addressed page is protected by the Block Protect
(BP2, BP1, and BP0) bits.
Figure 14 Page Program Instruction
11.13. Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased
state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept
the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by
driving the CS# pin low and shifting the instruction code “20h” followed a 24-bit sector address
A23-A0 (see Figure 1). The Sector Erase instruction sequence is shown in Figure 15 .
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
20
done the Sector Erase instruction will not be executed. After CS# is driven high, the self-timed
Sector Erase instruction will commence for a time duration of tSE (See “12.6 AC Electrical
Characteristics”). While the Sector Erase cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during
the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to
accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed
if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Table 2
Status Register Memory Protection table).
Figure 15 Sector Erase Instruction
11.14. 32KB Block Erase (BE32) (52h)
The 32KB Block Erase instruction sets all memory within a specified block (32K-bytes) to the
erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will
accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is
initiated by driving the CS# pin low and shifting the instruction code “52h” followed a 24-bit block
address A23-A0. The Block Erase instruction sequence is shown in Figure 16.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After CS# is driven high, the self-timed
Block Erase instruction will commence for a time duration of tBE2 (See 12.6 AC Electrical
Characteristics”). While the Block Erase cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Block
Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Block Erase instruction will not be executed if the
addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Table 2 Status
Register Memory Protection table).
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
21
Figure 16 32KB Block Erase Instruction (SPI Mode)
11.15. 64KB Block Erase (BE) (D8h)
The 64KB Block Erase instruction sets all memory within a specified block (64K-bytes) to the
erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will
accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is
initiated by driving the CS# pin low and shifting the instruction code “D8h” followed a 24-bit block
address A23-A0. The Block Erase instruction sequence is shown in Figure 17.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After CS# is driven high, the self-timed
Block Erase instruction will commence for a time duration of tBE1 (See 12.6 AC Electrical
Characteristics”). While the Block Erase cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Block
Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Block Erase instruction will not be executed if the
addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Table 2 Status
Register Memory Protection table).
Figure 17 Block Erase Instruction
11.16. Chip Erase (CE) (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
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Write Enable instruction must be executed before the device will accept the Chip Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS#
pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is
shown in Figure 18.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After CS# is driven high, the self-timed Chip Erase
instruction will commence for a time duration of tCE (See “12.6 AC Electrical Characteristics”).
While the Chip Erase cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and
becomes a 0 when finished and the device is ready to accept other instructions again. After the
Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect
(BP2, BP1, and BP0) bits.
Figure 18 Chip Erase Instruction
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Ver. 1.5
Datasheet
23
11.17. Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be
further reduced with the Power-down instruction. The lower power consumption makes the
Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in
12.4 DC Electrical Characteristics”). The instruction is initiated by driving the CS# pin low and
shifting the instruction code “B9h” as shown in Figure 19.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the
Power-down instruction will not be executed. After CS# is driven high, the power-down state will
enter within the time duration of tDP (See “12.6 AC Electrical Characteristics”). While in the powerdown state only the Release from Power- down / Device ID instruction, which restores the device
to normal operation, will be recognized. All other instructions are ignored. This includes the Read
Status Register instruction, which is always available during normal operation. Ignoring all but
one instruction makes the Power Down state a useful condition for securing maximum write
protection. The device always powers-up in the normal operation with the standby current of ICC1.
Figure 19 Deep Power-down Instruction
11.18. Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be
used to release the device from the power-down state, or obtain the devices electronic
identification (ID) number.
To release the device from the power-down state, the instruction is issued by driving the CS# pin
low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 20. Release from
power-down will take the time duration of tRES1 (See “12.6 AC Electrical Characteristics”) before
the device will resume normal operation and other instructions are accepted. The CS# pin must
remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is
initiated by driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy
bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit
(MSB) first as shown in Figure 20. The Device ID value for the FM25F01 is listed in Table 3
Manufacturer and Device Identification table. The Device ID can be read continuously. The
instruction is completed by driving CS# high.
When used to release the device from the power-down state and obtain the Device ID, the
instruction is the same as previously described, and shown in Figure 21, except that after CS# is
driven high it must remain high for a time duration of tRES2 (See “12.6 AC Electrical
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
24
Characteristics”). After this time duration the device will resume normal operation and other
instructions will be accepted. If the Release from Power-down / Device ID instruction is issued
while an Erase, Program or Write cycle is in process (when WIP equals 1) the instruction is
ignored and will not have any effect on the current cycle.
Figure 20 Release Power-down Instruction
Figure 21 Release Power-down / Device ID Instruction
11.19. Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific
device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down /
Device ID instruction. The instruction is initiated by driving the CS# pin low and shifting the
instruction code “90h” followed by a 24-bit address A23-A0 of 000000h. After which, the
Manufacturer ID for Shanghai Fudan Microelectronics Group Co., Ltd (A1h) and the Device ID
are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure
22. The Device ID value for the FM25F01 is listed in Table 3 Manufacturer and Device
Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first
and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
25
Figure 22 Read Manufacturer / Device ID Instruction
11.20. Read Unique ID Number(4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is
unique to each FM25F01 device. The ID number can be used in conjunction with user software
methods to help prevent copying or cloning of a system. The Read Unique ID instruction is
initiated by driving the CS# pin low and shifting the instruction code “4Bh” followed by a four bytes
of dummy clocks. After which, the 64- bit ID is shifted out on the falling edge of CLK as shown in
Figure 23.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
26
102
101
100
Figure 23 Read Unique ID Number Instruction (SPI Mode only)
11.21. Read JEDEC ID (9Fh)
For compatibility reasons, the FM25F01 provides several instructions to electronically determine
the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard
for SPI compatible serial memories. The instruction is initiated by driving the CS# pin low and
shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Shanghai
Fudan Microelectronics Group Co., Ltd (A1h) and two Device ID bytes, Memory Type (ID15-ID8)
and Capacity ID7-ID0 are then shifted out on the falling edge of CLK with most significant bit
(MSB) first as shown in Figure 24. For memory type and capacity values refer to Table 3
Manufacturer and Device Identification table.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
27
Figure 24 Read JEDEC ID Instruction
11.22. Enter OTP Mode (3Ah)
This Flash has an extra 256 bytes security sector, user must issue ENTER OTP MODE
command to read, program or erase security sector. After entering OTP mode, the security sector
is mapping to sector 31, SRP bit becomes LB and can be read with RDSR command. Program /
Erase command will be disabled when LB is ‘1’
WRSR command will ignore the input data and program LB to 1. User must clear the protect bits
before enter OTP mode.
Security sector can only be program and erase before LB equal ‘1’ and BP[2:0] = ‘000’. In OTP
mode, user can read other sectors, but program/erase other sectors only allowed when LB equal
‘0’.
User can use WRDI (04h) command to exit OTP mode.
Table 6
Security Sector Address
Sector
Sector Size
31
256 byte
Note: The Secruty sector is mapping to sector 31
Address Range
01F000h – 01F0FFh
While in OTP mode, user can use Sector Erase (20h) command only to erase OTP data.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
28
CS#
Mode3
CLK Mode0
0 1
2
3
4
5
6
7
Instruction (3Ah)
DI
DO
HIGH IMPEDANCE
Figure 23 Enter OTP Mode
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
29
12.
Electrical Characteristics
12.1.
Absolute Maximum Ratings
Operating Temperature
Storage Temperature
Voltage on I/O Pin with Respect to Ground
VCC
-40°C to +85°C
-65°C to +150°C
-0.5V to VCC+0.4V
-0.5V to 4.0V
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
12.2.
Pin Capacitance
SYMBOL
CIN(1)
COUT(1)
PARAMETER
Input Capacitance
Output Capacitance
CONDITIONS
VIN = 0V; TA = 25°C; f = 5 MHz;
VCC = 2.7V
VOUT = 0V; TA = 25°C; f = 5 MHz;
VCC = 2.7V
MAX
UNIT
6
pF
8
pF
Note: 1. This parameter is characterized and is not 100% tested.
12.3.
Power-up Timing
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC =2.3V to 3.6V, (unless
otherwise noted).
SYMBOL
tVSL
tPUW
SPEC
PARAMETER
VCC (min) to CS# Low
Time Delay Before Write Instruction
MIN
MAX
10
1
10
UNIT
µs
ms
Figure 25 Power-up Timing
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
30
12.4.
DC Electrical Characteristics
Table 7
DC Characteristics
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.3V to 3.6V, (unless
otherwise noted).
SYMBOL
PARAMETER
Vcc
ILI
ILO
Supply Voltage
Input Leakage Current
Output Leakage Current
ICC1
Standby Current
ICC2
Deep Power-down
Current
ICC3(1)
Operating Current
(READ)
ICC4
ICC5
ICC6
ICC7
VIL(2)
VIH(2)
VOL
VOH
VWI
Operating Current
(WRSR)
Operating Current (PP)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Write Inhibit Threshold
Voltage
CONDITIONS
MIN
SPEC
TYP
2.3
VCC=3.6V, CS# = VCC,
VIN = Vss or VCC
VCC=3.6V, CS# = VCC,
VIN = Vss or VCC
VCC=3.6V,
CLK=0.1VCC/0.9VCC, at
100MHz, DQ open
MAX
UNIT
3.6
±2
±2
V
µA
µA
1
5
µA
1
5
µA
25
mA
VCC=3.6V, CS#=VCC
8
12
mA
VCC=3.6V, CS#=VCC
VCC=3.6V, CS#=VCC
VCC=3.6V, CS#=VCC
20
20
20
25
25
25
0.3VCC
VCC+0.4
0.4
mA
mA
mA
V
V
V
V
2.2
V
-0.5
0.7VCC
IOL = 1.6 mA
IOH = -100 µA
VCC-0.2
1.0
Notes:
1. Checker Board Pattern.
2. VIL min and VIH max are reference only and are not tested.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
31
12.5.
AC Measurement Conditions
Table 8
SYMBOL
CL
TR, TF
VIN
IN
OUT
AC Measurement Conditions
SPEC
PARAMETER
MIN
Load Capacitance
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
UNIT
MAX
20
5
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
0.5VCC
pF
ns
V
V
V
Figure 26 AC Measurement I/O Waveform
12.6.
AC Electrical Characteristics
Table 9
AC Characteristics
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.7V to 3.6V, (unless
otherwise noted).
SYMBOL
FR
fR
(1)
tCH
tCL(1)
tCLCH(2)
tCHCL(2)
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ(2)
tCLQX
tDVCH
tCHDX
tHLCH
PARAMETER
MIN
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
Serial Clock Frequency for READ, RDSR, RDID
Serial Clock High Time
4
Serial Clock Low Time
4
Serial Clock Rise Time (Slew Rate)
0.1
Serial Clock Fall Time (Slew Rate)
0.1
CS# Active Setup Time
5
CS# Active Hold Time
5
CS# Not Active Setup Time
5
CS# Not Active Hold Time
5
CS# Deselect Time (for Array Read
Array Read/
10/50
Erase or Program
Read Status Register)
Output Disable Time
Output Hold Time
0
Data In Setup Time
2
Data In Hold Time
5
HOLD# Low Setup Time ( relative to CLK )
5
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
SPEC
TYP
MAX
UNIT
100
MHz
50
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
6
ns
ns
ns
ns
ns
Datasheet
32
SYMBOL
PARAMETER
tHHCH
tCHHH
tCHHL
HOLD# High Setup Time ( relative to CLK )
HOLD# Low Hold Time ( relative to CLK )
HOLD# High Hold Time ( relative to CLK )
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Valid from CLK
Write Protect Setup Time before CS# Low
Write Protect Hold Time after CS# High
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic
Signature Read
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time
tHLQZ(2)
tHHQX(2)
tCLQV
tWHSL
tSHWL
tDP(2)
tRES1(2)
tRES2(2)
MIN
SPEC
TYP
MAX
5
5
5
3
ns
ns
ns
ns
ns
ns
ns
ns
µs
3
µs
1.8
µs
15
5
0.3
2
1.2
4
ms
ms
s
s
s
s
6
6
8
20
100
tW
tPP
tSE
tBE1
tBE2
tCE
Notes:
1. tCH+tCL >= 1 / FR or 1/fR ;
3. This parameter is characterized and is not 100% tested.
10
1.5
0.09
0.5
0.3
1.5
UNIT
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.3V to 2.7V, (unless
otherwise noted).
SYMBOL
FR
fR
tPP
tSE
tBE1
tBE2
tCE
PARAMETER
MIN
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
Serial Clock Frequency for READ, RDSR, RDID
Page Programming Time
Sector Erase Time
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
SPEC
TYP
10
0.2
2
1.5
7
MAX
UNIT
80
MHz
33
25
0.8
4
3
20
MHz
ms
s
s
s
s
Datasheet
33
Figure 27 Serial Output Timing
Figure 28 Serial Input Timing
Figure 29 Hold Timing
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
34
13.
Ordering Information
Note:
1. For SO, TS and DN package, MSL1 package are available, for detail please contact local
sales office.
2. For Thinner package please contact local sales office.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
35
14.
Part Marking Scheme
14.1.
SOP8 (150mil)
14.2.
TSSOP8
14.3.
TDFN8 (2x3)
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
36
15.
Packaging Information
SOP 8 (150mil)
Symbol
MIN
A
1.350
A1
0.050
b
0.330
c
0.150
D
4.700
E1
3.700
E
5.800
e
1.270(BSC)
L
0.400
θ
0°
NOTE:
1. Dimensions are in Millimeters.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
MAX
1.750
0.250
0.510
0.260
5.150
4.100
6.200
1.270
8°
Datasheet
37
TSSOP8
Symbol
MIN
D
2.900
E1
4.300
b
0.190
c
0.090
E
6.200
A
A1
0.050
e
0.650 (BSC)
L
0.450
θ
0°
NOTE:
1. Dimensions are in Millimeters.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
MAX
3.100
4.500
0.300
0.200
6.600
1.200
0.150
0.750
8°
Datasheet
38
TDFN8 (2x3mm)
Symbol
MIN
A
0.700
A1
0.000
D
1.900
E
2.900
D2
1.400
E2
1.400
k
0.150(MIN)
b
0.200
e
0.500(TYP)
L
0.200
NOTE:
1. Dimensions are in Millimeters.
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
MAX
0.800
0.050
2.100
3.100
1.600
1.700
0.300
0.500
Datasheet
39
16.
Revision History
Version
preliminary
Publication
Pages
date
Jul. 2012
40
Revise Description
Initial Document Release.
1.
2.
3.
4.
1.
2.
3.
4.
1.
Added TDFN8 (2x3) offering and parts.
Updated packaging information of TSSOP8.
Updated Table1.
Updated “Pin Capacitance”
Corrected the typo
Updated the “Ordering Information”
Updated “Part Marking Scheme”
Updated the “Sales and Service”
Updated the Ordering Information and Part Marking
Scheme.
2. Updated the Supply Voltage.
1.0
Oct. 2012
41
1.1
Aug. 2013
41
1.2
Dec. 2014
41
1.3
May. 2015
41
Corrected the typo
1.4
Jun. 2015
41
Updated the AC Electrical Characteristics under 2.3V.
1.5
Oct, 2016
41
Updated the packaging information
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
40
Sales and Service
Shanghai Fudan Microelectronics Group Co., Ltd.
Address: Bldg No. 4, 127 Guotai Rd,
Shanghai City China.
Postcode: 200433
Tel: (86-021) 6565 5050
Fax: (86-021) 6565 9115
Shanghai Fudan Microelectronics (HK) Co., Ltd.
Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road,
Tsimshatsui East, Kowloon, Hong Kong
Tel: (852) 2116 3288 2116 3338
Fax: (852) 2116 0882
Beijing Office
Address: Room 423, Bldg B, Gehua Building,
1 QingLong Hutong, Dongzhimen Alley north Street,
Dongcheng District, Beijing City, China.
Postcode: 100007
Tel: (86-010) 8418 6608
Fax: (86-010) 8418 6211
Shenzhen Office
Address: Room.1301, Century Bldg, No. 4002, Shengtingyuan Hotel,
Huaqiang Rd (North),
Shenzhen City, China.
Postcode: 518028
Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611
Fax: (86-0755) 8335 9011
Shanghai Fudan Microelectronics (HK) Ltd Taiwan
Representative Office
Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist.,
Taipei City 114, Taiwan
Tel : (886-2) 7721 1890 (886-2) 7721 1889
Fax: (886-2) 7722 3888
Shanghai Fudan Microelectronics (HK) Ltd Singapore
Representative Office
Address : 237, Alexandra Road, #07-01 The Alexcier, Singapore
159929
Tel : (65) 6472 3688
Fax: (65) 6472 3669
Shanghai Fudan Microelectronics Group Co., Ltd NA Office
Address: 2490 W. Ray Road Suite#2
Chandler, AZ 85224 USA
Tel : (480) 857-6500 ext 18
Web Site: http://www.fmsh.com/
FM25F01 1M-BIT SERIAL FLASH MEMORY
Ver. 1.5
Datasheet
41
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