HEF4016BT,652

HEF4016B Quad single-pole single-throw analog switch Rev. 4 — 24 October 2016 Product data sheet 1. General description The HEF4016B provides four single-pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. 2. Features and benefits       Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications  Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4016BT 40 C to +85 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4016B Nexperia Quad single-pole single-throw analog switch 5. Functional diagram < ( < ( < ( < (   =    Q< =  9''   =  9'' Q(   966 9'' = 966  Q= DDJ Fig 1. 966 DDD Functional diagram Fig 2. Logic diagram (one switch) 6. Pinning information 6.1 Pinning +()% <   9&& =   ( =   ( <   < (   = (   = *1'   < DDD Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description 1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output 1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output 1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH) VSS 7 ground (0 V) VDD 14 supply voltage HEF4016B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 24 October 2016 © Nexperia B.V. 2017. All rights reserved 2 of 15 HEF4016B Nexperia Quad single-pole single-throw analog switch 7. Functional description Table 3. Function table[1] Input nE Switch H ON L OFF [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V II/O input/output current - 10 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Ptot total power dissipation - 500 mW - 100 mW [1] Tamb = 40 C to +85 C SO14 P power dissipation [2] per switch [1] To avoid drawing VDD current out of terminal nZ, when switch current flows into terminals nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VDD current will flow out of terminals nY, in this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VDD or VSS. [2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +85 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V HEF4016B Product data sheet VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V All information provided in this document is subject to legal disclaimers. Rev. 4 — 24 October 2016 © Nexperia B.V. 2017. All rights reserved 3 of 15 HEF4016B Nexperia Quad single-pole single-throw analog switch 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions Tamb = 40 C VDD Min VIH VIL HIGH-level input IO < 1 A voltage LOW-level input voltage IO < 1 A Max Tamb = 25 C Tamb = 85 C Min Min Max Unit Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 15 V - - - 0.3 - 1.0 A II input leakage current IS(OFF) OFF-state leakage current per channel; see Figure 4 15 V - - - 200 - - nA IDD supply current all valid input combinations 5V - 1.0 - 1.0 - 7.5 A 10 V - 2.0 - 2.0 - 15.0 A 15 V - 4.0 - 4.0 - 30.0 A - - - - 7.5 - - pF CI input capacitance nE input 10.1 Test circuit 9'' Q( 9,/ Q= 9, Q< ,6 966 92 DDN Fig 4. Test circuit for measuring OFF-state leakage current HEF4016B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 24 October 2016 © Nexperia B.V. 2017. All rights reserved 4 of 15 HEF4016B Nexperia Quad single-pole single-throw analog switch 10.2 ON resistance Table 7. ON resistance Tamb = 25 C; ISW = 100 A; VSS = 0 V. Symbol Parameter Conditions VDD Typ Max RON(peak) ON resistance (peak) VI = 0 V to VDD; see Figure 5 and Figure 6 5V 8000 -  10 V 230 690  15 V 115 350  5V 140 425  10 V 65 195  RON(rail) ON resistance (rail) VI = 0 V; see Figure 5 and Figure 6 VI = VDD; see Figure 5 and Figure 6 RON ON resistance mismatch between channels VI = 0 V to VDD; see Figure 5 Unit 15 V 50 145  5V 170 515  10 V 95 285  15 V 75 220  5V 200 -  10 V 15 -  15 V 10 -  10.2.1 ON resistance waveform and test circuit DDD   521 ȍ  96:   9'' Q( 9,+ Q< 9,  Q= 966 ,6:      9,9 DDN ISW = 100 A. RON = VSW / ISW. (1) VDD = 10 V (2) VDD = 15 V Fig 5. Test circuit for measuring RON HEF4016B Product data sheet Fig 6. Typical RON as a function of input voltage All information provided in this document is subject to legal disclaimers. Rev. 4 — 24 October 2016 © Nexperia B.V. 2017. All rights reserved 5 of 15 HEF4016B Nexperia Quad single-pole single-throw analog switch 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = 0 V; for test circuit see Figure 9. Symbol Parameter tPHL HIGH to LOW propagation delay nY, nZ to nZ, nY; see Figure 7 tPLH tPHZ tPLZ tPZH tPZL Conditions LOW to HIGH propagation delay nY, nZ to nZ, nY; see Figure 7 HIGH to OFF-state propagation delay nE to nY, nZ; see Figure 8 LOW to OFF-state propagation delay nE to nY, nZ; see Figure 8 OFF-state to HIGH propagation delay nE to nY, nZ; see Figure 8 OFF-state to LOW propagation delay nE to nY, nZ; see Figure 8 VDD Typ Max Unit 5V 25 50 ns 10 V 10 20 ns 15 V 5 10 ns 5V 20 40 ns 10 V 10 20 ns 15 V 5 10 ns 5V 90 130 ns 10 V 80 110 ns 15 V 75 100 ns 5V 85 120 ns 10 V 75 100 ns 15 V 75 100 ns 5V 40 80 ns 10 V 20 40 ns 15 V 15 30 ns 5V 40 80 ns 10 V 20 40 ns 15 V 15 30 ns Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown; VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 550  fi + (fo  CL)  VDD 10 V PD = 2600  fi + (fo  CL)  VDD2 fo = output frequency in MHz; 15 V PD = 6500  fi + (fo  CL)  VDD CL = output load capacitance in pF; 2 fi = input frequency in MHz; 2 VDD = supply voltage in V; (fo  CL) = sum of the outputs. HEF4016B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 24 October 2016 © Nexperia B.V. 2017. All rights reserved 6 of 15 HEF4016B Nexperia Quad single-pole single-throw analog switch 11.1 Waveforms and test circuit 9, 90 90 W3/+ W3+/ LQSXWQ