HEF4541BT,518

HEF4541B Programmable timer Rev. 5 — 15 December 2015 Product data sheet 1. General description The HEF4541B is a programmable timer which consists of a 16-stage binary counter, an integrated oscillator to be used with external timing components, an automatic power-on reset and output control logic. The frequency of the oscillator is determined by the external components RTC and CTC within the frequency range 1 Hz to 100 kHz. This oscillator may be replaced by an external clock signal at input RS, the timer advances on the positive-going transition of RS. A LOW on the auto reset input (AR) and a LOW on the master reset input (MR) enables the internal power-on reset. A HIGH level at input MR resets the counter independent on all other inputs. Resetting disables the oscillator to provide no active power dissipation. A HIGH at input AR turns off the power-on reset to provide a low quiescent power dissipation of the timer. The 16-stage counter divides the oscillator frequency by 28, 210, 213 or 216 depending on the state of the address inputs (A0, A1). The divided oscillator frequency is available at output O. The phase input (PH) features a complementary output signal. When the mode select input (MODE) is LOW the timer is a single transition timer and when HIGH the timer is a 2n frequency divider. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits      Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number HEF4541BT Package Name Description Version SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4541B Nexperia Programmable timer 4. Functional diagram 56 &7& 57&    $  $ 02'(   &21752/,13876 $5 05 3+ &3   32:(521 5(6(7 &'  287387 67$*( %,1$5< &2817(5 2  DDL Fig 1. Functional diagram &7& 57& &2817(5 &3 5(6(7 56  &2817(5 &3 5(6(7    $ 08; $ $5 32:(521 5(6(7 /$7&+ 05 02'( 3+ 2 DDL Fig 2. Logic diagram HEF4541B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 2 of 16 HEF4541B Nexperia Programmable timer 5. Pinning information 5.1 Pinning +()% 57&   9'' &7&   $ 56   $ QF   QF $5   02'( 05   3+ 966   2 DDL Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description RTC 1 external resistor connection CTC 2 external capacitor connection RS 3 external resistor connection (RS) or external clock input nc 4, 11 not connected AR 5 auto reset input (active low) MR 6 master reset input VSS 7 ground (0 V) O 8 timer output PH 9 phase input MODE 10 mode select input A0, A1 12, 13 address inputs VDD 14 supply voltage HEF4541B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 3 of 16 HEF4541B Nexperia Programmable timer 6. Functional description Table 3. Function table[1] Input MODE AR MR PH MODE H L X X auto reset disabled L L X X auto reset enabled[2] X H X X master reset active X L X H normal operation selected division to output X L X L single-cycle mode[3] X L L X output initially LOW after reset X L H X output initially HIGH, after reset [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [2] For correct power-on reset, the supply voltage should be above 8.5 V. For VDD < 8.5 V, disable the autoreset and connect AR to VDD. [3] The timer is initialized on a reset pulse and the output changes state after 2n-1 counts and remains in that state (latched). Reset of this latch is obtained by master reset or by a LOW to HIGH transition on the MODE input. Table 4. Frequency selection table A0 A1 Number of counter stages n f OSC ---------- = 2 n fO L L 13 8192 L H 10 1024 H L 8 256 H H 16 65536 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current VO < 0.5 V or VO > VDD + 0.5 V O output VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 - 10 V mA II/O input/output current - 10 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Ptot total power dissipation - 500 mW - 100 mW Tamb = 40 C to +85 C SO14 package P [1] power dissipation [1] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. HEF4541B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 4 of 16 HEF4541B Nexperia Programmable timer 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VDD VI Conditions Min Max Unit supply voltage 3 15 V input voltage 0 VDD V Tamb ambient temperature in free air 40 +85 C t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V VDD = 10 V - 0.5 s/V VDD = 15 V - 0.08 s/V 9. Static characteristics Table 7. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol VIH VIL VOH VOL IOH Parameter Conditions HIGH-level input voltage IO < 1 A LOW-level input voltage IO < 1 A HIGH-level output voltage LOW-level output voltage HIGH-level output current IO < 1 A IO < 1 A Tamb = 40 C Tamb = 25 C Tamb = 85 C Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V VDD Unit 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V 5V - 1.4 - 1.2 - 0.95 mA CTC, RTC; VO = 2.5 V VO = 4.6 V 5V - 0.5 - 0.4 - 0.3 mA VO = 9.5 V 10 V - 1.4 - 1.2 - 0.95 mA VO = 13.5 V 15 V - 4.8 - 4.0 - 3.2 mA VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 mA O; HEF4541B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 5 of 16 HEF4541B Nexperia Programmable timer Table 7. Static characteristics …continued VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol IOL Parameter Conditions LOW-level output current VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Min Max Min Min Max Unit Max CTC, RTC; VO = 0.4 V 5V 0.33 - 0.27 - 0.20 - mA VO = 0.5 V 10 V 1.0 - 0.85 - 0.68 - mA VO = 1.5 V 15 V 3.2 - 2.7 - 2.3 - mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.2 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 A 5V - 5 - 5 - 150 A 10 V - 10 - 10 - 300 A 15 V - 20 - 20 - 600 A - - - - 7.5 - - pF O; II input leakage current IDD supply current CI IO = 0 A input capacitance Table 8. Reset characteristics VSS = 0 V; VI = VSS or VDD; see Table 12 for test conditions; unless otherwise specified. Symbol Parameter IDD supply current supply current for 5V power-on reset 10 V enable; AR = MR = 0 V; Other 15 V inputs at 0 V or VDD VDD Conditions VDD supply voltage supply voltage for automatic reset initialization; AR = MR = 0 V; Other inputs at 0 V or VDD HEF4541B Product data sheet Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit Min Max Min Typ Max Min Max - 80 - 20 80 - 230 A - 750 - 250 600 - 700 A - 1.6 - 0.5 1.3 - 1.5 mA - - 8.5 5 - - - All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © V Nexperia B.V. 2017. All rights reserved 6 of 16 HEF4541B Nexperia Programmable timer 10. Dynamic characteristics Table 9. Dynamic characteristics VSS = 0 V; Tamb = 25 C unless otherwise specified. For test circuit, see Figure 5. Symbol Parameter propagation delay tpd Conditions RS to O; 28 selected; see Figure 4 pulse width fclk(max) fosc Min Typ[1] Max 348 ns + (0.55 ns/pF)CL - 375 750 10 V 139 ns + (0.23 ns/pF)CL - 150 300 ns 15 V 102 ns + (0.16 ns/pF)CL - 110 220 ns 5V 398 ns + (0.55 ns/pF)CL - 425 850 ns 10 V 154 ns + (0.23 ns/pF)CL - 165 330 ns 15 V 5V RS to O; 210 selected; see Figure 4 tW Extrapolation formula VDD [2] Unit ns 112 ns + (0.16 ns/pF)CL - 120 240 ns RS to O; 213 selected; see Figure 4 5V 483 ns + (0.55 ns/pF)CL - 510 1020 ns 10 V 179 ns + (0.23 ns/pF)CL - 190 380 ns 15 V 127 ns + (0.16 ns/pF)CL - 135 270 ns RS to O; 216 selected; see Figure 4 5V 548 ns + (0.55 ns/pF)CL - 575 1150 ns 10 V 199 ns + (0.23 ns/pF)CL - 210 420 ns 142 ns + (0.16 ns/pF)CL - 150 300 ns 60 30 - ns 10 V 15 V [3] RS LOW; MR HIGH; see Figure 4 5V 30 15 - ns 15 V 24 12 - ns maximum clock frequency RS; see Figure 4 5V 8 16 - MHz 10 V 15 30 - MHz 15 V 18 36 - MHz oscillator frequency Rt = 5 k; Ct = 1 nF; RS = 10 k; see Figure 6 5V - 90 - kHz 10 V - 90 - kHz 15 V - 90 - kHz Rt = 56 k; Ct = 1 nF; RS = 120 k; see Figure 6 5V - 8 - kHz 10 V - 8 - kHz 15 V - 8 - kHz [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] tpd is the same as tPHL and tPLH. [3] tW is the same as tWL(min) and tWH(min). HEF4541B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 7 of 16 HEF4541B Nexperia Programmable timer Table 10. Dynamic power dissipation PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol Parameter VDD Typical formula dynamic power dissipation 5V PD = 1300  fi + (fo  CL  VDD2) W 10 V PD = 5300  fi + (fo  CL  VDD2) W 15 V PD = 12000  fi + (fo  CL  VDD2) W 5V PD = 1300  fosc + foCLVDD2 + 2CTCVDD2 fosc + 10VDD W 10 V PD = 5300  fosc + foCLVDD2 + 2CTCVDD2 fosc + 100VDD W 15 V PD = 12000  fosc + foCLVDD2 + 2CTCVDD2 fosc + 400VDD W Per package PD Using the on-chip oscillator Total dynamic power dissipation PD(Tot) [1] fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; fosc = oscillator frequency in MHz; CTC = timing capacitance in pF. 11. Waveforms  IFONPD[ 9, 90 56LQSXW 966 92+ W:+PLQ W3/+ 2RXWSXW W:/PLQ W3+/ 90 92/ 9, 05LQSXW 966 W:+PLQ DDD VOL and VOH are typical output voltage levels that occur with the output load. Measurement are points given in Table 11, the test circuit in Figure 5 and the test data in Table 12 (1) 2n pulses as selected by address inputs (A0, A1). Fig 4. Propagation delay clock (RS) to output (O), clock pulse width and maximum clock frequency Table 11. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4541B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 8 of 16 HEF4541B Nexperia Programmable timer 9'' * 9, 92 '87 &/ 57 DDJ Test data is given in Table 12. Definitions for test circuit: DUT - Device Under Test. RL = Load resistance. CL = load capacitance. RT = Termination resistance should be equal to output impedance of Zo of the pulse generator. Fig 5. Test circuit for measuring switching times Table 12. Test data Supply Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD  20 ns 50 pF HEF4541B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 9 of 16 HEF4541B Nexperia Programmable timer 12. Application information RC oscillator timing component limitations The oscillator frequency is mainly determined by RTCCTC, provided RTC