74HC574DB,112

74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 — 4 March 2016 Product data sheet 1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Input levels:  For 74HC574: CMOS level  For 74HCT574: TTL level  3-state non-inverting outputs for bus oriented applications  8-bit positive, edge-triggered register  Common 3-state output enable input  Complies with JEDEC standard no. 7 A  Multiple package options  ESD protection:  HBM JESD22-A114F exceeds 2 000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package 74HC574D Temperature range Name Description Version 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74HCT574D 74HC574DB 74HCT574DB 74HC574PW 74HCT574PW 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 4. Functional diagram  ' 4   ' 4   '  '  '  ' 4   ' 4   ' 4  4  )) WR )) 4  67$7( 2873876 4   &3  2( PQD Fig 1. Functional diagram ' ' ' 4 ' ' &3 4 ' &3 )) ' 4 ' &3 )) ' 4 ' &3 )) ' 4 ' ' &3 )) 4 ' &3 )) ' 4 ' &3 )) 4 &3 )) )) &3 2( 4 4 4 4 4 4 4 4 DDK Fig 2. Logic diagram 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 2 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state   & (1          ' 4 ' 4 ' 4 ' 4 '  ' 4 ' 4 ' 4 2(  '                   4  Fig 3.  &3    PQD PQD Logic symbol Fig 4. IEC logic symbol 5. Pinning information 5.1 Pinning +& +&7 2(  '   9&&  4 '   4 '   4 '   4 '   4 '   4 '   4 '   4 *1'   &3 DDQ Fig 5. Pin configuration SO20, SSOP20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) CP 11 clock input (LOW-to-HIGH, edge triggered) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output VCC 20 supply voltage 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 3 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 6. Functional description Table 3. Function table[1] Operating mode OE CP Dn Internal flip-flop Load and read register L  l L L  h H H Load register and disable output H  l L Z H  h H Z [1] Input Output L Qn H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition; Z = high-impedance OFF-state;  = LOW-to-HIGH clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 35 mA ICC supply current - +70 mA IGND ground current - 70 mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] Conditions Min SO20, SSOP20 and TSSOP20 packages [1] Max Unit For SO20: Ptot derates linearly with 8 mW/K above 70 C. For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature 74HC_HCT574 Product data sheet Conditions 74HC574 74HCT574 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V 0 - VCC 0 - VCC V 0 - VCC 0 - VCC V 40 +25 +125 40 +25 +125 C All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 4 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 5. Recommended operating conditions …continued Voltages are referenced to GND (ground = 0 V) …continued Symbol Parameter t/V Conditions input transition rise and fall rate 74HC574 74HCT574 Unit Min Typ Max Min Typ Max - - 625 - - - VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V VCC = 2.0 V ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V VCC = 6.0 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 3.15 2.4 - 3.15 - 3.15 - V 4.2 3.2 - 4.2 - 4.2 - V 74HC574 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND - - 0.5 - 5.0 - 10.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 5 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 74HCT574 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 6 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A CI input capacitance 74HC_HCT574 Product data sheet per input pin; Dn inputs - 50 180 - 225 - 245 A per input pin; OE input - 125 450 - 563 - 613 A per input pin; CP input - 150 540 - 675 - 735 A - 3.5 - - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 6 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 30 - 35 - 45 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns VCC = 2.0 V - 44 140 - 175 - 210 ns VCC = 4.5 V - 16 28 - 35 - 42 ns VCC = 6.0 V - 13 24 - 30 - 36 ns VCC = 2.0 V - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns 74HC574 tpd ten tdis tt tW tsu th fmax propagation delay enable time CP to Qn; see Figure 6 OE to Qn; see Figure 8 disable time OE to Qn; see Figure 8 transition time pulse width set-up time hold time maximum frequency Qn; see Figure 6 [3] CP HIGH or LOW; see Figure 7 VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns Dn to CP; see Figure 7 VCC = 2.0 V 60 6 - 75 - 90 - ns VCC = 4.5 V 12 2 - 15 - 18 - ns VCC = 6.0 V 10 2 - 13 - 15 - ns Dn to CP; see Figure 7 VCC = 2.0 V 5 0 - 5 - 5 - ns VCC = 4.5 V 5 0 - 5 - 5 - ns VCC = 6.0 V 5 0 - 5 - 5 - ns CP; see Figure 6 VCC = 2.0 V 6.0 37 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 112 - 24 - 20 - MHz - 123 - - - - - MHz 35 133 - 28 - 24 - MHz VCC = 6.0 V Product data sheet [2] [4] VCC = 5 V; CL = 15 pF 74HC_HCT574 [1] All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 7 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter CPD power dissipation capacitance 25 C Conditions CL = 50 pF; f = 1 MHz; VI = GND to VCC [5] CP to Qn; see Figure 6 [1] 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 22 - - - - - pF 74HCT574 propagation delay tpd enable time ten VCC = 4.5 V - 18 33 - 41 - 50 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 19 33 - 41 - 50 ns - 16 28 - 35 - 42 ns - 5 12 - 15 - 18 ns 16 7 - 20 - 24 - ns 12 3 - 15 - 18 - ns 5 1 - 5 - 5 - ns 30 69 - 24 - 20 - MHz - 76 - - - - - MHz - 25 - - - - - pF OE to Qn; see Figure 8 [2] VCC = 4.5 V disable time OE to Qn; see Figure 8 tdis [3] VCC = 4.5 V tt tW [4] transition time Qn; see Figure 6 pulse width CP HIGH or LOW; see Figure 7 VCC = 4.5 V VCC = 4.5 V tsu set-up time Dn to CP; see Figure 7 th hold time Dn to CP; see Figure 7 VCC = 4.5 V VCC = 4.5 V maximum frequency fmax CP; see Figure 6 VCC = 4.5 V VCC = 5 V; CL = 15 pF power dissipation capacitance CPD [1] CL = 50 pF; f = 1 MHz; VI = GND to VCC  1.5 V [5] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 8 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 11. Waveforms IPD[ 9, &3LQSXW 90 *1' W: W3+/ 92+ W3/+  90 4QRXWSXW  92/ W7+/ W7/+ DDQ Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the maximum frequency (CP) 9, 90 &3LQSXW *1' W VX W VX WK WK 9, 90 'QLQSXW *1' 92+ 90 4QRXWSXW 92/ PQD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 9 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 9, 2(LQSXW 90 *1' W3/= W3=/ 9&& 4QRXWSXW /2:WR2)) 2))WR/2: 92/ 90 9; W3+= 92+ W3=+ 9< 4QRXWSXW +,*+WR2)) 2))WR+,*+ *1' 90 RXWSXWV HQDEOHG RXWSXWV GLVDEOHG RXWSXWV HQDEOHG DDK Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Enable and disable times Table 8. Measurement points Type Input Output VM VM VX VY 74HC574 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT574 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 10 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 9, W:  QHJDWLYH SXOVH 90 9 WI WU WU WI 9,  SRVLWLYH SXOVH 9 90  90 90  W: 9&& 9&& * 9, 92 5/ 6 RSHQ '87 &/ 57 DDG Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 9. Test circuit for measuring switching times Table 9. Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC574 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT574 3V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT574 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 11 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' $ ( ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ PP                                           LQFKHV        =       ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 10. Package outline SOT163-1 (SO20) 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 12 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F +( \ Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   Z 0 ES H GHWDLO;   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 11. Package outline SOT339-1 (SSOP20) 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 13 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F +( \ Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 12. Package outline SOT360-1 (TSSOP20) 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 14 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT574 v.7 20160304 Product data sheet - 74HC_HCT574 v.6 Modifications: 74HC_HCT574 v.6 Modifications: 74HC_HCT574 v.5 Modifications: 74HC_HCT574 v.4 Modifications: • Type numbers 74HC574N and 74HCT574N (SOT146-1) removed. 20150126 • 74HC_HCT574 v.5 Product data sheet - 74HC_HCT574 v.4 VX and VY measurement points added to Table 8. 20111219 • - Table 7: Power dissipation capacitance condition for 74HCT574 is corrected. 20120425 • Product data sheet Product data sheet - 74HC_HCT574 v.3 Legal pages updated. 74HC_HCT574 v.3 20101215 Product data sheet - 74HC_HCT574_CNV v.2 74HC_HCT574_CNV v.2 19970827 Product specification - - 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 15 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 16 of 18 74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74HC_HCT574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 March 2016 © Nexperia B.V. 2017. All rights reserved 17 of 18 Nexperia 74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 04 March 2016