74ALVCH16601DGGY

74ALVCH16601 18-bit universal bus transceiver; 3-state Rev. 3 — 13 August 2018 Product data sheet 1. General description The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features and benefits • • • • • • • • • CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Direct interface with TTL levels Bus hold on data inputs Output drive capability 50 Ω transmission lines at 85 °C Current drive ±24 mA at 3.0 V Complies with JEDEC standards: • JESD8-5 (2.3 V to 2.7 V) • JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V • CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74ALVCH16601DGG −40 °C to +85 °C Name Description Version TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 4. Functional diagram OEAB CEAB CPAB 1 56 55 2 LEAB OEBA 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 2 55 55 Fig. 1. A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 OEAB OEBA LEAB LEBA CPAB CPBA CEAB CEBA CEBA 54 CPBA 52 LEBA 27 29 30 28 51 49 3 A0 48 47 5 A1 45 A4 42 A5 41 A6 40 A7 38 A8 37 A9 36 A10 34 A11 33 31 A12 27 A14 A13 A15 28 A16 30 A17 29 2C3 C3 G2 EN4 G5 5C6 C6 G5 3D 1 1 4 1 6D 54 52 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 A3 43 G2 6 A2 44 EN1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 aaa-028854 aaa-028853 Logic symbol Fig. 2. IEC logic symbol VCC data input to internal circuit 001aal733 Fig. 3. Bus hold circuit 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 2 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state CPBA CPAB LEBA LEAB CEBA CEAB OEBA OEAB CE C1 CP An Bn 1D CE C1 CP 1D 18 identical channels to 17 other channels Fig. 4. aaa-028855 Logic diagram (one section) 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 3 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 5. Pinning information 5.1. Pinning 74ALVCH16601 OEAB 1 56 CEAB LEAB 2 55 CPAB A0 3 54 B0 GND 4 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 50 VCC A3 8 49 B3 A4 9 48 B4 A5 10 47 B5 GND 11 46 GND A6 12 45 B6 A7 13 44 B7 A8 14 43 B8 A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 35 VCC A15 23 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CPBA LEBA 28 29 CEBA aaa-028856 Fig. 5. Pin configuration for TSSOP56 (SOT364-1) 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 4 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 data inputs/outputs B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 data outputs/inputs OEAB, OEBA 1, 27 A to B / B to A output enable inputs (active LOW) LEAB, LEBA 2, 28 A to B / B to A latch enable inputs (active HIGH) CPBA, CPAB 30, 55 B to A / A to B clock inputs (active HIGH) CEBA, CEAB 29, 56 B to A / A to B clock enable inputs (active LOW) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6. Functional description Table 3. Function selection [1] [2] Operating mode Inputs Outputs CEAB OEAB LEAB CPAB An Bn Disabled X H X X X Z Transparent X L H X H H X L H X L L Hold H L L X X NC Clock data & Display L L L ↑ h H L L L ↑ l L L L L H X NC L L L L X NC Hold data & Display [1] [2] A-to-B data flow is shown; B-to-A flow is similar but uses CEBA, OEBA, LEBA, and CPBA. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the enable or clock transition; X = don’t care; NC = no change ↑ = LOW-to-HIGH enable or clock transition; Z = high-impedance OFF-state. 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 5 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage IIK input clamping current VI < 0 V IOK output clamping current IO (sink/source) output sink or source current ICC IGND Min Max Unit -0.5 +4.6 V data inputs [1] -0.5 control inputs [1] -0.5 [1] -0.5 VCC + 0.5 V +4.6 V VCC + 0.5 V -50 - mA VO > VCC or VO < 0 V - ±50 mA VO = 0 V to VCC - ±50 mA supply current - 100 mA ground current -100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 600 mW Min Max Unit VCC = 2.5 V: for maximum speed performance at CL = 30 pF 2.3 2.7 V VCC = 3.3 V: for maximum speed performance at CL = 50 pF 3.0 3.6 V [1] [2] Tamb = −40 °C to +85 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature in free air −40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 20 ns/V VCC = 3.0 V to 3.6 V 0 10 ns/V 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 6 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Tamb = −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max VIH HIGH-level input voltage VCC = 2.3 to 2.7 V 1.7 1.2 - V VCC = 2.7 to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 to 2.7 V - 1.2 0.7 V VCC = 2.7 to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V VIL VOH VOL LOW-level output voltage Unit VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V - 0.1 5 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V 45 - - μA VCC = 3.0 V; VI = 0.8 V 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V -500 - - μA IOZ OFF-state output current VCC = 2.7 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 3.6 V - 150 750 μA CI input capacitance - 4.0 - pF CI/O input/output capacitance - 8.0 - pF IBHH [1] All typical values are measured at Tamb = 25 °C. 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 7 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C; For test circuit, see Fig. 10. Symbol Parameter Conditions tpd propagation delay An to Bn; Bn to An; Fig. 6 VCC = 2.7 V 5.2 ns 4.7 ns 4.2 ns 1.0 3.6 6.2 ns - 3.4 5.4 ns 1.0 3.1 4.9 ns 1.0 3.4 5.9 ns - 3.5 5.8 ns 1.3 3.1 5.0 ns 1.1 3.1 5.3 ns - 3.3 6.1 ns 1.1 2.8 5.2 ns 1.4 2.8 4.9 ns - 3.3 4.8 ns 1.2 3.2 4.4 ns VCC = 2.3 V to 2.7 V 2.3 −0.2 - ns VCC = 2.7 V 2.4 0.0 - ns VCC = 3.0 V to 3.6 V 2.1 −0.2 - ns VCC = 2.3 V to 2.7 V 1.3 0.1 - ns VCC = 2.7 V 1.2 −0.2 - ns VCC = 3.0 V to 3.6 V 1.1 0.3 - ns VCC = 2.3 V to 2.7 V 2.0 −0.4 - ns VCC = 2.7 V 2.0 −0.7 - ns VCC = 3.0 V to 3.6 V 1.7 −0.2 - ns [2] VCC = 3.0 V to 3.6 V CPAB to Bn; CPBA to An; Fig. 7 [2] VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V OEAB to Bn; OEBA to An; Fig. 8 [2] VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V OEAB to Bn; OEBA to An; Fig. 8 [2] VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V set-up time 3.1 2.8 VCC = 2.7 V tsu 1.0 3.1 VCC = 2.3 V to 2.7 V disable time Unit - LEAB to Bn; LEBA to An; Fig. 7 tdis Max 1.0 VCC = 3.0 V to 3.6 V enable time Typ [1] [2] VCC = 2.3 V to 2.7 V ten Min An to CPAB; Bn to CPBA; Fig. 9 An to LEAB; Bn to LEBA; Fig. 9 CEAB to CPAB; CEBA to CPBA; 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 8 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state Symbol Parameter Conditions Min Typ [1] Max th hold time An to CPAB; Bn to CPBA; Fig. 9 Unit VCC = 2.3 V to 2.7 V 1.2 0.3 - ns VCC = 2.7 V 1.1 0.3 - ns VCC = 3.0 V to 3.6 V 1.0 −0.1 - ns VCC = 2.3 V to 2.7 V 1.3 0.2 - ns VCC = 2.7 V 1.6 0.1 - ns VCC = 3.0 V to 3.6 V 1.4 0.1 - ns VCC = 2.3 V to 2.7 V 1.1 0.4 - ns VCC = 2.7 V 1.2 0.6 - ns VCC = 3.0 V to 3.6 V 1.1 0.4 - ns VCC = 2.3 V to 2.7 V 3.3 1.6 - ns VCC = 2.7 V 3.3 0.7 - ns VCC = 3.0 V to 3.6 V 3.3 0.9 - ns VCC = 2.3 V to 2.7 V 3.3 2.0 - ns VCC = 2.7 V 3.3 1.2 - ns VCC = 3.0 V to 3.6 V 3.3 0.9 - ns VCC = 2.3 V to 2.7 V 150 390 - MHz VCC = 2.7 V 150 333 - MHz VCC = 3.0 V to 3.6 V 150 340 - MHz outputs enabled - 21 - pF outputs disabled - 3 - pF An to LEAB; Bn to LEBA; Fig. 9 CEAB to CPAB; CEBA to CPBA; tw pulse width LEAB HIGH; LEBA HIGH; Fig. 7 CPAB HIGH or LOW; CPBA HIGH or LOW; Fig. 7 fmax maximum frequency CPD [1] [2] [3] power dissipation capacitance CPAB, CPBA; Fig. 7 per latch; VI = GND to VCC [3] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V tpd is the same as tPHL and tPLH; ten is the same as tPZH and tPZL; tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 9 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 10.1. Waveforms and test circuit VI An, Bn input VM VM tPHL tPLH GND VOH Bn, An output VM VM VOL 001aal734 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. The input An, Bn to output Bn, An propagation delays. 1/fmax LEBA, LEAB CPBA, CPAB input VI VM VM VM GND tW tPHL tPLH VOH An, Bn output VM VM VOL aaa-028857 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Latch enable input (LEAB, LEBA) and clock input (CPAB, CPBA) to output (Bn, An) propagation delays; clock (CPAB, CPBA) pulse width and clock (CPAB, CPBA) maximum frequency VI OEAB, OEBA input VM VM GND tPLZ An, Bn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ An, Bn output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled aaa-028033 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. 3-state enable and disable times. 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 10 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state An, Bn input VI VM VM VM VM GND tsu VI CPAB, CPBA, LEAB, LEBA input GND th tsu th VM VM aaa-028858 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Data set-up and hold times for An and Bn inputs to LEAB, LEBA, CPAB or CPBA inputs. Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH16601 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 11 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 11. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 11. Package outline SOT364-1 (TSSOP56) 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 12 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16601 v.3 20180813 Product data sheet - 74ALVCH16601 v.2 Modifications: • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74ALVCH16601 v.2 19980924 Product specification - 74ALVCH16601 v.1 74ALVCH16601 v.1 19980831 Product specification - - 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 13 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ALVCH16601 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 14 / 15 74ALVCH16601 Nexperia 18-bit universal bus transceiver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 5 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 12 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 13 August 2018 74ALVCH16601 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 August 2018 © Nexperia B.V. 2018. All rights reserved 15 / 15