74LVT573DB,118

74LVT573 3.3 V octal D-type transparent latch; 3-state Rev. 8 — 22 November 2011 Product data sheet 1. General description The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE) input is High. The latch remains transparent to the data inputs while LE is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-state buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus. 2. Features and benefits            Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection  JESD78 class II exceeds 500 mA  ESD protection:  HBM JESD22-A114E exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT573D 40 C to +85 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVT573DB 40 C to +85 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74LVT573PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVT573BQ 40 C to +85 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5  4.5  0.85 mm 4. Functional diagram 11 1 1 2 3 4 5 6 7 8 9 2 OE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 Fig 1. Logic symbol 74LVT573 Product data sheet EN1 19 1D 3 18 4 17 16 5 16 15 6 15 14 7 14 8 13 9 12 18 17 13 12 LE 11 C1 mna807 mna808 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 2 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state D0 D1 D Q D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna810 Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 1 OE terminal 1 index area 74LVT573 20 VCC 74LVT573 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D3 5 16 Q3 D2 4 17 Q2 D4 6 15 Q4 D3 5 16 Q3 D5 7 14 Q5 D4 6 15 Q4 D6 8 D5 7 14 Q5 D6 8 13 Q6 D7 9 D7 9 12 Q7 GND 10 11 LE GND(1) 13 Q6 LE 11 GND 10 12 Q7 001aah712 Transparent top view 001aah713 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO20 and (T)SSOP20 74LVT573 Product data sheet Fig 5. Pin configuration for DHVQFN20 All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 3 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) LE 11 latch enable (active HIGH) Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output VCC 20 supply voltage 6. Functional description 6.1 Function table Table 3. Function table [1] Operating mode Control OE Control LE Input Dn Internal register Output Qn Load and read register enable L H L L L H H H Latch and read register L  l L L h H H Hold L L X NC NC Disable outputs H L X NC Z H Dn Dn Z [1] H = HIGH voltage level; L = LOW voltage level;  = HIGH-to-LOW latch enable transition; h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; Z = high-impedance OFF-state; NC = no change; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions output in OFF-state or HIGH-state Min Max Unit 0.5 +4.6 V [1] 0.5 +7.0 V [1] 0.5 +7.0 V IIK input clamping current VI < 0 V - 50 mA IOK output clamping current VO < 0 V - 50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - 64 mA 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 4 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tstg storage temperature Conditions junction temperature Tj Tamb = 40 C to +85 C total power dissipation Ptot Min Max Unit 65 +150 C [2] - 150 C [3] - 500 mW [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions Min Typ Max Unit 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current - - 32 mA IOL LOW-level output current - - 32 mA current duty cycle  50 %; fi  1 kHz - - 64 mA Tamb ambient temperature in free air 40 - +85 C t/V input transition rise and fall rate outputs enabled - - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIK input clamping voltage VCC = 2.7 V; IIK = 18 mA VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = 100 A VOL LOW-level output voltage Tamb = 40 C to +85 C Conditions power-up LOW-level output voltage 74LVT573 Product data sheet Typ[1] Max 1.2 0.9 - V - V VCC  0.2 VCC  0.1 VCC = 2.7 V; IOH = 8 mA 2.4 2.5 - V VCC = 3.0 V; IOH = 32 mA 2.0 2.2 - V VCC = 2.7 V; IOL = 100 A - 0.1 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V IOL = 32 mA - 0.3 0.5 V - 0.4 0.55 V - 0.13 0.55 V VCC = 3.0 V IOL = 64 mA VOL(pu) Unit Min VCC = 3.6 V; IO = 1 mA; VI = GND or VCC All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 [2] © Nexperia B.V. 2017. All rights reserved 5 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II Tamb = 40 C to +85 C Conditions input leakage current Unit Min Typ[1] Max - 1 10 A - 0.1 1 A all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V control pins; VCC = 3.6 V; VCC or GND data pins VCC = 3.6 V; VI = VCC [3] VCC = 3.6 V; VI = 0 V power-off leakage current IOFF 1 A 1 - A - 1 100 A 75 150 - A - 150 75 A [4] - - 500 A 500 - - A - 60 125 A - 1 100 A output HIGH: VO = 3.0 V - 1 5 A output LOW: VO = 0.5 V 5 1 - A - 0.13 0.19 mA bus hold LOW current IBHH bus hold HIGH current Dn input; VCC = 3 V; VI = 2.0 V IBHHO bus hold HIGH overdrive current Dn input; VCC = 3.6; VI = 0 V to 3.6 V IBHLO bus hold LOW overdrive current Dn input; VCC = 3.6; VI = 0 V to 3.6 V ILO output leakage current Qn output HIGH when VO = 5.5 V and VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC  1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OE = don’t care IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL supply current 0.1 [4] VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL ICC 5 Dn input; VCC = 3 V; VI = 0.8 V [5] VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - 3 12 mA [6] - 0.13 0.19 mA [7] - 0.1 0.2 mA ICC additional supply current CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF per input pin; VCC = 3 V to 3.6 V; one input at VCC  0.6 V and other inputs at VCC or GND [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V  0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. [6] ICC is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 6 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 11. Symbol Parameter LOW to HIGH propagation delay tPLH Tamb = 40 C to +85 C Unit Conditions Min Typ[1] Max 1.6 3.5 5.6 ns - - 6.3 ns 1.0 2.5 4.2 ns - - 4.7 ns 2.5 4.3 6.5 ns - - 7.2 ns 1.0 2.7 4.3 ns - - 5.2 ns 1.0 2.8 5.1 ns - - 6.2 ns 1.3 3.3 5.5 ns - - 6.6 ns 2.0 3.7 5.7 ns - - 6.7 ns 1.5 3.0 4.6 ns - - 5.1 ns 0.7 - - ns 0.6 - - ns LE to Qn; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V Dn to Qn; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 2.7 V HIGH to LOW propagation delay tPHL LE to Qn; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V Dn to Qn; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 2.7 V OFF-state to HIGH propagation delay tPZH OE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPZL OFF-state to LOW propagation delay OE to Qn; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPHZ HIGH to OFF-state propagation delay OE to Qn; see Figure 8 LOW to OFF-state propagation delay OE to Qn; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPLZ VCC = 3.0 V to 3.6 V VCC = 2.7 V set-up time tsu Dn to LE; see Figure 10 [2] VCC = 3.0 V to 3.6 V VCC = 2.7 V hold time th pulse width tW Dn to LE; see Figure 10 VCC = 3.0 V to 3.6 V 1.6 - - ns VCC = 2.7 V 1.8 - - ns VCC = 3.0 V to 3.6 V 3.3 - - ns VCC = 2.7 V 3.3 - - ns LE input HIGH; see Figure 6 [1] Typical values are at VCC = 3.3 V and Tamb = 25 C. [2] tsu is the same as tsu(L) and tsu(H). [3] th is the same as th(L) and th(H). [4] tW is the same as tWL and tWH. 74LVT573 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 [4] © Nexperia B.V. 2017. All rights reserved 7 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 11. Waveforms VI LE input VI VM VM Dn input 0V tWH 0V tWL tPHL VOH VOH VOL VOL 001aai743 Measurement points are given in Table 8. Fig 7. Propagation delay data input (Dn) to output (Qn) VI VI VM VM VM VM OE input 0V 0V tPZH tPHZ VOH Qn output 001aai742 Measurement points are given in Table 8. Propagation delays latch enable input (LE) to output (Qn), and latch enable (LE) pulse width OE input VM Qn output VM Qn output Fig 6. tPLH tPHL tPLH tPZL tPLZ 3.0 V VY Qn output VM VM VX VOL 0V 001aai745 001aai746 Measurement points are given in Table 8. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Output enable time to HIGH-state and output disable time from HIGH-state Fig 9. Output enable time to LOW-state and output disable time from LOW-state VI VM Dn input 0V th(L) th(H) tsu(H) tsu(L) VI LE input VM 0V 001aai744 Measurement points are given in Table 8. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs Table 8. Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 8 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 11. Test circuitry for switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V  10 MHz 500 ns  2.5 ns 50 pF 500  GND 6V open 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 9 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 10 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 13. Package outline SOT339-1 (SSOP20) 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 11 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 14. Package outline SOT360-1 (TSSOP20) 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 12 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT764-1 (DHVQFN20) 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 13 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT573 v.8 20111122 Product data sheet - 74LVT573 v.7 Modifications: • Legal pages updated. 74LVT573 v.7 20110912 Product data sheet - 74LVT573 v.6 74LVT573 v.6 20110727 Product data sheet - 74LVT573 v.5 74LVT573 v.5 20110629 Product data sheet - 74LVT573 v.4 74LVT573 v.4 20080915 Product data sheet - 74LVT573 v.3 74LVT573 v.3 20011217 Product data sheet - 74LVT573 v.2 74LVT573 v.2 19980219 Product specification - - 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 14 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 15 of 17 74LVT573 Nexperia 3.3 V octal D-type transparent latch; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LVT573 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2011 © Nexperia B.V. 2017. All rights reserved 16 of 17 Nexperia 74LVT573 3.3 V octal D-type transparent latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 November 2011