74HC191D,653

74HC191 Presettable synchronous 4-bit binary up/down counter Rev. 5 — 13 August 2019 Product data sheet 1. General description The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired value. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches '15' in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters as shown in Fig. 5 and Fig. 6. In Fig. 5, each RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this configuration in some applications. Fig. 6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the clock. In Fig. 7, the configuration shown avoids ripple delays and their associated restrictions. Combining the TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in each carry gate in order to inhibit counting. The TC output of a given stage it not affected by its own CE signal therefore the simple inhibit scheme of Fig. 5 and Fig. 6 does not apply. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • Complies with JEDEC standard no. 7A CMOS input levels: Synchronous reversible counting Asynchronous parallel load Count enable control for synchronous expansion Single up/down control input ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC191D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC191DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC191PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4. Functional diagram 15 15 D0 1 D1 10 D2 9 D3 11 PL 12 13 TC RC U/D CE CP 5 4 14 1 D0 3 Q1 2 Q2 6 Q3 7 D1 9 D2 D3 PL 11 Q0 10 U/D 5 CE 4 RC PARALLEL LOAD CIRCUIT CP 14 TC 12 BINARY COUNTER Q0 Q1 Q2 Q3 3 2 6 7 aaa-024376 Fig. 1. 13 Logic symbol aaa-024375 Fig. 2. Functional diagram 5. Pinning information 5.1. Pinning 74HC191 D1 1 16 VCC Q1 2 15 D0 Q0 3 14 CP D1 1 16 VCC Q1 2 15 D0 Q0 3 14 CP CE 4 13 RC CE 4 13 RC U/D 5 12 TC U/D 5 12 TC 6 11 PL 10 D2 Q2 6 11 PL Q2 Q3 7 10 D2 Q3 7 GND 8 GND 8 9 D3 aaa-024377 Fig. 3. 74HC191 Pin configuration SOT109-1 (SO16) 74HC191 Product data sheet 9 D3 aaa-024378 Fig. 4. Pin configuration SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 2 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 5.2. Pin description Table 2. Pin description Symbol Pin Description D0, D1, D2, D3 15, 1, 10, 9 data input Q0, Q1, Q2, Q3 3, 2, 6, 7 flip-flop output CE 4 count enable input (active LOW) U/D 5 up/down input GND 8 ground (0 V) PL 11 parallel load input (active LOW) TC 12 terminal count output RC 13 ripple clock output (active LOW) CP 14 clock input (LOW-to-HIGH, edge-triggered) VCC 16 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition Operating mode parallel load Output Input PL U/D CE CP Dn Qn L X X X L L L X X X H H count up H L l ↑ X count up count down H H l ↑ X count down Hold (do nothing) H X H X X no change Table 4. TC and RC Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; = one LOW level pulse; = TC goes LOW on a LOW-to-HIGH clock transition. Input Terminal count state Output U/D CE CP Q0 Q1 Q2 Q3 TC RC H H X H H H H L H L H X H H H H H H L L H H H H L H X L L L L L H H H X L L L L H H H L L L L L 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 3 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter DIRECTION CONTROL U/D U/D RC U/D RC ENABLE CE CE CE CLOCK CP CP CP RC aaa-024379 Fig. 5. N-stage ripple counter using ripple clock DIRECTION CONTROL U/D ENABLE RC U/D U/D RC CE CE CE CP CP CP CLOCK Fig. 6. RC aaa-024380 Synchronous n-stage counter using ripple carry/borrow DIRECTION CONTROL ENABLE U/D U/D U/D CE CE CE CP TC CP TC CLOCK Fig. 7. CP TC aaa-024381 Synchronous n-stage counter with parallel gated carry/borrow 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 4 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter D0 D1 D2 D3 PL U/D CE CP J SD Q RC TC Q0 CP FF1 K RD Q J SD Q CP FF1 K RD Q Q1 J SD Q Q2 CP FF1 K RD Q J SD Q CP FF1 K RD Q Q3 aaa-024382 Fig. 8. Logic diagram 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 5 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter PL D0 D1 D2 D3 CP U/D CE Q0 Q1 Q2 Q3 TC RC 13 14 load 15 0 1 count up 2 2 2 inhibit 1 0 15 14 13 count down aaa-024383 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit. Fig. 9. Typical timing sequence 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current IO output current ICC Min Max Unit -0.5 +7.0 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA VO = -0.5 V to VCC + 0.5 V - ±25 mA supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions [1] For SOT109-1 (SO16) packages: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT338-1 (SSOP16) packages: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT403-1 (TSSOP16) packages: Ptot derates linearly with 8.5 mW/K above 91 °C. 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 6 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Min Typ Max Unit 2.0 5.0 6.0 V 0 - VCC V 0 - VCC V -40 +25 +125 °C VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C Min Typ VIH VIL VOH VOL -40 °C to +85 °C -40 °C to +125 °C Unit Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2; VCC = 6.0 V HIGH-level input voltage LOW-level input voltage 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 μA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 μA CI input capacitance - 3.5 - - - - - pF 74HC191 Product data sheet VI = VCC or GND; VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 7 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 18. Symbol Parameter tpd Conditions 25 °C propagation CP to Qn; see Fig. 10 delay VCC = 2.0 V -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max [1] - 72 220 - 275 - 330 ns VCC = 4.5 V - 26 44 - 55 - 66 ns VCC = 5.0 V; CL = 15 pF - 22 - - - - - ns VCC = 6.0 V - 21 37 - 47 - 56 ns VCC = 2.0 V - 83 255 - 320 - 395 ns VCC = 4.5 V - 30 51 - 64 - 77 ns VCC = 6.0 V - 24 43 - 54 - 65 ns VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 30 - 38 - 45 ns VCC = 6.0 V - 14 26 - 33 - 38 ns VCC = 2.0 V - 33 130 - 165 - 195 ns VCC = 4.5 V - 12 26 - 33 - 39 ns VCC = 6.0 V - 10 22 - 28 - 33 ns VCC = 2.0 V - 61 220 - 275 - 330 ns VCC = 4.5 V - 22 44 - 55 - 66 ns VCC = 6.0 V - 18 37 - 47 - 56 ns VCC = 2.0 V - 61 220 - 275 - 330 ns VCC = 4.5 V - 22 44 - 55 - 66 ns VCC = 6.0 V - 18 37 - 47 - 56 ns VCC = 2.0 V - 44 190 - 240 - 285 ns VCC = 4.5 V - 16 38 - 48 - 57 ns VCC = 6.0 V - 13 32 - 41 - 48 ns VCC = 2.0 V - 50 210 - 265 - 315 ns VCC = 4.5 V - 18 42 - 53 - 63 ns VCC = 6.0 V - 14 36 - 45 - 54 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns CP to TC; see Fig. 10 CP to RC; see Fig. 11 CE to RC; see Fig. 11 Dn to Qn; see Fig. 12 PL to Qn; see Fig. 13 U/D to TC; see Fig. 14 U/D to RC; see Fig. 14 tt transition time 74HC191 Product data sheet see Fig. 15 [2] All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 8 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter tW pulse width Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 125 28 - 155 - 195 - ns VCC = 4.5 V 25 10 - 31 - 39 - ns VCC = 6.0 V 21 8 - 26 - 33 - ns VCC = 2.0 V 100 22 - 125 - 150 - ns VCC = 4.5 V 20 8 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 35 8 - 45 - 55 - ns VCC = 4.5 V 7 3 - 9 - 11 - ns VCC = 6.0 V 6 2 - 8 - 9 - ns VCC = 2.0 V 205 50 - 255 - 310 - ns VCC = 4.5 V 41 18 - 51 - 62 - ns VCC = 6.0 V 35 14 - 43 - 53 - ns VCC = 2.0 V 100 19 - 125 - 150 - ns VCC = 4.5 V 20 7 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 140 44 - 175 - 210 - ns VCC = 4.5 V 28 16 - 35 - 42 - ns VCC = 6.0 V 24 13 - 30 - 36 - ns VCC = 2.0 V 0 -39 - 0 - 0 - ns VCC = 4.5 V 0 -14 - 0 - 0 - ns VCC = 6.0 V 0 -11 - 0 - 0 - ns VCC = 2.0 V 0 -11 - 0 - 0 - ns VCC = 4.5 V 0 -4 - 0 - 0 - ns VCC = 6.0 V 0 -3 - 0 - 0 - ns VCC = 2.0 V 0 -28 - 0 - 0 - ns VCC = 4.5 V 0 -10 - 0 - 0 - ns VCC = 6.0 V 0 -8 - 0 - 0 - ns VCC = 2.0 V 4.0 11 - 3.2 - 2.6 - MHz VCC = 4.5 V 20 33 - 16 - 13 - MHz - 36 - - - - - MHz 24 39 - 19 - 15 - MHz CP; HIGH or LOW; see Fig. 10 PL; LOW; see Fig. 15 trec tsu recovery time set-up time PL to CP; see Fig. 15 U/D to CP; see Fig. 16 Dn to PL; see Fig. 17 CE to CP; see Fig. 16 th hold time U/D to CP; see Fig. 16 Dn to PL; see Fig. 17 CE to CP; see Fig. 16 fmax maximum frequency CP; see Fig. 10 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 9 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter CPD [1] [2] [3] Conditions 25 °C power VI = GND to VCC; VCC = 5 V; dissipation fi = 1 MHz capacitance [3] -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 31 - - - - - pF tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPLH tPHL VOH Qn, TC output VM VOL aaa-024384 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. The clock input (CP) to outputs (Qn, TC) propagation delays, clock pulse width and maximum clock frequency VI CP, CE input VM GND tPHL tPLH VOH VM RC output VOL aaa-024385 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 11. The clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation delays 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 10 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter VI Dn input VM GND tPHL tPLH VOH VM Qn output VOL aaa-024386 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 12. The input (Dn) to output (Qn) propagation delays Vl Dn input GND Vl PL input VM GND tPLH tPHL VOH Qn output VM VOL aaa-024387 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 13. The parallel load input (PL) to output (Qn) propagation delays VI U/D input VM GND tPLH tPHL VOH VM TC output VOL tPHL tPLH VOH VM RC output VOL aaa-024388 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 14. The up/down count input (U/D) to terminal count and ripple clock output (TC, RC) propagation delays 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 11 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter VI PL input VM GND tW trec VI CP input VM GND tPHL VOH 90 % 90 % VM Qn output 10 % VOL 10 % tTHL tTLH aaa-024389 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 15. The parallel load input (PL) to clock (CP) recovery times, parallel load pulse width and output (Qn) transition times Vl CP input VM GND tsu Vl CE, U/D input th VM GND tsu th Vl CE, U/D input VM GND aaa-024391 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 16. The count enable and up/down count inputs (CE, U/D) to clock input (CP) set-up and hold times 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 12 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter Vl Dn input VM GND tsu tsu th Vl PL input th VM aaa-024390 GND Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 17. The parallel load input (PL) to data input (Dn) set-up and hold times Table 9. Measurement points Input Output VM VI VM 0.5 x VCC GND to VCC 0.5 x VCC VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RT RL S1 open CL 001aad983 Test data is given in Table 10. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig. 18. Test circuit for measuring switching times Table 10. Test data Input S1 position Load VI tr, tf CL RL tPHL, tPLH VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 13 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 19. Package outline SOT109-1 (SO16) 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 14 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig. 20. Package outline SOT338-1 (SSOP16) 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 15 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 21. Package outline SOT403-1 (TSSOP16) 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 16 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 12. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC191 v.5 20190813 Product data sheet - 74HC191 v.4 Modifications: • • 74HC191 v.4 20181005 Modifications: • • • Type number 74HC191DB (SOT338-1 / SSOP16) added. Table 5: Derating values for Ptot total power dissipation updated 20170103 Modifications: • 74HC_HCT191_CNV v.2 74HC191 Product data sheet - 74HC191 v.3 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HC191DB (SOT338-1 / SSOP16) removed. 74HC191 v.3 • • Product data sheet Product data sheet - 74HC_HCT191 v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type numbers 74HCT191D, 74HCT191DB, 74HCT191PW removed. 19901201 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 - © Nexperia B.V. 2019. All rights reserved 17 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter 14. 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The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC191 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 18 / 19 74HC191 Nexperia Presettable synchronous 4-bit binary up/down counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 3 6. Functional description................................................. 3 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................7 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 14 12. Abbreviations............................................................ 17 13. Revision history........................................................17 14. Legal information......................................................18 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 13 August 2019 74HC191 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 13 August 2019 © Nexperia B.V. 2019. All rights reserved 19 / 19