74LVC161D,118

74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset Rev. 6 — 30 September 2013 Product data sheet 1. General description The 74LVC161 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula: 1 f max = ----------------------------------t PHL  max  + t su It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. 2. Features and benefits          5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Asynchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V) 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset  JESD8-C/JESD36 (2.7 V to 3.6 V)  Specified from 40 C to +85 C and 40 C to +125 C  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC161D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LVC161DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LVC161PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LVC161BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm SOT763-1 4. Functional diagram 1 15 9 TC 10 7 3 D0 Q0 14 4 D1 Q1 13 5 D2 Q2 12 6 D3 Q3 11 9 PE CEP CET CP 2 3 MR CTR4 R M1 G3 G4 C2/1,3,4+ 14 1,2D 4 13 5 12 6 11 15 4 CT = 15 7 Fig 1. Logic symbol 74LVC161 Product data sheet 10 2 1 mna905 mna906 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 2 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 3 4 D0 9 10 PE 5 D1 6 D2 D3 PARALLEL LOAD CIRCUITRY CET TC 7 2 1 CEP 15 BINARY COUNTER CP MR Q0 Q1 Q2 Q3 mna907 14 Fig 3. 13 12 11 Functional diagram 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 mna908 Fig 4. State diagram 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 3 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 5. Pinning information D0 3 14 Q0 D1 4 13 Q1 161 D2 5 D3 6 11 Q3 CEP 7 10 CET GND 8 9 CP 2 15 TC D0 3 14 Q0 D1 4 D2 5 D3 6 CEP 7 12 Q2 16 VCC 15 TC PE 13 Q1 161 GND(1) 12 Q2 11 Q3 10 CET 9 2 PE CP terminal 1 index area 1 16 VCC 8 1 GND MR MR 5.1 Pinning 001aad087 Transparent top view 001aad086 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration for SO16 and (T)SSOP16 Fig 6. Pin configuration for DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 synchronous master reset (active LOW) CP 2 clock input (LOW-to-HIGH, edge-triggered) D[0:3] 3, 4, 5, 6 data input CEP 7 count enable input GND 8 ground (0 V) PE 9 parallel enable input (active LOW) CET 10 count enable carry input Q[0:3] 14, 13, 12, 11 flip-flop output TC 15 terminal count output VCC 16 supply voltage 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 4 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset MR PE D0 D1 D2 D3 CP CEP CET Q0 Q1 Q2 Q3 TC 12 reset preset 13 14 15 0 1 2 count inhibit mna909 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit. Fig 7. Timing sequence 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 5 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset ' ' ' ' &(7 &(3 3( ' )) 4 ' &3 5' )) 4 ' &3 4 5' )) 4 ' &3 4 5' )) 4 &3 4 5' 4 &3 05 4 4 4 4 7& PQD Fig 8. Logic diagram 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 6 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 6. Functional description Table 3. Function table[1] Operating modes Input CP CEP CET PE Dn Qn TC Reset (clear) L X X X X X L L Parallel load H  X X l l L L H  X X l h H * Count H  h h h X count * Hold (do nothing) H X l X h X qn * H X X l h X qn L [1] MR Output * = the TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH) H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care  = LOW-to-HIGH clock transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 [1] VO > VCC or VO < 0 [2] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 0.5 VCC + 0.5 V - 50 mA VO output voltage IO output current ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO16 packages: above 70 C the value of PD derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 C the value of PD derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of PD derates linearly with 4.5 mW/K. 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 7 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage functional Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Product data sheet 40 C to +125 C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35  VCC - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC  0.2 - - VCC  0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V VI = VIH or VIL VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V 0.1 5 - 20 A input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC161 Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 8 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Typ[1] Min 40 C to +125 C Max Min Unit Max ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; - 5 500 - 5000 A VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF CI [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 14. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions Min Max Min Max - 17 - - - ns VCC = 1.65 V to 1.95 V 1.5 7.0 14.5 1.5 16.7 ns VCC = 2.3 V to 2.7 V 2.5 4.0 8.1 2.5 9.4 ns VCC = 2.7 V 1.5 3.8 7.2 1.5 9.0 ns 1.5 3.6 7.3 1.5 9.5 ns CP to Qn; see Figure 9 [2] VCC = 1.2 V VCC = 3.0 V to 3.6 V CP to TC; see Figure 9 [2] VCC = 1.2 V - 20 - - - ns VCC = 1.65 V to 1.95 V 1.8 8.1 15.5 1.8 17.9 ns VCC = 2.3 V to 2.7 V 2.8 4.6 8.7 2.8 10.1 ns VCC = 2.7 V 1.5 4.3 7.8 1.5 10.0 ns 1.5 4.2 7.8 1.5 10.0 ns - 16 - - - ns VCC = 1.65 V to 1.95 V 1.5 5.9 11.9 1.5 13.7 ns VCC = 3.0 V to 3.6 V CET to TC; see Figure 10 VCC = 1.2 V 74LVC161 Product data sheet 40 C to +125 C Unit Typ[1] [2] VCC = 2.3 V to 2.7 V 1.9 3.4 6.7 1.9 7.7 ns VCC = 2.7 V 1.5 3.6 6.5 1.5 8.5 ns VCC = 3.0 V to 3.6 V 1.5 3.1 6.0 1.5 7.5 ns All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 9 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 14. Symbol Parameter 40 C to +85 C Conditions Min tPHL HIGH to LOW propagation delay Typ[1] Max 40 C to +125 C Unit Min Max MR to Qn; see Figure 11 - 17 - - - ns VCC = 1.65 V to 1.95 V VCC = 1.2 V 1.5 6.2 12.7 1.5 14.6 ns VCC = 2.3 V to 2.7 V 1.9 3.6 7.1 1.9 8.3 ns VCC = 2.7 V 1.5 3.9 7.1 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 3.2 6.4 1.5 8.0 ns - 18 - - - ns VCC = 1.65 V to 1.95 V 1.7 8.3 15.9 1.7 18.4 ns VCC = 2.3 V to 2.7 V 2.7 4.8 8.9 2.7 10.3 ns VCC = 2.7 V 1.5 4.9 8.6 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.5 4.3 8.0 1.5 10.0 ns MR to TC; see Figure 11 VCC = 1.2 V tW pulse width clock HIGH or LOW; see Figure 9 VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns VCC = 2.7 V 5.0 - - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 4.0 - - 4.0 - ns VCC = 3.0 V to 3.6 V 3.0 1.6 - 3.0 - ns VCC = 1.65 V to 1.95 V 1.0 - - 1.0 - ns VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns VCC = 2.7 V 0.0 - - 0.0 - ns VCC = 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns master reset LOW; see Figure 11 trec recovery time 74LVC161 Product data sheet MR to CP; see Figure 11 All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 10 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 14. Symbol Parameter tsu set-up time 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max Dn to CP; see Figure 12 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.0 - - 3.0 - ns VCC = 3.0 V to 3.6 V 2.5 1.0 - 2.5 - ns VCC = 1.65 V to 1.95 V 4.5 - - 4.5 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.5 - - 3.5 - ns VCC = 3.0 V to 3.6 V 3.0 1.2 - 3.0 - ns VCC = 1.65 V to 1.95 V 8.0 - - 8.0 - ns VCC = 2.3 V to 2.7 V 6.0 - - 6.0 - ns VCC = 2.7 V 5.5 - - 5.5 - ns VCC = 3.0 V to 3.6 V 5.0 2.1 - 5.0 - ns PE to CP; see Figure 12 CEP, CET to CP; see Figure 13 hold time th maximum frequency fmax Dn, PE, CEP, CET to CP; see Figure 12 and 13 VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 0.0 - - 0.0 - ns VCC = 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns VCC = 1.65 V to 1.95 V 100 - - 80 - MHZ VCC = 2.3 V to 2.7 V 125 - - 100 - MHZ VCC = 2.7 V 150 - - 120 - MHz 150 200 - 120 - MHz - - 1.0 - 1.5 - 11.1 - pF VCC = 2.3 V to 2.7 V - 14.7 - pF VCC = 3.0 V to 3.6 V - 17.9 - pF see Figure 9 VCC = 3.0 V to 3.6 V tsk(o) CPD [1] output skew time VCC = 3.0 V to 3.6 V [3] power dissipation per input; VI = GND to VCC capacitance VCC = 1.65 V to 1.95 V [4] ns Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching (CL  VCC2  fo) = sum of outputs 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 11 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 11. Waveforms 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn, TC output VOL mna911 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and maximum frequency VI CET input VM GND t PLH t PHL VOH VM TC output VOL mna912 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Input (CET) to output (TC) propagation delays VI VM MR input GND t rec tW VI CP input VM GND t PHL VOH Qn, TC output VM VOL mna913 Fig 11. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays, and the master reset to clock (CP) removal times 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 12 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset VI VM PE input GND t su t su th th VI VM CP input GND t su t su th th VI VM Dn input GND mna914 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 12. Set-up and hold times for the input (Dn) and parallel enable input (PE) VI CEP, CET input VM GND th th t su t su VI CP input VM GND mna915 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 13. CEP and CET set-up and hold times Table 8. Measurement points Supply voltage Input VCC VI VM VM 1.2 V VCC 0.5  VCC 0.5  VCC 1.65 V to 1.95 V VCC 0.5  VCC 0.5  VCC 2.3 V to 2.7 V VCC 0.5  VCC 0.5  VCC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V 74LVC161 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 13 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 14. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC  2 ns 30 pF 1 k 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k 2.3 V to 2.7 V VCC  2 ns 30 pF 500  2.7 V 2.7 V  2.5 ns 50 pF 500  3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 14 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT109-1 (SO16) 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 15 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 16. Package outline SOT338-1 (SSOP16) 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 16 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 17. Package outline SOT403-1 (TSSOP16) 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 17 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 18. Package outline SOT763-1 (DHVQFN16) 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 18 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC161 v.6 20130930 Product data sheet - 74LVC161 v.5 Modifications: • Figure 8 corrected (errata). 74LVC161 v.5 20121123 Product data sheet - 74LVC161 v.4 74LVC161 v.4 20121122 Product data sheet - 74LVC161 v.3 74LVC161 v.3 20040330 Product specification - 74LVC161 v.2 74LVC161 v.2 19980520 Product specification - 74LVC161 v.1 74LVC161 v.1 19960823 Product specification - - 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 19 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC161 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 20 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LVC161 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 30 September 2013 © Nexperia B.V. 2017. All rights reserved 21 of 22 74LVC161 Nexperia Presettable synchronous 4-bit binary counter; asynchronous reset 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 September 2013