74HC194D,652

74HC194 4-bit bidirectional universal shift register Rev. 3 — 29 November 2016 Product data sheet 1. General description The 74HC194 is a 4-bit bidirectional universal shift register. The synchronous operation of the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0 and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift right or shift left data transfers without interfering with parallel load operation. If both S0 and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Complies with JEDEC standard no. 7A  Input levels:  For 74HC194: CMOS level  Shift-left and shift right capability  Synchronous parallel and serial data transfer  Easily expanded for both serial and parallel operation  Asynchronous master reset  Hold (‘do nothing’) mode  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and 40 C to +125 C 74HC194 Nexperia 4-bit bidirectional universal shift register 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC194D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC194DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 4. Functional diagram  '65  '  '  '  '  '6/  6 &21752//2*,&  6  &3 ))WR))  05 4  4  4   6 6  '65  ' 4   ' 4   ' 4   ' 4   '6/ &3 05 4   DDD Fig 1.  Functional diagram Fig 2.  DDD Logic symbol 65*           &    0   5 '  '  '  '  ' ' DDD Fig 3. IEC logic symbol 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 2 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register ' ' ' ' '6/ 6 6 '65 )) 4  6 6 )) 4  6 )) 4  6 )) 4  &3 &3 &3 &3 5 5 5 5 5' 5' 5' 5' &3 05 4 4 4 4 DDD Fig 4. Logic diagram 5. Pinning information 5.1 Pinning +& 05   9&& '65   4 '   4 '   4 '   4 ' '6/ *1'  +& 05   9&& '65   4 '   4 '   4 '   4 '   &3 '6/   6 *1'   &3   6   6 DDD Fig 5. Pin configuration SO16 74HC194 Product data sheet  6 DDD Fig 6. Pin configuration SSOP16 All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 3 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset (active LOW) DSR 2 serial data input (shift right) D0, D1, D2, D3 3, 4, 5, 6 parallel data inputs DSL 7 serial data input (shift left) GND 8 ground (0 V) S0, S1 9, 10 mode control inputs CP 11 clock input (LOW-to-HIGH, edge triggered) Q0, Q1, Q2, Q3 15, 14, 13, 12 parallel outputs VCC 16 positive supply voltage 6. Functional description Table 3. Function table[1] Operating mode Inputs CP Outputs MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3 Reset (clear) X L X X X X X L L L L Hold (do nothing) X H l l X X X q0 q1 q2 q3 Shift left  H h l X l X q1 q2 q3 L  H h l X h X q1 q2 q3 H  H l h l X X L q0 q1 q2  H l h h X X H q0 q1 q2  H h h X X dn d0 d1 d2 d3 Shift right Parallel load [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH CP transition; X = don’t care;  = LOW-to-HIGH clock transition. 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 4 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register &3 6 6 05 '65 '6/ ' + ' / ' + ' / 4 4 4 4 FOHDUORDG VKLIWULJKW VKLIWOHIW LQKLELW FOHDU DDD Typical timing sequence: Typical clear-load; shift-right; shift-left; inhibit and clear timing sequences. Fig 7. Typical timing sequence 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V Min Max Unit 0.5 +7.0 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature Ptot total power dissipation [1] 65 +150 C SO16 package [1] - 500 mW SSOP16 package [1] - 500 mW For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K. For SSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K. 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 5 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI VO input voltage 0 - VCC V output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min VIH VIL VOH VOL HIGH-level input voltage Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A LOW-level input voltage II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 A CI input capacitance - 3.5 - - - - - pF 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 6 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter 25 C Conditions Min tpd tPHL tt tW tW trec propagation delay pulse width pulse width recovery time 74HC194 Product data sheet Typ Max Min Max Min Max [1] CP to Qn; see Figure 8 VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 25 - 31 - 38 ns - 39 140 - 175 - 210 ns - 14 28 - 35 - 42 ns High to LOW MR to Qn; see Figure 9 propagation VCC = 2.0 V delay VCC = 4.5 V transition time 40 C to +85 C 40 C to +125 C Unit VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns VCC = 6.0 V - 11 24 - 30 - 36 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns [2] see Figure 8 CP HIGH or LOW; see Figure 8 MR pulse width LOW; see Figure 9 MR to CP; see Figure 9 VCC = 2.0 V 60 17 - 75 - 90 - ns VCC = 4.5 V 12 6 - 15 - 18 - ns VCC = 6.0 V 10 5 - 13 - 15 - ns All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 7 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter 25 C Conditions Min tsu set-up time 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max Dn to CP; see Figure 10 VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 12 6 - 17 - 20 - ns VCC = 2.0 V 70 19 - 90 - 105 - ns VCC = 4.5 V 14 7 - 18 - 21 - ns VCC = 6.0 V 12 6 - 15 - 18 - ns VCC = 2.0 V 0 14 - 0 - 0 - ns VCC = 4.5 V 0 5 - 0 - 0 - ns VCC = 6.0 V 0 4 - 0 0 - ns VCC = 2.0 V 0 11 - 0 - 0 - ns VCC = 4.5 V 0 4 - 0 - 0 - ns VCC = 6.0 V 0 3 - 0 0 - ns VCC = 2.0 V 0 17 - 0 - 0 - ns VCC = 4.5 V 0 6 - 0 - 0 - ns VCC = 6.0 V 0 5 - 0 0 - ns VCC = 2.0 V 6 31 - 4.8 - 4 - MHz VCC = 4.5 V 30 93 - 24 - 20 - MHz - 102 - - - - - MHz 35 111 - 28 - 24 - MHz S0, S1 to CP; see Figure 11 DSR, DSL to CP; see Figure 10 th hold time Dn to CP; see Figure 10 S0, S1 to CP; see Figure 11 DSR, DSL to CP; see Figure 10 fmax maximum frequency CP; see Figure 8 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 8 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter 25 C Conditions Min CPD [1] power dissipation capacitance VI = GND to VCC; fi = 1 MHz [3] - 40 C to +85 C 40 C to +125 C Unit Typ Max 40 - Min Max Min Max - - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 11. Waveforms 9, 05LQSXW IPD[ 90 90 *1' 9, &3 LQSXW WUHF W: 90 9, *1' &3LQSXW W: W3+/ 92+ 4Q RXWSXW W3/+  *1' W3+/  92+ 90 92/  4QRXWSXW  W7+/ 90 W7/+ 90 92/ DDD Fig 8. DDD Measurement points are given in Table 8. Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency 74HC194 Product data sheet Fig 9. The master reset (MR) pulse width, master reset to output (Qn) propagation delays, and the master reset to clock (CP) recovery times All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 9 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 9, &3LQSXW *1' 9, 90 66 LQSXW WVX 9, 'Q'65'6/ LQSXW *1' WVX WK WK WVX 90 &3LQSXW DDD WVX WK 9, *1' WK 90 *1' DDD Measurement points are given in Table 8. Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. The set-up and hold times from the data inputs (Dn, DSR and DSL) to the clock (CP) Table 8. 90 Fig 11. The set-up and hold times from the mode control inputs (Sn) to the clock input Measurement points Input Output VM VI VM 0.5  VCC GND to VCC 0.5  VCC 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 10 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 9, W:  QHJDWLYH SXOVH 90 9 9, WI WU WU WI  SRVLWLYH SXOVH 9 90  90 90  W: 9&& 9&& * 9, 92 5/ 57 6 RSHQ '87 &/ DDG Test data is given in Table 9. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig 12. Test circuit for measuring switching times Table 9. Test data Input Load S1 position VI tr, tf CL RL tPHL, tPLH VCC 6 ns 15 pF, 50 pF 1 k open 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 11 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 13. Package outline SOT109-1 (SO16) 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 12 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 14. Package outline SOT338-1 (SSOP16) 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 13 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC194 v.3 20161129 Product data sheet - 74HC_HCT194 v.2 Modifications: 74HC_HCT194 v.2 74HC194 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Type numbers 74HC194N, 74HCT194N and 74HCT194D removed. 19901201 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 - © Nexperia B.V. 2017. All rights reserved 14 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC194 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 15 of 17 74HC194 Nexperia 4-bit bidirectional universal shift register Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74HC194 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 29 November 2016 © Nexperia B.V. 2017. All rights reserved 16 of 17 Nexperia 74HC194 4-bit bidirectional universal shift register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 29 November 2016