74LVC594APW-Q100J

74LVC594A-Q100 8-bit shift register with output register Rev. 2 — 21 July 2017 1 Product data sheet General description The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. A LOW level on one of the two register reset pins (SHR and STR) clears the corresponding register. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2 Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) – Specified from -40 °C to +85 °C and from -40 °C to +125 °C • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low-power consumption • Direct interface with TTL levels • Balanced propagation delays • All inputs have Schmitt-trigger action • Complies with JEDEC standard: – JESD8-7A (1.65 V to 1.95 V) – JESD8-5A (2.3 V to 2.7 V) – JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: – MIL-STD-883, method 3015 exceeds 2000 V – HBM JESD22-A114F exceeds 2 000 V 74LVC594A-Q100 Nexperia 8-bit shift register with output register 3 Applications • Serial-to-parallel data conversion • Remote control holding register 4 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC594AD-Q100 -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LVC594APW-Q100 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74LVC594ABQ-Q100 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm 5 SOT763-1 Functional diagram SHCP STCP 11 12 9 DS 74LVC594A_Q100 Product data sheet 15 Q0 1 Q1 14 10 13 SHR STR Figure 1.  Logic symbol Q7S 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 DS SHCP SHR 14 11 8-STAGE SHIFT REGISTER 10 9 STCP STR 12 8-BIT STORAGE REGISTER 13 15 1 2 3 4 5 6 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc319 Q7S mbc320 Figure 2.  Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register STAGE 0 DS D STAGES 1 TO 6 Q D STAGE 7 Q FFSH0 CP D Q7S Q FFSH7 CP R R SHCP SHR D D Q FFST0 CP Q FFST7 CP R R STCP STR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc321 Figure 3.  Logic diagram SHCP DS STCP SHR STR Q0 Q1 Q6 Q7 Q7S mbc323 Figure 4.  Timing diagram 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 6 Pinning information 6.1 Pinning 1 Q1 terminal 1 index area 74LVC594A-Q100 16 VCC 74LVC594A-Q100 Q2 2 15 Q0 14 DS Q2 2 15 Q0 Q4 4 13 STR Q3 3 14 DS Q5 5 12 STCP Q4 4 13 STR Q5 5 12 STCP Q6 6 11 SHCP Q6 6 11 SHCP Q7 7 10 SHR Q7 7 10 SHR GND 8 9 Q7S 9 Q3 Q7S 16 VCC 8 1 GND Q1 3 aaa-009698 Transparent top view aaa-009697 Figure 5.  Pin configuration SO16 and TSSOP16 Figure 6.  Pin configuration DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output SHR 10 shift register reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input STR 13 storage register reset (active LOW) DS 14 serial data input VCC 16 supply voltage 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 7 Functional description Table 3. Function table [1] Input Output Function SHCP STCP SHR STR DS Q7S Qn X X L X X L NC a LOW-state on SHR only affects the shift register X X X L X NC L a LOW-state on STR only affects the storage register X ↑ L H X L L empty shift register loaded into storage register ↑ X H X H Q6S NC logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S) X ↑ H H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages ↑ ↑ H H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change. 8 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage Conditions VI < 0 V [1] VO > VCC or VO < 0 V Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V mA - ±50 mA 3-state [1] -0.5 6.5 V output HIGH or LOW state [1] -0.5 VCC + 0.5 V - ±50 mA IO output current ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C - 500 mW Ptot [1] [2] total power dissipation VO = 0 V to VCC Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 9 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions Min Typ 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V 3-state 0 - 5.5 V output HIGH or LOW state 0 - VCC V -40 - +125 °C - - 20 ns/V - - 10 ns/V functional VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 3.6 V Max Unit 10 Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C Min VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.2 V Product data sheet Typ -40 °C to +125 °C Max Min Max Unit 1.08 - - 1.08 - V 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC-0.2 - - VCC-0.3 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V VCC = 1.65 V to 1.95 V HIGH-level output VI = VIH or VIL voltage IO = -100 μA; VCC = 1.65 V to 3.6 V 74LVC594A_Q100 [1] All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 6 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register Symbol Parameter Conditions -40 °C to +85 °C Min VOL LOW-level output voltage [1] Typ -40 °C to +125 °C Max Min Max Unit VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V VCC = 3.6 V; VI = 5.5 V or GND - ±0.1 ±5 - ±20 μA II input leakage current IOFF power-off leakage VCC = 0 V; VI or VO = 5.5 V current - 0.1 10 - 20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 μA ΔICC additional supply current per input pin; VCC = 1.65 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 7 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 11 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter Conditions -40 °C to +85 °C Min tpd propagation delay SHCP to Q7S; see Figure 7 Max Min Max [2] [3] VCC = 1.2 V - 17.5 - - - ns VCC = 1.65 V to 1.95 V 2.0 5.2 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 3.2 8.1 1.5 9.3 ns VCC = 2.7 V 1.5 3.5 7.6 1.5 8.7 ns 1.5 3.1 6.7 1.5 7.7 ns - 19.3 - - - ns VCC = 1.65 V to 1.95 V 2.0 7.6 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 4.8 8.1 1.5 9.3 ns VCC = 2.7 V 1.5 5.2 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.2 4.5 6.7 1.2 7.7 ns - 12.0 - - - ns VCC = 1.65 V to 1.95 V 2.0 5.0 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 3.8 8.1 1.5 9.3 ns VCC = 2.7 V 1.2 3.9 7.6 1.2 8.7 ns VCC = 3.0 V to 3.6 V 1.2 3.3 6.7 1.2 7.7 ns - 20.0 - - - ns VCC = 1.65 V to 1.95 V 2.0 7.7 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 5.0 8.1 1.5 9.3 ns VCC = 2.7 V 1.2 5.3 7.6 1.2 8.7 ns VCC = 3.0 V to 3.6 V 1.2 4.4 6.7 1.2 7.7 ns VCC = 3.0 V to 3.6 V STCP to Qn; see Figure 8 VCC = 1.2 V tPHL [1] Typ -40 °C to +125 °C Unit SHR to Q7S; see Figure 11 HIGH to LOW propagation delay VCC = 1.2 V [2] STR to Qn; see Figure 12 VCC = 1.2 V 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register Symbol Parameter tW pulse width Conditions -40 °C to +85 °C [1] Min Typ VCC = 1.65 V to 1.95 V 6.0 VCC = 2.3 V to 2.7 V -40 °C to +125 °C Unit Max Min Max 2.5 - 7.0 - ns 5.0 2.0 - 5.5 - ns VCC = 2.7 V 4.5 1.5 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.5 - 4.5 - ns VCC = 1.65 V to 1.95 V 6.0 2.5 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 2.0 - 4.5 - ns VCC = 2.7 V 2.5 1.5 - 3.0 - ns VCC = 3.0 V to 3.6 V 2.5 1.5 - 3.0 - ns VCC = 1.65 V to 1.95 V 5.0 1.0 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 0.8 - 4.5 - ns VCC = 2.7 V 2.0 0.6 - 2.5 - ns VCC = 3.0 V to 3.6 V 2.0 0.6 - 2.5 - ns VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns VCC = 2.7 V 4.0 1.8 - 4.5 - ns VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns VCC = 2.7 V 4.0 1.8 - 4.5 - ns 4.0 1.7 - 4.5 - ns VCC = 1.65 V to 1.95 V 1.5 0.2 - 2.0 - ns VCC = 2.3 V to 2.7 V 1.5 0.1 - 2.0 - ns VCC = 2.7 V 1.5 -0.1 - 2.0 - ns VCC = 3.0 V to 3.6 V 1.0 -0.2 - 1.5 - ns SHCP, STCP HIGH or LOW; see Figure 7 and Figure 8 SHR, STR LOW; see Figure 11 and Figure 12 tsu set-up time DS to SHCP; see Figure 9 SHR to STCP; see Figure 10 SHCP to STCP; see Figure 8 VCC = 3.0 V to 3.6 V th hold time 74LVC594A_Q100 Product data sheet DS to SHCP; see Figure 9 [3] All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 9 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register Symbol Parameter Conditions -40 °C to +85 °C Min trec recovery time fmax maximum frequency CPD [1] [2] [3] [4] [5] output skew time power dissipation capacitance Max Min Max SHR to SHCP, STR to STCP; see Figure 11 and Figure 12 VCC = 1.65 V to 1.95 V 5.0 -2.7 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 -1.5 - 4.5 - ns VCC = 2.7 V 2.0 -1.0 - 2.5 - ns VCC = 3.0 V to 3.6 V 2.0 -1.0 - 2.5 - ns VCC = 1.65 V to 1.95 V 80 130 - 70 - MHz VCC = 2.3 V to 2.7 V 100 140 - 90 - MHz VCC = 2.7 V 110 150 - 100 - MHz 130 180 - 115 - MHz - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 50 - - - pF VCC = 2.3 V to 2.7 V - 45 - - - pF VCC = 3.0 V to 3.6 V - 44 - - - pF SHCP or STCP; see Figure 7 and Figure 8 VCC = 3.0 V to 3.6 V tsk(o) [1] Typ -40 °C to +125 °C Unit VCC = 3.0 V to 3.6 V [4] VI = GND to VCC [5] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. Cascadability is guaranteed under identical VCC and temperature conditions. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 10 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 12 Waveforms and test circuit 1/fmax VI SHCP input VM GND tW t PHL t PLH VOH VM Q7S output VOL mna557 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Figure 7.  The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency VI SHCP input VM GND 1/fmax t su VI STCP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna558 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Figure 8.  The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 11 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register VI VM SHCP input GND t su t su th th VI VM DS input GND VOH VM Q7S output VOL mna560 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Figure 9.  The data set-up and hold times for the serial data input (DS) SHR input VM tsu STCP input Qn outputs VM VM mbc326 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Figure 10.  The shift reset (SHR) to storage clock (STCP) set-up times 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 12 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register SHR input VM tW trec VM SHCP input tPHL VM Q7S output mbc324 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Figure 11.  The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the shift reset to shift clock (SHCP) recovery time STR input VM tW trec VM STCP input tPHL Qn outputs VM mbc325 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Figure 12.  The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays and the storage reset to storage clock (STCP) recovery time Table 8. Measurement points Supply voltage Input Output VCC VM VM VCC < 2.7 V 0.5 x VCC 0.5 x VCC VCC ≥ 2.7 V 1.5 V 1.5 V 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 13 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Figure 13.  Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 x VCC GND 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 x VCC GND 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 x VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 x VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 x VCC GND 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 14 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 13 Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 14.  Package outline SOT109-1 (SO16) 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 15 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Figure 15.  Package outline SOT403-1 (TSSOP16) 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 16 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm B D A A E A1 c detail X terminal 1 index area terminal 1 index area C e1 e b 2 y y1 C v M C A B w M C 7 L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Figure 16.  Package outline SOT763-1 (DHVQFN16) 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 17 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 14 Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military TTL Transistor-Transistor Logic 15 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC594A_Q100 v.2 20170721 Product data sheet - 74LVC594A_Q100 v.1 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Table 7: table note added for cascading purposes. 74LVC594A_Q100 v.1 20131115 74LVC594A_Q100 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 - © Nexperia B.V. 2017. All rights reserved. 18 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register 16 Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation 74LVC594A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 19 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 74LVC594A_Q100 Product data sheet 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 July 2017 © Nexperia B.V. 2017. All rights reserved. 20 / 21 74LVC594A-Q100 Nexperia 8-bit shift register with output register Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................2 Ordering information .......................................... 2 Functional diagram ............................................. 2 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 Limiting values .................................................... 5 Recommended operating conditions ................ 6 Static characteristics .......................................... 6 Dynamic characteristics .....................................8 Waveforms and test circuit .............................. 11 Package outline .................................................15 Abbreviations .................................................... 18 Revision history ................................................ 18 Legal information .............................................. 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 July 2017 Document identifier: 74LVC594A_Q100