74LV595DB,118

74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 4 — 18 March 2016 Product data sheet 1. General description The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS device and is pin and functionally compatible with the 74HC595 and 74HCT595. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial output (Q7S) for cascading the device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features and benefits          Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 C Specified from 40 C to +85 C and from 40 C to +125 C Has a shift register with direct clear Multiple package options Output capability:  Parallel outputs; bus driver  serial output; standard ESD protection:  HBM JESD22-A114E exceeds 2000 V  MM JESD22-A115-A exceeds 200 V 3. Applications  Serial-to-parallel data conversion  Remote control holding register 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 5. Functional diagram  (1    6+&3 67&3 46 4 4 4  4 '6 4 4 4 4 05  Fig 1. &   &   65* 5   ' '               2(    PQD PQD Logic symbol Fig 2. Logic symbol (IEEE/IEC)  '6  6+&3  05 67$*(6+,)75(*,67(5 46  67&3  2(  %,76725$*(5(*,67(5 67$7(2873876 4 4 4 4 4 4 4 4   Fig 3.       PQD Functional diagram 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 2 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 67$*( '6 ' 67$*(672 ' 4 67$*( ' 4 )) &3 46 4 )) &3 5 5 6+&3 05 ' 4 ' 4 /$7&+ /$7&+ &3 &3 67&3 2( PQD 4 Fig 4. 4 4 4 4 4 4 4 Logic diagram 6+&3 '6 67&3 05 2( =VWDWH 4 =VWDWH 4 =VWDWH 4 =VWDWH 4 46 PQD Fig 5. Timing diagram 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 3 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6. Pinning information 6.1 Pinning /9 4   9&& 4   4 4   '6 4   2( 4   67&3 4   6+&3 4  *1'  /9  05  46 4   9&& 4   4 4   '6 4   2( 4   67&3 4   6+&3 4   05 *1'   DDM Fig 6. 46 POD Pin configuration SO16 Fig 7. Pin configuration SSOP16, TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q0 to Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input VCC 16 supply voltage 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 4 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 7. Functional description Function table[1] Table 3. Input Output Function SHCP STCP OE MR DS Q7S Qn X L X L NC X L a LOW-state on MR only affects the shift register X  L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state  X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X  L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages   L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] H = HIGH voltage state; L = LOW voltage state;  = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK IO Conditions Min Max Unit 0.5 +4.6 V VI < 0.5 V or VI > VCC + 0.5 V - 20 mA output clamping current VI < 0.5 V or VI > VCC + 0.5 V - 50 mA output current 0.5 V < VO < VCC + 0.5 V - standard driver outputs 25 mA bus driver outputs 35 mA 50 mA ICC supply current standard driver outputs IGND ground current standard driver outputs 50 mA bus driver outputs 70 mA bus driver outputs Tstg storage temperature Ptot total power dissipation 70 mA 65 +150 C - 500 mW Tamb = 40 C to +125 C SO16, SSOP16, TSSOP16 [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 5 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Typ Max Unit 1.0 3.3 3.6 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 - +125 C t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V all outputs; VI = VIH or VIL; IO = 100 A; VCC = 1.2 V - 1.2 - - - V VCC = 2.0 V 1.8 2.0 - 1.8 - V VCC = 2.7 V 2.5 2.7 - 2.5 - V VCC = 3.0 V 2.8 3.0 - 2.8 - V 2.4 2.82 - 2.2 - V 2.4 2.82 - 2.2 - V standard outputs; VI = VIH or VIL; IO = 6 mA; VCC = 3.0 V bus outputs; VI = VIH or VIL; IO = 8 mA; VCC = 3.0 V 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 6 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 0 - - - V VCC = 2.0 V - 0 0.2 - 0.2 V VCC = 2.7 V - 0 0.2 - 0.2 V VCC = 3.0 V all outputs; VI = VIH or VIL; IO = 100 A; - 0 0.2 - 0.2 V standard driver outputs VCC = 3.0 V; IO = 6 mA - 0.25 0.4 - 0.5 V bus driver outputs VCC = 3.0 V; IO = 8 mA - 0.20 0.4 - 0.5 V II input leakage current VCC = 3.6 V; VI = 5.5 V or GND - - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VO =VCC or GND; VCC = 3.6 V - - 5 - 10 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - - 20 - 160 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V - - 500 - 850 A CI input capacitance - 3.5 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 7 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tpd 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 95 - - - ns VCC = 2.0 V - 32 61 - 75 ns VCC = 2.7 V - 24 45 - 55 ns propagation delay SHCP to Q7S; see Figure 8 [2] VCC = 3.3 V; CL = 15 pF VCC = 3.0 V to 3.6 V STCP to Qn; see Figure 9 [3] - 15 - - - ns - 18 36 - 44 ns - 100 - - - ns [2] VCC = 1.2 V VCC = 2.0 V - 34 65 - 77 ns VCC = 2.7 V - 25 48 - 56 ns - 16 - - - ns - 19 38 - 45 ns VCC = 1.2 V - 85 - - - ns VCC = 2.0 V - 29 56 - 66 ns VCC = 2.7 V - 21 41 - 49 ns VCC = 3.3 V; CL = 15 pF VCC = 3.0 V to 3.6 V [3] MR to Q7S; see Figure 11 VCC = 3.3 V; CL = 15 pF ten enable time VCC = 3.0 V to 3.6 V [3] OE to Qn; see Figure 12 [4] VCC = 1.2 V disable time - - ns - 33 ns - 85 - - - ns - 29 56 - 66 ns - 21 41 - 49 ns - 16 33 - 39 ns VCC = 1.2 V - 65 - - - ns VCC = 2.0 V - 24 40 - 49 ns - 18 32 - 37 ns - 14 26 - 30 ns OE to Qn; see Figure 12 VCC = 3.0 V to 3.6 V Product data sheet 33 VCC = 2.7 V [5] VCC = 2.7 V 74LV595 14 16 VCC = 2.0 V VCC = 3.0 V to 3.6 V tdis - [3] All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 8 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tW pulse width 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max 34 10 - 41 - ns 25 8 - 30 - ns 20 6 - 24 - ns 34 7 - 41 - ns 25 5 - 30 - ns 20 4 - 24 - ns 34 10 - 41 - ns 25 8 - 30 - ns 20 6 - 24 - ns VCC = 1.2 V - 40 - - - ns VCC = 2.0 V 26 14 - 31 - ns 19 10 - 23 - ns 15 8 - 18 - ns VCC = 1.2 V - 40 - - - ns VCC = 2.0 V 26 14 - 31 - ns VCC = 2.7 V 19 10 - 23 - ns 15 8 - 18 - ns VCC = 1.2 V - 10.0 - - - ns VCC = 2.0 V 5.0 4.0 - 5.0 - ns VCC = 2.7 V 5.0 3.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 5.0 2.0 - 5.0 - ns VCC = 1.2 V - 35 - - - ns VCC = 2.0 V 5.0 12.0 - 5.0 - ns 5.0 9.0 - 5.0 - ns 5.0 7.0 - 5.0 - ns SHCP, HIGH or LOW; see Figure 8 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] STCP, HIGH or LOW; see Figure 9 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] MR LOW; see Figure 11 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time [3] DS to SHCP; see Figure 10 VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] SHCP to STCP; see Figure 9 VCC = 3.0 V to 3.6 V th trec hold time recovery time [3] DS to SHCP; see Figure 10 MR to SHCP; see Figure 11 VCC = 2.7 V VCC = 3.0 V to 3.6 V 74LV595 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 9 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter fmax maximum frequency 40 C to +85 C Conditions Max Min Max VCC = 2.0 V 14.0 40.0 - 12 - MHz VCC = 2.7 V 19.0 58.0 - 16 - MHz SHCP or STCP; see Figure 8 and Figure 9 VCC = 3.0 V to 3.6 V power dissipation capacitance [1] VI = GND to VCC; VCC = 3.0 V - 77 - - - MHz [3] 24.0 70.0 - 20 - MHz [7] - 115 - - - pF Typical values are measured at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [3] Typical value measured at VCC = 3.3 V. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. [6] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [7] Unit Min VCC = 3.3 V; CL = 15 pF CPD 40 C to +125 C Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. Waveforms IPD[ 9, 6+&3LQSXW 90 *1' W: W 3+/ W 3/+ 92+ 46RXWSXW  92/ 90 PQD Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 8. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 10 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9, 6+&3LQSXW 90 *1' IPD[ W VX 9, 67&3LQSXW 90 *1' W: W 3+/ W 3/+ 92+ 90 4QRXWSXW  92/ PQD Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 9, 90 6+&3LQSXW *1' W VX W VX WK WK 9, 90 '6LQSXW *1' 92+ 90 46RXWSXW 92/ PQD Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The data set-up and hold times for the serial data input (DS) 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 11 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9, 90 05LQSXW  *1' W: W UHF 9, 6+&3LQSXW  *1' 90 W 3+/ 92+ 90 46RXWSXW 92/ PQD Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time 9, 90 2(LQSXW *1' W3/= W3=/ 9&& RXWSXW /2:WR2)) 2))WR/2: 90 9; 92/ W3+= 92+ W3=+ 9< RXWSXW +,*+WR2)) 2))WR+,*+ 90 *1' RXWSXWV HQDEOHG RXWSXWV GLVDEOHG RXWSXWV HQDEOHG DDH Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. Enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY VCC < 2.7 V 0.5VCC 0.5VCC VOL  0.1VCC VOH  0.1VCC VCC  2.7 V 1.5 V 1.5 V VOL  0.3 V VOH  0.3 V 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 12 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9, W:  QHJDWLYH SXOVH 90 9 WI WU WU WI 9,  SRVLWLYH SXOVH 9 90  90 90  W: 9(;7 9&& * 9, 5/ 92 '87 57 5/ &/ DDH Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH < 2.7 V VCC  2.5 ns 50 pF 1 k open 2VCC GND 2.7 V to 3.6 V 2.7 V  2.5 ns 50 pF 1 k open 2VCC GND 74LV595 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 13 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 13. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 14. Package outline SOT109-1 (SO16) 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 14 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 15. Package outline SOT338-1 (SSOP16) 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 15 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 16. Package outline SOT403-1 (TSSOP16) 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 16 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV595 v.4 20160318 Product data sheet - 74LV595 v.3 - 74LV595 v.2 Modifications: 74LV595 v.3 Modifications: • Type number 74LV595N (SOT38-4) removed. 20090421 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74LV595 v.2 980402 Product data sheet - 74LV595 v.1 74LV595 v.1 970606 Product data sheet - - 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 17 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LV595 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 18 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 March 2016 © Nexperia B.V. 2017. All rights reserved 19 of 20 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 18 March 2016