74AVCH4T245PW-Q10J

74AVCH4T245-Q100 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 3 — 12 March 2020 Product data sheet 1. General description The 74AVCH4T245-Q100 is a 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features two 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), an output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied with any voltage between 0.8 V and 3.6 V. This feature makes the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (nOE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn outputs are in the high-impedance OFF-state. The bus hold circuitry on the powered-up side always stays active. The 74AVCH4T245-Q100 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range: • VCC(A): 0.8 V to 3.6 V • VCC(B): 0.8 V to 3.6 V Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) ESD protection: • MIL-STD-883, method 3015 Class 3B exceeds 8000 V • HBM JESD22-A114E Class 3B exceeds 8000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω) Maximum data rates: • 380 Mbit/s (≥ 1.8 V to 3.3 V translation) • 200 Mbit/s (≥ 1.1 V to 3.3 V translation) • 200 Mbit/s (≥ 1.1 V to 2.5 V translation) • 200 Mbit/s (≥ 1.1 V to 1.8 V translation) • 150 Mbit/s (≥ 1.1 V to 1.5 V translation) • 100 Mbit/s (≥ 1.1 V to 1.2 V translation) 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state • • • • • • • Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH4T245D-Q100 -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74AVCH4T245PW-Q100 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74AVCH4T245BQ-Q100 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 4. Marking Table 2. Marking codes Type number Marking code 74AVCH4T245D-Q100 74AVCH4T245D 74AVCH4T245PW-Q100 CH4T245 74AVCH4T245BQ-Q100 H4T245 5. Functional diagram 13 12 1B1 VCC(A) 15 2 1B2 10 2B1 2B2 VCC(B) 1OE 2OE 1DIR 2DIR 1A1 4 Fig. 1. 11 1A2 5 2A1 6 14 3 2A2 7 001aak280 Logic symbol 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 2 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state DIR OE A1 B1 A2 B2 VCC(A) VCC(B) 001aak281 Fig. 2. Logic diagram (one 2-bit transceiver) 6. Pinning information 6.1. Pinning 74AVCH4T245-Q100 VCC(A) 1 16 VCC(B) 1DIR 2 15 1OE 2DIR 3 14 2OE 1A1 1A2 2A1 4 5 6 2A2 7 GND 8 74AVCH4T245-Q100 VCC(A) 1 13 1B1 12 1B2 11 2B1 10 2B2 9 16 VCC(B) 1DIR 2 15 1OE 2DIR 3 14 2OE 1A1 4 13 1B1 1A2 5 12 1B2 2A1 6 11 2B1 2A2 7 10 2B2 GND 8 GND 9 aaa-003609 aaa-003608 Fig. 3. Pin configuration SOT109-1 (SO16) 74AVCH4T245_Q100 Product data sheet GND Fig. 4. Pin configuration SOT403-1 (TSSOP16) All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 3 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 1 terminal 1 index area 16 VCC(B) VCC(A) 74AVCH4T245-Q100 1DIR 2 15 1OE 2DIR 3 14 2OE 1A1 4 13 1B1 1A2 5 12 1B2 2A1 6 2A2 7 GND(1) 11 2B1 8 9 GND GND 10 2B2 Transparent top view aaa-003610 (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 5. Pin configuration SOT763-1 (DHVQFN16) 6.2. Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage A (nAn, nOE and nDIR inputs arereferenced to VCC(A)) 1DIR, 2DIR 2, 3 direction control 1A1, 1A2 4, 5 data input or output 2A1, 2A2 6, 7 data input or output GND [1] 8, 9 ground (0 V) 2B2, 2B1 10, 11 data input or output 1B2, 1B1 12, 13 data input or output 2OE, 1OE 14, 15 output enable input (active LOW) VCC(B) 16 supply voltage B (nBn inputs are referenced to VCC(B)) [1] All GND pins must be connected to ground (0 V). 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input VCC(A), VCC(B) nOE [2] nDIR [2] nAn [2] nBn [2] 0.8 V to 3.6 V L L nAn = nBn input 0.8 V to 3.6 V L H input nBn = nAn 0.8 V to 3.6 V H X Z Z GND [1] X X Z Z [1] [2] Input/output [1] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 4 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC(A) supply voltage A -0.5 +4.6 V VCC(B) supply voltage B -0.5 +4.6 V IIK input clamping current VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode VI < 0 V [1] +4.6 -50 - [1] [2] [3] -0.5 Suspend or 3-state mode [1] -0.5 [2] IO output current VO = 0 V to VCCO ICC supply current per VCC(A) or VCC(B) pin IGND ground current per GND pin Tstg storage temperature Ptot total power dissipation [1] [2] [3] [4] -50 -0.5 Tamb = -40 °C to +125 °C [4] mA V mA VCCO + 0.5 V +4.6 V - ±50 mA - 100 mA -100 - mA -65 +150 °C - 500 mW The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Min Max Unit VCC(A) supply voltage A Conditions 0.8 3.6 V VCC(B) supply voltage B 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCCO V Tamb ambient temperature Δt/ΔV input transition rise and fall rate Active mode [1] Suspend or 3-state mode [1] [2] VCCI = 0.8 V to 3.6 V [2] 0 3.6 V -40 +125 °C - 5 ns/V VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 5 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 10. Static characteristics Table 7. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). VCCO is the supply voltage associated with the output port; VCCI is the supply voltage associated with the data input port. Symbol Parameter Conditions Min Typ Max VOH HIGH-level output voltage VOL VI = VIH or VIL; IO = -1.5 mA; VCC(A) = VCC(B) = 0.8 V - 0.69 - V LOW-level output voltage VI = VIH or VIL; IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V - 0.07 - V II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V - ±0.025 IBHL bus hold LOW current A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V [1] - 26 - μA IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V [2] - -24 - μA IBHLO bus hold LOW overdrive current A or B port; VCC(A) = VCC(B) = 1.2 V [3] - 27 - μA IBHHO bus hold HIGH overdrive current A or B port; VCC(A) = VCC(B) = 1.2 V [4] - -26 - μA IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [5] - ±0.5 ±2.5 μA suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [5] - ±0.5 ±2.5 μA suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [5] - ±0.5 ±2.5 μA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±0.1 ±1 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±0.1 ±1 μA IOFF power-off leakage current Unit ±0.25 μA CI input capacitance nDIR, nOE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 1.0 - pF CI/O input/output capacitance A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 4.0 - pF [1] [2] [3] [4] [5] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND and then raising it to VIL max. The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from LOW to HIGH. An external driver must sink at least IBHHO to switch this node from HIGH to LOW. For I/O ports, the parameter IOZ includes the input leakage current. 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 6 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). VCCO is the supply voltage associated with the output port; VCCI is the supply voltage associated with the data input port. Symbol Parameter VIH HIGH-level input voltage Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCCI = 0.8 V 0.70VCCI - 0.70VCCI - V VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V VCCI = 3.0 V to 3.6 V 2 - 2 - V VCC(A) = 0.8 V 0.70VCC(A) - 0.70VCC(A) - V VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V VCC(A) = 3.0 V to 3.6 V 2 - 2 - V - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCO - 0.1 - VCCO - 0.1 - V IO = -3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - 0.85 - V IO = -6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - 1.05 - V IO = -8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - 1.2 - V IO = -9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - 1.75 - V IO = -12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - 2.3 - V IO = 100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V - 0.1 - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - 0.25 - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - 0.35 - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - 0.45 - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - 0.55 - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - 0.7 - 0.7 V - ±1 - ±5 μA data input nDIR, nOE input VIL LOW-level input data input voltage VCCI = 0.8 V nDIR, nOE input VOH VOL II HIGH-level output voltage LOW-level output voltage input leakage current 74AVCH4T245_Q100 Product data sheet VI = VIH or VIL IO = -100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V VI = VIH or VIL nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 7 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Symbol Parameter IBHL IBHH IBHLO IBHHO IOZ IOFF bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V 15 - 15 - μA VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V 25 - 25 - μA VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V 45 - 45 - μA VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V 100 - 90 - μA VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V -15 - -15 - μA VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V -25 - -25 - μA VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V -45 - -45 - μA VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V -100 - -100 - μA VCC(A) = VCC(B) = 1.6 V 125 - 125 - μA VCC(A) = VCC(B) = 1.95 V 200 - 200 - μA VCC(A) = VCC(B) = 2.7 V 300 - 300 - μA VCC(A) = VCC(B) = 3.6 V 500 - 500 - μA VCC(A) = VCC(B) = 1.6 V -125 - -125 - μA VCC(A) = VCC(B) = 1.95 V -200 - -200 - μA VCC(A) = VCC(B) = 2.7 V -300 - -300 - μA VCC(A) = VCC(B) = 3.6 V -500 - -500 - μA A or B port [1] A or B port [2] A or B port [3] A or B port [4] A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [5] - ±5 - ±30 μA suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [5] - ±5 - ±30 μA suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [5] - ±5 - ±30 μA A port; VI or VO = 0 V to 3.6 V; power-off leakage current VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±5 - ±30 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±5 - ±30 μA OFF-state output current 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 8 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Symbol Parameter ICC supply current Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 10 - 55 μA VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 8 - 50 μA VCC(A) = 3.6 V; VCC(B) = 0 V - 8 - 50 μA VCC(A) = 0 V; VCC(B) = 3.6 V -2 - -12 - μA VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 10 - 55 μA VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 8 - 50 μA VCC(A) = 3.6 V; VCC(B) = 0 V -2 - -12 - μA VCC(A) = 0 V; VCC(B) = 3.6 V - 8 - 50 μA A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 20 - 70 μA A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 16 - 65 μA A port; VI = 0 V or VCCI; IO = 0 A B port; VI = 0 V or VCCI; IO = 0 A [1] [2] [3] [4] [5] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND and then raising it to VIL max. The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from LOW to HIGH. An external driver must sink at least IBHHO to switch this node from HIGH to LOW. For I/O ports, the parameter IOZ includes the input leakage current. Table 9. Typical total supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 μA 0.8 V 0.1 0.1 0.1 0.1 0.1 0.3 1.6 μA 1.2 V 0.1 0.1 0.1 0.1 0.1 0.1 0.8 μA 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.4 μA 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.2 μA 2.5 V 0.1 0.3 0.1 0.1 0.1 0.1 0.1 μA 3.3 V 0.1 1.6 0.8 0.4 0.2 0.1 0.1 μA 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 9 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 11. Dynamic characteristics Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD [1] [2] Conditions VCC(A) = VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V power dissipation A port: (direction nAn to nBn); output enabled capacitance 0.2 0.2 0.2 0.2 0.3 0.4 pF A port: (direction nAn to nBn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF A port: (direction nBn to nAn); output enabled 9.5 9.7 9.8 9.9 10.7 11.9 pF A port: (direction nBn to nAn); output disabled 0.6 0.6 0.6 0.6 0.7 0.7 pF B port: (direction nAn to nBn); output enabled 9.5 9.7 9.8 9.9 10.7 11.9 pF B port: (direction nAn to nBn); output disabled 0.6 0.6 0.6 0.6 0.7 0.7 pF B port: (direction nBn to nAn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF B port: (direction nBn to nAn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 10 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 11. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for wave forms see Fig. 6 and Fig. 7. tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Symbol Parameter Conditions VCC(B) 0.8 V tpd tdis ten propagation delay disable time enable time 1.2 V 1.5 V Unit 1.8 V 2.5 V 3.3 V nAn to nBn 14.5 7.3 6.5 6.2 5.9 6.0 ns nBn to nAn 14.5 12.7 12.4 12.3 12.1 12.0 ns nOE to nAn 14.3 14.3 14.3 14.3 14.3 14.3 ns nOE to nBn 17.0 9.9 9.0 9.4 9.0 9.7 ns nOE to nAn 18.2 18.2 18.2 18.2 18.2 18.2 ns nOE to nBn 19.2 10.7 9.8 9.6 9.7 10.2 ns Table 12. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for wave forms see Fig. 6 and Fig. 7 tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Symbol Parameter Conditions 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V tpd nAn to nBn 14.5 12.7 12.4 12.3 12.1 12.0 ns nBn to nAn 14.5 7.3 6.5 6.2 5.9 6.0 ns nOE to nAn 14.3 5.5 4.1 4.0 3.0 3.5 ns nOE to nBn 17.0 13.8 13.4 13.1 12.9 12.7 ns nOE to nAn 18.2 5.6 4.0 3.2 2.4 2.2 ns nOE to nBn 19.2 14.6 14.1 13.9 13.7 13.6 ns tdis ten propagation delay disable time enable time 74AVCH4T245_Q100 Product data sheet VCC(A) All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 Unit © Nexperia B.V. 2020. All rights reserved 11 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 13. Dynamic characteristics for temperature range -40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for wave forms see Fig. 6 and Fig. 7. tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V propagation delay nAn to nBn 0.5 9.4 0.5 7.1 0.5 6.2 0.5 5.2 0.5 5.1 ns nBn to nAn 0.5 9.4 0.5 8.9 0.5 8.7 0.5 8.4 0.5 8.2 ns tdis disable time nOE to nAn 1.8 10.9 1.8 10.9 1.8 10.9 1.8 10.9 1.8 10.9 ns nOE to nBn 1.9 12.4 1.9 9.6 1.9 9.5 1.4 8.1 1.2 9.1 ten enable time nOE to nAn 1.4 12.8 1.4 12.8 1.4 12.8 1.4 12.8 1.4 12.8 ns nOE to nBn 1.1 13.3 1.1 10.0 1.1 8.9 1.0 7.9 1.0 7.7 ns 8.9 0.3 6.3 0.3 5.2 0.3 4.2 0.3 4.2 ns ns tpd ns VCC(A) = 1.4 V to 1.6 V tpd propagation delay nAn to nBn 0.3 nBn to nAn 0.7 7.1 0.7 6.3 0.5 6.0 0.4 5.7 0.3 5.6 tdis disable time nOE to nAn 1.8 10.2 1.8 10.2 1.5 10.2 1.3 10.2 1.6 10.2 ns nOE to nBn 1.9 11.3 1.9 10.3 1.9 9.1 1.4 7.4 1.2 7.6 ns nOE to nAn 1.1 9.4 1.4 9.4 1.1 9.4 0.7 9.4 0.4 9.4 ns nOE to nBn 1.4 12.1 1.4 9.6 1.1 7.7 0.9 5.8 0.9 5.6 ns ten enable time VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay nAn to nBn 0.1 8.7 0.1 6.0 0.1 4.9 0.1 3.9 0.3 3.9 ns nBn to nAn 0.6 6.2 0.6 5.3 0.5 4.9 0.3 4.6 0.3 4.5 ns disable time nOE to nAn 1.8 8.6 1.6 8.6 1.8 8.6 1.3 8.6 1.6 8.6 ns nOE to nBn 1.7 10.9 1.7 9.9 1.6 8.7 1.2 6.9 1.0 6.9 ns nOE to nAn 1.0 7.2 1.0 7.2 1.0 7.2 0.6 7.2 0.4 7.2 ns nOE to nBn 1.2 11.7 1.2 9.2 1.0 7.4 0.8 5.3 0.8 4.6 ns propagation delay nAn to nBn 0.1 8.4 0.1 5.7 0.1 4.6 0.2 3.5 0.1 3.6 ns nBn to nAn 0.6 5.2 0.6 4.2 0.4 3.9 0.2 3.4 0.2 3.3 ns disable time nOE to nAn 1.0 6.2 1.0 6.2 1.0 6.2 1.0 6.2 1.0 6.2 ns nOE to nBn 1.5 10.4 1.5 8.8 1.3 8.2 1.1 6.2 0.9 5.2 ns nOE to nAn 0.7 4.8 0.7 4.8 0.7 4.8 0.6 4.8 0.4 4.8 ns nOE to nBn 0.9 11.3 0.9 8.8 0.8 7.0 0.6 4.8 0.6 4.0 ns propagation delay nAn to nBn 0.1 8.2 0.1 5.6 0.1 4.5 0.1 3.3 0.1 2.9 ns nBn to nAn 0.6 5.1 0.6 4.2 0.4 3.4 0.2 3.0 0.1 2.8 ns disable time nOE to nAn 0.7 5.6 0.7 5.6 0.7 5.6 0.7 5.6 0.7 5.6 ns nOE to nBn 1.4 10.2 1.4 9.3 1.2 8.1 1.0 6.4 0.8 6.2 ns nOE to nAn 0.6 3.8 0.6 3.8 0.6 3.8 0.6 3.8 0.4 3.8 ns nOE to nBn 0.8 11.3 0.8 8.7 0.6 6.8 0.5 4.7 0.5 3.8 ns enable time VCC(A) = 2.3 V to 2.7 V tpd tdis ten enable time VCC(A) = 3.0 V to 3.6 V tpd tdis ten enable time 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 12 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 14. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for wave forms see Fig. 6 and Fig. 7 tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V propagation delay nAn to nBn 0.5 10.4 0.5 7.9 0.5 6.9 0.5 5.8 0.5 5.7 ns nBn to nAn 0.5 10.4 0.5 9.8 0.5 9.6 0.5 9.3 0.5 9.1 ns tdis disable time nOE to nAn 1.8 12.0 1.8 12.0 1.8 12.0 1.8 12.0 1.8 12.0 ns nOE to nBn 1.9 13.7 1.9 10.6 1.9 10.5 1.4 9.0 1.2 10.1 ns ten enable time nOE to nAn 1.4 14.1 1.4 14.1 1.4 14.1 1.4 14.1 1.4 14.1 ns nOE to nBn 1.1 14.7 1.1 11.0 1.1 9.8 1.0 8.7 1.0 8.5 ns 9.8 0.3 7.0 0.3 5.8 0.3 4.7 0.3 4.7 ns ns tpd VCC(A) = 1.4 V to 1.6 V tpd propagation delay nAn to nBn 0.3 nBn to nAn 0.7 7.9 0.7 7.0 0.5 6.6 0.4 6.3 0.3 6.2 tdis disable time nOE to nAn 1.8 11.3 1.8 11.3 1.5 11.3 1.3 11.3 1.6 11.3 ns nOE to nBn 1.9 12.5 1.9 11.4 1.9 10.1 1.4 8.2 1.2 8.4 nOE to nAn 1.1 10.4 1.4 10.4 1.1 10.4 0.7 10.4 0.4 10.4 ns nOE to nBn 1.4 13.3 1.4 10.6 1.1 8.5 0.9 6.4 0.9 6.2 ns ten enable time ns VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay nAn to nBn 0.1 9.6 0.1 6.6 0.1 5.4 0.1 4.3 0.3 4.3 ns nBn to nAn 0.6 6.9 0.6 5.9 0.5 5.4 0.3 5.1 0.3 5.0 ns disable time nOE to nAn 1.8 9.5 1.6 9.5 1.8 9.5 1.3 9.5 1.6 9.5 ns nOE to nBn 1.7 12.0 1.7 10.9 1.6 9.6 1.2 7.6 1.0 7.6 ns nOE to nAn 1.0 8.0 1.0 8.0 1.0 8.0 0.6 8.0 0.4 8.0 ns nOE to nBn 1.2 12.9 1.2 10.2 1.0 8.2 0.8 5.9 0.8 5.1 ns propagation delay nAn to nBn 0.1 9.3 0.1 6.3 0.1 5.1 0.2 4.0 0.1 4.0 ns nBn to nAn 0.6 5.8 0.6 4.7 0.4 4.3 0.2 3.9 0.2 3.8 ns disable time nOE to nAn 1.0 6.9 1.0 6.9 1.0 6.9 1.0 6.9 1.0 6.9 ns nOE to nBn 1.5 11.5 1.5 10.4 1.3 9.1 1.1 6.9 0.9 5.8 ns nOE to nAn 0.7 5.3 0.7 5.3 0.7 5.3 0.6 5.3 0.4 5.3 ns nOE to nBn 0.9 12.4 0.9 9.7 0.8 7.7 0.6 5.3 0.6 4.4 ns propagation delay nAn to nBn 0.1 9.1 0.1 6.2 0.1 5.0 0.1 3.8 0.1 3.3 ns nBn to nAn 0.6 5.7 0.6 4.7 0.4 3.9 0.2 3.4 0.1 3.3 ns disable time nOE to nAn 0.7 6.2 0.7 6.2 0.7 6.2 0.7 6.2 0.7 6.2 ns nOE to nBn 1.4 11.3 1.4 10.3 1.2 9.0 1.0 7.1 0.8 6.9 ns nOE to nAn 0.6 4.2 0.6 4.2 0.6 4.2 0.6 4.2 0.4 4.2 ns nOE to nBn 0.8 12.4 0.8 9.6 0.6 7.5 0.5 5.2 0.5 4.2 ns enable time VCC(A) = 2.3 V to 2.7 V tpd tdis ten enable time VCC(A) = 3.0 V to 3.6 V tpd tdis ten enable time 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 13 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 11.1. Waveforms VI nAn, nBn input VM GND tPHL tPLH VOH nBn, nAn output VM VOL 001aak285 Measurement points are given in Table 15. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times VI VM nOE input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCCO VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled 001aak286 Measurement points are given in Table 15. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. Enable and disable times Table 15. Measurement points Supply voltage Input [1] Output [2] VCC(A), VCC(B) VM VM VX VY 0.8 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V 3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 14 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 16. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig. 8. Test circuit for measuring switching times Table 16. Test data Supply voltage Input Load VEXT VCC(A), VCC(B) VI [1] Δt/ΔV [2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ [3] 0.8 V to 1.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO 1.65 V to 2.7 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO 3.0 V to 3.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO [1] [2] [3] VCCI is the supply voltage associated with the data input port. dV/dt ≥ 1.0 V/ns VCCO is the supply voltage associated with the output port. 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 15 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 11.2. Typical propagation delay characteristics 001aai476 24 tpd (ns) (1) (2) (3) (4) (5) (6) tpd (ns) (1) 20 001aai477 21 17 16 12 8 4 13 (2) (3) (4) (5) (6) 0 20 40 CL (pF) 60 a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V (1) VCC(B) = 0.8 V. (2) VCC(B) = 1.2 V. (3) VCC(B) = 1.5 V. (4) VCC(B) = 1.8 V. (5) VCC(B) = 2.5 V. (6) VCC(B) = 3.3 V. Fig. 9. 9 0 20 40 CL (pF) 60 b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V (1) VCC(A) = 0.8 V. (2) VCC(A) = 1.2 V. (3) VCC(A) = 1.5 V. (4) VCC(A) = 1.8 V. (5) VCC(A) = 2.5 V. (6) VCC(A) = 3.3 V. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 16 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 001aai478 7 tPLH (ns) 001aai491 7 (1) tPHL (ns) (2) 5 (1) 5 (3) (2) (3) (4) (4) (5) (5) 3 1 3 0 20 40 CL (pF) 1 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V (1) tPLH (ns) 5 20 40 CL (pF) 001aai480 7 tPHL (ns) (1) 5 (2) (3) (2) (3) (4) (5) 3 1 0 20 40 CL (pF) 60 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V 001aai479 7 0 (4) (5) 3 60 c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V 1 0 20 40 CL (pF) 60 d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 17 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 001aai481 7 (1) tPLH (ns) 5 001aai482 7 tPHL (ns) (1) 5 (2) (3) (3) (4) 3 1 (2) (5) 0 20 40 CL (pF) 1 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V tPLH (ns) 0 20 40 CL (pF) 60 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V 001aai483 7 (4) (5) 3 001aai486 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) 1 (3) (4) 3 3 (5) 0 20 40 CL (pF) 60 c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V 1 (4) (5) 0 20 40 CL (pF) 60 d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig. 11. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 18 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 001aai485 7 tPLH (ns) 001aai484 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) 3 3 (4) (4) (5) (5) 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V 1 0 20 40 CL (pF) 60 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig. 12. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 19 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 13. Package outline SOT109-1 (SO16) 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 20 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 14. Package outline SOT403-1 (TSSOP16) 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 21 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm B D A A E A1 c detail X terminal 1 index area terminal 1 index area C e1 e b 2 7 y y1 C v M C A B w M C L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig. 15. Package outline SOT763-1 (DHVQFN16) 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 22 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state 13. Abbreviations Table 17. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVCH4T245_Q100 v.3 20200312 Product data sheet - Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 2 updated. Table 5: Derating values for Ptot total power dissipation updated. 74AVCH4T245_Q100 v.2 20151217 Modifications: • 74AVCH4T245_Q100 v.1 20130916 74AVCH4T245_Q100 Product data sheet 74AVCH4T245_Q100 v.2 Product data sheet - 74AVCH4T245_Q100 v.1 Table 5: conditions ICC and IGND changed (errata). Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 - © Nexperia B.V. 2020. All rights reserved 23 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 24 / 25 74AVCH4T245-Q100 Nexperia 4-bit dual supply translating transceiver with configurable voltage translation; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 4 7. Functional description................................................. 4 8. Limiting values............................................................. 5 9. Recommended operating conditions..........................5 10. Static characteristics..................................................6 11. Dynamic characteristics...........................................10 11.1. Waveforms............................................................... 14 11.2. Typical propagation delay characteristics.................16 12. Package outline........................................................ 20 13. Abbreviations............................................................ 23 14. Revision history........................................................23 15. Legal information......................................................24 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 12 March 2020 74AVCH4T245_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 March 2020 © Nexperia B.V. 2020. All rights reserved 25 / 25