74AVC16T245DGG,112

74AVC16T245 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 7 — 14 January 2019 Product data sheet 1. General description The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs. The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state. 2. Features and benefits • • • • • • • • • Wide supply voltage range: • VCC(A): 0.8 V to 3.6 V • VCC(B): 0.8 V to 3.6 V Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F Class 3B exceeds 8000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101D exceeds 1000 V Maximum data rates: • 380 Mbit/s (≥ 1.8 V to 3.3 V translation) • 200 Mbit/s (≥ 1.1 V to 3.3 V translation) • 200 Mbit/s (≥ 1.1 V to 2.5 V translation) • 200 Mbit/s (≥ 1.1 V to 1.8 V translation) • 150 Mbit/s (≥ 1.1 V to 1.5 V translation) • 100 Mbit/s (≥ 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Specified from -40 °C to +85 °C and -40 °C to +125 °C 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC16T245DGG -40 °C to +125 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74AVC16T245DGV -40 °C to +125 °C TSSOP48 [1] plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 [1] Also known as TVSOP48. 4. Functional diagram 1DIR 2DIR 1OE 1A1 2OE 2A1 1B1 VCC(A) VCC(B) 2B1 VCC(A) to other seven channels Fig. 1. VCC(B) to other seven channels 001aak426 Logic diagram 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 2 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 1B1 VCC(A) 1B2 1B3 1B4 1B5 1B6 1B7 1B8 VCC(B) 1OE 1DIR 1A1 1A2 2B1 VCC(A) 1A3 2B2 1A4 2B3 1A5 2B4 1A6 2B5 1A7 2B6 1A8 2B7 2B8 VCC(B) 2OE 2DIR 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 001aak425 Fig. 2. Logic symbol 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 3 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 5. Pinning information 5.1. Pinning 74AVC16T245 1DIR 1 48 1OE 1B1 2 47 1A1 1B2 3 46 1A2 GND 4 45 GND 1B3 5 44 1A3 1B4 6 43 1A4 VCC(B) 7 42 VCC(A) 1B5 8 41 1A5 1B6 9 40 1A6 GND 10 39 GND 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 14 35 2A2 GND 15 34 GND 2B3 16 33 2A3 2B4 17 32 2A4 VCC(B) 18 31 VCC(A) 2B5 19 30 2A5 2B6 20 29 2A6 GND 21 28 GND 2B7 22 27 2A7 2B8 23 26 2A8 2DIR 24 25 2OE 001aak427 Fig. 3. Pin configuration SOT362-1 and SOT480-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1DIR, 2DIR 1, 24 direction control 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7, 1B8 2, 3, 5, 6, 8, 9, 11, 12 data input or output 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7, 2B8 13, 14, 16, 17, 19, 20, 22, 23 data input or output GND [1] 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC(B) 7, 18 supply voltage B (nBn inputs are referenced to VCC(B)) 1OE, 2OE 48, 25 output enable input (active LOW) 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7, 1A8 47, 46, 44, 43, 41, 40, 38, 37 data input or output 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7, 2A8 36, 35, 33, 32, 30, 29, 27, 26 data input or output VCC(A) 31, 42 supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A)) [1] All GND pins must be connected to ground (0 V). 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 4 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input VCC(A), VCC(B) nOE [2] nDIR [2] nAn [2] nBn [2] 0.8 V to 3.6 V L L nAn = nBn input 0.8 V to 3.6 V L H input nBn = nAn 0.8 V to 3.6 V H X Z Z GND [1] X X Z Z [1] [2] Input/output [1] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC(A) supply voltage A Conditions -0.5 +4.6 V VCC(B) supply voltage B -0.5 +4.6 V IIK input clamping current -50 - VI input voltage [1] -0.5 +4.6 IOK output clamping current VO < 0 V VO output voltage Active mode [1][2][3] -0.5 Suspend or 3-state mode [1] -0.5 +4.6 V [2] - ±50 mA - 100 mA -100 - mA -65 +150 °C - 500 mW VI < 0 V IO output current VO = 0 V to VCCO ICC supply current per VCC(A) or VCC(B) pin IGND ground current per GND pin Tstg storage temperature Ptot total power dissipation [1] [2] [3] [4] Tamb = -40 °C to +125 °C; -50 [4] - mA V mA VCCO + 0.5 V The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 5 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC(A) supply voltage A 0.8 3.6 V VCC(B) supply voltage B 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCCO V 0 3.6 V -40 +125 °C - 5 ns/V Unit Active mode [1] Suspend or 3-state mode Tamb ambient temperature Δt/ΔV input transition rise and fall rate [1] [2] VCCI = 0.8 V to 3.6 V [2] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 9. Static characteristics Table 6. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V VOL IOFF power-off leakage current Min Typ Max - 0.69 - V - 0.07 - V - ±0.025 ±0.25 μA [2] - ±0.5 ±2.5 μA suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [2] - ±0.5 ±2.5 μA suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [2] - ±0.5 ±2.5 μA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±0.1 ±1 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±0.1 ±1 μA IO = -1.5 mA; VCC(A) = VCC(B) = 0.8 V IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V CI input capacitance nDIR, nOE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 2.0 - pF CI/O input/output capacitance A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 4.5 - pF [1] [2] VCCO is the supply voltage associated with the output port. For I/O ports, the parameter IOZ includes the input leakage current. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 6 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter Conditions VIH data input HIGH-level input voltage -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCCI = 0.8 V 0.70VCCI - 0.70VCCI - V VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V VCCI = 3.0 V to 3.6 V 2 - 2 - V VCC(A) = 0.8 V 0.70VCC(A) - 0.70VCC(A) - V VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V VCC(A) = 3.0 V to 3.6 V 2 - 2 - V VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCO - 0.1 - VCCO - 0.1 - V IO = -3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - 0.85 - V IO = -6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - 1.05 - V IO = -8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - 1.2 - V IO = -9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - 1.75 - V IO = -12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - 2.3 - V IO = 100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V - 0.1 - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - 0.25 - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - 0.35 - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - 0.45 - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - 0.55 - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - 0.7 - 0.7 V nDIR, nOE input VIL LOW-level input voltage data input nDIR, nOE input VOH VOL HIGH-level output voltage LOW-level output voltage 74AVC16T245 Product data sheet VI = VIH or VIL IO = -100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 7 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max - ±1 - ±5 μA II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [2] - ±5 - ±30 μA suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [2] - ±5 - ±30 μA suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [2] - ±5 - ±30 μA A port; VI or VO = 0 V to 3.6 V; power-off leakage current VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±5 - ±30 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±5 - ±30 μA VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 30 - 125 μA VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 25 - 100 μA VCC(A) = 3.6 V; VCC(B) = 0 V - 25 - 100 μA VCC(A) = 0 V; VCC(B) = 3.6 V -5 - -20 - μA VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 30 - 125 μA VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 25 - 100 μA VCC(A) = 3.6 V; VCC(B) = 0 V -5 - -20 - μA VCC(A) = 0 V; VCC(B) = 3.6 V - 25 - 100 μA A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 55 - 185 μA A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 45 - 150 μA IOFF ICC supply current A port; VI = 0 V or VCCI; IO = 0 A B port; VI = 0 V or VCCI; IO = 0 A [1] [2] VCCI is the supply voltage associated with the data input port; VCCO is the supply voltage associated with the output port. For I/O ports, the parameter IOZ includes the input leakage current. Table 8. Typicaltotal supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0 0.1 0.1 0.1 0.1 0.1 0.1 μA 0.8 V 0.1 0.1 0.1 0.1 0.1 0.3 1.6 μA 1.2 V 0.1 0.1 0.1 0.1 0.1 0.1 0.8 μA 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.4 μA 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.2 μA 2.5 V 0.1 0.3 0.1 0.1 0.1 0.1 0.1 μA 3.3 V 0.1 1.6 0.8 0.4 0.2 0.1 0.1 μA 0V 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 8 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 10. Dynamic characteristics Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V). [1][2] Symbol Parameter CPD [1] [2] Conditions VCC(A) = VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A port: (direction nAn to nBn); output enabled power dissipation A port: (direction nAn to nBn); output disabled capacitance A port: (direction nBn to nAn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF 0.2 0.2 0.2 0.2 0.3 0.4 pF 9 9.7 9.8 10.3 11.7 13.7 pF A port: (direction nBn to nAn); output disabled 0.6 0.6 0.6 0.7 0.7 0.7 pF B port: (direction nAn to nBn); output enabled 9 9.7 9.8 10.3 11.7 13.7 pF B port: (direction nAn to nBn); output disabled 0.6 0.6 0.6 0.7 0.7 0.7 pF B port: (direction nBn to nAn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF B port: (direction nBn to nAn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF 2 2 CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; 2 N = number of inputs switching; Σ(CL × VCC × fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for wave forms see Fig. 4 and Fig. 5. [1] Symbol Parameter tpd propagation delay tdis disable time ten [1] enable time Conditions VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V nAn to nBn 14.4 7.0 6.2 6.0 5.9 6.0 ns nBn to nAn 14.4 12.4 12.1 11.9 11.8 11.8 ns nOE to nAn 16.2 16.2 16.2 16.2 16.2 16.2 ns nOE to nBn 17.6 10.0 9.0 9.1 8.7 9.3 ns nOE to nAn 21.9 21.9 21.9 21.9 21.9 21.9 ns nOE to nBn 22.2 11.1 9.8 9.4 9.4 9.6 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for wave forms see Fig. 4 and Fig. 5. [1] Symbol Parameter tpd propagation delay tdis disable time ten [1] enable time Conditions VCC(A) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V nAn to nBn 14.4 12.4 12.1 11.9 11.8 11.8 ns nBn to nAn 14.4 7.0 6.2 6.0 5.9 6.0 ns nOE to nAn 16.2 5.9 4.4 4.2 3.1 3.5 ns nOE to nBn 17.6 14.2 13.7 13.6 13.3 13.1 ns nOE to nAn 21.9 6.4 4.4 3.5 2.6 2.3 ns nOE to nBn 22.2 17.7 17.2 17.0 16.8 16.7 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 9 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for wave forms see Fig. 4 and Fig. 5. [1] Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay nAn to nBn 0.5 9.2 0.5 6.9 0.5 6.0 0.5 5.1 0.5 4.9 ns nBn to nAn 0.5 9.2 0.5 8.7 0.5 8.5 0.5 8.2 0.5 8.0 ns disable time nOE to nAn 1.5 11.6 1.5 11.6 1.5 11.6 1.5 11.6 1.5 11.6 ns nOE to nBn 1.5 12.5 1.5 9.7 1.5 9.5 1.0 8.1 1.0 8.9 nOE to nAn 1.0 14.5 1.0 14.5 1.0 14.5 1.0 14.5 1.0 14.5 ns nOE to nBn 1.1 14.9 1.1 11.0 1.1 9.6 1.0 8.1 1.0 7.7 ns propagation delay nAn to nBn 0.5 8.7 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7 ns nBn to nAn 0.5 6.9 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5 ns disable time nOE to nAn 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 ns nOE to nBn 1.5 11.4 1.5 8.7 1.5 7.5 1.0 6.5 1.0 6.3 ns nOE to nAn 1.0 10.1 1.0 10.1 1.0 10.1 1.0 10.1 1.0 10.1 ns nOE to nBn 1.0 13.5 1.0 10.1 0.5 8.1 0.5 5.9 0.5 5.2 ns enable time ns VCC(A) = 1.4 V to 1.6 V tpd tdis ten enable time VCC(A) = 1.65 V to 1.95 V propagation delay nAn to nBn 0.5 8.5 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3 ns nBn to nAn 0.5 6.0 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4 ns tdis disable time nOE to nAn 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 ns nOE to nBn 1.5 11.1 1.5 8.4 1.5 7.1 1.0 5.9 1.0 5.7 ns ten enable time nOE to nAn 1.0 7.8 1.0 7.8 1.0 7.8 1.0 7.8 1.0 7.8 ns nOE to nBn 1.0 13.0 1.0 9.2 0.5 7.4 0.5 5.3 0.5 4.5 ns tpd VCC(A) = 2.3 V to 2.7 V tpd propagation delay nAn to nBn 0.5 8.2 0.5 5.6 0.5 4.6 0.5 3.3 0.5 2.8 ns nBn to nAn 0.5 5.1 0.5 4.1 0.5 3.7 0.5 3.4 0.5 3.2 ns tdis disable time nOE to nAn 1.0 6.1 1.0 6.1 1.0 6.1 1.0 6.1 1.0 6.1 ns nOE to nBn 1.0 10.6 1.0 7.9 1.0 6.6 1.0 6.1 1.0 5.2 ns nOE to nAn 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 ns nOE to nBn 0.5 12.5 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5 ns propagation delay nAn to nBn 0.5 8.0 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7 ns nBn to nAn 0.5 4.9 0.5 3.7 0.5 3.3 0.5 2.9 0.5 2.7 ns disable time nOE to nAn 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 ns nOE to nBn 1.0 10.3 1.0 7.7 1.0 6.5 1.0 5.2 0.5 5.0 ns nOE to nAn 0.5 4.3 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4.0 ns nOE to nBn 0.5 12.4 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4.0 ns ten enable time VCC(A) = 3.0 V to 3.6 V tpd tdis ten [1] enable time tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 10 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for wave forms see Fig. 4 and Fig. 5. [1] Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay nAn to nBn 0.5 10.2 0.5 7.6 0.5 6.6 0.5 5.7 0.5 5.4 ns nBn to nAn 0.5 10.2 0.5 9.6 0.5 9.4 0.5 9.1 0.5 8.8 ns disable time nOE to nAn 1.5 12.8 1.5 12.8 1.5 12.8 1.5 12.8 1.5 12.8 ns nOE to nBn 1.5 13.8 1.5 10.7 1.5 10.5 1.0 9.0 1.5 9.8 nOE to nAn 1.0 16.0 1.0 16.0 1.0 16.0 1.0 16.0 1.0 16.0 ns nOE to nBn 1.1 16.4 1.1 12.1 1.1 10.6 1.0 9.0 1.0 8.5 ns propagation delay nAn to nBn 0.5 9.6 0.5 6.9 0.5 5.8 0.5 4.6 0.5 4.1 ns nBn to nAn 0.5 7.6 0.5 6.9 0.5 6.5 0.5 6.2 0.5 6.1 ns disable time nOE to nAn 1.5 10.1 1.5 10.1 1.5 10.1 1.5 10.1 1.5 10.1 ns nOE to nBn 1.5 12.6 1.5 9.6 1.5 8.3 1.0 7.2 1.0 7.0 nOE to nAn 1.0 11.2 1.0 11.2 1.0 11.2 1.0 11.2 1.0 11.2 ns nOE to nBn 1.0 14.9 1.0 11.2 0.5 9.0 0.5 6.5 0.5 5.8 ns enable time ns VCC(A) = 1.4 V to 1.6 V tpd tdis ten enable time ns VCC(A) = 1.65 V to 1.95 V propagation delay nAn to nBn 0.5 9.4 0.5 6.5 0.5 5.3 0.5 4.1 0.5 3.7 ns nBn to nAn 0.5 6.6 0.5 5.8 0.5 5.3 0.5 5.0 0.5 4.9 ns tdis disable time nOE to nAn 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 ns nOE to nBn 1.5 12.3 1.5 9.3 1.5 7.9 1.0 6.5 1.0 6.3 ns ten enable time nOE to nAn 1.0 8.6 1.0 8.6 1.0 8.6 1.0 8.6 1.0 8.6 ns nOE to nBn 1.0 14.3 1.0 10.2 0.5 8.2 0.5 5.9 0.5 5.0 ns tpd VCC(A) = 2.3 V to 2.7 V tpd propagation delay nAn to nBn 0.5 9.1 0.5 6.2 0.5 5.1 0.5 3.7 0.5 3.1 ns nBn to nAn 0.5 5.7 0.5 4.6 0.5 4.1 0.5 3.8 0.5 3.6 ns tdis disable time nOE to nAn 1.0 6.8 1.0 6.8 1.0 6.8 1.0 6.8 1.0 6.8 ns nOE to nBn 1.0 11.7 1.0 8.7 1.0 7.3 1.0 6.8 1.0 5.8 ns nOE to nAn 0.5 5.9 0.5 5.9 0.5 5.9 0.5 5.9 0.5 5.9 ns nOE to nBn 0.5 13.8 0.5 10.4 0.5 8.1 0.5 5.7 0.5 5.0 ns propagation delay nAn to nBn 0.5 8.8 0.5 6.1 0.5 4.9 0.5 3.6 0.5 3.0 ns nBn to nAn 0.5 5.4 0.5 4.1 0.5 3.7 0.5 3.2 0.5 3.0 ns disable time nOE to nAn 0.5 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 5.5 ns nOE to nBn 1.0 11.4 1.0 8.5 1.0 7.2 1.0 5.8 0.5 5.5 ns nOE to nAn 0.5 4.8 0.5 4.8 0.5 4.7 0.5 4.6 0.5 4.4 ns nOE to nBn 0.5 13.7 0.5 10.3 0.5 8.0 0.5 5.4 0.5 4.4 ns ten enable time VCC(A) = 3.0 V to 3.6 V tpd tdis ten [1] enable time tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 11 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 10.1. Waveforms and test circuit VI nAn, nBn input VM GND tPHL tPLH VOH nBn, nAn output VM VOL 001aak285 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times VI VM nOE input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCCO VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled 001aak286 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. Enable and disable times Table 14. Measurement points Supply voltage Input [1] Output [2] VCC(A), VCC(B) VM VM VX VY 0.8 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V 3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 12 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 15. Test data Supply voltage Input VCC(A), VCC(B) VI [1] Δt/ΔV [2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ [3] 0.8 V to 1.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO 1.65 V to 2.7 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO 3.0 V to 3.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO [1] [2] [3] Load VEXT VCCI is the supply voltage associated with the data input port. dV/dt ≥ 1.0 V/ns VCCO is the supply voltage associated with the output port. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 13 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 11. Typical propagation delay characteristics 001aai476 24 tpd (ns) (1) (2) (3) (4) (5) (6) tpd (ns) (1) 20 001aai477 21 17 16 12 8 4 13 (2) (3) (4) (5) (6) 0 20 40 CL (pF) 60 a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V (1) VCC(B) = 0.8 V. (2) VCC(B) = 1.2 V. (3) VCC(B) = 1.5 V. (4) VCC(B) = 1.8 V. (5) VCC(B) = 2.5 V. (6) VCC(B) = 3.3 V. Fig. 7. 9 0 20 40 CL (pF) 60 b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V (1) VCC(A) = 0.8 V. (2) VCC(A) = 1.2 V. (3) VCC(A) = 1.5 V. (4) VCC(A) = 1.8 V. (5) VCC(A) = 2.5 V. (6) VCC(A) = 3.3 V. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 14 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 001aai478 7 tPLH (ns) 001aai491 7 (1) tPHL (ns) (2) 5 (1) 5 (3) (2) (3) (4) (4) (5) (5) 3 1 3 0 20 40 CL (pF) 1 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V (1) tPLH (ns) 20 40 CL (pF) 60 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V 001aai479 7 0 001aai480 7 tPHL (ns) (1) 5 5 (2) (3) (2) (3) (4) (5) 3 1 0 20 40 CL (pF) (4) (5) 3 60 c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V 1 0 20 40 CL (pF) 60 d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig. 8. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 15 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 001aai481 7 (1) tPLH (ns) 5 001aai482 7 tPHL (ns) (1) 5 (2) (3) (3) (4) 3 1 (2) (5) 0 20 40 CL (pF) 1 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V tPLH (ns) 0 20 40 CL (pF) 60 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V 001aai483 7 (4) (5) 3 001aai486 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) (4) 3 3 (4) (5) (5) 1 0 20 40 CL (pF) 60 c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V 1 0 20 40 CL (pF) 60 d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig. 9. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 16 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 001aai485 7 tPLH (ns) 001aai484 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) 3 3 (4) (4) (5) (5) 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V 1 0 20 40 CL (pF) 60 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 °C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 17 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit max nom min mm A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig. 11. Package outline SOT362-1 (TSSOP48) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 18 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 E D A X c y HE v M A Z 25 48 Q A2 (A 3) A1 pin 1 index A θ Lp L detail X 1 24 w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.85 0.25 0.23 0.13 0.20 0.09 9.8 9.6 4.5 4.3 0.4 6.6 6.2 1 0.7 0.5 0.4 0.3 0.2 0.07 0.08 0.4 0.1 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT480-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 12. Package outline SOT480-1 (TSSOP48) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 19 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 13. Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVC16T245 v.7 20190114 Product data sheet - Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74AVC16T245EV (SOT702-1) and 74AVC16T245BX (SOT1134-2) removed. 74AVC16T245 v.6 20130909 Modifications: • 74AVC16T245 v.5 20120309 Modifications: • 74AVC16T245 v.4 20111208 Modifications: • 74AVC16T245 v.3 20110609 74AVC16T245 v.2 74AVC16T245 v.1 74AVC16T245 Product data sheet 74AVC16T245 v.6 Product data sheet - 74AVC16T245 v.5 Table 4: conditions ICC and IGND changed (errata). Product data sheet - 74AVC16T245 v.4 For type number 74AVC16T245BX the sot code has changed to SOT1134-2. Product data sheet - 74AVC16T245 v.3 Product data sheet - 74AVC16T245 v.2 20100330 Product data sheet - 74AVC16T245 v.1 20091001 Product data sheet - - Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 20 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state 15. 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Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 21 / 22 74AVC16T245 Nexperia 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................6 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 9 10.1. Waveforms and test circuit...................................... 12 11. Typical propagation delay characteristics.............. 14 12. Package outline........................................................ 18 13. Abbreviations............................................................ 20 14. Revision history........................................................20 15. Legal information......................................................21 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 14 January 2019 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 14 January 2019 © Nexperia B.V. 2019. All rights reserved 22 / 22