74HCT74D-Q100,118

74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 4 — 21 April 2020 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Input levels: • For 74HC74-Q100: CMOS level • For 74HCT74-Q100: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDEC standard no. 7A ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package 74HC74D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74HCT74D-Q100 74HC74PW-Q100 74HCT74PW-Q100 74HC74BQ-Q100 74HCT74BQ-Q100 SOT762-1 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 4. Functional diagram 4 2 3 4 4 10 3 1SD 2SD 2 12 3 11 SD 1Q 1D D Q 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 2 1 5 9 10 6 8 11 12 13 1RD 2RD 1 13 Fig. 1. S 5 1 6 10 Logic symbol Fig. 2. 12 S 9 11 C1 1D Q CP Q 1Q 5 6 2SD 2D 2CP SD D Q CP FF Q 2Q 2Q 9 8 RD R 13 IEC logic symbol FF 1Q 1RD 8 Fig. 3. 2RD mna420 Functional diagram Q C C 1CP SD D R mna419 mna418 1D RD C1 1D 1SD C C C C D Q C RD C SD CP mna421 C C Fig. 4. Logic diagram for one flip-flop 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 2 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 5. Pinning information 5.1. Pinning 1RD 1 terminal 1 index area 1D 2 13 2RD 12 2D 1CP 3 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q 1SD 4 11 2CP 1Q 5 1Q 6 GND(1) 13 2RD 10 2SD 9 2Q aaa-004597 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. aaa-004596 Fig. 5. 12 2D 8 14 VCC 3 7 1 2 2Q 1RD 1D 1CP GND 74HC74-Q100 74HCT74-Q100 14 VCC 74HC74-Q100 74HCT74-Q100 Pin configuration for SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 6. Pin configuration for SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 output 2SD 10 asynchronous set-direct input (active LOW) 2CP 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) VCC 14 supply voltage 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 3 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition. Input Output nSD nRD nCP nD nQn+1 nQn+1 H H ↑ L L H H H ↑ H H L 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - +100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [1] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 4 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC74-Q100 74HCT74-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V Tamb = -40 °C to +125 °C Unit 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = -40 °C to +85 °C Min Typ [1] Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V VI = VIH or VIL HIGH-level output voltage IO = -4.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 4.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V - - ±1.0 - ±1.0 μA 74HC74-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage II input leakage current VI = VCC or GND; VCC = 6.0 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 40 - 80 μA CI input capacitance - 3.5 - - - pF 74HCT74-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 5 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger Symbol Parameter VOH VOL Conditions Tamb = -40 °C to +85 °C Typ [1] Max Min Max VI = VIH or VIL; VCC = 4.5 V HIGH-level output voltage IO = -4 mA 3.84 4.32 - 3.7 - V VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage IO = 4.0 mA - 0.15 0.33 - 0.4 V - - ±1.0 - ±1.0 μA - - 40 - 80 μA per input pin; nD, nRD inputs - 70 315 - 343 μA per input pin; nSD, nCP input - 80 360 - 392 μA - 3.5 - - - pF input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ΔICC VI = VCC - 2.1 V; additional supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A [1] Unit Min II CI Tamb = -40 °C to +125 °C VI = VCC or GND; VCC = 5.5 V input capacitance All typical values are measured at Tamb = 25 °C. 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 9. Symbol Parameter Conditions Tamb = -40 °C to +85 °C Tamb = -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 2.0 V - 47 220 - 265 ns VCC = 4.5 V - 17 44 - 53 ns VCC = 5 V; CL = 15 pF - 14 - - - ns - 14 37 - 45 ns VCC = 2.0 V - 50 250 - 300 ns VCC = 4.5 V - 18 50 - 60 ns VCC = 5 V; CL = 15 pF - 15 - - - ns - 14 43 - 51 ns VCC = 2.0 V - 52 250 - 300 ns VCC = 4.5 V - 19 50 - 60 ns VCC = 5 V; CL = 15 pF - 16 - - - ns - 15 43 - 51 ns VCC = 2.0 V - 19 95 - 110 ns VCC = 4.5 V - 7 19 - 22 ns VCC = 6.0 V - 6 16 - 19 ns 74HC74-Q100 tpd propagation delay nCP to nQ, nQ; see Fig. 7 [2] VCC = 6.0 V nSD to nQ, nQ; see Fig. 8 [2] VCC = 6.0 V nRD to nQ, nQ; see Fig. 8 [2] VCC = 6.0 V tt transition time 74HC_HCT74_Q100 Product data sheet nQ, nQ; see Fig. 7 [3] All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 6 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger Symbol Parameter tW pulse width Conditions Tamb = -40 °C to +85 °C Tamb = -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 2.0 V 100 19 - 120 - ns VCC = 4.5 V 20 7 - 24 - ns VCC = 6.0 V 17 6 - 20 - ns VCC = 2.0 V 100 19 - 120 - ns VCC = 4.5 V 20 7 - 24 - ns VCC = 6.0 V 17 6 - 20 - ns VCC = 2.0 V 40 3 - 45 - ns VCC = 4.5 V 8 1 - 9 - ns VCC = 6.0 V 7 1 - 8 - ns VCC = 2.0 V 75 6 - 90 - ns VCC = 4.5 V 15 2 - 18 - ns VCC = 6.0 V 13 2 - 15 - ns VCC = 2.0 V 3 -6 - 3 - ns VCC = 4.5 V 3 -2 - 3 - ns VCC = 6.0 V 3 -2 - 3 - ns VCC = 2.0 V 4.8 23 - 4.0 - MHz VCC = 4.5 V 24 69 - 20 - MHz - 76 - - - MHz 28 82 - 24 - MHz - 24 - - - pF VCC = 4.5 V - 18 44 - 53 ns VCC = 5 V; CL = 15 pF - 15 - - - ns - 23 50 - 60 ns - 18 - - - ns VCC = 4.5 V - 24 50 - 60 ns VCC = 5 V; CL = 15 pF - 18 - - - ns nCP HIGH or LOW; see Fig. 7 nSD, nRD LOW; see Fig. 8 trec tsu th fmax recovery time set-up time hold time maximum frequency nSD, nRD; see Fig. 8 nD to nCP; see Fig. 7 nD to nCP; see Fig. 7 nCP; see Fig. 7 VCC = 5 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [4] nCP to nQ, nQ; see Fig. 7 [2] 74HCT74-Q100 tpd propagation delay nSD to nQ, nQ; see Fig. 8 [2] VCC = 4.5 V VCC = 5 V; CL = 15 pF nRD to nQ, nQ; see Fig. 8 74HC_HCT74_Q100 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 7 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger Symbol Parameter tt transition time Conditions Tamb = -40 °C to +85 °C nQ, nQ; see Fig. 7 pulse width Unit Min Typ [1] Max Min Max - 7 19 - 22 ns 23 9 - 27 - ns 20 9 - 24 - ns 8 1 - 9 - ns 15 5 - 18 - ns 3 -3 - 3 - ns 22 54 - 18 - MHz - 59 - - - MHz - 29 - - - pF [3] VCC = 4.5 V tW Tamb = -40 °C to +125 °C nCP HIGH or LOW; see Fig. 7 VCC = 4.5 V nSD, nRD LOW; see Fig. 8 VCC = 4.5 V trec recovery time nSD, nRD; see Fig. 8 VCC = 4.5 V tsu set-up time nD to nCP; see Fig. 7 VCC = 4.5 V th hold time nD to nCP; see Fig. 7 VCC = 4.5 V fmax maximum frequency nCP; see Fig. 7 VCC = 4.5 V VCC = 5 V; CL = 15 pF CPD [1] [2] [3] [4] power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC - 1.5 V [4] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 8 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 10.1. Waveforms VI nD input VM GND th th tsu 1/fmax tsu VI nCP input VM GND tW tPHL tPLH VOH VM nQ output VOL tPLH tPHL VOH nQ output 90 % 90 % VM VOL 10 % 10 % tTLH tTHL aaa-004005 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the maximum frequency (CP) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 9 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. The set (nSD) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse widths and the nSD, nRD to nCP recovery time Table 9. Measurement points Type Input Output VM VM 74HC74-Q100 0.5VCC 0.5VCC 74HCT74-Q100 1.3 V 1.3 V 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 10 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig. 9. Test circuit for measuring switching times Table 10. Test data Type Input Load Test VI tr, tf CL RL 74HC74-Q100 VCC 6 ns 15 pF, 50 pF 1 kΩ tPLH, tPHL 74HCT74-Q100 3V 6 ns 15 pF, 50 pF 1 kΩ tPLH, tPHL 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 11 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 12 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 11. Package outline SOT402-1 (TSSOP14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 13 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 12. Package outline SOT762-1 (DHVQFN14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 14 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger 12. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT74_Q100 v.4 20200421 Product data sheet - Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 2 updated. Table 5: Derating values for Ptot total power dissipation updated. 74HC_HCT74_Q100 v.3 20151204 Modifications: • 74HC_HCT74_Q100 v.2 20130906 Modifications: • 74HC_HCT74_Q100 v.1 20120807 74HC_HCT74_Q100 Product data sheet 74HC_HCT74_Q100 v.3 Product data sheet - 74HC_HCT74_Q100 v.2 Type number 74HC74N-Q100 (SOT27-1) removed. Product data sheet - 74HC_HCT74_Q100 v.1 - - 74HC74N-Q100 (DIP14) added. Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 15 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 16 / 17 74HC74-Q100; 74HCT74-Q100 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms.................................................................9 11. Package outline........................................................ 12 12. Abbreviations............................................................ 15 13. Revision history........................................................15 14. Legal information......................................................16 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 April 2020 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 21 April 2020 © Nexperia B.V. 2020. All rights reserved 17 / 17