74LVC74AD-Q100J

74LVC74A-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 3 — 18 June 2020 Product data sheet 1. General description The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package 74LVC74AD-Q100 Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC74APW-Q100 -40 °C to +125 °C 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Type number Package Temperature range 74LVC74ABQ-Q100 -40 °C to +125 °C Name Description Version DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 4. Functional diagram 4 2 3 4 4 10 3 1SD 2SD 2 12 3 11 SD 1D D 2D 1CP CP 2CP 2 1Q Q 2Q 1 5 9 10 FF Q RD 1Q 2Q 6 8 11 12 13 1RD 2RD 1 13 Fig. 1. S 5 1 Logic symbol Fig. 2. 6 10 12 S 9 11 C1 1D Q CP Q 1Q 5 6 2SD 2D 2CP SD D Q CP FF Q 2Q 2Q 9 8 RD R 13 IEC logic symbol FF 1Q 1RD 8 Fig. 3. 2RD mna420 Functional diagram Q C C 1CP SD D R mna419 mna418 1D RD C1 1D 1SD C C C C D Q C RD C SD CP mna421 C C Fig. 4. Logic diagram for one flip-flop 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 2 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1. Pinning 1 12 2D 4 11 2CP 1Q 5 1Q 6 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 8 3 1SD 1Q 5 10 2SD 2Q 1CP 1D 1Q 6 9 2Q GND 7 8 2Q GND(1) 13 2RD 10 2SD 9 2Q 001aad107 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 001aad106 Fig. 5. 2 7 14 VCC 1D GND 1 14 VCC terminal 1 index area 74LVC74A 1RD 1RD 74LVC74A Pin configuration for SOT108-1 (SO14), SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) Fig. 6. Pin configuration for SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 true output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 true output 2SD 10 asynchronous set-direct input (active LOW) 2CP 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) VCC 14 supply voltage 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 3 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H Table 4. Function table H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition Input Output nSD nRD nCP nD nQn+1 nQ n+1 H H ↑ L L H H H ↑ H H L 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current ICC Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA -0.5 VCC + 0.5 - ±50 mA supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] [3] Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] VO = 0 V to VCC Tamb = -40 °C to +125 °C [3] mA V The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 4 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Min Typ Max Unit for maximum speed performance 1.65 - 3.6 V for low-voltage applications 1.2 - 3.6 V 0 - 5.5 V 0 - VCC V -40 - +125 °C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage Conditions -40 °C to +85 °C VCC = 1.2 V VCC = 1.65 V to 1.95 V -40 °C to +125 °C Unit Min Typ[1] Max Min Max 1.08 - - 1.08 - V 0.65xVCC - - 0.65xVCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35xVCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC - 0.2 - - VCC - 0.3 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V VI = VIH or VIL HIGH-level output voltage IO = -100 μA; VCC = 1.65 V to 3.6 V VI = VIH or VIL LOW-level output voltage IO = 100 μA; VCC = 1.65 V to 3.6 V 0.35xVCC V II input leakage VCC = 3.6 V; VI = 5.5 V or GND current - ±0.1 ±5 - ±20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 μA 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 5 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Min Typ[1] Max Min Max Unit ΔICC additional per input pin; supply current VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance - 4.0 - - - pF [1] VCC = 0 V to 3.6 V; VI = GND to VCC All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 9. Symbol Parameter Conditions tpd nCP to nQ, nQ; see Fig. 7 propagation delay -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max - 15 - - - ns VCC = 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns VCC = 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns VCC = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns - 15 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns VCC = 2.7 V 1.0 2.9 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns - 15 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns VCC = 2.7 V 1.0 3.0 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns VCC = 1.2 V [2] nSD to nQ, nQ; see Fig. 8 VCC = 1.2 V nRD to nQ, nQ; see Fig. 8 VCC = 1.2 V tW pulse width clock HIGH or LOW; see Fig. 7 set or reset LOW; see Fig. 8 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 6 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter trec recovery time tsu set-up time th hold time fmax maximum frequency Conditions -40 °C to +85 °C Min Typ[1] Max Min Max VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns VCC = 2.7 V 1.5 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 -3.0 - 1.0 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.2 - - 2.2 - ns VCC = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns VCC = 1.65 V to 1.95 V 2.0 - - 2.0 - ns VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 -0.2 - 1.0 - ns VCC = 1.65 V to 1.95 V 100 - - 80 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz VCC = 2.7 V 150 - - 120 - MHz VCC = 3.0 V to 3.6 V 150 250 - 120 - MHz - - 1.0 - 1.5 ns - 12.4 - - - pF VCC = 2.3 V to 2.7 V - 16.0 - - - pF VCC = 3.0 V to 3.6 V - 19.1 - - - pF set or reset; see Fig. 8 nD to nCP; see Fig. 7 nD to nCP; see Fig. 7 nCP; see Fig. 7 tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation per flip-flop; VI = GND to VCC capacitance VCC = 1.65 V to 1.95 V [4] [1] [2] [3] [4] -40 °C to +125 °C Unit Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. tpd is the same as tPLH and tPHL. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL x VCC x fo) = sum of the outputs 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 7 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 10.1. Waveforms and test circuit VI VM nD input GND th t su 1/fmax t su th VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL mna422 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, and the maximum frequency 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 8 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, and the nRD to nCP recovery time Table 9. Measurement points Supply voltage Input Output VCC VI VM VM 1.2 V VCC 0.5 x VCC 0.5 x VCC 1.65 V to 1.95 V VCC 0.5 x VCC 0.5 x VCC 2.3 V to 2.7 V VCC 0.5 x VCC 0.5 x VCC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 9 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig. 9. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr, tf CL RL 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 74LVC74A_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 10 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 11 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 11. Package outline SOT402-1 (TSSOP14) 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 12 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit max nom min mm A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 12. Package outline SOT762-1 (DHVQFN14) 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 13 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 12. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC74A_Q100 v.3 20200618 Product data sheet - 74LVC74A_Q100 v.2 Modifications: • • • • • • 74LVC74A_Q100 v.2 Modifications: 74LVC74A_Q100 v.1 74LVC74A_Q100 Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Table 5: Derating values for Ptot total power dissipation have been updated. Table 10 corrected (errata). Package outline drawing of SOT762-1 (Fig. 12) updated. 20130405 • Product data sheet - 74LVC74A_Q100 v.1 #unique_17: removed redundant temperature range. 20130326 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 - © Nexperia B.V. 2020. All rights reserved 14 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 15 / 16 74LVC74A-Q100 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 8 11. Package outline........................................................ 11 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 18 June 2020 74LVC74A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 16 / 16