74HC112PW,118

74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev. 3 — 9 August 2016 Product data sheet 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits  Input levels:  For 74HC112: CMOS level  For 74HCT112: TTL level  Asynchronous set and reset  Specified in compliance with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74HC112D Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HCT112D 74HC112DB 74HCT112DB 74HC112PW 74HCT112PW SOT338-1 SOT403-1 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 4. Functional diagram   6' 6' 6'   -   &3 &3 &3   . . . 4 4 4   ))  5' 4 4 4   Fig 1. &   .  5' 5'  -     6      5 6 &   . 5 DDD DDD Logic symbol Fig 2. IEC logic symbol 4 . & & & & 4 - & & & & 6 5 &3 & & Fig 3. DDD Logic diagram (one flip-flop) 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 2 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 5. Pinning information 5.1 Pinning +& +&7 &3   9&& .   5' -   5' 6'   &3 4   . 4 4 *1'  +& +&7  -   6'   4 &3   9&& .   5' -   5' 6'   &3 4   . 4   - 4   6' *1'  4 DDD DDD Fig 4.  Pin configuration for SO16 Fig 5. Pin configuration for (T)SSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description 1CP, 2CP 1, 13 clock input (HIGH-to-LOW; edge-triggered) 1K, 2K 2, 12 data input 1J, 2J 3, 11 data input 1SD, 2SD 4, 10 set input (active LOW) 1Q, 2Q 5, 9 true flip-flop output 1Q, 2Q 6, 7 complement flip-flop output GND 8 ground (0 V) 1RD, 2RD 15, 14 reset input (active LOW) VCC 16 supply voltage 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 3 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 6. Functional description Table 3. Function selection[1] Operating modes Input Output nSD nRD nCP nJ nK nQ nQ Asynchronous set L H X X X H L Asynchronous reset H L X X X L H Undetermined L L X X X H L Toggle H H  h h q q Load 0 (reset) H H  l h L H Load 1 (set) H H  h l H L Hold no change H H  l l q q [1] If nSD and nRD simultaneously go from LOW-to-HIGH, the output states are unpredictable. H = HIGH voltage level h = HIGH voltage level one set-up time before the HIGH-to-LOW clock transition L = LOW voltage level l = LOW voltage level one set-up time before the HIGH-to-LOW clock transition q = lowercase letters indicate the state of the referenced output one set-up time before the HIGH-to-LOW clock transition X = don’t care  = HIGH-to-LOW clock transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max 0.5 +7 Unit V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] SO16 and (T)SSOP16 packages [1] For SO16 packages: above 70 C, the value of Ptot derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 C, the value of Ptot derates linearly with 5.5 mW/K. 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 4 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC112 Min Typ 74HCT112 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V 74HC112 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A - - 4.0 - 40 - 80 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 5 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT112 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V IO = 4.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A - - 4.0 - 40 - 80 A - 50 180 - 225 - 245 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ICC additional per input pin; VI = VCC  2.1 V; supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V nSD inputs CI input capacitance 74HC_HCT112 Product data sheet nK inputs - 60 216 - 270 - 294 A nRD inputs - 65 236 - 293 - 319 A nJ, and nCP inputs - 100 360 - 450 - 490 A - 3.5 - - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 6 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max VCC = 2.0 V - 55 175 - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 30 - 37 - 45 ns - 55 175 - 220 - 265 ns 74HC112 tpd propagation delay nCP to nQ; see Figure 6 [2] nCP to nQ; see Figure 6 VCC = 2.0 V VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 30 - 37 - 45 ns VCC = 2.0 V - 58 180 - 225 - 270 ns VCC = 4.5 V - 21 36 - 45 - 54 ns VCC = 5 V; CL = 15 pF - 18 - - - - - ns VCC = 6.0 V - 17 31 - 38 - 46 ns - 50 155 - 295 - 235 ns nRD to nQ, nQ; see Figure 7 nSD to nQ, nQ; see Figure 7 VCC = 2.0 V VCC = 4.5 V - 18 31 - 39 - 47 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 14 26 - 33 - 40 ns VCC = 6.0 V tt tW transition time pulse width nQ, nQ; see Figure 6 [3] VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns nCP HIGH or LOW; see Figure 6 nSD, nRD LOW; see Figure 7 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 7 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8. Symbol Parameter trec 25 C Conditions 40 C to +85 C 40 C to +125 C Min Typ[1] Max Min Max Min Max Unit recovery time nRD to nCP; see Figure 7 VCC = 2.0 V 80 22 - 125 - 150 - ns VCC = 4.5 V 16 8 - 25 - 30 - ns VCC = 6.0 V 14 6 - 21 - 26 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 0 11 - 0 - 0 - ns VCC = 4.5 V 0 4 - 0 - 0 - ns VCC = 6.0 V 0 3 - 0 - 0 - ns VCC = 2.0 V 6 20 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 60 - 24 - 20 - MHz nSD to nCP; see Figure 7 tsu th fmax set-up time hold time maximum frequency nJ and nK to nCP; see Figure 6 nJ and nK to nCP; see Figure 6 nCP; see Figure 6 VCC = 5 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance 74HC_HCT112 Product data sheet CL = 50 pF; f = 1 MHz; VI = GND to VCC [4] - 66 - - - - - MHz 35 71 - 28 - 24 - MHz - 27 - - - pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 8 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max - 21 35 - 44 - 53 ns - 19 - - - - - ns 74HCT112 tpd propagation delay [2] nCP to nQ; see Figure 6 VCC = 4.5 V VCC = 5 V; CL = 15 pF [2] nCP to nQ; see Figure 6 VCC = 4.5 V - 23 40 - 50 - 60 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns nRD to nQ, nQ; see Figure 7 VCC = 4.5 V - 22 37 - 46 - 56 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns nSD to nQ, nQ; see Figure 7 tt tW VCC = 4.5 V - 18 32 - 40 - 48 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 7 15 - 19 - 22 ns 16 8 - 20 - 24 - ns 18 10 - 23 - 27 - ns 20 11 - 25 - 30 - ns 20 8 - 25 - 30 - ns 16 7 - 20 - 24 - ns 0 7 - 0 - 0 - ns 30 64 - 24 - 20 - MHz - 70 - - - - - MHz transition time nQ, nQ; see Figure 6 pulse width nCP HIGH or LOW; see Figure 6 [3] VCC = 4.5 V VCC = 4.5 V nSD, nRD LOW; see Figure 7 VCC = 4.5 V trec recovery time nRD to nCP; see Figure 7 VCC = 4.5 V nSD to nCP; see Figure 7 VCC = 4.5 V tsu set-up time nJ and nK to nCP; see Figure 6 th hold time nJ and nK to nCP; see Figure 6 VCC = 4.5 V VCC = 4.5 V fmax maximum frequency nCP; see Figure 6 VCC = 4.5 V VCC = 5 V; CL = 15 pF 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 9 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8. Symbol Parameter CPD power dissipation capacitance 25 C Conditions CL = 50 pF; f = 1 MHz; VI = GND to VCC [1] All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [4] 40 C to +85 C 40 C to +125 C Min Typ[1] Max Min Max Min Max - 30 - - - - - [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in W). Unit pF PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 10 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 11. Waveforms 9, 90 Q-Q.LQSXW *1' WK WK WVX WVX IPD[ 9, 90 Q&3LQSXW *1' W: W3+/ 92+ W3/+   90 Q4RXWSXW  92/  W7+/ W3/+ W7/+ W3+/ 92+  Q4RXWSXW  90  92/  W7/+ W7+/ DDD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Clock propagation delays, output transition time, pulse width, set-up, hold times, and maximum frequency 74HC_HCT112 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 11 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 9O 90 Q&3LQSXW *1' 9O 90 Q6'LQSXW *1' W: WUHF W: 9O 90 Q5'LQSXW *1' W3/+ W 3+/ 92+ Q4RXWSXW 90 92/ 92+ 90 Q4RXWSXW 92/ W3+/ W3/+ DDD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Set and reset propagation delays, pulse widths and recovery time Table 8. Measurement points Type Input Output VM VM 74HC112 0.5VCC 0.5VCC 74HCT112 1.3 V 1.3 V 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 12 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 9, QHJDWLYH SXOVH W:  90 90  *1' WI 9, WI  SRVLWLYH SXOVH *1' WU WU 90 90  W: 9&& * 9, 92 '87 57 &/ DDK  Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 8. Test circuit for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL 74HC112 VCC 6 ns 15 pF, 50 pF tPLH, tPHL 74HCT112 3V 6 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 13 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG Fig 9. 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Package outline SOT109-1 (SO16) 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 14 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 10. Package outline SOT338-1 (SSOP16) 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 15 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 11. Package outline SOT403-1 (TSSOP16) 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 16 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT112 v.3 20160809 Product data sheet - 74HC_HCT112_CNV v.2 Modifications: 74HC_HCT112_CNV v.2 74HC_HCT112 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Type numbers 74HC112N and 74HCT112N removed. 19980610 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 - © Nexperia B.V. 2017. All rights reserved 17 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 15. 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In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT112 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 18 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74HC_HCT112 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 August 2016 © Nexperia B.V. 2017. All rights reserved 19 of 20 74HC112; 74HCT112 Nexperia Dual JK flip-flop with set and reset; negative-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 09 August 2016