74LVC1G74DC-Q100H

74LVC1G74-Q100 Single D-type flip-flop with set and reset; positive edge trigger Rev. 4 — 25 January 2019 Product data sheet 1. General description The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop. It has individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G74DP-Q100 -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC1G74DC-Q100 -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC1G74GT-Q100 -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 4. Marking Table 2. Marking codes Type number Marking code [1] 74LVC1G74DP-Q100 V74 74LVC1G74DC-Q100 V74 74LVC1G74GT-Q100 V74 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram SD D CP SD Q D CP Q S FF Q C1 Q 1D RD RD Fig. 1. R 001aah757 001aah758 Logic symbol Fig. 2. IEC logic symbol Q C C C C C C D Q C RD C SD CP mna421 C C Fig. 3. Logic diagram 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 2 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 6. Pinning information 6.1. Pinning 74LVC1G74 CP 1 8 VCC D 2 7 SD Q 3 6 RD GND 4 5 Q 74LVC1G74 CP 1 8 VCC D 2 7 SD Q 3 6 RD GND 4 5 Q 001aab658 001aab659 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Transparent top view Fig. 5. Pin configuration SOT833-1 (XSON8) 6.2. Pin description Table 3. Pin description Symbol Pin Description CP 1 clock input (LOW-to-HIGH, edge-triggered) D 2 data input Q 3 complement output GND 4 ground (0 V) Q 5 true output RD 6 asynchronous reset-direct input (active LOW) SD 7 asynchronous set-direct input (active LOW) VCC 8 supply voltage 7. Functional description Table 4. Function table for asynchronous operation H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Output SD RD CP D Q Q L H X X H L H L X X L H L L X X H H 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 3 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger Table 5. Function table for synchronous operation H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. Input Output SD RD CP D Qn+1 Qn+1 H H ↑ L L H H H ↑ H H L 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode [1] -0.5 Power-down mode; VCC = 0 V [1] -0.5 +6.5 V IO output current - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Ptot total power dissipation - 300 mW Tstg storage temperature -65 +150 °C [1] [2] VI < 0 V [1] VO = 0 V to VCC Tamb = -40 °C to +125 °C [2] mA VCC + 0.5 V The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 7. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74LVC1G74_Q100 Product data sheet Conditions Min Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V °C -40 +125 VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 4 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage Conditions Tamb = -40 °C to +85 °C VCC = 1.65 V to 1.95 V Tamb = -40 °C to +125 °C Min Typ [1] Max Min Max Unit 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC - 0.1 - - VCC - 0.1 - V IO = -4 mA; VCC = 1.65 V 1.2 1.54 - 0.95 - V IO = -8 mA; VCC = 2.3 V 1.9 2.15 - 1.7 - V IO = -12 mA; VCC = 2.7 V 2.2 2.50 - 1.9 - V IO = -24 mA; VCC = 3.0 V 2.3 2.62 - 2.0 - V IO = -32 mA; VCC = 4.5 V 3.8 4.11 - 3.4 - V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - 0.07 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - 0.12 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - 0.17 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - 0.39 0.55 - 0.80 V 0.35VCC V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 - ±1 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±2 - ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 - 4 μA ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 - 500 μA CI input capacitance - 4.0 - - - pF [1] All typical values are measured at Tamb = 25 °C. 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 5 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8. Symbol Parameter tpd propagation delay Conditions Tamb = -40 °C to +85 °C Min Typ [1] Max Min Max VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 1.5 13.4 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 1.0 7.1 ns VCC = 2.7 V 1.0 3.5 7.1 1.0 7.1 ns VCC = 3.0 V to 3.6 V 1.0 3.5 5.9 1.0 5.9 ns 1.0 2.5 4.1 1.0 4.1 ns VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns VCC = 2.7 V 2.7 - - 2.7 - ns VCC = 3.0 V to 3.6 V 2.7 1.3 - 2.7 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns VCC = 2.7 V 2.7 - - 2.7 - ns VCC = 3.0 V to 3.6 V 2.7 1.6 - 2.7 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns VCC = 1.65 V to 1.95 V 1.9 - - 1.9 - ns VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - ns VCC = 2.7 V 1.3 - - 1.3 - ns VCC = 3.0 V to 3.6 V +1.2 -3.0 - +1.2 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns CP to Q, Q; see Fig. 6 [2] VCC = 4.5 V to 5.5 V SD to Q, Q; see Fig. 7 RD to Q, Q; see Fig. 7 tW pulse width Tamb = Unit -40 °C to +125 °C [2] [2] CP HIGH or LOW; see Fig. 6 SD and RD LOW; see Fig. 7 trec recovery time 74LVC1G74_Q100 Product data sheet SD or RD; see Fig. 7 All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 6 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger Symbol Parameter tsu th fmax CPD [1] [2] [3] set-up time hold time maximum frequency power dissipation capacitance Conditions Tamb = -40 °C to +85 °C Tamb = Unit -40 °C to +125 °C Min Typ [1] Max Min Max VCC = 1.65 V to 1.95 V 2.9 - - 2.9 - ns VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - ns VCC = 2.7 V 1.7 - - 1.7 - ns VCC = 3.0 V to 3.6 V 1.3 0.5 - 1.3 - ns VCC = 4.5 V to 5.5 V 1.1 - - 1.1 - ns VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.6 - 1.0 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns VCC = 1.65 V to 1.95 V 80 - - 80 - MHz VCC = 2.3 V to 2.7 V 175 - - 175 - MHz VCC = 2.7 V 175 - - 175 - MHz VCC = 3.0 V to 3.6 V 175 280 - 175 - MHz VCC = 4.5 V to 5.5 V 200 - - 200 - MHz - 15 - - - pF D to CP; see Fig. 6 D to CP; see Fig. 6 CP; see Fig. 6 VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 7 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 11.1. Waveforms and test circuit tW VI VM CP input GND 1/fmax VI VM D input GND th th t su t su t PHL t PLH VOH VM Q output VOL VOH Q output VM VOL t PLH t PHL mnb141 Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. The clock input (CP) to output (Q, Q) propagation delays and pulse width, D to CP set-up, CP to D hold times and the maximum frequency 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 8 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger VI VM CP input GND t rec VI VM SD input t rec GND tW tW VI VM RD input GND t PLH t PHL VOH Q output VM VOL VOH VM Q output VOL t PHL t PLH mnb142 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, pulse widths and the RD to CP recovery time Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 9 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 8. Test circuit for measuring switching times Table 11. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2 × VCC 74LVC1G74_Q100 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 10 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 11 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v w y 0.2 0.08 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Fig. 10. Package outline SOT765-1 (VSSOP8) 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 12 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig. 11. Package outline SOT833-1 (XSON8) 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 13 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger 13. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G74_Q100 v.4 20190125 Product data sheet - Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVC1G74GD-Q100 (SOT996-2) removed. Type number 74LVC1G74GT-Q100 (SOT833-1) added. 74LVC1G74_Q100 v.3 20161209 Modifications: • 74LVC1G74_Q100 v.2 20130514 Modifications: • 74LVC1G74_Q100 v.1 20120807 74LVC1G74_Q100 Product data sheet 74LVC1G74_Q100 v.3 Product data sheet - 74LVC1G74_Q100 v.2 Table 8: The maximum limits for leakage current and supply current have changed. Product data sheet - 74LVC1G74_Q100 v.1 - - 74LVC1G74GD-Q100 (XSON8) added. Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 14 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 15 / 16 74LVC1G74-Q100 Nexperia Single D-type flip-flop with set and reset; positive edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 8 12. Package outline........................................................ 11 13. Abbreviations............................................................ 14 14. Revision history........................................................14 15. Legal information......................................................15 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 January 2019 74LVC1G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 16 / 16