74ALVC162836A
20-bit registered driver with inverted register enable and
30 Ω termination resistors; 3-state
Rev. 3 — 6 April 2018
1
Product data sheet
General description
The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output
enable (OE), latch enable (LE) and clock inputs (CP).
When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is
held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the Adata is stored in the latch/flip-flop.
The 74ALVC162836A is designed with 30 Ω series resistors in both HIGH or LOW output
stages.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not affect the state of the
latch/flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied
to VCC through a pullup resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 12 mA at 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
Integrated 30 Ω termination resistors
Diode clamps to VCC and GND on all inputs
Input diodes to accommodate strong drivers
Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
3
Ordering information
Table 1. Ordering information
Type number
74ALVC162836ADGG
4
Package
Temperature range Name
Description
−40 °C to +85 °C
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
TSSOP56
Version
Functional diagram
1
OE
56
CP
29
LE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
OE
CP
LE
A1
D
LE
Y1
CP
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
EN5
3C4
G7
4D
1, 2
8D
5, 6
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
aaa-028395
aaa-026917
Figure 1. Logic diagram (one channel)
Figure 2. IEC logic symbol
VCC
A1
002aac725
Figure 3. Typical input (data or control)
74ALVC162836A
Product data sheet
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2 / 15
74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
5
Pinning information
5.1 Pinning
74ALVC162836A
OE
1
56 CP
Y1
2
55 A1
Y2
3
54 A2
GND
4
53 GND
Y3
5
52 A3
Y4
6
51 A4
VCC
7
Y5
8
50 VCC
49 A5
Y6
9
48 A6
Y7 10
47 A7
GND 11
46 GND
Y8 12
45 A8
Y9 13
44 A9
Y10 14
43 A10
Y11 15
42 A11
Y12 16
41 A12
Y13 17
40 A13
GND 18
39 GND
Y14 19
38 A14
Y15 20
37 A15
Y16 21
36 A16
VCC 22
Y17 23
35 VCC
34 A17
Y18 24
33 A18
GND 25
32 GND
Y19 26
31 A19
Y20 27
30 A20
n.c. 28
29 LE
aaa-028396
Figure 4. Pin configuration TSSOP56 (SOT364-1)
74ALVC162836A
Product data sheet
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3 / 15
74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
A1, A2, A3, A4, A5,
A6, A7, A8, A9, A10,
A11, A12, A13, A14, A15,
A16, A17, A18, A19, A20
55, 54, 52, 51, 49,
48, 47, 45, 44, 43,
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
data inputs
Y1, Y2, Y3, Y4, Y5,
Y6, Y7, Y8, Y9, Y10,
Y11, Y12, Y13, Y14, Y15,
Y16, Y17, Y18, Y19, Y20
2, 3, 5, 6, 8,
9, 10, 12, 13, 14,
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
data outputs
n.c.
28
no connection
LE
29
latch enable input (active LOW)
OE
1
output enable input (active LOW)
CP
56
clock input
(LOW-to-HIGH, edge-triggered)
GND
4, 11, 18, 25, 32, 39, 46, 53
ground (0 V)
VCC
7, 22, 35, 50
supply voltage
6
Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock
transition.
Output
Input
OE
LE
CP
An
Yn
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
H
X
Y0
[1]
L
H
L
X
Y0
[2]
[1] Y0 = Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low.
[2] Y0 = Output level before the indicated steady-state input conditions were established.
74ALVC162836A
Product data sheet
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
-0.5
+4.6
V
input voltage
[1]
-0.5
+4.6
V
VO
output voltage
[1]
-0.5
IIK
input clamping current
VI < 0 V
-
-50
mA
IOK
output clamping current
VO > VCC or VO < 0 V
-
±50
mA
IO
output current
VO = 0 V to VCC
-
±50
mA
ICC
supply current
-
100
mA
IGND
ground current
-100
-
mA
Tstg
storage temperature
-65
+150
°C
-
600
mW
VI
Ptot
[2]
total power dissipation
VCC + 0.5 V
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 package: Ptot derates linearly with 8 mW/K above 55 °C.
8
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
maximum speed performance
VCC = 2.5 V; CL = 30 pF
2.3
-
2.7
V
VCC = 3.3 V; CL = 50 pF
3.0
-
3.6
V
1.2
-
3.6
V
LOW-voltage applications
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
operating in free-air
-40
-
+85
°C
Δt/ΔV
input transition rise and fall rate
VCC = 2.3 V to 3.0 V
0
-
20
ns/V
VCC = 3.0 V to 3.6 V
0
-
10
ns/V
74ALVC162836A
Product data sheet
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; Tamb = −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
Conditions
Min
VIH
HIGH-level input
voltage
VCC = 2.3 V to 2.7 V
1.7
1.2
-
V
VCC = 2.7 V to 3.6 V
2.0
1.5
-
V
LOW-level input
voltage
VCC = 2.3 V to 2.7 V
-
1.2
0.7
V
VCC = 2.7 V to 3.6 V
-
1.5
0.8
V
HIGH-level output
voltage
VI = VIH or VIL
VCC = 2.3 V to 3.6 V; IO = -100 μA
VCC - 0.2
VCC
-
V
VCC = 2.3 V; IO = -4 mA
VCC - 0.4
VCC - 0.11
-
V
VCC = 2.3 V; IO = -6 mA
VCC - 0.6
VCC - 0.17
-
V
VCC = 2.7 V; IO = -4 mA
VCC - 0.5
VCC - 0.09
-
V
VCC = 2.7 V; IO = -8 mA
VCC - 0.7
VCC - 0.19
-
V
VCC = 3.0 V; IO = -6 mA
VCC - 0.6
VCC - 0.13
-
V
VCC = 3.0 V; IO = -12 mA
VCC - 1.0
VCC - 0.27
-
V
VCC = 2.3 V to 3.6 V; IO = 100 μA
-
GND
0.20
V
VCC = 2.3 V; IO = 4 mA
-
0.07
0.40
V
VCC = 2.3 V; IO = 6 mA
-
0.11
0.55
V
VCC = 2.7 V; IO = 4 mA
-
0.06
0.40
V
VCC = 2.7 V; IO = 8 mA
-
0.13
0.60
V
VCC = 3.0 V; IO = 6 mA
-
0.09
0.55
V
VCC = 3.0 V; IO = 12 mA
-
0.19
0.80
V
VIL
VOH
VOL
LOW-level output
voltage
Typ
[1]
Symbol Parameter
Max
Unit
VI = VIH or VIL
II
input leakage current
VCC = 2.3 V to 3.6 V; VI = VCC or GND
-
0.1
5
μA
IOZ
OFF-state output
current
VCC = 2.3 V to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
-
0.1
10
μA
ICC
supply current
VCC = 2.3 V to 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.2
40
μA
ΔICC
additional supply
current
VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A
-
150
750
μA
CI
input capacitance
-
4.0
-
pF
CO
output capacitance
-
8.0
-
pF
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
10 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C; For test circuit, see Figure 11.
Symbol Parameter
tpd
propagation delay
Conditions
Min
Typ
1.0
[1]
Max
Unit
3.5
4.4
ns
-
3.3
4.6
ns
1.2
2.8
4.3
ns
1.1
3.5
5.0
ns
-
3.4
4.8
ns
1.4
2.8
4.4
ns
1.0
3.7
5.4
ns
-
3.8
5.2
ns
1.1
3.2
4.9
ns
1.1
3.5
5.0
ns
-
3.7
5.0
ns
1.2
2.7
4.5
ns
1.0
2.8
4.5
ns
-
3.5
4.9
ns
1.7
3.4
4.8
ns
VCC = 2.3 V to 2.7 V
3.3
1.0
-
ns
VCC = 2.7 V
3.3
1.2
-
ns
VCC = 3.0 V to 3.6 V
3.3
0.7
-
ns
VCC = 2.3 V to 2.7 V;
3.3
0.7
-
ns
VCC = 2.7 V
3.3
0.6
-
ns
VCC = 3.0 V to 3.6 V
3.3
0.6
-
ns
An to CP; VCC = 2.3 V to 3.6 V; Figure 9
1.0
-
-
ns
An to LE; VCC = 2.3 V to 3.6 V; Figure 7
1.5
-
-
ns
[2]
An to Yn; Figure 5
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
LE to Yn; Figure 6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
CP to Yn; Figure 8
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
ten
enable time
OE to Yn; Figure 10
[3]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tdis
disable time
OE to Yn; Figure 10
[4]
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tw
pulse width
CP HIGH or LOW; Figure 8
LE HIGH; see Figure 6
tsu
set-up time
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Product data sheet
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
Symbol Parameter
Conditions
th
An to CP; Figure 9
hold time
[1]
Min
Typ
Max
Unit
VCC = 2.3 V to 2.7 V
1.0
0.4
-
ns
VCC = 2.7 V
1.2
0.4
-
ns
VCC = 3.0 V to 3.6 V
1.2
1.2
-
ns
VCC = 2.3 V to 2.7 V
0.5
0.1
-
ns
VCC = 2.7 V
1.0
0.1
-
ns
VCC = 3.0 V to 3.6 V
1.0
0.4
-
ns
VCC = 2.3 V to 2.7 V
150
190
-
MHz
VCC = 2.7 V
150
190
-
MHz
150
240
-
MHz
transparent mode; output enabled
-
10
-
pF
transparent mode; output disabled
-
3
-
pF
clocked mode; output enabled
-
21
-
pF
clocked mode; output disabled
-
15
-
pF
An to LE; Figure 7
fmax
maximum frequency
CP; Figure 8
VCC = 3.0 V to 3.6 V
CPD
power dissipation
capacitance
[5]
per driver; VI = GND to VCC
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V
[2] tpd is the same as tPHL and tPLH.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in μW):
2
2
PD = CPD x VCC x fi x N +∑(CL x VCC x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
∑(CL x VCC x fo) = sum of outputs.
10.1 Waveforms and test circuit
An input
VI
VM
tPHL
Yn output
tPLH
VM
LE input
tw
GND
VOH
VM
Yn output
VM
tPHL
tPLH
GND
VOH
VM
VOL
002aac727
VOL
002aac726
VI
Measurement points are given in Table 8.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with
VOL and VOH are typical voltage output levels that occur with the output load.
the output load.
Figure 6. LE input pulse width,
Figure 5. Input (An) to output (Yn) propagation delay
LE input to Yn output propagation delays
74ALVC162836A
Product data sheet
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
An
input
LE
input
VM
VI
VM
th
tsu
tsu
GND
th
VM
VI
VM
GND
1 / fmax
CP input
VM
tw
Yn output
VI
VM
GND
tPLH
tPHL
VOH
VM
VOL
002aac729
002aac728
Measurement points are given in Table 8.
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with
the output load.
Figure 7. Data set-up and hold times,
An input to LE input
Figure 8. CP input to Yn output propagation delays,
clock pulse width and maximum clock frequency
CP
input
VI
VM
tsu
th
tsu
th
GND
OE input
VI
An
input
GND
VOH
Yn
output
VOL
002aac730
Measurement points are given in Table 8.
output
LOW-to-OFF
OFF-to-LOW
Figure 9. Data set-up and hold times,
An input to CP input
74ALVC162836A
Product data sheet
tPLZ
VOL
tPZH
VY
outputs
enabled
VCC
VM
VX
output
HIGH-to-OFF
OFF-to-HIGH
GND
tPZL
tPHZ
VOL and VOH are typical voltage output levels that occur with
the output load.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
VI
VM
VM
outputs
disabled
VOH
GND
outputs
enabled
002aac731
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with
the output load.
Figure 10. 3-state enable and disable times
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
Table 8. Measurement points
Supply voltage
Input
VCC
VI
VM
VM
VX
VY
≤ 2.3 V
VCC
0.5 x VCC
0.5 x VCC
VOL + 0.15 V
VOH - 0.15 V
2.3 V to 2.7 V
VCC
0.5 x VCC
0.5 x VCC
VOL + 0.15 V
VOH - 0.15 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
Output
VI
negative
pulse
tW
90 %
VM
0V
VI
positive
pulse
0V
VM
10 %
tf
tr
tr
tf
90 %
VM
VM
10 %
tW
VEXT
VCC
G
VI
RL
VO
DUT
RT
CL
RL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Figure 11. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
≤ 2.3 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2 × VCC
GND
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2 × VCC
GND
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
74ALVC162836A
Product data sheet
Load
VEXT
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
11 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3 )
A1
pin 1 index
A
θ
Lp
L
1
28
w M
bp
e
detail X
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Figure 12. Package outline SOT364-1 (TSSOP56)
74ALVC162836A
Product data sheet
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74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
12 Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
13 Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVC162836A v.3
20180406
Product data sheet
-
74ALVC162836A v.2
Modifications:
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74ALVC162836A v.2
20000620
Product specification
-
74ALVC162836A v.1
74ALVC162836A v.1
20000314
Product specification
-
74ALVC162836 v.1
74ALVC162836 v.1
20000103
Product specification
-
-
74ALVC162836A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 April 2018
© Nexperia B.V. 2018. All rights reserved.
12 / 15
74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
14 Legal information
14.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Notwithstanding any damages that
customer might incur for any reason whatsoever, Nexperia's aggregate and
cumulative liability towards customer for the products described herein shall
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74ALVC162836A
Product data sheet
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification. Customers are responsible for the
design and operation of their applications and products using Nexperia
products, and Nexperia accepts no liability for any assistance with
applications or customer product design. It is customer’s sole responsibility
to determine whether the Nexperia product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 April 2018
© Nexperia B.V. 2018. All rights reserved.
13 / 15
74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
74ALVC162836A
Product data sheet
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 April 2018
© Nexperia B.V. 2018. All rights reserved.
14 / 15
74ALVC162836A
Nexperia
20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
10.1
11
12
13
14
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Functional diagram ............................................. 2
Pinning information ............................................ 3
Pinning ............................................................... 3
Pin description ................................................... 4
Functional description ........................................4
Limiting values .................................................... 5
Recommended operating conditions ................ 5
Static characteristics .......................................... 6
Dynamic characteristics .....................................7
Waveforms and test circuit ................................ 8
Package outline .................................................11
Abbreviations .................................................... 12
Revision history ................................................ 12
Legal information .............................................. 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 6 April 2018
Document identifier: 74ALVC162836A
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