74HC4520D-Q100J

74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter Rev. 2 — 14 February 2019 Product data sheet 1. General description The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Complies with JEDEC standard no. 7A Input levels: • For 74HC4520-Q100: CMOS level • For 74HCT4520-Q100: TTL level ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) 3. Applications • • • Multistage synchronous counting Multistage asynchronous counting Frequency dividers 4. Ordering information Table 1. Ordering information Type number Package 74HC4520D-Q100 74HCT4520D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 5. Functional diagram 1Q0 3 1 1CP0 1Q1 4 2 1CP1 1Q2 5 1Q3 6 7 1MR 2Q0 11 9 2CP0 2Q1 12 10 2CP1 2Q2 13 2Q3 14 15 2MR 001aae698 Fig. 1. Functional diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 nCP0 nCP1 nMR 3 4 nQ0 nQ1 nQ2 nQ3 001aae707 Fig. 2. Timing diagram nQ0 nCP1 nCP0 FF1 CP Q nQ1 FF2 CP RD Q Q RD Q nQ2 FF3 CP nQ3 Q FF4 CP RD Q Q RD Q nMR aaa-015608 Fig. 3. Logic diagram for one counter 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 2 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 6. Pinning information 6.1. Pinning 74HC4520-Q100 74HCT4520-Q100 1CP0 1 16 VCC 1CP1 2 15 2MR 1Q0 3 14 2Q3 1Q1 4 13 2Q2 1Q2 5 12 2Q1 1Q3 6 11 2Q0 1MR 7 10 2CP1 GND 8 9 2CP0 aaa-015632 Fig. 4. Pin configuration SOT109-1 (SO16) 6.2. Pin description Table 2. Pin description Symbol Pin Description 1CP0, 2CP0 1, 9 clock input (LOW-to-HIGH edge-triggered) 1CP1, 2CP1 2, 10 clock input (HIGH-to-LOW edge-triggered) 1Q0 to 1Q3 3, 4, 5, 6 output 1MR, 2MR 7, 15 asynchronous master reset input (active HIGH) GND 8 ground (0 V) 2Q0 to 2Q3 11, 12, 13, 14 output VCC 16 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition. nCP0 nCP1 nMR Mode ↑ H L counter advances L ↓ L counter advances ↓ X L no change X ↑ L no change ↑ L L no change H ↓ L no change X X H nQ0 to nQ3 = LOW 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 3 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7.0 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW 74HCT4520-Q100 Unit [1] [1] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC4520-Q100 Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature °C Δt/ΔV input transition rise and fall rate -40 +25 +125 -40 +25 +125 VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V -40 °C to +125 °C Unit 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C Min Typ -40 °C to +85 °C Max Min Max Min Max 74HC4520-Q100 VIH VIL HIGH-level input voltage LOW-level input voltage 74HC_HCT4520_Q100 Product data sheet VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 4 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter Symbol Parameter Conditions 25 °C Min VOH VOL HIGH-level output voltage LOW-level output voltage Typ -40 °C to +85 °C -40 °C to +125 °C Max Min Max Min Max Unit VI = VIH or VIL IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V μA VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 μA CI input capacitance - 3.5 - - - - - pF 74HCT4520-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 μA - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V μA II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80.0 - 160.0 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A pin nCP0, nCP1 - 80 288 - 360 - 392 μA pin nMR - 150 540 - 675 - 735 μA - 3.5 - - - - - pF CI input capacitance 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 5 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 7. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 77 240 - 300 - 360 ns VCC = 4.5 V - 28 48 - 60 - 72 ns VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns - 22 41 - 51 - 61 ns VCC = 2.0 V - 77 240 - 300 - 360 ns VCC = 4.5 V - 28 48 - 60 - 72 ns VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns VCC = 6.0 V - 22 41 - 51 - 61 ns - 44 150 - 190 - 225 ns - 16 30 - 38 - 45 ns - 13 - - - - - ns - 13 26 - 33 - 38 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 120 39 - 150 - 180 - ns VCC = 4.5 V 24 14 - 30 - 36 - ns VCC = 6.0 V 20 11 - 26 - 31 - ns VCC = 2.0 V 0 -28 - 0 - 0 - ns VCC = 4.5 V 0 -10 - 0 - 0 - ns VCC = 6.0 V 0 -8 - 0 - 0 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns 74HC4520-Q100 tpd propagation delay nCP0 to nQn; see Fig. 5 [1] VCC = 6.0 V nCP1 to nQn; see Fig. 5 tPHL [1] HIGH to LOW nMR to nQn; see Fig. 5 propagation VCC = 2.0 V delay VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tt tW transition time pulse width nQn; see Fig. 5 [2] nCP0, nCP1 HIGH or LOW; see Fig. 6 nMR HIGH; see Fig. 6 trec tsu recovery time nMR to nCP0, nCP1; see Fig. 6 set-up time 74HC_HCT4520_Q100 Product data sheet nCP0 to nCP1; nCP1 to nCP0; see Fig. 5 All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 6 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter Symbol Parameter fmax Conditions 25 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 6 19 - 4.8 - 4 - MHz VCC = 4.5 V 30 58 - 24 - 20 - MHz - 68 - - - - - MHz 35 69 - 28 - 24 - MHz - 29 - - - - - pF VCC = 4.5 V - 28 53 - 66 - 80 ns VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns VCC = 4.5 V - 25 53 - 66 - 80 ns VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns HIGH to LOW nMR to nQn; see Fig. 5 propagation VCC = 4.5 V delay VCC = 5.0 V; CL = 15 pF - 16 35 - 44 - 53 ns - 13 - - - - - ns - 7 15 - 19 - 22 ns 20 10 - 25 - 30 - ns 20 12 - 25 - 30 - ns 0 -8 - 0 - 0 - ns 16 6 - 20 - 24 - ns 30 58 - 24 - 20 - MHz - 64 - - - - - MHz - 24 - - - - - pF maximum frequency nCP0, nCP1; see Fig. 6 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD -40 °C to +85 °C power dissipation capacitance VI = GND to VCC; VCC = 5 V; fi = 1 MHz [3] nCP0 to nQn; see Fig. 5 [1] 74HCT4520-Q100 tpd propagation delay nCP1 to nQn; see Fig. 5 tPHL [1] tt transition time nQn; see Fig. 5 [2] tW pulse width nCP0, nCP1 HIGH or LOW; see Fig. 6 VCC = 4.5 V VCC = 4.5 V nMR HIGH; see Fig. 6 VCC = 4.5 V trec recovery time nMR to nCP0, nCP1; see Fig. 6 VCC = 4.5 V tsu set-up time nCP0 to nCP1; nCP1 to nCP0; see Fig. 5 VCC = 4.5 V fmax maximum frequency nCP0, nCP1; see Fig. 6 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD [1] [2] [3] power dissipation capacitance VI = GND to VCC - 1.5 V; VCC = 5 V; [3] fi = 1 MHz tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 7 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 11.1. Waveforms and test circuit VI VM nCP0 input 0V VI nCP1 input VM 0V 0V tsu tsu VI nMR input VM 0V tPHL tPLH VOH tPHL 90 % nQn output VM 10 % VOL tt tt 001aae702 Measurement points are given in Table 8. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig. 5. nCP0 and nCP1 set-up times, propagation delays and output transition times 1/fmax VI nCP1 input (nCP0 = LOW) VM 0V tW VI nCP0 input (nCP1 = HIGH) VM 0V tW VI nMR input VM 0V tW trec 001aae701 Measurement points are given in Table 8. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig. 6. nMR recovery time, minimum nCP0, nCP1, nMR pulse widths and maximum frequency Table 8. Measurement points Type Input Output VM VI VM 74HC4520-Q100 0.5 × VCC GND to VCC 0.5 × VCC 74HCT4520-Q100 1.3 V GND to 3 V 1.3 V 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 8 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VCC VO DUT RT RL S1 open CL 001aad983 Test data is given in Table 9. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig. 7. Test circuit for measuring switching times Table 9. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH 74HC4520-Q100 GND to VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT4520-Q100 GND to 3 V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 9 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 10 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4520_Q100 v.2 20190214 Product data sheet - Modifications: • • • 74HC_HCT4520_Q100 v.1 74HC_HCT4520_Q100 Product data sheet 74HC_HCT4520_Q100 v.1 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HC4520PW-Q100 (SOT403-1) removed. 20141204 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 - © Nexperia B.V. 2019. All rights reserved 11 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 12 / 13 Nexperia 74HC4520-Q100; 74HCT4520-Q100 Dual 4-bit synchronous binary counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 8 12. Package outline........................................................ 10 13. Abbreviations............................................................ 11 14. Revision history........................................................11 15. Legal information......................................................12 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 14 February 2019 74HC_HCT4520_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 February 2019 © Nexperia B.V. 2019. All rights reserved 13 / 13