74HC4024D-Q100J

74HC4024-Q100 7-stage binary ripple counter Rev. 2 — 23 November 2018 Product data sheet 1. General description The 74HC4024-Q100 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Low-power dissipation Complies with JEDEC standard no. 7A CMOS input levels ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω) 3. Applications • • Frequency dividing circuits Time delay circuits. 4. Ordering information Table 1. Ordering information Type number Package 74HC4024D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC4024-Q100 Nexperia 7-stage binary ripple counter 5. Functional diagram Q6 3 Q5 4 7-STAGE COUNTER 1 Q1 Q3 9 Q1 11 6 Q0 12 2 4 Q5 3 Q6 CP MR 1 2 001aab906 Fig. 1. CP T Fig. 2. Q T FF 2 Q + Q T Q FF 3 T FF 4 Q RD 11 6 CT 5 CT = 0 4 3 001aab907 Fig. 3. Q T FF 5 Q RD 12 9 6 Functional diagram Q RD 0 001aab908 Logic symbol FF 1 1 5 Q4 MR CTR7 Q2 9 11 Q2 2 Q3 6 12 Q0 CP Q4 5 IEC logic symbol Q T FF 6 Q RD Q T Q FF 7 Q RD Q RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 001aab909 Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74HC4024 CP 1 14 VCC MR 2 13 n.c. Q6 3 12 Q0 Q5 4 11 Q1 Q4 5 10 n.c. Q3 6 9 Q2 GND 7 8 n.c. 001aab905 Fig. 5. Pin configuration SOT108-1 (SO14) 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 2 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter 6.2. Pin description Table 2. Pin description Symbol Pin Description CP 1 clock input (HIGH-to-LOW, edge-triggered) MR 2 master reset input (active HIGH) Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0 3, 4, 5, 6, 9, 11, 12 parallel output GND 7 ground (0 V) n.c. 8, 10, 13 not connected VCC 14 positive supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. Output Input MR CP Qn H X L L ↑ no change ↓ count 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage -0.5 +7 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions Min [1] Max Unit For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 3 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Δt/ΔV input transition rise and fall rate Tamb VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V -40 - +125 ambient temperature °C 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V Tamb = 25 °C VIH VIL VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 μA CI input capacitance - 3.5 - pF 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 4 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 - - V IO = -20 μA; VCC = 4.5 V 4.4 - - V IO = -20 μA; VCC = 6.0 V 5.9 - - V IO = -4 mA; VCC = 4.5 V 3.84 - - V IO = -5.2 mA; VCC = 6.0 V 5.34 - - V IO = 20 μA; VCC = 2.0 V - - 0.1 V IO = 20 μA; VCC = 4.5 V - - 0.1 V IO = 20 μA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V Tamb = -40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 μA VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 - - V IO = -20 μA; VCC = 4.5 V 4.4 - - V IO = -20 μA; VCC = 6.0 V 5.9 - - V IO = -4 mA; VCC = 4.5 V 3.7 - - V IO = -5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 μA; VCC = 2.0 V - - 0.1 V IO = 20 μA; VCC = 4.5 V - - 0.1 V IO = 20 μA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V Tamb = -40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 μA 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 5 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Fig. 7. Symbol Parameter Min Typ Max Unit VCC = 2.0 V - 47 175 ns VCC = 4.5 V - 17 35 ns VCC = 6.0 V - 14 30 ns VCC = 5.0 V; CL = 15 pF - 14 - ns VCC = 2.0 V - 25 80 ns VCC = 4.5 V - 9 16 ns VCC = 6.0 V - 7 14 ns VCC = 2.0 V - 63 200 ns VCC = 4.5 V - 23 40 ns VCC = 6.0 V - 18 34 ns VCC = 2.0 V - 19 75 ns VCC = 4.5 V - 7 15 ns VCC = 6.0 V - 6 13 ns VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns VCC = 2.0 V 80 22 - ns VCC = 4.5 V 16 8 - ns VCC = 6.0 V 14 6 - ns VCC = 2.0 V 50 6 - ns VCC = 4.5 V 10 2 - ns VCC = 6.0 V 9 2 - ns VCC = 2.0 V 6.0 27 - MHz VCC = 4.5 V 30 82 - MHz VCC = 6.0 V 35 98 - MHz - 90 - MHz - 25 - pF Conditions Tamb = 25 °C tpd propagation delay CP to Q0; see Fig. 6 Qn to Qn+1; see Fig. 6 tPHL tt tW HIGH to LOW propagation delay transition time pulse width [1] [1] MR to Q0; see Fig. 6 see Fig. 6 [2] CP HIGH or LOW; see Fig. 6 MR HIGH; see Fig. 6 trec fmax recovery time maximum frequency MR to CP; see Fig. 6 CP; see Fig. 6 VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance 74HC4024_Q100 Product data sheet VI = GND to VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 6 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter Symbol Parameter Min Typ Max Unit VCC = 2.0 V - - 220 ns VCC = 4.5 V - - 44 ns VCC = 6.0 V - - 37 ns VCC = 2.0 V - - 100 ns VCC = 4.5 V - - 20 ns VCC = 6.0 V - - 17 ns VCC = 2.0 V - - 250 ns VCC = 4.5 V - - 50 ns - - 43 ns VCC = 2.0 V - - 95 ns VCC = 4.5 V - - 19 ns VCC = 6.0 V - - 16 ns VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 65 - - ns VCC = 4.5 V 13 - - ns VCC = 6.0 V 11 - - ns VCC = 2.0 V 4.8 - - MHz VCC = 4.5 V 24 - - MHz VCC = 6.0 V 28 - - MHz Conditions Tamb = -40 °C to +85 °C tpd propagation delay CP to Q0; see Fig. 6 Qn to Qn+1; see Fig. 6 tPHL HIGH to LOW propagation delay [1] [1] MR to Q0; see Fig. 6 VCC = 6.0 V tt tW transition time pulse width see Fig. 6 [2] CP HIGH or LOW; see Fig. 6 MR HIGH; see Fig. 6 trec fmax recovery time maximum frequency 74HC4024_Q100 Product data sheet MR to CP; see Fig. 6 CP; see Fig. 6 All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 7 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter Symbol Parameter Min Typ Max Unit VCC = 2.0 V - - 265 ns VCC = 4.5 V - - 53 ns VCC = 6.0 V - - 45 ns VCC = 2.0 V - - 120 ns VCC = 4.5 V - - 24 ns VCC = 6.0 V - - 20 ns VCC = 2.0 V - - 300 ns VCC = 4.5 V - - 60 ns - - 51 ns VCC = 2.0 V - - 110 ns VCC = 4.5 V - - 22 ns VCC = 6.0 V - - 19 ns VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns VCC = 2.0 V 4.0 - - MHz VCC = 4.5 V 20 - - MHz VCC = 6.0 V 24 - - MHz Conditions Tamb = -40 °C to +125 °C tpd propagation delay CP to Q0; see Fig. 6 Qn to Qn+1; see Fig. 6 tPHL HIGH to LOW propagation delay [1] [1] MR to Q0; see Fig. 6 VCC = 6.0 V tt transition time tW pulse width see Fig. 6 [2] CP HIGH or LOW; see Fig. 6 MR HIGH; see Fig. 6 trec recovery time fmax [1] [2] [3] maximum frequency MR to CP; see Fig. 6 CP; see Fig. 6 tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 8 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter 11.1. Waveforms and test circuit MR input VM tW trec 1/fmax VM CP input tPHL tPLH tW 90 % Q0 or Qn output tPHL 90 % VM 10 % 10 % tTLH tTHL 001aab910 Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) recovery time. VM = 0.5 x VCC. Fig. 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency VI negative pulse VM tf tr tr VI GND VM 10 % GND positive pulse tW 90 % tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 8. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig. 7. Test circuit for measuring switching times Table 8. Test data Supply Input VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.0 V VCC 6 ns 50 pF 5.0 V VCC 6 ns 15 pF 74HC4024_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 9 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 Fig. 8. JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 10 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter 13. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC4024_Q100 v.2 20181123 Product data sheet - 74HC4024_Q100 v.1 Modifications: • • • 74HC4024_Q100 v.1 74HC4024_Q100 Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HC4024PW-Q100 (SOT402-1/TSSOP14) removed. 20131127 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 - © Nexperia B.V. 2018. All rights reserved 11 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. 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In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 12 / 13 74HC4024-Q100 Nexperia 7-stage binary ripple counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................4 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 9 12. Package outline........................................................ 10 13. Abbreviations............................................................ 11 14. Revision history........................................................11 15. Legal information......................................................12 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 23 November 2018 74HC4024_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 November 2018 © Nexperia B.V. 2018. All rights reserved 13 / 13