RTL8201FI-VC-CG
SINGLE-CHIP/PORT 10/100M ETHERNET
PHYCEIVER WITH AUTO MDIX
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.1
11 March 2015
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8201FI
Datasheet
COPYRIGHT
©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2011/12/06
2015/03/11
Summary
First release.
Corrected Figure 3 Pin Assignments, page 5 (Corrected the package marking from
RTL8201FI to 8201FI.)
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Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................2
3.
APPLICATIONS ................................................................................................................................................................3
3.1.
APPLICATION DIAGRAM ...............................................................................................................................................3
4.
BLOCK DIAGRAM ...........................................................................................................................................................4
5.
PIN ASSIGNMENTS .........................................................................................................................................................5
5.1.
6.
PIN DESCRIPTIONS.........................................................................................................................................................6
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
7.
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................5
MII INTERFACE ............................................................................................................................................................6
SERIAL MANAGEMENT INTERFACE ..............................................................................................................................7
RMII INTERFACE .........................................................................................................................................................8
CLOCK INTERFACE .......................................................................................................................................................8
10MBPS/100MBPS NETWORK INTERFACE ...................................................................................................................8
TRANSMIT BIAS REFERENCE ........................................................................................................................................9
DEVICE CONFIGURATION INTERFACE ..........................................................................................................................9
POWER AND GROUND PINS ........................................................................................................................................10
RESET AND OTHER PINS .............................................................................................................................................11
REGISTER DESCRIPTIONS.........................................................................................................................................12
7.1.
REGISTER 0 BASIC MODE CONTROL REGISTER ..........................................................................................................12
7.2.
REGISTER 1 BASIC MODE STATUS REGISTER .............................................................................................................13
7.3.
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................14
7.4.
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................14
7.5.
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ...................................................................14
7.6.
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)....................................................15
7.7.
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ............................................................................16
7.8.
PAGE 0 REGISTER 13 MACR (MMD ACCESS CONTROL REGISTER; ADDRESS 0X0D) ...............................................17
7.9.
PAGE 0 REGISTER 14 MAADR (MMD ACCESS ADDRESS DATA REGISTER; ADDRESS 0X0E)...................................17
7.10.
REGISTER 24 POWER SAVING MODE REGISTER (PSMR) ...........................................................................................17
7.11.
REGISTER 28 FIBER MODE AND LOOPBACK REGISTER...............................................................................................18
7.12.
REGISTER 30 INTERRUPT INDICATORS AND SNR DISPLAY REGISTER ........................................................................18
7.13.
REGISTER 31 PAGE SELECT REGISTER .......................................................................................................................18
7.14.
PAGE 4 REGISTER 16 EEE CAPABILITY ENABLE REGISTER .......................................................................................19
7.15.
PAGE 4 REGISTER 21 EEE CAPABILITY REGISTER .....................................................................................................19
7.16.
PAGE 7 REGISTER 16 RMII MODE SETTING REGISTER (RMSR) ................................................................................19
7.17.
PAGE 7 REGISTER 17 CUSTOMIZED LEDS SETTING REGISTER ...................................................................................20
7.18.
PAGE 7 REGISTER 18 EEE LEDS ENABLE REGISTER .................................................................................................20
7.19.
PAGE 7 REGISTER 19 INTERRUPT, WOL ENABLE, AND LEDS FUNCTION REGISTERS ................................................21
7.20.
PAGE 7 REGISTER 20 MII TX ISOLATE REGISTER ......................................................................................................22
7.21.
PAGE 7 REGISTER 24 SPREAD SPECTRUM CLOCK REGISTER ......................................................................................22
7.22.
MMD REGISTER MAPPING AND DEFINITION .............................................................................................................22
7.22.1.
EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) .............................................................22
7.22.2.
EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01) ................................................................23
7.22.3.
EEECR (EEE Capability Register, MMD Device 3; Address 0x14)................................................................23
7.22.4.
EEEWER (EEE Wake Error Register, MMD Device 3; Address 0x16) ..........................................................23
7.22.5.
EEEAR (EEE Advertisement Register, MMD Device 7; Address 0x3c) ..........................................................24
7.22.6.
EEELPAR (EEE Link Partner Ability Register, MMD Device 7; Address 0x3d) ............................................24
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8.
FUNCTIONAL DESCRIPTION.....................................................................................................................................25
8.1.
MII AND MANAGEMENT INTERFACE ..........................................................................................................................26
8.1.1. Data Transition ....................................................................................................................................................26
8.1.2. Serial Management Interface ...............................................................................................................................26
8.2.
INTERRUPT .................................................................................................................................................................28
8.3.
AUTO-NEGOTIATION AND PARALLEL DETECTION .....................................................................................................28
8.3.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................28
8.4.
LED FUNCTIONS ........................................................................................................................................................29
8.4.1. LED and PHY Address .........................................................................................................................................29
8.4.2. Link Monitor.........................................................................................................................................................29
8.4.3. RX LED ................................................................................................................................................................30
8.4.4. TX LED.................................................................................................................................................................30
8.4.5. TX/RX LED...........................................................................................................................................................31
8.4.6. LINK/ACT LED ....................................................................................................................................................31
8.4.7. Customized LED...................................................................................................................................................32
8.4.8. EEE LED Behavior...............................................................................................................................................33
8.5.
POWER DOWN AND LINK DOWN POWER SAVING MODES ..........................................................................................33
8.6.
10M/100M TRANSMIT AND RECEIVE.........................................................................................................................34
8.6.1. 100Base-TX Transmit and Receive Operation .....................................................................................................34
8.6.2. 100Base-FX Fiber Transmit and Receive Operation ...........................................................................................34
8.6.3. 10Base-T Transmit and Receive Operation..........................................................................................................34
8.7.
RESET AND TRANSMIT BIAS .......................................................................................................................................35
8.8.
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT......................................................................................35
8.9.
AUTOMATIC POLARITY CORRECTION ........................................................................................................................36
8.10.
FAR END FAULT INDICATION .....................................................................................................................................36
8.11.
WAKE-ON-LAN (WOL)............................................................................................................................................36
8.11.1.
Magic Packet and Wake-Up Frame Format....................................................................................................36
8.11.2.
Active Low Wake-On-LAN...............................................................................................................................37
8.11.3.
Pulse Low Wake-On-LAN................................................................................................................................38
8.11.4.
Wake-On-LAN Pin Types (MII Mode) .............................................................................................................39
8.11.5.
Wake-On-LAN Pin Types (RMII Mode)...........................................................................................................39
8.12.
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................40
8.13.
SPREAD SPECTRUM CLOCK (SSC) .............................................................................................................................40
9.
CHARACTERISTICS......................................................................................................................................................41
9.1.
DC CHARACTERISTICS ...............................................................................................................................................41
9.1.1. Absolute Maximum Ratings ..................................................................................................................................41
9.1.2. Recommended Operating Conditions ...................................................................................................................41
9.1.3. Power On and PHY Reset Sequence.....................................................................................................................42
9.1.4. RMII Input Mode Power Dissipation ...................................................................................................................43
9.1.5. Input Voltage: Vcc................................................................................................................................................43
9.2.
AC CHARACTERISTICS ...............................................................................................................................................44
9.2.1. MII Transmission Cycle Timing ...........................................................................................................................44
9.2.2. MII Reception Cycle Timing.................................................................................................................................45
9.2.3. RMII Transmission and Reception Cycle Timing .................................................................................................46
9.2.4. MDC/MDIO Timing .............................................................................................................................................48
9.2.5. Transmission without Collision ............................................................................................................................49
9.2.6. Reception without Error .......................................................................................................................................49
9.3.
CRYSTAL CHARACTERISTICS .....................................................................................................................................50
9.4.
OSCILLATOR REQUIREMENTS ....................................................................................................................................50
9.5.
CLOCK REQUIREMENTS .............................................................................................................................................51
9.6.
TRANSFORMER CHARACTERISTICS ............................................................................................................................51
10.
MECHANICAL DIMENSIONS.................................................................................................................................52
11.
ORDERING INFORMATION ...................................................................................................................................53
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List of Tables
TABLE 1. MII INTERFACE ..............................................................................................................................................................6
TABLE 2. SERIAL MANAGEMENT INTERFACE ................................................................................................................................7
TABLE 3. RMII INTERFACE ...........................................................................................................................................................8
TABLE 4. CLOCK INTERFACE .........................................................................................................................................................8
TABLE 5. 10MBPS/100MBPS NETWORK INTERFACE ......................................................................................................................8
TABLE 6. TRANSMIT BIAS REFERENCE ..........................................................................................................................................9
TABLE 7. DEVICE CONFIGURATION INTERFACE.............................................................................................................................9
TABLE 8. POWER AND GROUND PINS ..........................................................................................................................................10
TABLE 9. RESET AND OTHER PINS ...............................................................................................................................................11
TABLE 10. REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................12
TABLE 11. REGISTER 1 BASIC MODE STATUS REGISTER ...............................................................................................................13
TABLE 12. REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................14
TABLE 13. REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................14
TABLE 14. REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) .....................................................................14
TABLE 15. REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................15
TABLE 16. REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ..............................................................................16
TABLE 17. PAGE 0 REGISTER 13 MACR (MMD ACCESS CONTROL REGISTER; ADDRESS 0X0D).................................................17
TABLE 18. PAGE 0 REGISTER 14 MAADR (MMD ACCESS ADDRESS DATA REGISTER; ADDRESS 0X0E) ....................................17
TABLE 19. REGISTER 24 POWER SAVING MODE REGISTER (PSMR) .............................................................................................17
TABLE 20. REGISTER 28 FIBER MODE AND LOOPBACK REGISTER ................................................................................................18
TABLE 21. REGISTER 30 INTERRUPT INDICATORS AND SNR DISPLAY REGISTER ..........................................................................18
TABLE 22. REGISTER 31 PAGE SELECT REGISTER .........................................................................................................................18
TABLE 23. PAGE4 REGISTER 16 EEE CAPABILITY ENABLE REGISTER ..........................................................................................19
TABLE 24. PAGE4 REGISTER 21 EEE CAPABILITY REGISTER ........................................................................................................19
TABLE 25. PAGE7 REGISTER 16 RMII MODE SETTING REGISTER (RMSR)...................................................................................19
TABLE 26. CUSTOMIZED LED MATRIX TABLE .............................................................................................................................20
TABLE 27. PAGE7 REGISTER 17 CUSTOMIZED LEDS SETTING REGISTER .....................................................................................20
TABLE 28. PAGE7 REGISTER 18 EEE LEDS ENABLE REGISTER ....................................................................................................20
TABLE 29. PAGE7 REGISTER 19 INTERRUPT, WOL ENABLE, AND LEDS FUNCTION REGISTERS ...................................................21
TABLE 30. PAGE7 REGISTER 20 MII TX ISOLATE REGISTER.........................................................................................................22
TABLE 31. PAGE7 REGISTER 24 SPREAD SPECTRUM CLOCK REGISTER ........................................................................................22
TABLE 32. MMD REGISTER MAPPING AND DEFINITION ...............................................................................................................22
TABLE 33. EEEPC1R (PCS CONTROL 1 REGISTER, MMD DEVICE 3, ADDRESS 0X00) ................................................................22
TABLE 34. EEEPS1R (PCS STATUS 1 REGISTER, MMD DEVICE 3, ADDRESS 0X01)....................................................................23
TABLE 35. EEECR (EEE CAPABILITY REGISTER, MMD DEVICE 3; ADDRESS 0X14) ...................................................................23
TABLE 36. EEEWER (EEE WAKE ERROR REGISTER, MMD DEVICE 3; ADDRESS 0X16).............................................................23
TABLE 37. EEEAR (EEE ADVERTISEMENT REGISTER, MMD DEVICE 7; ADDRESS 0X3C)...........................................................24
TABLE 38. EEELPAR (EEE LINK PARTNER ABILITY REGISTER, MMD DEVICE 7; ADDRESS 0X3D) ...........................................24
TABLE 39. MANAGEMENT FRAME FORMAT ..................................................................................................................................26
TABLE 40. SERIAL MANAGEMENT ................................................................................................................................................27
TABLE 41. SETTING THE MEDIUM TYPE AND INTERFACE MODE TO MAC....................................................................................28
TABLE 42. POWER SAVING MODE PIN SETTINGS ..........................................................................................................................33
TABLE 43. WAKE-ON-LAN PIN TYPES (MII MODE) ....................................................................................................................39
TABLE 44. WAKE-ON-LAN PIN TYPES (RMII MODE)..................................................................................................................39
TABLE 45. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................41
TABLE 46. RECOMMENDED OPERATING CONDITIONS ...................................................................................................................41
TABLE 47. POWER ON AND PHY RESET SEQUENCE ......................................................................................................................42
TABLE 48. RMII INPUT MODE POWER DISSIPATION (WHOLE SYSTEM)........................................................................................43
TABLE 49. INPUT VOLTAGE: VCC .................................................................................................................................................43
TABLE 50. MII TRANSMISSION CYCLE TIMING .............................................................................................................................45
TABLE 51. MII RECEPTION CYCLE TIMING ...................................................................................................................................46
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TABLE 52. RMII TRANSMISSION AND RECEPTION CYCLE TIMING ................................................................................................47
TABLE 53. MDC/MDIO TIMING ...................................................................................................................................................48
TABLE 54. CRYSTAL CHARACTERISTICS .......................................................................................................................................50
TABLE 55. OSCILLATOR REQUIREMENTS ......................................................................................................................................50
TABLE 56. CLOCK REQUIREMENTS ...............................................................................................................................................51
TABLE 57. TRANSFORMER CHARACTERISTICS ..............................................................................................................................51
TABLE 58. ORDERING INFORMATION ............................................................................................................................................53
List of Figures
FIGURE 1. APPLICATION DIAGRAM ................................................................................................................................................3
FIGURE 2. BLOCK DIAGRAM ..........................................................................................................................................................4
FIGURE 3. PIN ASSIGNMENTS ........................................................................................................................................................5
FIGURE 4. READ CYCLE ...............................................................................................................................................................27
FIGURE 5. WRITE CYCLE .............................................................................................................................................................27
FIGURE 6. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................29
FIGURE 7. RX LED......................................................................................................................................................................30
FIGURE 8. TX LED......................................................................................................................................................................30
FIGURE 9. TX/RX LED ...............................................................................................................................................................31
FIGURE 10. LINK/ACT LED ........................................................................................................................................................31
FIGURE 11. CUSTOMIZED LED WITH/WITHOUT LPI LED MODE...................................................................................................32
FIGURE 12. EEE LED BEHAVIOR ..................................................................................................................................................33
FIGURE 13. ACTIVE LOW WHEN RECEIVING A MAGIC PACKET ....................................................................................................37
FIGURE 14. ACTIVE LOW WHEN RECEIVING A WAKE-UP FRAME .................................................................................................37
FIGURE 15. PULSE LOW WHEN RECEIVING A MAGIC PACKET ......................................................................................................38
FIGURE 16. PULSE LOW WHEN RECEIVING A WAKE-UP FRAME ...................................................................................................38
FIGURE 17. SPECTRUM SPREAD CLOCK ........................................................................................................................................40
FIGURE 18. POWER ON AND PHY RESET SEQUENCE ....................................................................................................................42
FIGURE 19. MII INTERFACE SETUP/HOLD TIME DEFINITIONS .......................................................................................................44
FIGURE 20. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................44
FIGURE 21. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................44
FIGURE 22. MII RECEPTION CYCLE TIMING-1 ..............................................................................................................................45
FIGURE 23. MII RECEPTION CYCLE TIMING-2 ..............................................................................................................................45
FIGURE 24. RMII INTERFACE SETUP, HOLD TIME, AND OUTPUT DELAY TIME DEFINITIONS ........................................................46
FIGURE 25. RMII TRANSMISSION AND RECEPTION CYCLE TIMING ...............................................................................................47
FIGURE 26. MDC/MDIO INTERFACE SETUP, HOLD TIME, AND VALID FROM MDC RISING EDGE TIME DEFINITIONS .................48
FIGURE 27. MDC/MDIO TIMING ..................................................................................................................................................48
FIGURE 28. MAC TO PHY TRANSMISSION WITHOUT COLLISION ..................................................................................................49
FIGURE 29. PHY TO MAC RECEPTION WITHOUT ERROR .............................................................................................................49
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1.
General Description
The RTL8201FI-VC-CG is a single-chip/single-port 10/100Mbps Ethernet PHYceiver that supports:
•
MII (Media Independent Interface)
•
RMII (Reduced Media Independent Interface)
The RTL8201FI-VC implements all 10/100M Ethernet Physical-layer functions including the Physical
Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent
Sublayer (TP-PMD), 10Base-TX Encoder/Decoder, and Twisted-Pair Media Access Unit (TPMAU). The
RTL8201FI-VC also supports auto MDIX.
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides
excellent performance under all operating conditions.
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2.
Features
Supports IEEE 802.3az-2010 (EEE)
Supports Interrupt function
100Base-TX IEEE 802.3u Compliant
Supports Wake-On-LAN (WOL)
10Base-T IEEE 802.3 Compliant
Adaptive Equalization
Supports MII mode
Automatic Polarity Correction
Supports RMII mode
Provides two network status LEDs
Full/half duplex operation
Supports 25MHz external crystal or OSC
Twisted pair or fiber mode output
Supports 50MHz external OSC Clock input
Supports Auto-Negotiation
Provides 50MHz clock source for MAC
Supports power down mode
Supports Link Down Power Saving
Low power supply 1.1V and 3.3V; 1.1V is
generated by an internal regulator
Supports Base Line Wander (BLW)
compensation
0.11µm CMOS process
32-pin MII/RMII QFN ‘Green’ package
Supports auto MDIX
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3.
Applications
DTV (Digital TV)
Printer and Office Machine
MAU (Media Access Unit)
DVD Player and Recorder
CNR (Communication and Network Riser)
Ethernet Hub
Game Console
Ethernet Switch
In addition, the RTL8201FI-VC can be used in any embedded system with an Ethernet MAC that needs a
UTP physical connection or Fiber PECL interface to an external 100Base-FX optical transceiver module.
Magnet ic s
R J-45
3.1. Application Diagram
Figure 1. Application Diagram
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4.
Block Diagram
100 M
LPI
Indication
5B
4B
Decoder
(LPI Detection)
MII / RMII
Interface
10 /100
Half/Full
Switch
Logic
Data
Alignment
Descrambler
RXD
RXC 25M
4B
5B
Encoder
(LPI Generation)
TXD
Scrambler
TXC 25M
PMEB
WOL
10 /100 M Auto-Negotiation
Control Logic
( EEE Capability Exchange)
Link Pulse
10M
TXC10
TXD10
Manchester Coded
Waveform
RXC10
RXD10
Data Recovery
TXD
TXC25M
Support TD+
EEE Quiet
Parallel to Serial
10M Output Waveform
Shaping
(Amplitude Reduction)
Receive Low Pass Filter
3 Level
Driver
TXO+
Adaptive
Equalizer
RXIN+
TXO-
Variable Current
3 Level
Comparator
MLT-3
to NRZI
RXIN-
RXD
RXC 25M
Serial to
Parallel
ck
data
Slave
PLL
Master
PLL
25 M or 50M
Figure 2. Block Diagram
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5.
Pin Assignments
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 3). The version is shown in the location
marked ‘V’.
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6.
Pin Descriptions
I: Input
LI: Latched Input during Power up or Reset
O: Output
IO: Bi-directional Input and Output
P: Power
HZ: High Impedance During Power On Reset
PU: Internal Pull Up During Power On Reset
PD: Internal Pull Down During Power On Reset
OD: Open Drain Output
6.1. MII Interface
Name
TXC
Type
O/PD
Pin No.
15
TXEN
I/PD
20
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RXC
I/PD
I/PD
I/PD
I/PD
O/PD
16
17
18
19
13
COL
O/PD
27
CRS/
CRS_DV
RXDV
O/PD
26
LI/O/PD
8
Table 1. MII Interface
Description
Transmit Clock.
This pin provides a continuous clock as a timing reference for TXD [3:0] and
TXEN signals.
TXC is 25MHz in 100Mbps mode and 2.5MHz in 10Mbps mode.
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD [3:0]. An
internal weakly pulled low resistor prevents the bus floating.
Transmit Data.
The MAC will source TXD [0:3] synchronous with TXC when TXEN is asserted.
An internal weakly pulled low resistor prevents the bus floating.
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD [0:3] signals.
RXC is 25MHz in 100Mbps mode and 2.5MHz in 10Mbps mode.
Collision Detect.
COL is asserted high when a collision is detected on the media.
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on the
rising edge of the RXC.
This pin should be pulled low when operating in MII mode.
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the default of MII mode. It is
possible to use an external 4.7KΩ pulled high resistor to enable RMII mode.
After power on, the pin operates as the Receive Data Valid pin.
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Name
RXD[0]
RXD[1]
RXD[2]/
INTB
Type
O/PD
LI/O/PD
O/PD
Pin No.
9
10
11
RXD[3]/
CLK_CTL
LI/O/PD
12
RXER/
FXEN
LI/O/PD
28
Description
Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
Note 1: An internal weakly pulled low resistor sets RXD[1] to the LED function
(default). Use an external 4.7KΩ pulled high resistor to enable the WOL function.
Note 2: The Pin11 is named RXD[2]/INTB. When in RMII mode, this pin is used for
the interrupt function. See Table 9, page 11 for INTB descriptions.
Receive Data.
This is the parallel receive data line aligned on the nibble boundaries driven
synchronously to the RXC for reception by the external physical unit (PHY).
RXD[3]/CLK_CTL pin is the Hardware strap in RMII Mode.
1: REF_CLK input mode
0: REF_CLK output mode
Note: An internal weakly pulled low resistor sets RXD[3]/CLK_CTL to REF_CLK
output mode (default).
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid symbol,
this pin will go high.
Fiber/UTP Enable.
This pin’s status is latched at power on reset to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weakly pulled low resistor sets this to the default of UTP mode. It is
possible to use an external 4.7KΩ pulled high resistor to enable fiber mode. After
power on, the pin operates as the Receive Error pin.
6.2. Serial Management Interface
Name
MDC
Type
I/PU
Pin No.
22
MDIO
IO/PU
23
Table 2. Serial Management Interface
Description
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be asynchronous to
the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz.
Use an internal weakly pulled high resistor to prevent the bus floating.
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
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6.3. RMII Interface
Name
TXC
Type
IO/PD
CRS/CRS_DV
O/PD
TXEN
TXD[0:1]
RXD[0:1]
RXER/FXEN
I/PD
I/PD
O/PD
LI/O/PD
Table 3. RMII Interface
Pin No. Description
15
Synchronous 50MHz Clock Reference for Receive, Transmit, and Control
Interface. The direction is decided by Page 7, Register 16.
The default direction is reference clock output mode if RXD[3]/CLK_CTL pin
floating.
26
Carrier Sense/Receive Data Valid.
CRS_DV shall be asserted by the PHY when the receive medium is non-idle.
20
Transmit Enable.
16, 17 Transmit Data.
9, 10
Receive Data.
28
Receive Error. RX_ER is a required output of the PHY, but is an optional input
for the MAC.
6.4. Clock Interface
Name
CKXTAL2
Type
IO
CKXTAL1
I
Table 4. Clock Interface
Pin No. Description
32
25MHz Crystal Output.
This pin provides the 25MHz crystal output.
If an external 25MHz/50MHz oscillator or clock is used, connect CKXTAL2 to
the oscillator or clock output (see section 9.4 Oscillator Requirements, page 50).
31
25MHz Crystal Input.
This pin provides the 25MHz crystal input.
Must be shorted to GND when an external 25MHz/50MHz oscillator or clock
drives CKXTAL2.
6.5. 10Mbps/100Mbps Network Interface
Name
MDI+[0]
MDI-[0]
Type
IO
MDI+[1]
MDI-[1]
IO
Table 5. 10Mbps/100Mbps Network Interface
Pin No. Description
3
Transmit Output.
4
Differential transmit output pair shared by 100Base-TX, 100Base-FX, and
10Base-T modes. When configured as 100Base-TX, output is an MLT-3 encoded
waveform. When configured as 100Base-FX, the output is pseudo-ECL level.
5
Receive Input.
6
Differential receive input pair shared by 100Base-TX, 100Base-FX, and
10Base-T modes.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Datasheet
6.6. Transmit Bias Reference
Name
RSET
Type
I
Pin No.
1
Table 6. Transmit Bias Reference
Description
Transmit Bias Resistor Connection.
This pin should be pulled to GND by a 2.49KΩ (1%) resistor to define driving
current for the transmit DAC.
6.7. Device Configuration Interface
Name
RXDV
Type
LI/O/PD
RXD[1]
LI/O/PD
LED0/
PHYAD[0]/
PMEB
LI/O/PU
LED1/
PHYAD[1]
LI/O/PD
Table 7. Device Configuration Interface
Pin No. Description
8
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD [3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on the
rising edge of the RXC.
This pin should be pulled low when operating in MII mode.
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the default of MII mode. It is
possible to use an external 4.7KΩ pulled high resistor to enable RMII mode.
After power on, the pin operates as the Receive Data Valid pin.
10
An internal weakly pulled low resistor sets RXD[1] to the LED function (default).
Use an external 4.7KΩ pulled high resistor to enable the WOL function for the
RTL8201FI-VC.
PHY Address and Customized LED Settings.
24
The default available PHY addresses is 00000~00011.
Traditional LED Function Selection
LED_Sel
00
01
10
11
25
LED0
ACTALL LinkALL/ACTALL Link10/ACTALL
LINK10/ACT10
LED1
LINK100
LINK100
LINK100
LINK100/ACT100
Note 1: For Customized LED Settings, see section 7.17, page 20.
Note 2: LED_Sel default is 11. Refer to section 7.19, page 21.
An internal weakly pulled low resistor sets RXD[1] to the LED function (default).
Use an external 4.7KΩ pulled high resistor to enable the WOL function.
Traditional LED Function Selection with WOL Enabled
With the WOL function enabled, the PHY address must be 00001 or 00011.
LED_Sel
00
01
10
11
LED1
LINK100
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
LINK100
9
LINK100
LINK100/ACT100
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Datasheet
Name
RXD[3]/
CLK_CTL
Type
LI/O/PD
RXER/
FXEN
LI/O/PD
Pin No. Description
12
Receive Data.
This is the parallel receive data line aligned on the nibble boundaries driven
synchronously to the RXC for reception by the external physical unit (PHY).
RXD [3]/CLK_CTL pin is the Hardware strap in RMII Mode.
1: REF_CLK input mode
0: REF_CLK output mode
Note: An internal weakly pulled low resistor sets RXD[3]/CLK_CTL to REF_CLK
output mode (default).
28
Fiber/UTP Interface.
This pin’s status is latched at power on reset to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weakly pulled low resistor sets this to the default of UTP mode. It is
possible to use an external 4.7KΩ pulled high resistor to enable fiber mode.
6.8. Power and Ground Pins
Name
AVDD33
Type
P
Pin No.
7, 30
DVDD33
P
14
AVDD10OUT
O
2
DVDD10OUT
O
29
GND
P
E-PAD
Table 8. Power and Ground Pins
Description
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well decoupled.
3.3V Digital Power Input.
3.3V power supply for digital circuit.
Power Output.
Be sure to connect a 0.1µF ceramic capacitor for decoupling purposes.
The connection method is outlined in section 8.8 3.3V Power Supply and Voltage
Conversion Circuit, page 35.
Power Output.
Be sure to connect a 0.1µF ceramic capacitor for decoupling purposes.
The connection method is outlined in 8.8 3.3V Power Supply and Voltage
Conversion Circuit, page 35.
Ground. Should be connected to a larger GND plane.
Exposed Pad (E-Pad) is Analog and Digital Ground.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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6.9. Reset and Other Pins
Name
PHYRSTB
Type
I/HZ
Pin No.
21
RXD[2]/INTB
O/PD
11
PMEB
O/OD
24
Table 9. Reset and Other Pins
Description
RESETB.
Set low to reset the chip. For a complete reset, this pin must be asserted low for at
least 10ms.
Note: When the WOL function is enabled, keep the pin high.
Interrupt.
Set low if link status changed, duplex changed, or auto negotiation failed. Active
Low.
This pin is an open-drain design and should be pulled high by an external 4.7KΩ.
If not used, keep floating.
Note: This pin is used for the interrupt function only when in the RMII mode.
Power Management Enable.
Set low if received a magic packet or wake up frame; active low.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Datasheet
7.
Register Descriptions
This section describes the functions and usage of the registers available in this file. In this section the
following abbreviations are used.
RW: Read/Write
RW/EFUS: Read/Write/eFUSE Burnable
RO: Read Only
RW/LI: Read/Write/Latch In
RC: Read Clear
RW/SC: Read/Write/Self-Clearing
SC: Self-Clear
Note: RW/EFUS and RW/LI types will return to default values after a software reset (set Reg.0 Bit15 to
1).
7.1. Register 0 Basic Mode Control Register
Address Name
0:15
Reset
0:14
Loopback
0:13
Speed Selection
0:12
Auto Negotiation
Enable
0:11
Power Down
0:10
Isolate
Table 10. Register 0 Basic Mode Control Register
Description
This bit sets the status and control registers of the PHY in the
default state. This bit is self-clearing.
1: Software reset
0: Normal operation
Register 0 and register 1 will return to default values after a
software reset (set Bit15 to 1).
This action may change the internal PHY state and the state of the
physical link associated with the PHY.
This bit enables loopback of transmit data nibbles TXD3:0 to the
receive data path.
1: Enable loopback
0: Normal operation
This bit sets the network speed.
1: 100Mbps
0: 10Mbps
After completing auto negotiation, this bit will reflect the speed
status.
1: 100Base-T
0: 10Base-T
When 100Base-FX mode is enabled, this bit=1 and is read only.
This bit enables/disables the NWay auto-negotiation function.
1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the
link speed and the data transfer mode, respectively
When 100Base-FX mode is enabled, this bit=0 and is read only.
This bit turns down the power of the PHY chip, including the
internal crystal oscillator circuit.
The MDC, MDIO is still alive for accessing the MAC.
1: Power down
0: Normal operation
1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII.
PHY is still able to respond to MDC/MDIO.
0: Normal operation
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
12
Mode
RW/
SC
Default
0
RW
0
RW
1
RW
1
RW
0
RW
0
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Rev. 1.1
RTL8201FI
Datasheet
Address Name
0:9
Restart Auto
Negotiation
0:8
Duplex Mode
0:7
Collision Test
0:6
Speed Selection[1]
0:5~0
Reserved
Description
This bit allows the NWay auto-negotiation function to be reset.
1: Re-start auto-negotiation
0: Normal operation
This bit sets the duplex mode if auto-negotiation is disabled (bit
0:12=0).
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex
status.
1: Full duplex
0: Half duplex
Collision Test.
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted in
response to the TXEN assertion within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the
TXEN de-assertion.
Speed Select Bit 1.
Refer to bit 0.13.
Reserved.
Mode
RW/
SC
RW
Default
0
RW
0
RW
0
-
-
1
7.2. Register 1 Basic Mode Status Register
Table 11. Register 1 Basic Mode Status Register
Address Name
Description
1:15
100Base-T4
1: Enable 100Base-T4 support
0: Suppress 100Base-T4 support
1:14
100Base_TX_FD
1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
1:13
100Base_TX_HD
1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
1:12
10Base_T_FD
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1:11
10_Base_T_HD
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
1:10~7 Reserved
Reserved.
1:6
MF Preamble Suppression
The RTL8201FI-VC will accept management frames with
preamble suppressed.
A minimum of 32 preamble bits are required for the first
management interface read/write transaction after reset.
One idle bit is required between any two management
transactions as per IEEE 802.3u specifications.
1:5
Auto Negotiation Complete 1: Auto-negotiation process completed
0: Auto-negotiation process not completed
1:4
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band
signal Far-End-Fault has been detected (see 8.10 Far End
Fault Indication, page 36).
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
13
Mode
RO
Default
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
0
RC
0
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RTL8201FI
Datasheet
Address Name
1:3
Auto-Negotiation Ability
1:2
Link Status
1:1
Jabber Detect
1:0
Extended Capability
Description
1: PHY is able to perform auto-negotiation
0: PHY is not able to perform auto-negotiation
1: Valid link established
0: No valid link established
This bit indicates whether the link was lost since the last
read. For the current link status, read this register twice.
1: Jabber condition detected
0: No jabber condition detected
1: Extended register capable (permanently=1)
0: Not extended register capable
Mode
RO
Default
1
RO
0
RO
0
RO
1
7.3. Register 2 PHY Identifier Register 1
Address Name
2:15~0
OUI
Table 12. Register 2 PHY Identifier Register 1
Description
Composed of the 6th to 21st bits of the Organizationally Unique
Identifier (OUI), respectively.
Mode
Default
RO
001Ch
Mode
RO
RO
RO
Default
110010
000001
0110
7.4. Register 3 PHY Identifier Register 2
Address
3:15~10
3:9~4
3:3~0
Name
OUI_LSB
Model Number
Revision Number
Table 13. Register 3 PHY Identifier Register 2
Description
Assigned to the 0 through 5th bits of the OUI.
Model Number
Revision Number
7.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Address
4:15
4:14
4:13
4:12
4:11
4:10
Table 14. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Name
Description
Mode
Next Page
Next Page Bit.
RW
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
Acknowledge
1: Acknowledge reception of link partner capability data word
RO
0: Do not acknowledge reception
Remote Fault
1: Advertise remote fault detection capability
RW
0: Do not advertise remote fault detection capability
Reserved
Reserved.
1: Advertise asymmetric pause support
RW
Asymmetric
PAUSE
0: No support of asymmetric pause
Pause
Reserved.
RW
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
14
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Default
0
0
0
0
0
Rev. 1.1
RTL8201FI
Datasheet
Address
4:9
Name
100Base-T4
4:8
100Base-TX-FD
4:7
100Base-TX
4:6
10Base-T-FD
4:5
10Base-T
4:4~0
Selector Field
Description
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full duplex supported by local node
0: 10Base-T full duplex not supported by local node
1: 10Base-T is supported by local node
0: 10Base-T not supported by local node
Binary Encoded Selector Supported by This Node.
Currently only CSMA/CD 00001 is specified. No other
protocols are supported.
Mode
RO
Default
0
RW
1
RW
1
RW
1
RW
1
RO
00001
7.6. Register 5 Auto-Negotiation Link Partner Ability Register
(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during auto-negotiation. The
content changes after a successful auto-negotiation if Next-pages are supported.
Address
5:15
5:14
5:13
5:12
5:11
5:10
5:9
5:8
Table 15. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Name
Description
Mode
Next Page
Next Page Bit.
RO
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
Acknowledge
RO
1: Link partner acknowledges reception of local node’s
capability data word
0: No acknowledgement
Remote Fault
1: Link partner is indicating a remote fault
RO
0: Link partner is not indicating a remote fault
Reserved
Reserved.
Asymmetric Pause
1: Asymmetric Flow control supported by Link Partner
RO
0: No Asymmetric flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link
Partner ability.
Pause
1: Flow control supported by Link Partner
RO
0: No flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link
Partner ability (read only).
100Base-T4
1: 100Base-T4 is supported by link partner
RO
0: 100Base-T4 not supported by link partner
100Base-TX-FD
1: 100Base-TX full duplex is supported by link partner
RO
0: 100Base-TX full duplex not supported by link partner
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15
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Default
0
0
0
0
0
0
0
Rev. 1.1
RTL8201FI
Datasheet
Address
5:7
Name
100Base-TX
5:6
10Base-T-FD
5:5
10Base-T
5:4~0
Selector Field
Description
1: 100Base-TX is supported by link partner
0: 100Base-TX not supported by link partner
This bit will also be set if the link in 100Base-TX is
established by parallel detection.
1: 10Base-T full duplex is supported by link partner
0: 10Base-T full duplex not supported by link partner
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
This bit will also be set if the link in 10Base-T is established
by parallel detection.
Link Partner’s Binary Encoded Node Selector.
Currently only CSMA/CD 00001 is specified.
Mode
RO
Default
0
RO
0
RO
0
RO
00001
7.7. Register 6 Auto-Negotiation Expansion Register (ANER)
This register contains additional status for NWay auto-negotiation.
Table 16. Register 6 Auto-Negotiation Expansion Register (ANER)
Address Name
Description
6:15~5 Reserved
Reserved.
6:4
Parallel Detection 1: A fault has been detected via the Parallel Detection function
Fault
0: No fault has been detected via the Parallel Detection function
6:3
Link Partner Next 1: Link Partner is Next Page able
Page Ability
0: Link Partner is not Next Page able
6:2
Local Next Page 1: Next Page is able
Ability
0: Not Next Page able
6:1
Page Received
1: A New Page has been received
0: A New Page has not been received
6:0
If Auto-Negotiation is Enabled, This Bit Means:
Link Partner
Auto-Negotiation 1: Link Partner is Auto-Negotiation able
Ability
0: Link Partner is not Auto-Negotiation able
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
16
Mode
RC
Default
0
RO
0
RO
0
RC
0
RO
0
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Datasheet
7.8. Page 0 Register 13 MACR (MMD Access Control Register;
Address 0x0D)
Table 17. Page 0 Register 13 MACR (MMD Access Control Register; Address 0x0D)
Bit
Name
RW
Default
Description
13.15:14 Function
WO
0
00: Address
01: Data; no post increment
10: Data; post increment on reads and writes
11: Data; post increment on writes only
13.13:5 RSVD
RO
000000000 Reserved.
13.4:0 DEVAD
WO
0
Device Address.
Note 1: Used in conjunction with the MAADR (Register 14) to provide access to the MMD address space.
Note 2: If the access of MAADR is for address (Function=00) then it is directed to the address register within the MMD
associated with the value in the DEVAD field.
Note 3: If the access of MAADR is for data (Function=00) then both the DEVAD field and the MMD address register
direct the MAADR data accesses to the appropriate registers within the MMD.
7.9. Page 0 Register 14 MAADR (MMD Access Address Data
Register; Address 0x0E)
Table 18. Page 0 Register 14 MAADR (MMD Access Address Data Register; Address 0x0E)
Bit
Name
RW
Default
Description
14.15:0 Address Data
RW
0x0000
13.15:14=00
Æ MMD DEVAD’s address register
13.15:14=01, 10, or 11
Æ MMD DEVAD’s data register as indicated by the contents of
its address register
Note: Used in conjunction with the MACR (Register 13) to provide access to the MMD address space.
7.10. Register 24 Power Saving Mode Register (PSMR)
Table 19. Register 24 Power Saving Mode Register (PSMR)
Address Name
Description
Mode Default
24:15
Enpwrsave
Enable Power Saving Mode.
RW
1
The bit will return to default value by software reset.
24:14~0 Reserved
Reserved.
Note: If the REF_CLK output is needed in RMII output mode, LDPS (Link Down Power Saving) must be disabled (see
Table 42, page 33).
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Datasheet
7.11. Register 28 Fiber Mode and Loopback Register
Address
28:15~6
28:5
28:4~3
28:2
28:1
28:0
Table 20. Register 28 Fiber Mode and Loopback Register
Name
Description
Reserved
Reserved.
Fxmode
Enable Fiber Mode.
Reserved
Reserved.
En_autoMDIX
Enable Auto MDIX Function.
Force_MDI
Force MDI/MDIX Mode.
If enable auto MDIX function is disabled:
1: Force MDI
0: Force MDIX
Reserved
Reserved.
Mode
RW
RW
RW
Default
0
1
1
-
-
7.12. Register 30 Interrupt Indicators and SNR Display Register
Address
30:15
30:14
30:13
30:12
30:11
30:10~4
30:3~0
Table 21. Register 30 Interrupt Indicators and SNR Display Register
Name
Description
Mode
Anerr
Auto-Negotiation Error Interrupt.
RC
1: Enable
0: Disable
Spdchg
Speed Mode Change Interrupt.
RC
1: Enable
0: Disable
Duplexchg
Duplex Mode Change Interrupt.
RC
1: Enable
0: Disable
Reserved
Reserved.
Linkstatuschg
Link Status Change Interrupt.
RC
1: Enable
0: Disable
Reserved
Reserved.
SNR_O
These 4-Bits Show the Signal to Noise Ratio Value.
RO
Default
0
0
0
0
0000
7.13. Register 31 Page Select Register
Address
31:15~8
31:7~0
Name
Reserved
PAGE SEL
Table 22. Register 31 Page Select Register
Description
Reserved for Internal Testing.
Select Page Address: 00000000~11111111.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
18
Mode
RW
Default
00000000
Track ID: JATR-8275-15
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RTL8201FI
Datasheet
7.14. Page 4 Register 16 EEE Capability Enable Register
Address
16:15~14
16:13
16:12
Table 23. Page4 Register 16 EEE Capability Enable Register
Name
Description
Reserved
Reserved.
EEE_10_cap
Enable EEE 10M Capability.
EEE_nway_en Enable Next Page Exchange in NWay for EEE 100M.
16:11~10
16:9
Reserved
Tx_quiet_en
16:8
Rx_quiet_en
16:7:0
Reserved
Reserved.
Enable Ability to Turn Off Power 100TX when TX in Quiet State.
This bit is recommended to be set to 1 when EEE is enabled.
Enable Ability to Turn Off Power 100RX when RX in Quiet state.
This bit is recommended to be set to 1 when EEE is enabled.
Reserved.
Mode
RW
RW/
EFUS
RW/
EFUS
RW/
EFUS
-
Default
1
1
Mode
RW
RO
Default
0
0
1
1
-
7.15. Page 4 Register 21 EEE Capability Register
Address
21:15~13
21:12
21:11~1
21:0
Table 24. Page4 Register 21 EEE Capability Register
Name
Description
Reserved
Reserved.
Rg_dis_ldvt
Set to 1 to Disable the Line Driver of the Analog Circuit.
Reserved
Reserved.
EEE_100_cap NWay Result to Indicate Link Partner Supports EEE 100M.
7.16. Page 7 Register 16 RMII Mode Setting Register (RMSR)
Table 25. Page7 Register 16 RMII Mode Setting Register (RMSR)
Name
Description
Mode
Default
Reserved
Reserved.
Rg_rmii_clkdir
This Bit Sets the Type of TXC in RMII Mode.
RW/LI
0
0: Output
1: Input
16:11~8
Rg_rmii_tx_offset
Adjust RMII TX Interface Timing.
RW/EFUS
1111
16:7~4
Rg_rmii_rx_offset
Adjust RMII RX Interface Timing.
RW/EFUS
1111
16:3
0: MII Mode
RW/LI
0
RMII Mode
1: RMII Mode
16:2
0: CRS/CRS_DV pin is CRS_DV signal
RW/EFUS
0
Rg_rmii_rxdv_sel
1: CRS/CRS_DV pin is RXDV signal
16:1
Rg_rmii_rxdsel
0: RMII data only
RW/EFUS
1
1: RMII data with SSD Error
16:0
Reserved
Reserved.
Note: Set Page7, Register 16 to ‘7FFB’ when an external clock (25MHz and 50MHz) inputs to the CKXTAL2 pin.
Address
16:15~13
16:12
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
19
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RTL8201FI
Datasheet
7.17. Page 7 Register 17 Customized LEDs Setting Register
This register is for setting customized LEDs. Table 26 shows the customized LED matrix table.
LED0
LED1
LED Pin
LINK=0
LINK>0
Address
17:15~8
17:7~4
17:3~0
Table 26. Customized LED Matrix Table
LINK
10M
100M
Bit0
Bit1
Bit4
Bit5
ACT=0
Floating
Selected Speed LINK
ACT
Bit3
Bit7
ACT=1
All Speed ACT
Selected Speed LINK+ACT
Table 27. Page7 Register 17 Customized LEDs Setting Register
Name
Description
Reserved
Reserved.
LED_sel1
Customized LED1 Setting.
Set Bit3 (Page7 Register 19; Table 29, page 21) to 1 to
enable customized LED function.
LED_sel0
Customized LED0 Setting.
Set Bit3 (Page7 Register 19; Table 29, page 21) to 1 to
enable customized LED function.
Mode
RW/
EFUS
Default
0000
RW/
EFUS
0000
Mode
RW
RW
Default
0
0
7.18. Page 7 Register 18 EEE LEDs Enable Register
Address
18:15~2
18:1
18:0
Table 28. Page7 Register 18 EEE LEDs Enable Register
Name
Description
Reserved
Reserved.
EEE_LED_en1
Enable LED1 in EEE/LPI Mode.
EEE_LED_en0
Enable LED0 in EEE/LPI Mode.
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Datasheet
7.19. Page 7 Register 19 Interrupt, WOL Enable, and LEDs
Function Registers
Table 29. Page7 Register 19 Interrupt, WOL Enable, and LEDs Function Registers
Address Name
Description
Mode
19:15~14 Reserved
Reserved.
19:13
Int_linkchg
Link Change Interrupt Mask.
RW
1: Interrupt pin Enable
0: Interrupt pin Disable
This bit set to 0 only masks the link change interrupt event in the
INTB pin. Reg30 Bit11 always reflects the link change interrupt
behavior (see Table 21, page 18).
19:12
Int_dupchg
Duplex Change Interrupt Mask.
RW
1: Interrupt pin Enable
0: Interrupt pin Disable
This bit set to 0 only masks the duplex change interrupt event in
the INTB pin. Reg30 Bit13 always reflects the duplex change
interrupt behavior (see Table 21, page 18).
19:11
Int_anerr
NWay Error Interrupt Mask.
RW
1: Interrupt pin Enable
0: Interrupt pin Disable
This bit set to 0 only masks the NWay Error interrupt event in the
INTB pin.Reg30 Bit15 always reflects the NWay Error interrupt
behavior (see Table 21, page 18).
19:10
Rg_led0_wol_sel
LED and Wake-On-LAN Function Selection.
RW/LI
1: Wake-On-LAN Function Enable
0: LED Function Enable
An internal weakly pulled low resistor sets RXD[1] to the LED
function (default). Use an external 4.7KΩ pulled high resistor to
enable the WOL function for the RTL8201FI-VC.
19:9~6
Reserved
Reserved.
19:5~4
LED_sel[1:0]
Traditional LED Function Selection.
RW/
EFUS
LED_sel 00
01
10
11
19:3
19:2~1
19:0
Customized_LED
Reserved
En10mlpi
LED0
ACTALL
LinkALL/
ACTALL
Link10/
ACTALL
LED1
LINK100
LINK100
LINK100
21
0
0
0
11
LINK10/
ACT10
LINK100/
ACT100
Customized LED Enable.
1: Customized LED function enable
0: Customized LED function disable
See the section 8.4.7 Customized LED, page 32 for detail.
Reserved.
Enable 10M LPI LED Function.
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0
RW/
EFUS
0
RW
0
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7.20. Page 7 Register 20 MII TX Isolate Register
Address
20:15
20:14~0
Table 30. Page7 Register 20 MII TX Isolate Register
Name
Description
Rg_tx_isolate_en
Isolate MII TX Path Signals when TX Idle.
Reserved
Reserved.
Mode
RW
-
Default
0
-
7.21. Page 7 Register 24 Spread Spectrum Clock Register
Address
24:15~1
24:0
Table 31. Page7 Register 24 Spread Spectrum Clock Register
Name
Description
Reserved
Reserved.
Rg_dis_ssc
0: SSC function is enabled
1: SSC function is disabled
Mode
RW
Default
0
7.22. MMD Register Mapping and Definition
Note: MMD registers are placed at Page 0 Register 13 and Register 14.
Device
3
3
Offset
0
1
Access
RW
RO/
RO, LH
3
20
RO
3
22
RC
7
60
RW
7
61
RO
Note: LH: Latching High.
Table 32. MMD Register Mapping and Definition
Name
Description
EEEPC1R
EEE PCS Control 1 Register
EEEPS1R
EEE PCS Status Control 1 Register
EEECR
EEEWER
EEEAR
EEELPAR
EEE Capability Register
EEE Wake Error Register
EEE Advertisement Register
EEE Link Partner Ability Register
7.22.1. EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00)
Table 33. EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00)
Bit
Name
RW Default Description
3.0.15:11 RSVD
RW
0
Reserved.
3.0.10 Clock Stop Enable
RW
0
1: PHY stops RXC in LPI
0: RXC not stoppable
3.0.9:0 RSVD
RW
0
Reserved.
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7.22.2. EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01)
Table 34. EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01)
Bit
Name
RW
Default Description
3.1.15:12 RSVD
RO
0
Reserved.
3.1.11 TX LPI Received
RO, LH
0
1: TX PCS has received LPI
0: LPI not received
3.1.10 RX LPI Received
RO, LH
0
1: RX PCS has received LPI
0: LPI not received
3.1.9
TX LPI Indication
RO
0
1: TX PCS is currently receiving LPI
0: TX PCS is not currently receiving LPI
3.1.8
RX LPI Indication
RO
0
1: RX PCS is currently receiving LPI
0: RX PCS is not currently receiving LPI
3.1.7
RSVD
RO
0
Reserved.
3.1.6
Clock Stop Capable
RO
1
1: MAC stops TXC in LPI
0: TXC not stoppable
3.1.5:0 RSVD
RO
0
Reserved.
7.22.3. EEECR (EEE Capability Register, MMD Device 3; Address 0x14)
Table 35. EEECR (EEE Capability Register, MMD Device 3; Address 0x14)
Bit
Name
RW
Default Description
3.20.15:2 RSVD
RO
0
Reserved.
3.20.1 100Base-TX EEE
RO
1
1: EEE is supported for 100Base-TX EEE
0: EEE is not supported for 100Base-TX EEE
3.20.0 RSVD
RO
1
Reserved.
7.22.4. EEEWER (EEE Wake Error Register, MMD Device 3;
Address 0x16)
Table 36. EEEWER (EEE Wake Error Register, MMD Device 3; Address 0x16)
Bit
Name
RW
Default Description
3.22.15:0 EEE Wake Error Counter
RC
0
Used by PHY types that support EEE to count wake time
faults where the PHY fails to complete its normal wake
sequence within the time required for the specific PHY type.
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Datasheet
7.22.5. EEEAR (EEE Advertisement Register, MMD Device 7;
Address 0x3c)
Table 37. EEEAR (EEE Advertisement Register, MMD Device 7; Address 0x3c)
Bit
Name
RW
Default Description
7.60.15:3 RSVD
RW
0
Reserved.
7.60.1 100Base-TX EEE
RW
1
Advertise 100Base-TX EEE Capability.
1: Advertise
0: Do not advertise
7.60.0 RSVD
RW
0
Reserved.
7.22.6. EEELPAR (EEE Link Partner Ability Register, MMD Device 7;
Address 0x3d)
Table 38. EEELPAR (EEE Link Partner Ability Register, MMD Device 7; Address 0x3d)
Bit
Name
RW
Default Description
7.61.15:3 RSVD
RO
0
Reserved.
7.61.1 LP 100Base-TX EEE
RO
0
1: Link Partner is capable of 100Base-TX EEE
0: Link Partner is not capable of 100Base-TX EEE
7.61.0
RSVD
RO
0
Reserved.
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Datasheet
8.
Functional Description
The RTL8201FI-VC PHYceiver is a physical layer device that integrates 10Base-T and
100Base-TX/100Base-FX functions, and some extra power management features. This device supports
the following functions:
•
MII interface with MDC/MDIO management interface to communicate with the MAC
•
IEEE 802.3u clause 28 Auto-Negotiation ability
•
Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
•
Power Down mode support
•
4B/5B transform
•
Scrambling/De-scrambling
•
NRZ to NRZI, NRZI to MLT-3
•
Manchester Encode and Decode for 10Base-T operation
•
Clock and Data recovery
•
Adaptive Equalization
•
Automatic Polarity Correction
•
Far End Fault Indication (FEFI) in fiber mode
•
Network status LEDs
•
Wake-On-LAN (WOL)
•
Energy Efficient Ethernet (EEE)
•
Spread Spectrum Clock (SSC) for RMII REF_CLK output mode
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8.1. MII and Management Interface
8.1.1.
Data Transition
The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying
a standard interface between the PHY and MAC layer.
This interface operates at two frequencies, 25MHz and 2.5MHz, to support 100Mbps/10Mbps bandwidth
for both transmit and receive functions.
Transmission
The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the
PHY via TXD[3:0]. The PHY will sample TXD[3:0] synchronously with TXC – the transmit clock signal
supplied by the PHY – during the interval TXEN is asserted.
Reception
The PHY asserts the RXDV signal. It passes the received nibble data RXD[3:0] clocked by RXC. CRS
and COL signals are used for collision detection and handling.
In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is
recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble
has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.
The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/
or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur, e.g., an invalid J/K,
invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the
reconciliation sublayer that an error was detected somewhere in the frame.
8.1.2.
Serial Management Interface
The MAC layer device can use the MDC/MDIO management interface to control a maximum of four
devices, configured with different PHY addresses (00b to 11b without WOL). Frames transmitted on the
MDC/MDIO Management Interface should have the frame structure shown in Table 39.
Read
Write
Preamble
1…1
1…1
ST
01
01
Table 39. Management Frame Format
Management Frame Fields
OP
PHYAD REGAD TA
DATA
10
AAAAA RRRRR
Z0
DDDDDDDDDDDDDDDD
01
AAAAA RRRRR
10
DDDDDDDDDDDDDDDD
IDLE
Z
Z
During a hardware reset, the logic levels of pins 24 and 25 are latched to be set as the PHY address for
management communication via the serial interface. The read and write frame structure for the
management interface is illustrated in Figure 4 and Figure 5, page 27.
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Figure 4. Read Cycle
MDC
MDIO(MAC)
z
1...1 0 1 0
Pre
Start
1 0 0 0 0
Write
OP
(Code)
PHY Address
0x01
1 0 0 0 0 0
Reg. Address
0x00(BMCR)
1 0 0 0 0
1 0 0
Turn
1 1 0
1 0 0 0 0 0 0 z
Reg. Data
0x 1340
Around
Idle
Figure 5. Write Cycle
Name
Preamble
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
Table 40. Serial Management
Description
32 Contiguous Logical 1’s sent by the MAC on MDIO, along with 32 Corresponding Cycles on MDC.
This provides synchronization for the PHY.
Start of Frame.
Indicated by a 01 pattern.
Operation Code.
Read: 10
Write: 01
PHY Address.
Up to 4 PHYs can be connected to one MAC. This 2-bit field selects which PHY the frame is directed to.
Register Address.
This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Turnaround.
This is a 2-bit-time spacing between the register address and the data field of a frame to avoid contention
during a read transaction. For a read transaction, both the STA and the PHY remain in a high-impedance
state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit time of the
turnaround of a read transaction.
Data.
These are the 16 bits of data.
Idle Condition.
Not truly part of the management frame. This is a high impedance state. Electrically, the PHY’s pull-up
resistor will pull the MDIO line to a logical ‘1’.
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8.2. Interrupt
Whenever there is a status change on the media detected by the RTL8201FI-VC, they will drive the
interrupt pin (INTB) low to issue an interrupt event. The MAC senses the status change and accesses the
page0 register30 through the MDC/MDIO interface in response.
Once these status registers page0 register30 have been read by the MAC through the MDC/MDIO, the
INTB is de-asserted.
Note 1: The RXD[2]/INTB pin (Pin11) is used for the interrupt function only when in the RMII mode.
Note 2: The Interrupt function is disabled by default. To enable this function, refer to Table 29, page 21
(Page7 Register 19 Bit[13:11]).
8.3. Auto-Negotiation and Parallel Detection
The RTL8201FI-VC supports IEEE 802.3u clause 28 Auto-negotiation for operation with other
transceivers supporting auto-negotiation. The RTL8201FI-VC can auto-detect the link partner’s abilities
and determine the highest speed/duplex configuration possible between the two devices. If the link
partner does not support auto-negotiation, then the RTL8201FI-VC will enable half-duplex mode and
enter parallel detection mode. The RTL8201FI-VC will default to transmitting FLP (Fast Link Pulse) and
wait for the link partner to respond. If the RTL8201FI-VC receives a FLP, then the auto-negotiation
process will continue. If it receives an NLP (Normal Link Pulse), then the RTL8201FI-VC will change to
10Mbps and half-duplex mode. If it receives a 100Mbps IDLE pattern, it will change to 100Mbps and
half-duplex mode.
8.3.1.
Setting the Medium Type and Interface Mode to MAC
FXEN
H
H
H
L
L
L
Table 41. Setting the Medium Type and Interface Mode to MAC
RXDV
Operation Mode
L
Fiber Mode and MII Mode
H
Fiber Mode and RMII Mode
X
Fiber Mode and MII Mode
L
UTP Mode and MII Mode
H
UTP Mode and RMII Mode
X
UTP Mode and MII Mode
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8.4. LED Functions
The RTL8201FI-VC supports two LED signals in four configurable operation modes. The following
sections describe the various LED actions.
8.4.1.
LED and PHY Address
As the PHYAD strap options share the LED output pins, the external combinations required for strapping
and LED usage must be considered in order to avoid contention. Specifically, when the LED outputs are
used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled
by the corresponding PHYAD input upon power-up/reset.
For example, as Figure 6 (left-side) shows, if a given PHYAD input is resistively pulled high then the
corresponding output will be configured as an active low driver. On the right side, we can see that if a
given PHYAD input is resistively pulled low then the corresponding output will be configured as an
active high driver. The PHY address configuration pins should not be connected to GND or VCC directly,
but must be pulled high or low through a resistor (e.g., 4.7KΩ). If no LED indications are needed, the
components of the LED path (LED+510Ω) can be removed.
PHY Address[:] = Logical 1
PHY Address[:] = Logical 0
LED Indication = Active low
LED Indication = Active high
Figure 6. LED and PHY Address Configuration
8.4.2.
Link Monitor
The Link Monitor senses link integrity, such as LINK10, LINK100, LINK10/ACT, or LINK100/ACT.
Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected,
the link LED pin is driven high, indicating that no network connection exists.
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8.4.3.
RX LED
In 10/100M mode, blinking of the RX LED indicates that receive activity is occurring.
Figure 7. RX LED
8.4.4.
TX LED
In 10/100M mode, blinking of the TX LED indicates that transmit activity is occurring.
Figure 8. TX LED
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8.4.5.
TX/RX LED
In 10/100M mode, blinking of the TX/RX LED indicates that both transmit and receive activity is
occurring.
Figure 9. TX/RX LED
8.4.6.
LINK/ACT LED
In 10/100M mode, blinking of the LINK/ACT LED indicates that the RTL8201FI-VC is linked and
operating properly. When this LED is high for extended periods, it indicates that a link problem exists.
Figure 10. LINK/ACT LED
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8.4.7.
Customized LED
The RTL8201FI-VC supports programmable LEDs in 10/100Mbps mode. This function can be
enabled/disabled via page7, reg19[3] register (Figure 11).
Refer to section 7.17, page 20 for customized LED register setting.
Figure 11. Customized LED with/without LPI LED Mode
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8.4.8.
EEE LED Behavior
EEE Idle mode: LED continuous slow blinking.
EEE Active mode: LED fast and slow blinking (on packet transmission and reception).
Refer to Table 28, page 20 for EEE LED enable setting.
Figure 12. EEE LED Behavior
8.5. Power Down and Link Down Power Saving Modes
Two types of Power Saving mode operation are supported. This section describes how to implement each
mode through software.
Table 42. Power Saving Mode Pin Settings
Mode
PWD
LDPS
Description
Setting bit 11 of register 0 to 1 puts the RTL8201FI-VC into Power Down Mode (PWD). This is the
maximum power saving mode while the RTL8201FI-VC is still ‘live’. In PWD mode, the RTL8201FIVC will turn off all analog/digital functions except the MDC/MDIO management interface. Therefore, if
the RTL8201FI-VC is put into PWD mode and the MAC wants to recall the PHY, it must create the
MDC/MDIO timing by itself (this is done by software).
Setting bit 15 of register 24 to 1 will put the RTL8201FI-VC into LDPS (Link Down Power Saving)
mode. In LDPS mode, the RTL8201FI-VC will detect the link status to decide whether or not to turn off
the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted.
However, some signals similar to NLP will be transmitted. Once the receiver detects leveled signals, it
will stop the signal and transmit FLP or 100Mbps IDLE/10Mbps NLP again. This can cut power used by
60%~80% when the link is down.
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8.6. 10M/100M Transmit and Receive
8.6.1.
100Base-TX Transmit and Receive Operation
100Base-TX Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201FI-VC will have different scrambler seeds and so spread the
output of the MLT-3 signals.
100Base-TX Receive
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The Phase Locked Loop (PLL) then
recovers the timing information from the signals and from the receive clock. With this, the received signal
is sampled to form NRZI (Non-Return-to-Zero Inverted) data. The next steps are the NRZI to NRZ (NonReturn-to-Zero) process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing
of the 4B nibble to the MII interface.
8.6.2.
100Base-FX Fiber Transmit and Receive Operation
The RTL8201FI-VC can be configured to 100Base-FX mode via hardware configuration. The hardware
100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.
100Base-FX Transmit
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pair form.
100Base-FX Receive
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
8.6.3.
10Base-T Transmit and Receive Operation
10Base-T Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a band-limited filter embedded in the RTL8201FI-VC and then transmitted.
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10Base-T Receive
In 10Base-T receive mode, the Manchester decoder in the RTL8201FI-VC converts the Manchester
encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. The serial NRZ
data stream is then converted to a parallel 4-bit nibble signal (RXD[0:3]).
8.7. Reset and Transmit Bias
There are two RTL8201FI-VC reset types:
1. Hardware Reset: Pull the PHYRSTB pin high for at least 150ms to access the RTL8201FI-VC registers.
Pull the PHYRSTB pin low for at least 10ms and then pull high. All registers will return to default values
after a hardware reset. The media interface will disconnect and restart the auto-negotiation/parallel
detection process.
2. Software Reset: Set register 0 bit 15 to 1 for at least 20ms to access the RTL8201FI-VC registers. A
Software reset will only partially reset the registers, and will reset the chip status to ‘initializing’.
The RSET pin must be pulled low by a 2.49KΩ resistor with 1% accuracy for reference. Keep its circuitry
away from other clock traces and transmit/receive paths to avoid signal interference.
8.8. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201FI-VC is fabricated in a 0.11µm process. The core circuit needs to be powered by 1.1V,
however, the digital IO and DAC circuits need a 3.3V power supply. Regulators are embedded in the
RTL8201FI-VC to convert 3.3V to 1.1V.
Note: The internal linear regulator output voltage is 1.1V.
As with many commercial voltage conversion devices, the 1.1V output pin of this circuit requires the use
of an output capacitor (0.1µF X7R low-ESR ceramic capacitor) as part of the device frequency
compensation.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
Note: The embedded 1.1V LDO is designed for PHYceiver device internal use only. Do not provide this
power to other devices.
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8.9. Automatic Polarity Correction
The RTL8201FI-VC automatically corrects polarity errors on the receive pairs in 10Base-T mode
(polarity is irrelevant in 100Base-TX mode). In 10Base-T mode, polarity errors are corrected based on the
detection of validly spaced link pulses. Detection begins during the MDI crossover detection phase and
locks when the 10Base-T link is up. The polarity becomes unlocked when the link goes down.
8.10. Far End Fault Indication
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled,
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method that is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201FI-VC detects this pattern three
times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On
the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201FI-VC will start sending
this pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive
path has a problem from the point of view of the RTL8201FI-VC. The FEFI mechanism is used only in
100Base-FX mode.
8.11. Wake-On-LAN (WOL)
8.11.1. Magic Packet and Wake-Up Frame Format
The RTL8201FI-VC can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the
system via the LED0/PHYAD[0]/PMEB (Power Management Event; ‘B’ means low active) pin when
such a packet or event occurs. The system can then be restored to a normal state to process incoming jobs.
The LED0/PHYAD[0]/PMEB pin must be connected with a 4.7k-ohm resistor and pulled up to 3.3V
when using the WOL function. When the Wake-Up Frame or a Magic Packet is sent to the PHY, the
LED0/PHYAD[0]/PMEB pin will be set low to notify the system to wake up. Refer to the WOL
application note for details.
Magic Packet Wake-Up occurs only when the following conditions are met:
•
The destination address of the received Magic Packet is acceptable to the RTL8201FI-VC, e.g., a
broadcast, multicast, or unicast packet addressed to the current RTL8201FI-VC.
•
The received Magic Packet does not contain a CRC error.
•
The Magic Packet pattern matches; i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)
in any part of a valid Ethernet packet.
A Wake-Up Frame event occurs only when the following conditions are met:
•
The destination address of the received Wake-Up Frame is acceptable to the RTL8201FI-VC, e.g., a
broadcast, multicast, or unicast address to the current RTL8201FI-VC.
•
The received Wake-Up Frame does not contain a CRC error.
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RTL8201FI
Datasheet
•
The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up
Frame pattern given by the local machine’s OS. Or, the RTL8201FI-VC is configured to allow direct
packet wake up, e.g., a broadcast, multicast, or unicast network packet.
Note 1: 16-bit CRC: The RTL8201FI-VC supports eight long Wake-Up frames (covering 128 mask bytes
from offset 0 to 127 of any incoming network packet). CRC16 polynomial=x16+x12+x5+1.
Note 2: Refer to the WOL Application Note for detailed Wake-On-LAN register settings and waveform
timings.
8.11.2. Active Low Wake-On-LAN
When the PHY receives a Wake-Up Frame or a Magic Packet from the link partner, the
LED0/PHYAD[0]/PMEB pin will go low and the MAC will wake up after a T cycle. The PMEB pin will
be reset to high via the system or MAC (Figure 13 and Figure 14).
Refer to the WOL Application Note for details.
Figure 13. Active Low When Receiving a Magic Packet
Figure 14. Active Low When Receiving a Wake-Up Frame
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Datasheet
8.11.3. Pulse Low Wake-On-LAN
When the PHY receives a Wake-Up Frame or a Magic Packet from the link partner, the
LED0/PHYAD[0]/PMEB pin will go low for a period (84ms, 168ms (default), 336ms, or 672ms; set
through the MDC/MDIO), and will wake up after a T cycle (Figure 15 and Figure 16).
Refer to the WOL Application Note for details.
WOL Enable
From Link Partner
Magic Packet
PMEB
T
Period controlled by the PHY
Figure 15. Pulse Low When Receiving a Magic Packet
WOL Enable
From Link Partner
Wake Up Frame
PMEB
T
Period controlled by the PHY
Figure 16. Pulse Low When Receiving a Wake-Up Frame
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8.11.4. Wake-On-LAN Pin Types (MII Mode)
Table 43. Wake-On-LAN Pin Types (MII Mode)
Name
Type
Normal
100M
10M
Idle
TXC
O/PD
25M CLK Output
2.5M CLK Output
2.5M CLK Output
TXEN
I/PD
I
I
I
TXD[0:3]
I/PD
I
I
I
RXC
O/PD
25M CLK Output
2.5M CLK Output
2.5M CLK Output
COL
LI/O/PD
O
O
O
CRS
LI/O/PD
O
O
O
RXDV
LI/O/PD
O
O
O
RXD[0:2]
O/PD
O
O
O
RXD[3]
LI/O/PD
O
O
O
RXER
LI/O/PD
O
O
O
MDC
I/PU
I
I
I
MDIO
IO/PU
IO
IO
IO
Note 1: If TX Isolate=1, the TXC is halted and the pin type is ‘L’.
Set page0, register0, and bit10=1 to change the TXC pin type to ‘PD’.
Note 2: If RX Isolate=1, all the MII RX interfaces are halted and the pin types are ‘PD’.
WOL Enable
O (2.5M/25M)/L/PD1
I/PD
I/PD
O (2.5M/25M)/PD2
O or PD2
O or PD2
O or PD2
O or PD2
O or PD2
O or PD2
I/PU
IO/PU
8.11.5. Wake-On-LAN Pin Types (RMII Mode)
Table 44. Wake-On-LAN Pin Types (RMII Mode)
Normal
WOL Enable
100M
10M
Idle
50M
CLK
50M
CLK
50M
CLK
TXC (REF_CLK)1 IO/PD
I/O (50M)2
Input/Output
Input/Output
Input/Output
TXEN
I/PD
I
I
I
I/PD
TXD[0:1]
I/PD
I
I
I
I/PD
CRS_DV
LI/O/PD
O
O
O
O or PD3
RXD[0:1]
O/PD
O
O
O
O or PD3
RXER
LI/O/PD
O
O
O
O or PD3
MDC
I/PU
I
I
I
I/PU
MDIO
IO/PU
IO
IO
IO
IO/PU
Note 1: If TXC (REF_CLK) is in input mode (MAC to PHY), the REF_CLK cannot halt at WOL Enable.
Note 2: When REF_CLK is in output mode (PHY to MAC), the REF_CLK cannot halt (always toggles 50MHz out). To set
the TXC pin type to ‘PD’, set page0, register0, bit10=1.
Note 3: If RX Isolate=1, all RMII RX interfaces are halted and the pin types are ‘PD’.
Name
Type
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201FI
Datasheet
8.12. Energy Efficient Ethernet (EEE)
The RTL8201FI-VC supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE), at
10Mbps and 100Mbps. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being
transmitted, the system goes to Low Power Idle mode to save power. When packets need to be
transmitted, the system returns to normal mode, and does this without changing the link status and
without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled; however,
the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer
protocols and applications.
EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported.
Refer to http://www.ieee802.org/3/az/index.html for more details.
8.13. Spread Spectrum Clock (SSC)
The RMII REF_CLK path can be a source of EMI noise. Spread Spectrum Clock (SSC) spreads the
REF_CLK signal across a wider bandwidth, reducing the peak radiated energy at any one frequency, and
lowering unwanted EMI noise.
The SSC function is enabled by default when using RMII REF_CLK output mode (see section 7.21 Page
7 Register 24 Spread Spectrum Clock Register, page 22).
Figure 17. Spectrum Spread Clock
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Datasheet
9.
Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 45. Absolute Maximum Ratings
Symbol
Description
Minimum
Maximum
DVDD33, AVDD33
Supply Voltage 3.3V
-0.4
+3.7
-0.1
+1.26
DVDD10, DVDD10OUT, Supply Voltage 1.05V*
AVDD10OUT
DC Input
Input Voltage
-0.3
Corresponding Supply Voltage +0.5V
DC Output
Output Voltage
-0.3
Corresponding Supply Voltage +0.5V
Storage Temperature
N/A
-55
+125
Note: The internal linear regulator output voltage is 1.1V.
9.1.2.
Unit
V
V
V
V
°C
Recommended Operating Conditions
Table 46. Recommended Operating Conditions
Description
Pins
Minimum
Typical
Supply Voltage VDD
DVDD33, AVDD33
2.97
3.30
DVDD10, DVDD10OUT,
1.00
1.05*
AVDD10OUT
Ambient Operating Temperature TA
-40
Maximum Junction Temperature
Note: The internal linear regulator output voltage is 1.1V.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Maximum
3.63
1.16
85
125
Track ID: JATR-8275-15
Unit
V
V
°C
°C
Rev. 1.1
RTL8201FI
Datasheet
9.1.3.
Power On and PHY Reset Sequence
The RTL8201FI-VC needs 150ms power on time. After 150ms it can access the PHY register from
MDC/MDIO.
Figure 18. Power On and PHY Reset Sequence
Table 47. Power On and PHY Reset Sequence
Symbol
Description
Minimum
Rt1
3.3V Rise Time@ Power On Sequence
100µs
Rt2
1.05V Rise Time@ Power On and PHY Reset Sequence
100µs
Rt3
PHYRSTB De-Assert after PHY_3.3V Stable
80µs
Note: Rt2 requires 100µs Rise Time only when using an external 1.05V power supply.
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Maximum
-
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9.1.4.
RMII Input Mode Power Dissipation
The whole system power dissipation (including regulator loss) is shown in Table 48.
Symbol
P10IDLE
P10F
P10FEEE
P100IDLE
P100IDLEEEE
P100F
PLDPS
PPHYRST
9.1.5.
Table 48. RMII Input Mode Power Dissipation (Whole System)
Condition
RTL8201FI-VC
10Base-T Idle
29.7
10Base-T Full Duplex (EEE not Enabled)
122.1
10Base-T Full Duplex with EEE
112.2
100Base-T Idle (EEE not Enabled)
141.9
100Base-T Idle with EEE
33
100Base-T Full Duplex
165
Link Down Power Saving
13.2
PHY Reset
3.3
Unit
mW
mW
mW
mW
mW
mW
mW
mW
Input Voltage: Vcc
Symbol
TTL VIH
TTL VIL
TTL VOH
TTL VOL
TTL IOZ
IIN
IPL
IPH
PECL VIH
PECL VIL
PECL VOH
PECL VOL
Table 49. Input Voltage: Vcc
Condition
Input High Voltage
Input Low Voltage
Output High Voltage
IOH=-8mA
Output Low Voltage
IOL=8mA
Tri-State Leakage
Vout=Vcc or GND
Input Current
Vin=Vcc or GND
Vin=Vcc or GND
Input Current with Internal Weakly Pulled
Low Resistor
Vin=Vcc or GND
Input Current with Internal Weakly Pulled
High Resistor
PECL Input High Voltage
PECL Input Low Voltage
PECL Output High Voltage
PECL Output Low Voltage
-
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
43
Minimum
0.5*Vcc
-0.5V
0.65*Vcc
-110µA
-1µA
-1µA
Maximum
Vcc+0.5V
0.7V
Vcc
0.7V
10µA
10µA
100µA
-110µA
10µA
Vdd-1.16V
Vdd-1.81V
Vdd-1.02V
-
Vdd-0.88V
Vdd-1.47V
Vdd-1.62V
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Datasheet
9.2. AC Characteristics
All output timing assumes equivalent loading between 10pF and 25pF that includes PCB layout traces
and other connected devices (e.g., MAC).
9.2.1.
MII Transmission Cycle Timing
Figure 19. MII Interface Setup/Hold Time Definitions
Figure 20 and Figure 21 and show an example of a packet transfer from MAC to PHY on the MII
interface.
t3
VI H(min)
VI L(max)
TXCLK
t4
t5
t1
t2
VI H(min)
VI L(max)
TXD[0:3]
TXEN
Figure 20. MII Transmission Cycle Timing-1
TXCLK
TXEN
TXD[0:3]
t6
t7
CRS
Figure 21. MII Transmission Cycle Timing-2
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Datasheet
Symbol
t1
t2
t3
t4
t5
t6
t7
9.2.2.
Table 50. MII Transmission Cycle Timing
Description
Minimum
TXCLK High Pulse Width
100Mbps
14
10Mbps
140
TXCLK Low Pulse Width
100Mbps
14
10Mbps
140
TXCLK Period
100Mbps
10Mbps
TXEN, TXD[0:3]
100Mbps
10
Setup to TXCLK Rising Edge
10Mbps
5
TXEN, TXD[0:3]
100Mbps
0
Hold After TXCLK Rising Edge
10Mbps
0
TXEN Sampled to CRS High
100Mbps
10Mbps
TXEN Sampled to CRS Low
100Mbps
10Mbps
-
Typical
20
200
20
200
40
400
-
Maximum
26
260
26
260
40
400
160
2000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MII Reception Cycle Timing
Figure 22 and Figure 23 show an example of a packet transfer from PHY to MAC on the MII interface.
t3
V
RXCLK
V
t4
t5
t1
I H(min)
I L(max)
t2
RXD[0:3]
RXDV
RXER
V
V
I H(min)
I L(max)
Figure 22. MII Reception Cycle Timing-1
RXCLK
t9
t8
RXDV
RXD[0:3]
t6
t7
CRS
TPRX+Figure 23. MII Reception Cycle Timing-2
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201FI
Datasheet
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
9.2.3.
Table 51. MII Reception Cycle Timing
Minimum
100Mbps
14
10Mbps
140
RXCLK Low Pulse Width
100Mbps
14
10Mbps
140
RXCLK Period
100Mbps
10Mbps
RXER, RXDV, RXD[0:3]
100Mbps
10
Setup to RXCLK Rising Edge
10Mbps
10
RXER, RXDV, RXD[0:3]
100Mbps
10
Hold After RXCLK Rising Edge
10Mbps
10
Receive Frame to CRS High
100Mbps
10Mbps
End of Receive Frame to CRS Low
100Mbps
10Mbps
Receive Frame to Sampled Edge of RXDV
100Mbps
10Mbps
End of Receive Frame to Sampled Edge of RXDV 100Mbps
10Mbps
Description
RXCLK High Pulse Width
Typical
20
200
20
200
40
400
-
Maximum
26
260
26
260
130
2000
240
1000
150
3200
120
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RMII Transmission and Reception Cycle Timing
MAC to PHY
Setup/Hold Time
RMII TX
RTL8201FI-VC
REFCLK
MAC
RMII RX
PHY to MAC
Output Delay Time
Figure 24. RMII Interface Setup, Hold Time, and Output Delay Time Definitions
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201FI
Datasheet
Figure 25. RMII Transmission and Reception Cycle Timing
Table 52. RMII Transmission and Reception Cycle Timing
Description
Minimum Typical Maximum Unit
Frequency of Reference Clock
50
MHz
Duty Cycle of Reference Clock
35
65
%
TXD[1:0]/TXEN Setup Time to REFCLK
4
ns
TXD[1:0]/TXEN Hold Time from REFCLK
2
ns
2
ns
RXD[1:0]/CRS_DV/RXER Output Delay Time
from REFCLK
Note 1: RMII TX timing can be adjusted by setting page7, register16[11:8]; the minimum adjustable resolution is 2ns.
Any changes for these bits are not recommended as the default value is the optimum setting.
Note 2: RMII RX timing can be adjusted by setting page7, register16[7:4]; the minimum adjustable resolution is 2ns. Any
changes for these bits are not recommended as the default value is the optimum setting.
Symbol
REFCLK Frequency
REFCLK Duty Cycle
T_ipsu_tx_rmii
T_iphd_tx_rmii
T_ophd_rx_rmii
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Datasheet
9.2.4.
MDC/MDIO Timing
MAC to PHY
MDIO Setup/Hold Time
MDC
RTL8201FI-VC
MAC
MDIO
PHY to MAC
MDIO Vaild from MDC Rising Edge
Figure 26. MDC/MDIO Interface Setup, Hold Time, and Valid from MDC Rising Edge Time Definitions
Figure 27. MDC/MDIO Timing
Symbol
t1
t2
t3
t4
t5
t6
Table 53. MDC/MDIO Timing
Description
Minimum
MDC High Pulse Width
160
MDC Low Pulse Width
160
MDC Period
400
MDIO Setup to MDC Rising Edge
10
MDIO Hold Time from MDC Rising Edge
10
MDIO Valid from MDC Rising Edge
0
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
48
Maximum
300
Unit
ns
ns
ns
ns
ns
ns
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Rev. 1.1
RTL8201FI
Datasheet
9.2.5.
Transmission without Collision
Figure 28 shows an example of a packet transfer from MAC to PHY.
Figure 28. MAC to PHY Transmission without Collision
9.2.6.
Reception without Error
Figure 29 shows an example of a packet transfer from PHY to MAC.
Figure 29. PHY to MAC Reception Without Error
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Datasheet
9.3. Crystal Characteristics
Table 54. Crystal Characteristics
Symbol
Description/Condition
Minimum
To
Operating Temperature Range
-40
Fref
Parallel Resonant Crystal Reference Frequency,
Fundamental Mode, AT-Cut Type.
-30
Fref Stability
Parallel Resonant Crystal Frequency Stability,
Fundamental Mode, AT-Cut Type. Ta=-40°C~85°C.
Fref Tolerance
-50
Parallel Resonant Crystal Frequency Tolerance,
Fundamental Mode, AT-Cut Type. Ta=25°C.
Fref Duty Cycle
Reference Clock Input Duty Cycle.
40
ESR
Equivalent Series Resistance.
DL
Drive Level.
Jitter
Broadband Peak-to-Peak Jitter1, 2
Note 1: 25KHz to 25MHz RMS < 3ps.
Note 2: Broadband RMS < 9ps.
9.4.
Typical
25
Maximum
85
-
Unit
°C
MHz
-
+30
ppm
-
+50
ppm
-
60
30
0.3
500
%
Ω
mW
ps
Oscillator Requirements
Parameter
Operating Temperature Range
Frequency
Frequency Stability
Frequency Tolerance
Duty Cycle
Broadband Peak-to-Peak Jitter1, 2
Vpeak-to-peak
Rise Time (10%~90%)
Fall Time (10%~90%)
Note 1: 25KHz to 25MHz RMS < 3ps.
Note 2: Broadband RMS < 9ps.
Table 55. Oscillator Requirements
Condition
Minimum
Typical
-40
25/50
Ta=-40°C~85°C
-30
Ta=25°C
-50
40
3.15
3.3
-
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
50
Maximum
85
30
50
60
500
3.45
10
10
Track ID: JATR-8275-15
Unit
°C
MHz
ppm
ppm
%
ps
V
ns
ns
Rev. 1.1
RTL8201FI
Datasheet
9.5. Clock Requirements
Parameter
Frequency
Frequency Stability
Frequency Tolerance
Duty Cycle
Broadband Peak-to-Peak Jitter1, 2
Vpeak-to-peak
Rise Time (10%~90%)
Fall Time (10%~90%)
Note 1: 25KHz to 25MHz RMS < 3ps.
Note 2: Broadband RMS < 9ps.
Table 56. Clock Requirements
Minimum
Typical
25/50
-30
-50
40
3.15
3.3
-
Maximum
30
50
60
500
3.45
10
10
Unit
MHz
ppm
ppm
%
ps
V
ns
ns
9.6. Transformer Characteristics
Parameter
Turn Ratio
Inductance (min.)
Table 57. Transformer Characteristics
Transmit End
1:1 CT
350µH @ 8mA
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
51
Receive End
1:1 CT
350µH @ 8mA
Track ID: JATR-8275-15
Rev. 1.1
10. Mechanical Dimensions
Symbol
A
A1
A3
b
c
D/E
D2/E2
e
L
Min
0.75
0.00
0.18
3.10
0.30
Dimension in mm
Nom
0.85
0.02
0.20REF
0.25
5.00BSC
3.35
0.50BSC
0.40
Max
1.00
0.05
Min
0.030
0.000
0.30
0.6
0.007
-
3.60
0.122
0.50
0.012
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
Dimension in inch
Nom
0.034
0.001
0.008REF
0.010
0.197BSC
0.132
0.020BSC
0.016
Max
0.039
0.002
0.012
0.024
0.142
0.020
RTL8201FI
Datasheet
11. Ordering Information
Table 58. Ordering Information
Part Number
Package
RTL8201FI-VC-CG 32-Pin QFN ‘Green’ Package
Note: See page 5 for package identification.
Status
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-578-0211 Fax: 886-3-577-6047
www.realtek.com
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-8275-15
Rev. 1.1
