AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Features
Consumer Electronics
Set Top Box
DVDRW Players
Graphics Cards
ESD Protect for Transition Minimized Differential
Signaling (TMDS) channels
Protects four I/O lines
Provide ESD protection for each line to
IEC 61000-4-2 (ESD) ±15kV (air), ±10kV (contact)
Description
IEC 61000-4-5 (Lightning) 3.5A (8/20µs)
AZ1045-04F is a design which includes ESD
rated diode arrays to protect high speed data
interfaces. The AZ1045-04F has been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD).
AZ1045-04F is a unique design which includes
ESD rated, ultra low capacitance steering diodes
and a unique design of clamping cell which is an
equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
the transient to either the internal ESD line or to
ground line. The internal unique design of
clamping cell prevents over-voltage on the
internal ESD line and on the I/O line, which is
protecting any downstream components.
AZ1045-04F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
For operating voltage of 5V and below
Ultra low capacitance : 0.5pF typical
Fast turn-on and Low clamping voltage
Array of ESD rated diodes with internal
equivalent TVS (Transient Voltage
Suppression) diode
Simplified layout for HDMI connectors
Solid-state silicon-avalanche and active circuit
triggering technology
Green part
Applications
High Definition Multi-Media Interface (HDMI)
1.3 & 1.4 version
DisplayPort interface
SATA and eSATA interface
USB3.0
Digital Visual Interface (DVI)
USB2.0 up to 480Mb/s
IEEE 1394 up to 3.2 Gb/s
Ethernet port: 10/100/1000 Mb/s
Desktop and Notebooks PCs
Circuit Diagram
1
2
4
Pin Configuration
5
3,8
Line-1
1
10 NC
Line-2
2
9
GND
3
Line-3
4
7
NC
Line-4
5
6
NC
8
NC
GND
DFN2510P10E (Top View)
Revision 2013/03/08
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1
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNITS
Peak Pulse Current (tp =8/20µs)
IPP
3.5
A
Peak Pulse Power (tp =8/20µs)
PPP
30
W
Operating Voltage (I/O pin-GND)
VDC
(GND – 0.5) to 6
V
ESD per IEC 61000-4-2 (Air)
15
VESD
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
TSOL
Operating Temperature
260 (10 sec.)
o
-55 to +85
o
-55 to +150
o
TOP
Storage Temperature
TSTO
kV
10
C
C
C
ELECTRICAL CHARACTERISTICS
PARAMETER
Reverse Stand-Off
Voltage
Channel Leakage
Current
Reverse Breakdown
Voltage
Forward Voltage
ESD Clamping
Voltage
ESD Dynamic
Turn-on Resistance
Channel Input
Capacitance
Channel to Channel
Input Capacitance
Revision 2013/03/08
SYMBOL
CONDITIONS
VRWM
Pin-1,-2,-4,-5 to pin-3,-8, T=25 oC
ICH-Leak
VPin-1,-2,-4,-5 = 5V, VPin-3,-8 = 0V, T=25 oC
VBV
VF
Vclamp
Rdynamic
CIN
CCROSS
IBV = 1mA, T=25 oC, Pin-1,-2,-4,-5 to
pin-3,-8
IF = 15mA, T=25 oC, pin-3,-8 to
pin-1,-2,-4,-5
IEC 61000-4-2 +6kV,T=25 oC,
Contact mode, any I/O pin to Ground
IEC 61000-4-2, 0~+6kV,T=25 oC,
Contact mode, any I/O pin to Ground
Vpin-3,-8 = 0V,VIN = 2.5V,f = 1MHz,T=25
o
C, any I/O pin to Ground
Vpin-3,-8 = 0V, VIN = 2.5V, f = 1MHz,
T=25 oC , between I/O pins
©2013 Amazing Micro.
2
MIN
TYP
MAX
UNITS
5
V
1.5
µA
6
V
0.9
1.1
V
12
V
0.3
Ω
0.5
0.65
pF
0.04
0.08
pF
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Typical Characteristics
Typical Variation of CIN vs. VIN
0.9
0.09
0.8
0.08
0.7
Typical Variation of CIO-to-IO vs. VIN
0.10
Input Capacitance (pF)
Input Capacitance (pF)
1.0
o
f = 1MHz, T=25 C,
0.6
0.5
0.4
0.3
0.2
0.1
0.07
f = 1MHz, T=25 oC,
0.06
0.05
0.04
0.03
0.02
0.01
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.00
0.0
4.0
0.5
Input Voltage (V)
2.0
2.5
3.0
3.5
4.0
Analog Cross Talk
20
0
10
Analog Cross Talk (dB)
-3
Insertion Loss (dB)
1.5
Input Voltage (V)
insertion Loss S21 (I/O-to-GND)
-6
-9
-12
-15
-18
-21
-24
3GHz: -0.92dB
4.3GHz: -3dB
-27
0
-10
-20
-30
-40
-50
-60
-70
-30
-80
1e+8
1e+9
1e+8
Frequency (Hz)
Transmission Line Pulsing (TLP) Current (A)
1.0
1e+9
Frequency (Hz)
Transmission Line Pulsing (TLP) Measurement
18
16
14
V_pulse
12
Pulse from a
transmission line
TLP_I
10
100ns
+
TLP_V
8
DUT
-
6
4
I/O to GND
2
0
0
2
4
6
8
10
12
14
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2013/03/08
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Applications Information
A. Device Connection
The AZ1045-04F is designed to protect four
data lines from transient over-voltage (such as
ESD stress pulse). The device connection of
AZ1045-04F is shown in the Fig. 1. In Fig. 1, the
four protected data lines are connected to the
ESD protection pins (pin1, pin2, pin4, and pin5)
of AZ1045-04F. The ground pins (pin3 and pin8)
of AZ1045-04F are the negative reference pins.
data line
I/O 1
I/O 2
I/O 2
Line-1
Line-2
1
10 NC
2
9
GND
3
Line-3
Line-4
To
I/O-port
Connector
I/O 1
data line
4
AZ1045-04F
To
I/O-port
Connector
These pins should be directly connected to the
GND rail of PCB (Printed Circuit Board). To get
minimum parasitic inductance, the path length
should keep as short as possible.
AZ1045-04F can provide ESD protection for
4 I/O signal lines simultaneously. If the number of
I/O signal lines is less than 4, the unused I/O pins
can be simply left as NC pins.
NC
GND
8
5
7
NC
6
NC
I/O 3
I/O 3
data line
I/O 4
To
Protected
IC
data line
To
Protected
IC
I/O 4
Fig. 1 Data lines connection of AZ1045-04F.
B. Application
AZ1045-04F is designed for protecting high
speed I/O ports from over-voltage caused by
Electrostatic Discharging (ESD). Thus, a lot of
kinds of high speed I/O ports can be the
applications of AZ1045-04F, especially, the HDMI
port.
HDMI Protection for High and Low speed
signals
The HDMI Compliance Test Specification
(CTS) requires sink (receiver) ports maintain a
differential impedance of 100 Ohms +/- 15%.
ESD protection devices have an inherent
junction capacitance. Even a small amount of
added capacitance on a HDMI port will cause the
impedance of the differential pair to drop. Thus,
some form of compensation to the layout will be
required to bring the differential pairs back within
the required 100 Ohm +/- 15% range. The higher
the added capacitance, the more extreme the
modifications will need to be. If the added
capacitance is too high, compensation may not
even be possible. The AZ1045-04F presents
0.5pF capacitance to each differential signal
while being rated to handle >8kV ESD contact
Revision 2013/03/08
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
discharges (>15kV air discharge) as outlined in
IEC 61000-4-2. Therefore, it is possible to make
none adjustment to the board layout parameters
to compensate for the added capacitance of the
AZ1045-04F. Figure 2 shows how to implement
the AZ1045-04F in a HDMI application.
The AZ1045-04F is designed for allowing the
traces to run straight through the device to
simplify the PCB layout. As shown in Figure 2,
the best way to design the PCB trace is using the
flow through layout. The solid line represents the
PCB trace. Note that the PCB traces are used to
connect the pin pairs for each line (pin 1 to pin 10,
pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). For
example, line 1 enters at pin 1 and exits at Pin 10
and the PCB trace connects pin 1 and 10
together. Lines 2, 3, and 4 have the same way of
connection. The ground pins (pin3 and pin8) of
AZ1045-04F are the negative reference pins.
These pins should be directly connected to the
GND plane of PCB. To get minimum parasitic
inductance, the path length should keep as short
as possible. In Figure 2, the none-TMDS
signals, DDC_CLK, DDC_DAT, CE_REMOTE,
and HOTPLUG_DET, can be protected with
another low cost part, e.g., AZC199-04S.
Line -1 1
10 NC
TMDS_GND
Line -2 2
9
NC
8
GND
7
NC
6
NC
TMDS_D2-
GND
AZ1045-04F
TMDS_D2+
3
TMDS_D1+
Line -3 4
TMDS_GND
Line -4 5
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D11
10 NC
Line-2
2
9
NC
TMDS_D0-
GND
3
8
GND
TMDS_CK+
Line-3
4
7
NC
TMDS_GND
Line-4
5
6
NC
TMDS_GND
AZ1045-04F
Line-1
TMDS_D0+
TMDS_D0+
TMDS_D0-
TMDS_CK+
TMDS_CK-
TMDS_CKCE_REMOTE
CE_REMOTE
Via hole to GND
N/C
DDC_DAT
GND
3
GND
2
DDC_CLK
1
AZC199-04S
DDC_CLK
4
5
+5V
6
Via hole to +5V
DDC_DAT
+5V OUT
Via hole to GND
C=100nF
(optional)
HOTPLUG_DET
HOTPLUG_DET
HDMI
Connector
Fig. 2 HDMI Protection for High and Low speed signals.
Revision 2013/03/08
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
C. Measurement Results on a HDMI port
Fig. 3a and 3b show the test boards for
measuring the differential impedance of a HDMI
port without using ESD protection array, and with
using AZ1045-04F ESD protection array,
respectively.
Fig. 4 shows the differential impedance
measurement results. The range of the
differential impedance without ESD protection
array on it is from 96Ω to 106Ω, which meets the
spec of 100 Ohms +/- 15%. And the range of the
differential impedance with AZ1045-04F ESD
protection array on it is from 88.9Ω to 104Ω,
which still meets the spec of 100 Ohms +/- 15%.
From the measured results shown in Fig. 4, the
degradation of the differential impedance
induced by the parasitic effects of AZ1045-04F is
at the range of 12.8Ω to 14.2Ω. This
demonstrates when the PCB differential
impedance is designed at around 105Ω, then
none adjustment to the board layout parameters
is needed to compensate for the added ultra
small capacitance of the AZ1045-04F and the
test results can pass the spec of 100Ω +/- 15%.
Fig. 5 shows the HDMI Eye Diagram
performance when the AZ1045-04F is under
used. No apparent affection is shown due to the
low capacitance feature of the AZ1045-04F.
Fig. 3a The test board for measuring the
differential impedance of a HDMI port without
using ESD protection array.
Fig. 3b The test board for measuring the
differential impedance of a HDMI port with using
ESD protection array, AZ1045-04F.
Fig. 4a The measured differential impedance of
Data0- and Data0+ (103.3Ω without ESD
protection array, and 89.1Ω with AZ1045-04F).
Fig. 4b The measured differential impedance of
Data1- and Data1+ (102.7Ω without ESD
protection array, and 89.1Ω with AZ1045-04F).
Revision 2013/03/08
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Fig. 4c The measured differential impedance of
Data2- and Data2+ (104.2Ω without ESD
protection array, and 90.8Ω with AZ1045-04F).
Fig. 4d The measured differential impedance of
Clock- and Clock+ (101.7Ω without ESD
protection array, and 88.9Ω with AZ1045-04F).
Fig. 5 the HDMI Eye Diagram performance when the AZ1045-04F is under used. No apparent affection
is shown due to the low capacitance feature of the AZ1045-04F.
Revision 2013/03/08
©2013 Amazing Micro.
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
PACKAGE OUTLINE
(DFN2510P10E)
TOP VIEW (unit in mm)
BOTTOM VIEW (unit in mm)
SIDE VIEW (unit in mm)
Symbol
A
A1
A3
D
E
D1
E1
b
e
L1
L2
b2
L
Revision 2013/03/08
Millimeters
min
max
0.40
0.55
0.00
0.05
0.152REF.
2.45
2.55
0.95
1.05
0.35
0.45
0.35
0.45
0.15
0.25
0.5 BSC
0.075 REF
0.05 REF
0.20
0.30
0.35
0.45
©2013 Amazing Micro.
8
Inches
min
max
0.016
0.022
0.000
0.002
0.006 BSC
0.096
0.100
0.037
0.041
0.014
0.018
0.014
0.018
0.006
0.010
0.019 BSC
0.0029 REF
0.0019 REF
0.0079
0.012
0.014
0.018
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
LAND LAYOUT
D
D1
Dimensions
B F
A
E
C
C1
Notes:
Index
Millimeter
Inches
A
0.875
0.034
B
0.20
0.008
C
0.50
0.02
C1
1.00
0.039
D
0.25
0.01
D1
0.4
0.016
E
0.675
0.027
F
1.55
0.061
This LAND LAYOUT is for reference
purposes only. Please consult your
manufacturing partners to ensure your
company’s PCB design guidelines are met.
MARKING CODE
Part Number
117XY
AZ1045-04F
(Green part)
117 = Device Code
X = Date Code
Y= Control Code
Marking Code
117XY
Note. Green means Pb-free, RoHS, and
Halogen free compliant.
Ordering Information
PN#
Material
Type
Reel size
MOQ/interal box
MOQ/carton
AZ1045-04F.R7G
Green
T/R
7 inch
4 reel= 12,000/box
6 box =72,000/carton
Revision 2013/03/08
©2013 Amazing Micro.
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AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Revision History
Revision
Modification Description
Revision 2008/12/09
Preliminary Release.
Revision 2009/01/16
The Initial Formal Release.
Revision 2009/05/15
Correct the typos at Package Outline.
Revision 2009/06/10
1. Correct the typos at the ABSOLUTE MAXIMUM RATINGS.
2. Update the information of the measurement results on a HDMI port.
Revision 2009/09/08
1. Update the bottom view indication of the Package Outline.
2. Update the “D” value of Land Layout.
Revision 2009/11/25
Increase the Lightning (8/20µs) spec.
Revision 2009/12/26
Update the PACKAGE DIMENSIONS.
Revision 2011/05/05
1. Update the Company Logo.
2. Add the Ordering Information.
Revision 2011/07/16
Add the Applications of USB3.0 and HDMI 1.4 version.
Revision 2012/02/09
Modify the Bottom View of Package Outline to add three parameters,
b2, L1, and L2.
Revision 2012/03/23
Add Fig. 5 of HDMI Eye Diagram.
Revision 2012/06/05
Update the diagram of the Pin Configuration on page 1.
Revision 2013/03/08
Update the “A” value of Package Outline.
Revision 2013/03/08
©2013 Amazing Micro.
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