DA14531-00000FX2

DA14531 Final Ultra Low Power Bluetooth 5.1 SoC General Description The DA14531 is an ultra-low power SoC integrating a 2.4 GHz transceiver and an Arm® Cortex-M0+ microcontroller with a RAM of 48 kB and a One-Time Programmable (OTP) memory of 32 kB. It can be used as a standalone application processor or as a data pump in hosted systems. The radio transceiver, the baseband processor, and the qualified Bluetooth® low energy stack is fully compliant with the Bluetooth® Low Energy 5.1 standard. The DA14531 has dedicated hardware for the Link Layer implementation of BLE and interface controllers for enhanced connectivity capabilities. The BLE firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute Protocol (ATT), the Generic Attribute Profile (GATT), and the Generic Access Profile (GAP). All profiles published by the Bluetooth® SIG as well as custom profiles are supported. The device is suitable for disposables, wireless sensor nodes, beacons, proximity tags and trackers, smart HID devices (stylus, keyboards, mice, and trackpads), toys, and medical and industrial applications. Key Features ■ Compatible with Bluetooth v5.1, ETSI EN 300 ■ Clocks 328 and EN 300 440 Class 2 (Europe), FCC □ 32 MHz crystal and 32 MHz RC osc. CFR47 Part 15 (US) and ARIB STD-T66 □ 32 kHz crystal and 32/512 kHz RC osc. (Japan) □ 15 kHz RCX as crystal replacement ■ Supports up to three BLE connections ■ Programmable Reset Circuitry ■ Typical cold boot to radio active 35 ms ■ 2× General purpose Timers with capture and ■ Processing power PWM capabilities □ 16 MHz 32-bit Arm® Cortex-M0+ with SWD interface □ 18300 EEMBC IoTMark-BLE® score □ Dedicated Link Layer and AES-128 Encryption Processor □ Software-based True Random Number Generator (TRNG) ■ Memories □ 32 kB One-Time-Programmable (OTP) □ 48 kB Retainable System RAM □ 144 kB ROM ■ Power management □ Integrated Buck/Boost DCDC converter □ Buck: 1.1 V ≤ VBAT_HIGH ≤ 3.3 V (min 1.8V if ■ Digital interfaces □ GPIOs: 6 (WLCSP17), 12 (FCGQFN24) □ 2× UARTs (one with flow control) □ SPI Master/Slave up to 32 MHz (Master) □ I2C bus at 100 kHz and 400 kHz □ 3-axis capable Quadrature Decoder □ Keyboard controller ■ Analog interfaces □ 4-channel 10-bit ADC ■ Radio transceiver □ Fully integrated 2.4 GHz CMOS transceiver □ Single wire antenna □ TX: 3.5 mA, RX: 2.2 mA (system currents OTP read needed) □ Boost: 1.1 V ≤ VBAT_LOW ≤ 1.65 V □ Clock-less hibernation mode: Buck 270 with DC-DC, VBAT_HIGH =3 V and 0 dBm) □ Programmable transmit output power from nA, Boost 240 nA -19.5 dBm to +2.5 dBm □ Built-in temperature sensor for die temperature monitoring Datasheet CFR0011-120-00 □ -94 dBm receiver sensitivity ■ Packages: □ WLCSP 17 balls, 1.7 × 2.05, 0.5 mm pitch □ FCGQFN 24 pins, 2.2 × 3, 0.4 mm pitch Revision 3.0 1 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Applications ■ Medical applications ■ Disposables ■ Beacons ■ Proximity tags and trackers ■ Wireless sensor nodes □ Fitness trackers □ Consumer health ■ Smartwatches ■ Human interface devices (HID) □ Stylus pens □ Keyboards □ Mouse devices □ Trackpads ■ Toys ■ Industrial appliances Key Benefits ■ Lowest power consumption ■ Smallest system size ■ Lowest system cost System Diagram Figure 1: System Diagram Datasheet CFR0011-120-00 Revision 3.0 2 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Contents General Description ............................................................................................................................ 1 Key Features ........................................................................................................................................ 1 Applications ......................................................................................................................................... 2 Key Benefits ......................................................................................................................................... 2 System Diagram .................................................................................................................................. 2 Contents ............................................................................................................................................... 3 Figures .................................................................................................................................................. 9 Tables ................................................................................................................................................. 10 1 Block Diagram ............................................................................................................................. 19 2 Packages and Pinout .................................................................................................................. 20 2.1 WLCSP17 ........................................................................................................................... 20 2.2 FCGQFN24 ......................................................................................................................... 24 3 Specifications .............................................................................................................................. 28 3.1 Absolute Maximum Ratings ................................................................................................ 30 3.2 Recommended Operating Conditions ................................................................................. 30 3.3 DC Characteristics .............................................................................................................. 31 3.4 Timing Characteristics......................................................................................................... 33 3.5 RCX Oscillator ..................................................................................................................... 33 3.6 XTAL32MHz Oscillator ........................................................................................................ 34 3.7 XTAL32kHz Oscillator ......................................................................................................... 34 3.8 RC32MHz Oscillator ............................................................................................................ 35 3.9 DC-DC Converter ................................................................................................................ 35 3.10 LDO_LOW Characteristics .................................................................................................. 36 3.11 Digital I/O Characteristics.................................................................................................... 37 3.12 Power On Reset .................................................................................................................. 39 3.13 GP ADC .............................................................................................................................. 39 3.14 Temperature Sensor ........................................................................................................... 41 3.15 Radio ................................................................................................................................... 41 4 System Overview ......................................................................................................................... 46 4.1 Internal Blocks..................................................................................................................... 46 4.2 Power Management Unit..................................................................................................... 47 4.2.1 Introduction .......................................................................................................... 47 4.2.2 Architecture .......................................................................................................... 47 4.2.2.1 Digital Power Domains .................................................................... 49 4.2.2.2 Power Modes ................................................................................... 50 4.2.2.3 VDD Level in Hibernation ................................................................ 53 4.2.2.4 Retainable Registers ....................................................................... 53 4.2.3 Programming ....................................................................................................... 53 4.2.3.1 Buck Configuration .......................................................................... 53 4.2.3.2 Boost Configuration ......................................................................... 54 4.2.3.3 Bypass Configuration....................................................................... 55 4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep) .............................................................. 56 Datasheet CFR0011-120-00 Revision 3.0 3 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 4.4 4.5 4.3.1 Power-up/Wake-up in Buck Configuration........................................................... 56 4.3.2 Power-up/Wake-up in Boost Configuration ......................................................... 58 4.3.3 Go-to-Sleep and Refresh Bandgap ..................................................................... 59 OTP Memory Layout ........................................................................................................... 60 4.4.1 OTP Header ......................................................................................................... 60 4.4.2 Configuration Script ............................................................................................. 62 BootROM Sequence ........................................................................................................... 63 5 Reset ............................................................................................................................................. 67 5.1 Introduction ......................................................................................................................... 67 5.2 Architecture ......................................................................................................................... 67 5.2.1 POR, HW, and SW Reset .................................................................................... 67 5.2.2 POR Functionality ................................................................................................ 69 5.2.2.1 POR Timer Clock ............................................................................. 69 5.2.2.2 RST Pad .......................................................................................... 69 5.2.2.3 POR from GPIO ............................................................................... 69 5.2.3 POR Timing Diagram ........................................................................................... 69 5.2.4 POR Considerations ............................................................................................ 70 5.3 Programming ....................................................................................................................... 70 6 Arm Cortex-M0+........................................................................................................................... 71 6.1 Introduction ......................................................................................................................... 71 6.2 Architecture ......................................................................................................................... 72 6.2.1 Interrupts .............................................................................................................. 72 6.2.2 System Timer (systick) ........................................................................................ 74 6.2.3 Wake-Up Interrupt Controller ............................................................................... 74 6.3 Programming ....................................................................................................................... 74 7 AMBA Bus .................................................................................................................................... 75 7.1 Introduction ......................................................................................................................... 75 7.2 Architecture ......................................................................................................................... 75 7.3 Programming ....................................................................................................................... 76 8 Memory Map................................................................................................................................. 77 9 Memory Controller ...................................................................................................................... 79 9.1 Introduction ......................................................................................................................... 79 9.2 Architecture ......................................................................................................................... 79 9.2.1 Arbitration ............................................................................................................ 80 10 Clock Generation ......................................................................................................................... 81 10.1 Clock Tree ........................................................................................................................... 81 10.1.1 General Clock Constraints ................................................................................... 83 10.2 Crystal Oscillators ............................................................................................................... 83 10.2.1 Frequency Control (32 MHz Crystal) ................................................................... 83 10.2.2 Automated Trimming and Settling Notification .................................................... 84 10.3 RC Oscillators ..................................................................................................................... 85 10.3.1 Frequency Calibration.......................................................................................... 86 11 OTP Controller ............................................................................................................................. 87 11.1 Introduction ......................................................................................................................... 87 11.2 Architecture ......................................................................................................................... 87 Datasheet CFR0011-120-00 Revision 3.0 4 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 11.2.1 OTP Accessing Considerations ........................................................................... 89 11.3 Programming ....................................................................................................................... 89 12 DMA Controller ............................................................................................................................ 90 12.1 Introduction ......................................................................................................................... 90 12.2 Architecture ......................................................................................................................... 90 12.2.1 DMA Peripherals .................................................................................................. 90 12.2.2 Input/Output Multiplexer....................................................................................... 91 12.2.3 DMA Channel Operation...................................................................................... 91 12.2.4 DMA Arbitration ................................................................................................... 92 12.2.5 Freezing DMA Channels...................................................................................... 93 12.3 Programming ....................................................................................................................... 93 12.3.1 Memory to Memory Transfers.............................................................................. 93 12.3.2 Peripheral to Memory Transfers .......................................................................... 93 13 I2C Interface ................................................................................................................................. 95 13.1 Introduction ......................................................................................................................... 95 13.2 Architecture ......................................................................................................................... 95 13.2.1 I2C Bus Terms ..................................................................................................... 96 13.2.1.1 Bus Transfer Terms ......................................................................... 97 13.2.2 I2C Behavior ........................................................................................................ 97 13.2.2.1 START and STOP Generation ........................................................ 98 13.2.2.2 Combined Formats .......................................................................... 98 13.2.3 I2C Protocols ....................................................................................................... 98 13.2.3.1 START and STOP Conditions ......................................................... 98 13.2.3.2 Addressing Slave Protocol .............................................................. 99 13.2.3.3 Transmitting and Receiving Protocols ........................................... 100 13.2.4 Multiple Master Arbitration ................................................................................. 101 13.2.5 Clock Synchronization ....................................................................................... 102 13.3 Programming ..................................................................................................................... 103 14 UART ........................................................................................................................................... 105 14.1 Introduction ....................................................................................................................... 105 14.2 Architecture ....................................................................................................................... 106 14.2.1 UART (RS232) Serial Protocol .......................................................................... 106 14.2.2 Clock Support .................................................................................................... 107 14.2.3 Interrupts ............................................................................................................ 107 14.2.4 Programmable THRE Interrupt .......................................................................... 108 14.2.5 Shadow Registers .............................................................................................. 110 14.2.6 Direct Test Mode ............................................................................................... 110 14.3 Programming ..................................................................................................................... 110 15 SPI Interface ............................................................................................................................... 112 15.1 Introduction ....................................................................................................................... 112 15.2 Architecture ....................................................................................................................... 113 15.2.1 SPI Timing ......................................................................................................... 113 15.3 Programming ..................................................................................................................... 114 15.3.1 Master Mode ...................................................................................................... 114 15.3.2 Slave Mode ........................................................................................................ 115 Datasheet CFR0011-120-00 Revision 3.0 5 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 16 Quadrature Decoder .................................................................................................................. 116 16.1 Introduction ....................................................................................................................... 116 16.2 Architecture ....................................................................................................................... 116 16.3 Programming ..................................................................................................................... 118 17 Clockless Wakeup Controller................................................................................................... 119 17.1 Introduction ....................................................................................................................... 119 17.2 Architecture ....................................................................................................................... 119 17.3 Programming ..................................................................................................................... 120 18 Clocked Wakeup Controller ..................................................................................................... 121 18.1 Introduction ....................................................................................................................... 121 18.2 Architecture ....................................................................................................................... 121 18.3 Programming ..................................................................................................................... 122 19 Timer 0 ........................................................................................................................................ 124 19.1 Introduction ....................................................................................................................... 124 19.2 Architecture ....................................................................................................................... 124 19.3 Programming ..................................................................................................................... 126 19.3.1 Timer Functionality ............................................................................................ 126 19.3.2 PWM Generation ............................................................................................... 127 20 Timer 1 ........................................................................................................................................ 127 20.1 Introduction ....................................................................................................................... 127 20.2 Architecture ....................................................................................................................... 128 20.3 Programming ..................................................................................................................... 128 20.3.1 Timer Functionality ............................................................................................ 128 20.3.2 Capture Functionality ......................................................................................... 129 20.3.3 Frequency Measuring Functionality ................................................................... 129 21 Timer 2 ........................................................................................................................................ 130 21.1 Introduction ....................................................................................................................... 130 21.2 Architecture ....................................................................................................................... 131 21.3 Programming ..................................................................................................................... 132 21.3.1 PWM Generation ............................................................................................... 132 21.3.2 Freeze Functionality .......................................................................................... 132 22 Watchdog Timer ........................................................................................................................ 133 22.1 Introduction ....................................................................................................................... 133 22.2 Architecture ....................................................................................................................... 133 22.3 Programming ..................................................................................................................... 134 23 Temperature Sensor ................................................................................................................. 135 23.1 Introduction ....................................................................................................................... 135 23.2 Architecture ....................................................................................................................... 135 23.2.1 Programming ..................................................................................................... 136 23.2.1.1 Absolute Temperature ................................................................... 136 23.2.1.2 Relative Temperature .................................................................... 137 24 Keyboard Controller .................................................................................................................. 138 24.1 Introduction ....................................................................................................................... 138 24.2 Architecture ....................................................................................................................... 138 Datasheet CFR0011-120-00 Revision 3.0 6 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 24.2.1 Keyboard Scanner ............................................................................................. 138 24.2.2 GPIO Interrupt Generator .................................................................................. 139 24.3 Programming ..................................................................................................................... 140 24.3.1 Keyboard Scanner ............................................................................................. 140 24.3.2 GPIO Interrupts .................................................................................................. 140 25 Input/Output Ports ..................................................................................................................... 141 25.1 Introduction ....................................................................................................................... 141 25.2 Architecture ....................................................................................................................... 141 25.2.1 Programmable Pin Assignment ......................................................................... 141 25.2.1.1 Priority ............................................................................................ 142 25.2.1.2 Direction Control ............................................................................ 142 25.2.2 General Purpose Port Registers ........................................................................ 142 25.2.2.1 Port Data Register ......................................................................... 142 25.2.2.2 Port Set Data Output Register ....................................................... 142 25.2.2.3 Port Reset Data Output Register ................................................... 142 25.2.3 Fixed Assignment Functionality ......................................................................... 142 25.2.4 Types of GPIO Pads .......................................................................................... 143 25.2.5 Driving Strength ................................................................................................. 144 26 General Purpose ADC ............................................................................................................... 145 26.1 Introduction ....................................................................................................................... 145 26.2 Architecture ....................................................................................................................... 146 26.2.1 Input Channels ................................................................................................... 146 26.2.2 Operating Modes ............................................................................................... 147 26.2.2.1 Enabling the ADC .......................................................................... 148 26.2.2.2 Manual Mode ................................................................................. 148 26.2.2.3 Continuous Mode ........................................................................... 148 26.2.3 Conversion Modes ............................................................................................. 148 26.2.3.1 AD Conversion ............................................................................... 148 26.2.3.2 Averaging ....................................................................................... 150 26.2.3.3 Chopper Mode ............................................................................... 150 26.2.4 Additional Settings ............................................................................................. 150 26.2.5 Non-Ideal Effects ............................................................................................... 151 26.2.6 Offset Calibration ............................................................................................... 151 26.2.7 Zero-Scale Adjustment ...................................................................................... 151 26.2.8 Common Mode Adjustment ............................................................................... 152 26.2.9 Input Impedance, Inductance, and Input Settling .............................................. 152 26.3 Programming ..................................................................................................................... 152 27 Real Time Clock (RTC) .............................................................................................................. 153 27.1 Introduction ....................................................................................................................... 153 27.2 Architecture ....................................................................................................................... 153 27.3 Programming ..................................................................................................................... 154 28 Power .......................................................................................................................................... 155 28.1 DCDC Converter ............................................................................................................... 155 28.2 LDOs ................................................................................................................................. 157 28.3 POR Circuit ....................................................................................................................... 157 Datasheet CFR0011-120-00 Revision 3.0 7 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 29 BLE Core .................................................................................................................................... 158 29.1 Architecture ....................................................................................................................... 158 29.1.1 Exchange Memory ............................................................................................. 158 29.2 Programming ..................................................................................................................... 159 29.2.1 Wake-Up IRQ .................................................................................................... 159 29.2.2 Switch from BLE Active Mode to BLE Deep Sleep Mode ................................. 159 29.2.3 Switch from BLE Deep Sleep Mode to BLE Active Mode ................................. 160 29.2.3.1 Switching at an Anchor Point ......................................................... 160 29.2.3.2 Switching Due to an External Event .............................................. 162 30 Radio........................................................................................................................................... 163 30.1 Introduction ....................................................................................................................... 163 30.2 Architecture ....................................................................................................................... 163 30.2.1 Receiver ............................................................................................................. 163 30.2.2 Synthesizer ........................................................................................................ 164 30.2.3 Transmitter ......................................................................................................... 164 30.2.4 RFIO .................................................................................................................. 164 30.2.5 Biasing ............................................................................................................... 164 30.2.6 RF Monitoring .................................................................................................... 164 31 Registers .................................................................................................................................... 165 31.1 Analog Miscellaneous Registers ....................................................................................... 165 31.2 BLE Core Registers .......................................................................................................... 167 31.3 Clock Generation and Reset Registers ............................................................................. 194 31.4 DCDC Converter Registers ............................................................................................... 207 31.5 DMA Controller Registers ................................................................................................. 209 31.6 General Purpose ADC Registers ...................................................................................... 224 31.7 General Purpose I/O Registers ......................................................................................... 229 31.8 General Purpose Registers ............................................................................................... 236 31.9 I2C Interface Registers ..................................................................................................... 239 31.10 Keyboard Registers ........................................................................................................... 260 31.11 Miscellaneous Registers ................................................................................................... 264 31.12 OTP Controller Registers .................................................................................................. 267 31.13 Quadrature Decoder Registers ......................................................................................... 274 31.14 Real Time Clock Registers................................................................................................ 277 31.15 SPI Interface Registers ..................................................................................................... 283 31.16 Timer and Triple PWM Registers ...................................................................................... 288 31.17 Timer1 Registers ............................................................................................................... 293 31.18 UART Interface Registers ................................................................................................. 297 31.19 Chip Version Registers ..................................................................................................... 363 31.20 Wake-Up Registers ........................................................................................................... 364 31.21 Watchdog Registers .......................................................................................................... 367 32 Ordering Information ................................................................................................................ 369 33 Package Information ................................................................................................................. 370 33.1 Moisture Sensitivity Level (MSL) ....................................................................................... 370 33.2 WLCSP Handling .............................................................................................................. 370 33.3 Soldering Information ........................................................................................................ 370 Datasheet CFR0011-120-00 Revision 3.0 8 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 33.4 Package Outlines .............................................................................................................. 370 Revision History .............................................................................................................................. 373 Figures Figure 1: System Diagram ..................................................................................................................... 2 Figure 2: DA14531 Block Diagram ...................................................................................................... 19 Figure 3: WLCSP17 Ball Assignment (Top View) ............................................................................... 20 Figure 4: FCGQFN24 Pin Assignment (Top View) ............................................................................. 24 Figure 5: Boost configuration system diagram .................................................................................... 29 Figure 6: Buck configuration system diagram ..................................................................................... 29 Figure 7: Power Management Unit: Buck Configuration ..................................................................... 48 Figure 8: Power Management Unit: Boost Configuration .................................................................... 48 Figure 9: Power Management Unit: Bypass Configuration ................................................................. 49 Figure 10: Digital Power Domains ....................................................................................................... 49 Figure 11: Power-Up/Wake-Up/Sleep FSM Diagram .......................................................................... 56 Figure 12: Power-up (Buck)................................................................................................................. 57 Figure 13: Wake-Up from hibernation (Buck) ...................................................................................... 57 Figure 14: Wake-Up (Buck) ................................................................................................................. 58 Figure 15: Power-Up (Boost) ............................................................................................................... 58 Figure 16: Wake-Up from hibernation (Boost)..................................................................................... 59 Figure 17: Wake-Up from extended/deep sleep (Boost) ..................................................................... 59 Figure 18: Go-to-Sleep and Bandgap Refresh .................................................................................... 59 Figure 19: OTP Layout Scheme .......................................................................................................... 60 Figure 20: BootROM Sequence .......................................................................................................... 65 Figure 21: Reset Block Diagram ......................................................................................................... 67 Figure 22: POR Timing Diagram ......................................................................................................... 70 Figure 23: Arm Cortex-M0+ Block Diagram ........................................................................................ 71 Figure 24: AMBA Bus Architecture and Power Domains .................................................................... 75 Figure 25: Memory Controller Block Diagram ..................................................................................... 79 Figure 26: Clock Tree Diagram ........................................................................................................... 81 Figure 27: Crystal Oscillator Circuits ................................................................................................... 83 Figure 28: XTAL32MHz Oscillator Frequency Trimming ..................................................................... 84 Figure 29: Automated Mechanism for XTAL32M Trim and Settling .................................................... 85 Figure 30: OTP Controller Block Diagram ........................................................................................... 87 Figure 31: DMA Controller Block Diagram .......................................................................................... 90 Figure 32: DMA Channel Diagram ...................................................................................................... 92 Figure 33: I2C Controller Block Diagram ............................................................................................. 95 Figure 34: Master/Slave and Transmitter/Receiver Relationships ...................................................... 96 Figure 35: Data Transfer on the I2C Bus ............................................................................................ 97 Figure 36: START and STOP Conditions ............................................................................................ 98 Figure 37: 7-bit Address Format .......................................................................................................... 99 Figure 38: 10-bit Address Format........................................................................................................ 99 Figure 39: Master-Transmitter Protocol ............................................................................................. 100 Figure 40: Master-Receiver Protocol ................................................................................................. 101 Figure 41: START BYTE Transfer ..................................................................................................... 101 Figure 42: Multiple Master Arbitration ............................................................................................... 102 Figure 43: Multiple Master Clock Synchronization ............................................................................ 103 Figure 44: UART Block Diagram ....................................................................................................... 105 Figure 45: Serial Data Format ........................................................................................................... 106 Figure 46: Receiver Serial Data Sampling Points ............................................................................. 106 Figure 47: Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode ................... 109 Figure 48: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode ... 110 Figure 49: SPI Block Diagram ........................................................................................................... 112 Figure 50: SPI Slave Mode Timing (CPOL = 0, CPHA = 0) .............................................................. 113 Figure 51: Quadrature Decoder Block Diagram ................................................................................ 116 Figure 52: Moving Forward on Axis X ............................................................................................... 117 Datasheet Revision 3.0 12-Mar-2020 CFR0011-120-00 9 of 374 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Figure 53: Moving Backwards on Axis X ........................................................................................... 117 Figure 54: Digital Filtering and Edge Detection Circuit ..................................................................... 117 Figure 55: Clockless Wakeup Controller Circuit ................................................................................ 119 Figure 56: Clocked Wakeup Controller Block Diagram ..................................................................... 121 Figure 57: Event Counter State Machine for the Wakeup Interrupt Generator ................................. 122 Figure 58: Timer 0 Block Diagram ..................................................................................................... 124 Figure 59: Timer 0 PWM Mode ......................................................................................................... 126 Figure 60: Timer 1 Block Diagram ..................................................................................................... 128 Figure 61: Timer 2 Block Diagram ..................................................................................................... 130 Figure 62: Timer 2 Timing Diagram ................................................................................................... 132 Figure 63: Watchdog Timer Block Diagram ...................................................................................... 133 Figure 64: Temperature Sensor Behavior ......................................................................................... 135 Figure 65: Keyboard Controller Block Diagram ................................................................................. 138 Figure 66: Keyboard Scanner State Machine ................................................................................... 139 Figure 67: GPIO Interrupt Generator State Machine ........................................................................ 140 Figure 68: Port P0 with Programmable Pin Assignment and driving strength .................................. 141 Figure 69: Type A GPIO Pad - GPIO with Schmitt Trigger on Input ................................................. 143 Figure 70: Type B GPIO Pad - GPIO with Schmitt Trigger and RC Filter on Input ........................... 144 Figure 71: Block Diagram of GPADC ................................................................................................ 145 Figure 72: GPADC Operation Flow Diagram .................................................................................... 147 Figure 73: Real Time Clock Block Diagram ...................................................................................... 153 Figure 74: DCDC Block Diagram - Buck Configuration ..................................................................... 155 Figure 75: DCDC Block Diagram - Boost Configuration ................................................................... 155 Figure 76: DCDC Efficiency in Buck Configuration ........................................................................... 156 Figure 77: DCDC Efficiency in Boost Configuration .......................................................................... 157 Figure 78: BLE Core Block Diagram ................................................................................................. 158 Figure 79: Entering BLE Deep Sleep mode ...................................................................................... 160 Figure 80: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom In) ....................................... 161 Figure 81: Exit BLE Deep Sleep Mode after Predetermined Time (Zoom In) ................................... 161 Figure 82: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom Out) .................................... 161 Figure 83: Exit BLE Deep Sleep Mode Due to External Event ......................................................... 162 Figure 84: Bluetooth Radio Block Diagram ....................................................................................... 163 Figure 85: WLCSP17 Package Outline Drawing ............................................................................... 371 Figure 86: FCGQFN24 Package Outline Drawing ............................................................................ 372 Tables Table 1: DA14531 WLCSP17 Ball Description.................................................................................... 21 Table 2: DA14531 FCGQFN24 Pin Description .................................................................................. 24 Table 3: Absolute Maximum Ratings ................................................................................................... 30 Table 4: Recommended Operating Conditions ................................................................................... 30 Table 5: DC Characteristics................................................................................................................. 31 Table 6: Timing Characteristics ........................................................................................................... 33 Table 7: RCX Oscillator - Timing Characteristics ................................................................................ 33 Table 8: XTAL32MHz Oscillator - Recommended Operating Conditions ........................................... 34 Table 9: XTAL oscillator 32kHz - Recommended Operating Conditions ............................................ 34 Table 10: XTAL oscillator 32kHz - Timing Characteristics .................................................................. 35 Table 11: RC32MHz Oscillaor - Timing Characteristics ...................................................................... 35 Table 12: DCDC Converter - Recommended Operating Conditions................................................... 35 Table 13: DCDC Converter - DC Characteristics ................................................................................ 36 Table 14: LDO_LOW - Recommended Operating Conditions ............................................................ 36 Table 15: LDO_LOW - DC Characteristics.......................................................................................... 37 Table 16: Digital Pad - Recommended Operating Conditions ............................................................ 37 Table 17: Digital Pad - DC Characteristics .......................................................................................... 38 Table 18: Digital Pad with LPF - DC Characteristics ........................................................................... 38 Table 19: Digital Pad with LPF - Recommended Operating Conditions ............................................. 39 Datasheet Revision 3.0 12-Mar-2020 CFR0011-120-00 10 of 374 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 20: POR VBAT_LOW - DC Characteristics ............................................................................... 39 Table 21: POR VBAT_HIGH - DC Characteristics .............................................................................. 39 Table 22: GP ADC - Recommended Operating Conditions ................................................................ 39 Table 23: GP ADC - DC Characteristics ............................................................................................. 39 Table 24: GP ADC - Electrical performance........................................................................................ 40 Table 25: Temperature Sensor - DC Characteristics .......................................................................... 41 Table 26: BLE 1Mb/s specifications - Recommended Operating Conditions ..................................... 41 Table 27: BLE 1Mb/s specifications - AC Characteristics ................................................................... 41 Table 28: BLE 1Mb/s specifications - Timing Characteristics ............................................................. 44 Table 29: BLE 1Mb/s specifications - DC Characteristics ................................................................... 44 Table 30: Power Domains Description ................................................................................................ 50 Table 31: Power Modes, Digital Power Domains, Clocks, and Wake-up triggers .............................. 51 Table 32: Power Rails Drivers and Voltages ....................................................................................... 52 Table 33: VDD_Clamp recommended settings over temperature and load ....................................... 53 Table 34: Retainable Registers ........................................................................................................... 53 Table 35: OTP Header ........................................................................................................................ 60 Table 36: CS Commands and Description .......................................................................................... 62 Table 37: CS Example......................................................................................................................... 63 Table 38: Booting Sequence Steps ..................................................................................................... 66 Table 39: Reset Signals and Registers ............................................................................................... 68 Table 40: Interrupt List ......................................................................................................................... 72 Table 41: Arm Documents List ............................................................................................................ 74 Table 42: Memory Map........................................................................................................................ 77 Table 43: Generated Clocks Description ............................................................................................. 82 Table 44: DMA Served Peripherals ..................................................................................................... 91 Table 45: I2C Definition of Bits in First Byte in 10-bit Address Format ............................................... 99 Table 46: UART Baud Rate Generation ............................................................................................ 107 Table 47: UART Interrupt Priorities ................................................................................................... 108 Table 48: SPI Modes Configuration and SCK States ........................................................................ 113 Table 49: SPI Timing Parameters ..................................................................................................... 114 Table 50: Fixed Assignment of Specific Signals ............................................................................... 142 Table 51: ADC Input Channels .......................................................................................................... 146 Table 52: GPADC External Input Channels and Voltage Range ...................................................... 146 Table 53: ADC_LDO Start-Up Delay ................................................................................................. 148 Table 54: ADC Sampling Time Constant (τADC_SMPL) ......................................................................... 149 Table 55: ENOB in Oversampling Mode ........................................................................................... 150 Table 56: GPADC Calibration Procedure for Single-Ended and Differential Modes......................... 151 Table 57: Common Mode Adjustment ............................................................................................... 152 Table 58: Register map anamisc2632_bif_00 ................................................................................... 165 Table 59: CLK_REF_SEL_REG (0x50001600) ................................................................................ 165 Table 60: CLK_REF_CNT_REG (0x50001602) ................................................................................ 166 Table 61: CLK_REF_VAL_L_REG (0x50001604) ............................................................................ 166 Table 62: CLK_REF_VAL_H_REG (0x50001606) ............................................................................ 166 Table 63: Register map BLE ............................................................................................................. 167 Table 64: BLE_RWBLECNTL_REG (0x40000000) .......................................................................... 169 Table 65: BLE_VERSION_REG (0x40000004) ................................................................................ 171 Table 66: BLE_RWBLECONF_REG (0x40000008) ......................................................................... 171 Table 67: BLE_INTCNTL_REG (0x4000000C) ................................................................................. 171 Table 68: BLE_INTSTAT_REG (0x40000010).................................................................................. 172 Table 69: BLE_INTRAWSTAT_REG (0x40000014) ......................................................................... 173 Table 70: BLE_INTACK_REG (0x40000018) ................................................................................... 174 Table 71: BLE_BASETIMECNT_REG (0x4000001C) ...................................................................... 175 Table 72: BLE_FINETIMECNT_REG (0x40000020) ........................................................................ 175 Table 73: BLE_BDADDRL_REG (0x40000024) ............................................................................... 176 Table 74: BLE_BDADDRU_REG (0x40000028) ............................................................................... 176 Table 75: BLE_CURRENTRXDESCPTR_REG (0x4000002C) ........................................................ 176 Table 76: BLE_DEEPSLCNTL_REG (0x40000030) ......................................................................... 176 Table 77: BLE_DEEPSLWKUP_REG (0x40000034) ....................................................................... 177 Datasheet CFR0011-120-00 Revision 3.0 11 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 78: BLE_DEEPSLSTAT_REG (0x40000038) ......................................................................... 177 Table 79: BLE_ENBPRESET_REG (0x4000003C) .......................................................................... 177 Table 80: BLE_FINECNTCORR_REG (0x40000040) ...................................................................... 178 Table 81: BLE_BASETIMECNTCORR_REG (0x40000044) ............................................................ 178 Table 82: BLE_DIAGCNTL_REG (0x40000050) .............................................................................. 178 Table 83: BLE_DIAGSTAT_REG (0x40000054)............................................................................... 179 Table 84: BLE_DEBUGADDMAX_REG (0x40000058) .................................................................... 179 Table 85: BLE_DEBUGADDMIN_REG (0x4000005C) ..................................................................... 179 Table 86: BLE_ERRORTYPESTAT_REG (0x40000060) ................................................................. 180 Table 87: BLE_SWPROFILING_REG (0x40000064) ....................................................................... 182 Table 88: BLE_RADIOCNTL1_REG (0x40000074) .......................................................................... 182 Table 89: BLE_RADIOPWRUPDN_REG (0x40000080) .................................................................. 182 Table 90: BLE_ADVCHMAP_REG (0x40000090) ............................................................................ 183 Table 91: BLE_ADVTIM_REG (0x400000A0)................................................................................... 183 Table 92: BLE_ACTSCANSTAT_REG (0x400000A4) ...................................................................... 183 Table 93: BLE_WLPUBADDPTR_REG (0x400000B0) .................................................................... 183 Table 94: BLE_WLPRIVADDPTR_REG (0x400000B4) ................................................................... 184 Table 95: BLE_WLNBDEV_REG (0x400000B8) .............................................................................. 184 Table 96: BLE_AESCNTL_REG (0x400000C0) ............................................................................... 184 Table 97: BLE_AESKEY31_0_REG (0x400000C4) ......................................................................... 184 Table 98: BLE_AESKEY63_32_REG (0x400000C8) ....................................................................... 184 Table 99: BLE_AESKEY95_64_REG (0x400000CC) ....................................................................... 184 Table 100: BLE_AESKEY127_96_REG (0x400000D0) ................................................................... 185 Table 101: BLE_AESPTR_REG (0x400000D4) ............................................................................... 185 Table 102: BLE_TXMICVAL_REG (0x400000D8) ............................................................................ 185 Table 103: BLE_RXMICVAL_REG (0x400000DC) ........................................................................... 185 Table 104: BLE_RFTESTCNTL_REG (0x400000E0) ....................................................................... 185 Table 105: BLE_RFTESTTXSTAT_REG (0x400000E4) .................................................................. 186 Table 106: BLE_RFTESTRXSTAT_REG (0x400000E8) .................................................................. 186 Table 107: BLE_TIMGENCNTL_REG (0x400000F0) ....................................................................... 187 Table 108: BLE_GROSSTIMTGT_REG (0x400000F4) .................................................................... 187 Table 109: BLE_FINETIMTGT_REG (0x400000F8) ......................................................................... 187 Table 110: BLE_SAMPLECLK_REG (0x400000FC) ........................................................................ 187 Table 111: BLE_COEXIFCNTL0_REG (0x40000100) ...................................................................... 188 Table 112: BLE_COEXIFCNTL1_REG (0x40000104) ...................................................................... 188 Table 113: BLE_BLEMPRIO0_REG (0x40000108) .......................................................................... 189 Table 114: BLE_BLEMPRIO1_REG (0x4000010C) ......................................................................... 189 Table 115: BLE_CNTL2_REG (0x40000200) ................................................................................... 190 Table 116: BLE_EM_BASE_REG (0x40000208) ............................................................................. 192 Table 117: BLE_DIAGCNTL2_REG (0x4000020C) .......................................................................... 192 Table 118: BLE_DIAGCNTL3_REG (0x40000210) .......................................................................... 193 Table 119: Register map CRG .......................................................................................................... 194 Table 120: CLK_AMBA_REG (0x50000000) .................................................................................... 194 Table 121: CLK_FREQ_TRIM_REG (0x50000002) ......................................................................... 195 Table 122: CLK_PER_REG (0x50000004) ....................................................................................... 195 Table 123: CLK_RADIO_REG (0x50000008) ................................................................................... 196 Table 124: CLK_CTRL_REG (0x5000000A)..................................................................................... 196 Table 125: PMU_CTRL_REG (0x50000010) .................................................................................... 197 Table 126: SYS_CTRL_REG (0x50000012) ..................................................................................... 197 Table 127: SYS_STAT_REG (0x50000014) ..................................................................................... 198 Table 128: TRIM_CTRL_REG (0x50000016) ................................................................................... 199 Table 129: RAM_PWR_CTRL_REG (0x50000018) ......................................................................... 199 Table 130: CLK_RC32K_REG (0x50000020) ................................................................................... 200 Table 131: CLK_XTAL32K_REG (0x50000022) ............................................................................... 200 Table 132: CLK_RC32M_REG (0x50000024) .................................................................................. 200 Table 133: CLK_RCX_REG (0x50000026) ....................................................................................... 201 Table 134: BANDGAP_REG (0x50000028) ...................................................................................... 201 Table 135: ANA_STATUS_REG (0x5000002A) ............................................................................... 201 Datasheet CFR0011-120-00 Revision 3.0 12 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 136: XTAL32M_START_REG (0x50000030) ......................................................................... 202 Table 137: XTALRDY_CTRL_REG (0x50000034) ........................................................................... 202 Table 138: XTAL32M_CTRL0_REG (0x50000038) .......................................................................... 203 Table 139: POR_PIN_REG (0x50000040)........................................................................................ 203 Table 140: POR_TIMER_REG (0x50000042) .................................................................................. 203 Table 141: PMU_SLEEP_REG (0x50000050) .................................................................................. 204 Table 142: POWER_CTRL_REG (0x50000052) .............................................................................. 204 Table 143: POWER_LEVEL_REG (0x50000054) ............................................................................ 205 Table 144: XTAL32M_TRSTAT_REG (0x50000032) ....................................................................... 205 Table 145: Register map crg2632_preg_tim_00 ............................................................................... 206 Table 146: CLK_RTCDIV_REG (0x5000424C) ................................................................................ 206 Table 147: Register map crg2632_dcdc_dig_00 .............................................................................. 207 Table 148: DCDC_CTRL_REG (0x50000080).................................................................................. 207 Table 149: Register map DMA .......................................................................................................... 209 Table 150: DMA0_A_STARTL_REG (0x50003600) ......................................................................... 210 Table 151: DMA0_A_STARTH_REG (0x50003602) ........................................................................ 210 Table 152: DMA0_B_STARTL_REG (0x50003604) ......................................................................... 210 Table 153: DMA0_B_STARTH_REG (0x50003606) ........................................................................ 210 Table 154: DMA0_INT_REG (0x50003608) ...................................................................................... 211 Table 155: DMA0_LEN_REG (0x5000360A) .................................................................................... 211 Table 156: DMA0_CTRL_REG (0x5000360C) ................................................................................. 211 Table 157: DMA0_IDX_REG (0x5000360E) ..................................................................................... 213 Table 158: DMA1_A_STARTL_REG (0x50003610) ......................................................................... 213 Table 159: DMA1_A_STARTH_REG (0x50003612) ........................................................................ 213 Table 160: DMA1_B_STARTL_REG (0x50003614) ......................................................................... 213 Table 161: DMA1_B_STARTH_REG (0x50003616) ........................................................................ 213 Table 162: DMA1_INT_REG (0x50003618) ...................................................................................... 213 Table 163: DMA1_LEN_REG (0x5000361A) .................................................................................... 214 Table 164: DMA1_CTRL_REG (0x5000361C) ................................................................................. 214 Table 165: DMA1_IDX_REG (0x5000361E) ..................................................................................... 216 Table 166: DMA2_A_STARTL_REG (0x50003620) ......................................................................... 216 Table 167: DMA2_A_STARTH_REG (0x50003622) ........................................................................ 216 Table 168: DMA2_B_STARTL_REG (0x50003624) ......................................................................... 216 Table 169: DMA2_B_STARTH_REG (0x50003626) ........................................................................ 216 Table 170: DMA2_INT_REG (0x50003628) ...................................................................................... 216 Table 171: DMA2_LEN_REG (0x5000362A) .................................................................................... 217 Table 172: DMA2_CTRL_REG (0x5000362C) ................................................................................. 217 Table 173: DMA2_IDX_REG (0x5000362E) ..................................................................................... 218 Table 174: DMA3_A_STARTL_REG (0x50003630) ......................................................................... 218 Table 175: DMA3_A_STARTH_REG (0x50003632) ........................................................................ 219 Table 176: DMA3_B_STARTL_REG (0x50003634) ......................................................................... 219 Table 177: DMA3_B_STARTH_REG (0x50003636) ........................................................................ 219 Table 178: DMA3_INT_REG (0x50003638) ...................................................................................... 219 Table 179: DMA3_LEN_REG (0x5000363A) .................................................................................... 219 Table 180: DMA3_CTRL_REG (0x5000363C) ................................................................................. 219 Table 181: DMA3_IDX_REG (0x5000363E) ..................................................................................... 221 Table 182: DMA_REQ_MUX_REG (0x50003680) ........................................................................... 221 Table 183: DMA_INT_STATUS_REG (0x50003682) ....................................................................... 222 Table 184: DMA_CLEAR_INT_REG (0x50003684) ......................................................................... 223 Table 185: Register map GPADC ..................................................................................................... 224 Table 186: GP_ADC_CTRL_REG (0x50001500) ............................................................................. 224 Table 187: GP_ADC_CTRL2_REG (0x50001502) ........................................................................... 225 Table 188: GP_ADC_CTRL3_REG (0x50001504) ........................................................................... 226 Table 189: GP_ADC_OFFP_REG (0x50001508) ............................................................................. 226 Table 190: GP_ADC_OFFN_REG (0x5000150A) ............................................................................ 226 Table 191: GP_ADC_TRIM_REG (0x5000150C) ............................................................................. 227 Table 192: GP_ADC_CLEAR_INT_REG (0x5000150E) .................................................................. 227 Table 193: GP_ADC_RESULT_REG (0x50001510) ........................................................................ 227 Datasheet CFR0011-120-00 Revision 3.0 13 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 194: GP_ADC_SEL_REG (0x50001506) ................................................................................ 227 Table 195: Register map GPIO ......................................................................................................... 229 Table 196: P0_DATA_REG (0x50003000) ....................................................................................... 229 Table 197: P0_SET_DATA_REG (0x50003002) .............................................................................. 229 Table 198: P0_RESET_DATA_REG (0x50003004) ......................................................................... 230 Table 199: P00_MODE_REG (0x50003006) .................................................................................... 230 Table 200: P01_MODE_REG (0x50003008) .................................................................................... 231 Table 201: P02_MODE_REG (0x5000300A) .................................................................................... 232 Table 202: P03_MODE_REG (0x5000300C).................................................................................... 232 Table 203: P04_MODE_REG (0x5000300E) .................................................................................... 232 Table 204: P05_MODE_REG (0x50003010) .................................................................................... 233 Table 205: P06_MODE_REG (0x50003012) .................................................................................... 233 Table 206: P07_MODE_REG (0x50003014) .................................................................................... 233 Table 207: P08_MODE_REG (0x50003016) .................................................................................... 234 Table 208: P09_MODE_REG (0x50003018) .................................................................................... 234 Table 209: P010_MODE_REG (0x5000301A) .................................................................................. 234 Table 210: P011_MODE_REG (0x5000301C) ................................................................................. 234 Table 211: PAD_WEAK_CTRL_REG (0x5000301E) ....................................................................... 235 Table 212: Register map GPREG ..................................................................................................... 236 Table 213: SET_FREEZE_REG (0x50003300) ................................................................................ 236 Table 214: RESET_FREEZE_REG (0x50003302) ........................................................................... 236 Table 215: DEBUG_REG (0x50003304) ........................................................................................... 237 Table 216: GP_STATUS_REG (0x50003306) .................................................................................. 237 Table 217: GP_CONTROL_REG (0x50003308)............................................................................... 237 Table 218: BLE_TIMER_REG (0x5000330A) ................................................................................... 237 Table 219: Register map I2C............................................................................................................. 239 Table 220: I2C_CON_REG (0x50001300) ........................................................................................ 240 Table 221: I2C_TAR_REG (0x50001304) ......................................................................................... 241 Table 222: I2C_SAR_REG (0x50001308) ........................................................................................ 242 Table 223: I2C_DATA_CMD_REG (0x50001310) ............................................................................ 242 Table 224: I2C_SS_SCL_HCNT_REG (0x50001314) ...................................................................... 244 Table 225: I2C_SS_SCL_LCNT_REG (0x50001318) ...................................................................... 244 Table 226: I2C_FS_SCL_HCNT_REG (0x5000131C) ..................................................................... 244 Table 227: I2C_FS_SCL_LCNT_REG (0x50001320) ....................................................................... 245 Table 228: I2C_INTR_STAT_REG (0x5000132C) ........................................................................... 245 Table 229: I2C_INTR_MASK_REG (0x50001330) ........................................................................... 247 Table 230: I2C_RAW_INTR_STAT_REG (0x50001334) .................................................................. 247 Table 231: I2C_RX_TL_REG (0x50001338)..................................................................................... 249 Table 232: I2C_TX_TL_REG (0x5000133C) .................................................................................... 250 Table 233: I2C_CLR_INTR_REG (0x50001340) .............................................................................. 250 Table 234: I2C_CLR_RX_UNDER_REG (0x50001344) ................................................................... 250 Table 235: I2C_CLR_RX_OVER_REG (0x50001348) ..................................................................... 250 Table 236: I2C_CLR_TX_OVER_REG (0x5000134C) ..................................................................... 251 Table 237: I2C_CLR_RD_REQ_REG (0x50001350) ....................................................................... 251 Table 238: I2C_CLR_TX_ABRT_REG (0x50001354) ...................................................................... 251 Table 239: I2C_CLR_RX_DONE_REG (0x50001358) ..................................................................... 251 Table 240: I2C_CLR_ACTIVITY_REG (0x5000135C) ...................................................................... 251 Table 241: I2C_CLR_STOP_DET_REG (0x50001360) ................................................................... 252 Table 242: I2C_CLR_START_DET_REG (0x50001364) ................................................................. 252 Table 243: I2C_CLR_GEN_CALL_REG (0x50001368) .................................................................... 252 Table 244: I2C_ENABLE_REG (0x5000136C) ................................................................................. 252 Table 245: I2C_STATUS_REG (0x50001370).................................................................................. 253 Table 246: I2C_TXFLR_REG (0x50001374) .................................................................................... 254 Table 247: I2C_RXFLR_REG (0x50001378) .................................................................................... 254 Table 248: I2C_SDA_HOLD_REG (0x5000137C) ............................................................................ 254 Table 249: I2C_TX_ABRT_SOURCE_REG (0x50001380) .............................................................. 255 Table 250: I2C_DMA_CR_REG (0x50001388)................................................................................. 256 Table 251: I2C_DMA_TDLR_REG (0x5000138C) ............................................................................ 256 Datasheet CFR0011-120-00 Revision 3.0 14 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 252: I2C_DMA_RDLR_REG (0x50001390) ............................................................................ 257 Table 253: I2C_SDA_SETUP_REG (0x50001394) .......................................................................... 257 Table 254: I2C_ACK_GENERAL_CALL_REG (0x50001398) .......................................................... 257 Table 255: I2C_ENABLE_STATUS_REG (0x5000139C) ................................................................. 257 Table 256: I2C_IC_FS_SPKLEN_REG (0x500013A0) ..................................................................... 259 Table 257: Register map KBRD ........................................................................................................ 260 Table 258: GPIO_IRQ0_IN_SEL_REG (0x50001400) ..................................................................... 260 Table 259: GPIO_IRQ1_IN_SEL_REG (0x50001402) ..................................................................... 261 Table 260: GPIO_IRQ2_IN_SEL_REG (0x50001404) ..................................................................... 261 Table 261: GPIO_IRQ3_IN_SEL_REG (0x50001406) ..................................................................... 261 Table 262: GPIO_IRQ4_IN_SEL_REG (0x50001408) ..................................................................... 261 Table 263: GPIO_DEBOUNCE_REG (0x5000140C) ....................................................................... 261 Table 264: GPIO_RESET_IRQ_REG (0x5000140E) ....................................................................... 262 Table 265: GPIO_INT_LEVEL_CTRL_REG (0x50001410) .............................................................. 262 Table 266: KBRD_IRQ_IN_SEL0_REG (0x50001412) .................................................................... 262 Table 267: KBRD_CTRL_REG (0x50001414) .................................................................................. 263 Table 268: Register map crg2632_preg_aon_00 .............................................................................. 264 Table 269: HWR_CTRL_REG (0x50000300) ................................................................................... 264 Table 270: RESET_STAT_REG (0x50000304) ................................................................................ 264 Table 271: RAM_LPMX_REG (0x50000308).................................................................................... 264 Table 272: PAD_LATCH_REG (0x5000030C).................................................................................. 265 Table 273: HIBERN_CTRL_REG (0x50000310) .............................................................................. 265 Table 274: POWER_AON_CTRL_REG (0x50000320) .................................................................... 265 Table 275: GP_DATA_REG (0x50000324)....................................................................................... 266 Table 276: Register map OTPC ........................................................................................................ 267 Table 277: OTPC_MODE_REG (0x07F40000) ................................................................................ 267 Table 278: OTPC_STAT_REG (0x07F40004) .................................................................................. 268 Table 279: OTPC_PADDR_REG (0x07F40008) .............................................................................. 269 Table 280: OTPC_PWORD_REG (0x07F4000C) ............................................................................. 270 Table 281: OTPC_TIM1_REG (0x07F40010) ................................................................................... 270 Table 282: OTPC_TIM2_REG (0x07F40014) ................................................................................... 271 Table 283: OTPC_AHBADR_REG (0x07F40018) ............................................................................ 272 Table 284: OTPC_CELADR_REG (0x07F4001C) ............................................................................ 272 Table 285: OTPC_NWORDS_REG (0x07F40020) ........................................................................... 273 Table 286: Register map QDEC ........................................................................................................ 274 Table 287: QDEC_CTRL_REG (0x50000200).................................................................................. 274 Table 288: QDEC_XCNT_REG (0x50000202) ................................................................................. 274 Table 289: QDEC_YCNT_REG (0x50000204) ................................................................................. 274 Table 290: QDEC_CLOCKDIV_REG (0x50000206) ........................................................................ 275 Table 291: QDEC_CTRL2_REG (0x50000208)................................................................................ 275 Table 292: QDEC_ZCNT_REG (0x5000020A) ................................................................................. 276 Table 293: QDEC_EVENT_CNT_REG (0x5000020C) ..................................................................... 276 Table 294: Register map rtc2632_00 ................................................................................................ 277 Table 295: RTC_CONTROL_REG (0x50004100) ............................................................................ 277 Table 296: RTC_HOUR_MODE_REG (0x50004104) ...................................................................... 277 Table 297: RTC_TIME_REG (0x50004108) ..................................................................................... 278 Table 298: RTC_CALENDAR_REG (0x5000410C) .......................................................................... 278 Table 299: RTC_TIME_ALARM_REG (0x50004110) ....................................................................... 278 Table 300: RTC_CALENDAR_ALARM_REG (0x50004114) ............................................................ 279 Table 301: RTC_ALARM_ENABLE_REG (0x50004118) ................................................................. 279 Table 302: RTC_EVENT_FLAGS_REG (0x5000411C) ................................................................... 280 Table 303: RTC_INTERRUPT_ENABLE_REG (0x50004120) ......................................................... 280 Table 304: RTC_INTERRUPT_DISABLE_REG (0x50004124) ........................................................ 281 Table 305: RTC_INTERRUPT_MASK_REG (0x50004128) ............................................................. 281 Table 306: RTC_STATUS_REG (0x5000412C) ............................................................................... 282 Table 307: RTC_KEEP_RTC_REG (0x50004130) ........................................................................... 282 Table 308: Register map SPI ............................................................................................................ 283 Table 309: SPI_CTRL_REG (0x50001200) ...................................................................................... 283 Datasheet CFR0011-120-00 Revision 3.0 15 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 310: SPI_CONFIG_REG (0x50001204).................................................................................. 284 Table 311: SPI_CLOCK_REG (0x50001208) ................................................................................... 284 Table 312: SPI_FIFO_CONFIG_REG (0x5000120C) ....................................................................... 285 Table 313: SPI_IRQ_MASK_REG (0x50001210) ............................................................................. 285 Table 314: SPI_STATUS_REG (0x50001214) ................................................................................. 285 Table 315: SPI_FIFO_STATUS_REG (0x50001218) ....................................................................... 286 Table 316: SPI_FIFO_READ_REG (0x5000121C) ........................................................................... 286 Table 317: SPI_FIFO_WRITE_REG (0x50001220) .......................................................................... 286 Table 318: SPI_CS_CONFIG_REG (0x50001224) .......................................................................... 286 Table 319: SPI_FIFO_HIGH_REG (0x50001228) ............................................................................ 287 Table 320: SPI_TXBUFFER_FORCE_L_REG (0x5000122C) ......................................................... 287 Table 321: SPI_TXBUFFER_FORCE_H_REG (0x50001230) ......................................................... 287 Table 322: Register map Timer+3PWM ............................................................................................ 288 Table 323: TIMER0_CTRL_REG (0x50003400) ............................................................................... 288 Table 324: TIMER0_ON_REG (0x50003402) ................................................................................... 289 Table 325: TIMER0_RELOAD_M_REG (0x50003404) .................................................................... 289 Table 326: TIMER0_RELOAD_N_REG (0x50003406) ..................................................................... 289 Table 327: TRIPLE_PWM_FREQUENCY (0x50003408) ................................................................. 289 Table 328: PWM2_START_CYCLE (0x5000340A) .......................................................................... 290 Table 329: PWM3_START_CYCLE (0x5000340C) .......................................................................... 290 Table 330: PWM4_START_CYCLE (0x5000340E) .......................................................................... 290 Table 331: PWM5_START_CYCLE (0x50003410) .......................................................................... 290 Table 332: PWM6_START_CYCLE (0x50003412) .......................................................................... 290 Table 333: PWM7_START_CYCLE (0x50003414) .......................................................................... 290 Table 334: PWM2_END_CYCLE (0x50003416) ............................................................................... 291 Table 335: PWM3_END_CYCLE (0x50003418) ............................................................................... 291 Table 336: PWM4_END_CYCLE (0x5000341A) .............................................................................. 291 Table 337: PWM5_END_CYCLE (0x5000341C) .............................................................................. 291 Table 338: PWM6_END_CYCLE (0x5000341E) .............................................................................. 291 Table 339: PWM7_END_CYCLE (0x50003420) ............................................................................... 291 Table 340: TRIPLE_PWM_CTRL_REG (0x50003422) .................................................................... 292 Table 341: Register map Timer1 ....................................................................................................... 293 Table 342: TIMER1_CTRL_REG (0x50004000) ............................................................................... 293 Table 343: TIMER1_CAPTURE_REG (0x50004004) ....................................................................... 293 Table 344: TIMER1_STATUS_REG (0x50004008) .......................................................................... 294 Table 345: TIMER1_CAPCNT1_VALUE_REG (0x5000400C) ......................................................... 295 Table 346: TIMER1_CAPCNT2_VALUE_REG (0x50004010) ......................................................... 295 Table 347: TIMER1_CLR_EVENT_REG (0x50004014) ................................................................... 295 Table 348: Register map UART ........................................................................................................ 297 Table 349: UART_RBR_THR_DLL_REG (0x50001000) .................................................................. 300 Table 350: UART_IER_DLH_REG (0x50001004) ............................................................................ 300 Table 351: UART_IIR_FCR_REG (0x50001008).............................................................................. 302 Table 352: UART_LCR_REG (0x5000100C) .................................................................................... 304 Table 353: UART_MCR_REG (0x50001010) ................................................................................... 305 Table 354: UART_LSR_REG (0x50001014) ..................................................................................... 306 Table 355: UART_MSR_REG (0x50001018).................................................................................... 309 Table 356: UART_SCR_REG (0x5000101C) ................................................................................... 309 Table 357: UART_SRBR_STHR0_REG (0x50001030) .................................................................... 309 Table 358: UART_SRBR_STHR1_REG (0x50001034) .................................................................... 310 Table 359: UART_SRBR_STHR2_REG (0x50001038) .................................................................... 311 Table 360: UART_SRBR_STHR3_REG (0x5000103C) ................................................................... 312 Table 361: UART_SRBR_STHR4_REG (0x50001040) .................................................................... 313 Table 362: UART_SRBR_STHR5_REG (0x50001044) .................................................................... 314 Table 363: UART_SRBR_STHR6_REG (0x50001048) .................................................................... 315 Table 364: UART_SRBR_STHR7_REG (0x5000104C) ................................................................... 316 Table 365: UART_SRBR_STHR8_REG (0x50001050) .................................................................... 317 Table 366: UART_SRBR_STHR9_REG (0x50001054) .................................................................... 318 Table 367: UART_SRBR_STHR10_REG (0x50001058) .................................................................. 319 Datasheet CFR0011-120-00 Revision 3.0 16 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 368: UART_SRBR_STHR11_REG (0x5000105C) ................................................................. 320 Table 369: UART_SRBR_STHR12_REG (0x50001060) .................................................................. 321 Table 370: UART_SRBR_STHR13_REG (0x50001064) .................................................................. 322 Table 371: UART_SRBR_STHR14_REG (0x50001068) .................................................................. 323 Table 372: UART_SRBR_STHR15_REG (0x5000106C) ................................................................. 324 Table 373: UART_FAR_REG (0x50001070) .................................................................................... 325 Table 374: UART_USR_REG (0x5000107C) ................................................................................... 326 Table 375: UART_TFL_REG (0x50001080) ..................................................................................... 327 Table 376: UART_RFL_REG (0x50001084) ..................................................................................... 327 Table 377: UART_SRR_REG (0x50001088) .................................................................................... 327 Table 378: UART_SRTS_REG (0x5000108C) ................................................................................. 327 Table 379: UART_SBCR_REG (0x50001090).................................................................................. 328 Table 380: UART_SDMAM_REG (0x50001094) .............................................................................. 328 Table 381: UART_SFE_REG (0x50001098)..................................................................................... 329 Table 382: UART_SRT_REG (0x5000109C) .................................................................................... 329 Table 383: UART_STET_REG (0x500010A0) .................................................................................. 330 Table 384: UART_HTX_REG (0x500010A4) .................................................................................... 330 Table 385: UART_DMASA_REG (0x500010A8) .............................................................................. 330 Table 386: UART_DLF_REG (0x500010C0) .................................................................................... 331 Table 387: UART_UCV_REG (0x500010F8) .................................................................................... 331 Table 388: UART_UCV_HIGH_REG (0x500010FA) ........................................................................ 331 Table 389: UART_CTR_REG (0x500010FC) ................................................................................... 331 Table 390: UART_CTR_HIGH_REG (0x500010FE) ........................................................................ 331 Table 391: UART2_RBR_THR_DLL_REG (0x50001100) ................................................................ 331 Table 392: UART2_IER_DLH_REG (0x50001104) .......................................................................... 332 Table 393: UART2_IIR_FCR_REG (0x50001108) ........................................................................... 334 Table 394: UART2_LCR_REG (0x5000110C) .................................................................................. 336 Table 395: UART2_MCR_REG (0x50001110) ................................................................................. 337 Table 396: UART2_LSR_REG (0x50001114)................................................................................... 338 Table 397: UART2_SCR_REG (0x5000111C) ................................................................................. 340 Table 398: UART2_SRBR_STHR0_REG (0x50001130) .................................................................. 341 Table 399: UART2_SRBR_STHR1_REG (0x50001134) .................................................................. 341 Table 400: UART2_SRBR_STHR2_REG (0x50001138) .................................................................. 342 Table 401: UART2_SRBR_STHR3_REG (0x5000113C) ................................................................. 343 Table 402: UART2_SRBR_STHR4_REG (0x50001140) .................................................................. 344 Table 403: UART2_SRBR_STHR5_REG (0x50001144) .................................................................. 345 Table 404: UART2_SRBR_STHR6_REG (0x50001148) .................................................................. 346 Table 405: UART2_SRBR_STHR7_REG (0x5000114C) ................................................................. 347 Table 406: UART2_SRBR_STHR8_REG (0x50001150) .................................................................. 348 Table 407: UART2_SRBR_STHR9_REG (0x50001154) .................................................................. 349 Table 408: UART2_SRBR_STHR10_REG (0x50001158)................................................................ 350 Table 409: UART2_SRBR_STHR11_REG (0x5000115C) ............................................................... 351 Table 410: UART2_SRBR_STHR12_REG (0x50001160) ................................................................ 352 Table 411: UART2_SRBR_STHR13_REG (0x50001164) ................................................................ 353 Table 412: UART2_SRBR_STHR14_REG (0x50001168) ................................................................ 354 Table 413: UART2_SRBR_STHR15_REG (0x5000116C) ............................................................... 355 Table 414: UART2_FAR_REG (0x50001170) .................................................................................. 356 Table 415: UART2_USR_REG (0x5000117C) ................................................................................. 357 Table 416: UART2_TFL_REG (0x50001180) ................................................................................... 358 Table 417: UART2_RFL_REG (0x50001184) ................................................................................... 358 Table 418: UART2_SRR_REG (0x50001188) .................................................................................. 358 Table 419: UART2_SBCR_REG (0x50001190)................................................................................ 358 Table 420: UART2_SDMAM_REG (0x50001194) ............................................................................ 359 Table 421: UART2_SFE_REG (0x50001198)................................................................................... 359 Table 422: UART2_SRT_REG (0x5000119C) .................................................................................. 360 Table 423: UART2_STET_REG (0x500011A0) ................................................................................ 360 Table 424: UART2_HTX_REG (0x500011A4) .................................................................................. 360 Table 425: UART2_DMASA_REG (0x500011A8) ............................................................................ 361 Datasheet CFR0011-120-00 Revision 3.0 17 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 426: UART2_DLF_REG (0x500011C0) .................................................................................. 361 Table 427: UART2_UCV_REG (0x500011F8) .................................................................................. 361 Table 428: UART2_UCV_HIGH_REG (0x500011FA) ...................................................................... 361 Table 429: UART2_CTR_REG (0x500011FC) ................................................................................. 361 Table 430: UART2_CTR_HIGH_REG (0x500011FE) ...................................................................... 362 Table 431: Register map Version ...................................................................................................... 363 Table 432: CHIP_ID1_REG (0x50003200) ....................................................................................... 363 Table 433: CHIP_ID2_REG (0x50003204) ....................................................................................... 363 Table 434: CHIP_ID3_REG (0x50003208) ....................................................................................... 363 Table 435: CHIP_ID4_REG (0x5000320C) ....................................................................................... 363 Table 436: Register map WKUP ....................................................................................................... 364 Table 437: WKUP_CTRL_REG (0x50000100) ................................................................................. 364 Table 438: WKUP_COMPARE_REG (0x50000102) ........................................................................ 365 Table 439: WKUP_IRQ_STATUS_REG (0x50000104) .................................................................... 365 Table 440: WKUP_COUNTER_REG (0x50000106) ......................................................................... 365 Table 441: WKUP_SELECT_GPIO_REG (0x50000108) ................................................................. 365 Table 442: WKUP2_SELECT_GPIO_REG (0x5000010A) ............................................................... 365 Table 443: WKUP_POL_GPIO_REG (0x5000010C) ........................................................................ 366 Table 444: WKUP2_POL_GPIO_REG (0x5000010E) ...................................................................... 366 Table 445: Register map WDOG ...................................................................................................... 367 Table 446: WATCHDOG_REG (0x50003100) .................................................................................. 367 Table 447: WATCHDOG_CTRL_REG (0x50003102) ...................................................................... 367 Table 448: Ordering Information (Samples) ...................................................................................... 369 Table 449: Ordering Information (Production) ................................................................................... 369 Table 450: MSL Classification ........................................................................................................... 370 Datasheet CFR0011-120-00 Revision 3.0 18 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 1 Block Diagram Arm Cortex-M0+ XTAL 32.768 kHz DCDC (BUCK/BOOST) XTAL 32 MHz LDO RET CORE LDO SYS CLAMP RC 32 MHz LDO LDO LDO SYS SYS RF RC 32/512 kHz RCX POR HIGH Temperature Sensor 24 April 2012 POR LOW SWD (JTAG) Bluetooth 5.1 Core 4-CH DMA ROM 144 KB KEYBOARD CTRL QUAD DECODER GP ADC I2C FIFO FIFO SPI UART2 UART Timer 2 6xPWM FIFO Timer 1 Capture FIFO OTPC CLOCKED WAKEUP CTRL DMA Timer 0 1xPWM CLOCK-LESS WAKEUP CTRL OTP 32 KB TIMERS Real Time Clock SysRAM3 20 KB POWER/CLOCK Management (PMU) SysRAM2 12 KB APB bridge Memory Controller SysRAM1 16 KB Radio Transceiver LINK LAYER HARDWARE AES-128 GPIO MULTIPLEXING Figure 2: DA14531 Block Diagram Datasheet CFR0011-120-00 Revision 3.0 19 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 2 Packages and Pinout The DA14531 comes in two packages: ● A Wafer Level Chip Scale Package (WLCSP) with 17 balls ● A Quad Flat Package No Leads (FCGQFN) with 24 pins The actual pin/ball assignment is depicted in the following sections. 2.1 WLCSP17 DA14531 1 A 2 3 RFIOP P0_3 XTAL32kp GNDRF2 D E 5 P0_4 XTAL32km RFIOM B C 4 GNDRF1 P0_2 XTAL32Mp P0_5 XTAL32Mm F VSS P0_1 RST P0_0 GND_DCDC G VBAT_LOW LX BAT_HIGH (Top view) Switching signal, high current No connection Static signal, high current, Static signal, low current, Analog signal Quiet ground Digital signal Noisy ground Figure 3: WLCSP17 Ball Assignment (Top View) Datasheet CFR0011-120-00 Revision 3.0 20 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 1: DA14531 WLCSP17 Ball Description Ball Pin Name no. Type Reset Description State General Purpose I/Os (Note 3) F4 E5 C5 B4 A5 D4 P0_0 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during powerdown. RST DIO (Type B) RST active high hardware reset (default). P0_1 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. ADC0 AI INPUT. Analog to Digital Converter input 0. SWDIO DIO INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. P0_2 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. ADC1 AI INPUT. Analog to Digital Converter input 1. SWCLK DIO INPUT JTAG clock signal (by default). P0_3 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Check GP_DATA_REG[P03_P04_FILT_DIS] for correct pad filter settings. XTAL32kp AI INPUT. Analog input of the XTAL32K crystal oscillator. DI INPUT. Digital input for an external clock (square wave). P0_4 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Check GP_DATA_REG[P03_P04_FILT_DIS] for correct pad filter settings. XTAL32km AO OUTPUT. Analog output of the XTAL32K crystal oscillator. P0_5 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Datasheet CFR0011-120-00 Revision 3.0 21 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Ball Pin Name no. SWDIO Type Reset Description State DIO INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication (by default). Debug Interface E5 D4 SWDIO DIO I-PD INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Mapped on P0_1 or P0_5 (P0_5 by default). C5 SWCLK DIO I-PD INPUT JTAG clock signal. Mapped on P0_2 (by default). Clocks D2 XTAL32Mp AI INPUT. Crystal input for the 32 MHz XTAL. E1 XTAL32Mm AO OUTPUT. Crystal output for the 32 MHz XTAL. B4 XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL. Mapped on P0_3. A5 XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL. Mapped on P0_4. QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports. QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports. QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports. QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports. QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports. QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports. SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports. SPI_DI DI INPUT. SPI Data input. Mapped on Px ports (Note 1). SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports (Note 2). SPI_EN DI/DO INPUT/OUTPUT. SPI Clock enable. Mapped on Px ports. SDA DIO/DIOD INPUT/OUTPUT. I2C bus data with open drain port. Mapped on Px ports. The mapped Px pin is automatically configured with a pull-up resistor (25KOhm) when pin x is mapped to the I2C_SDA PID function. SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port. In open drain mode, SCL is monitored to support bit stretching by a slave. Mapped on Px ports. The mapped Px pin is automatically configured with a pullup resistor (25KOhm) when pin x is mapped to the I2C_SCL PID function. Quadrature Decoder SPI Bus Interface I2C Bus Interface Datasheet CFR0011-120-00 Revision 3.0 22 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Ball Pin Name no. Type Reset Description State UART interface UTX DO OUTPUT. UART transmit data. Mapped on Px ports. URX DI INPUT. UART receive data. Mapped on Px ports. URTS DO OUTPUT. UART Request to Send. Mapped on Px ports. UCTS DI INPUT. UART Clear to Send. Mapped on Px ports. UTX2 DO OUTPUT. UART2 transmit data. Mapped on Px ports. URX2 DI INPUT. UART2 receive data. Mapped on Px ports. ADC IO Channels E5 ADC0 AI INPUT. Analog to Digital Converter input 0. Mapped on P0_1. C5 ADC1 AI INPUT. Analog to Digital Converter input 1. Mapped on P0_2. Radio Transceiver A1 RFIOp AIO RF input/output. Impedance 50 Ω A3 RFIOm AIO RF ground. C3 GND_RF1 AIO RF ground. C1 GND_RF2 AIO RF ground. Miscellaneous F4 RST DIO INPUT. Reset signal (active high). Mapped on P0_0 (by default). G3 LX AIO INPUT/OUTPUT. Connection for the external DC-DC converter inductor. Power and Ground E3 VSS AIO Digital ground. G5 VBAT_HIGH AIO INPUT/OUTPUT. Battery connection or DCDC output in BUCK/BOOST mode, respectively.IO-supply. G1 VBAT_LOW AIO INPUT/OUTPUT. Battery connection or DCDC output in BOOST/BUCK mode, respectively. System supply. F2 GND_DCDC AIO DCDC ground Note 1 Data input only. MOSI in SPI slave mode and MISO in SPI master mode. Note 2 Data output only. MISO in SPI slave mode and MOSI in SPI master mode. Note 3 The differences between Type A and Type B GPIO pads are presented in Types of GPIO Pads. Datasheet CFR0011-120-00 Revision 3.0 23 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 2.2 FCGQFN24 Figure 4: FCGQFN24 Pin Assignment (Top View) Table 2: DA14531 FCGQFN24 Pin Description Pin Pin Name no. Type Reset Description State General Purpose I/Os (Note 3) 10 11 P0_0 DIO (Type B) RST DIO (Type B) P0_1 DIO (Type B) ADC0 AI Datasheet CFR0011-120-00 I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. RST active high hardware reset (default). I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. INPUT. Analog to Digital Converter input 0. Revision 3.0 24 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Pin Pin Name no. Type Reset Description State 12 P0_2 DIO (Type B) I-PD ADC1 AI INPUT. Analog to Digital Converter input 1. SWCLK DIO INPUT JTAG clock signal (by default). P0_3 DIO (Type B) XTAL32kp AI INPUT. Analog input of the XTAL32K crystal oscillator. DI INPUT. Digital input for an external clock (square wave). 13 14 I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Check GP_DATA_REG[P03_P04_FILT_DIS] for correct pad filter settings. P0_4 DIO (Type B) XTAL32km AO 24 P0_5 DIO (Type B) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. 22 P0_6 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. ADC2 AI P0_7 DIO (Type A) ADC3 AI P0_8 DIO (Type A) 15 17 Datasheet CFR0011-120-00 I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Check GP_DATA_REG[P03_P04_FILT_DIS] for correct pad filter settings. OUTPUT. Analog output of the XTAL32K crystal oscillator. INPUT. Analog to Digital Converter input 2. I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. INPUT. Analog to Digital Converter input 3. I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Revision 3.0 25 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Pin Pin Name no. Type Reset Description State 16 P0_9 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. 9 P0_10 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. SWDIO DIO P0_11 DIO (Type A) I-PD INPUT/OUTPUT with selectable pull up/down resistors. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. 8 INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication (by default). Debug Interface 9 SWDIO DIO I-PD INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Mapped on P0_10 (by default). 12 SWCLK DIO I-PD INPUT JTAG clock signal. Mapped on P0_2 (by default). Clocks 3 XTAL32Mp AI INPUT. Crystal input for the 32 MHz XTAL. 4 XTAL32Mm AO OUTPUT. Crystal output for the 32 MHz XTAL. 13 XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL. Mapped on P0_3. 14 XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL. Mapped on P0_4. Quadrature Decoder QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports. QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports. QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports. QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports. QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports. QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports. SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports. SPI_DI DI INPUT. SPI Data input. Mapped on Px ports (Note 1). SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports (Note 2). SPI Bus Interface Datasheet CFR0011-120-00 Revision 3.0 26 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Pin Pin Name no. SPI_EN Type Reset Description State DI/DO INPUT/OUTPUT. SPI Clock enable. Mapped on Px ports. SDA DIO/DIOD INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on Px ports. The mapped Px pin is automatically configured with a pull-up resistor (25KOhm) when pin x is mapped to the I2C_SDA PID function. SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port. In open drain mode, SCL is monitored to support bit stretching by a slave. Mapped on Px ports. The mapped Px pin is automatically configured with a pullup resistor (25KOhm) when pin x is mapped to the I2C_SCL PID function. UTX DO OUTPUT. UART transmit data. Mapped on Px ports. URX DI INPUT. UART receive data. Mapped on Px ports. URTS DO OUTPUT. UART Request to Send. Mapped on Px ports. UCTS DI INPUT. UART Clear to Send. Mapped on Px ports. UTX2 DO OUTPUT. UART2 transmit data. Mapped on Px ports. URX2 DI INPUT. UART2 receive data. Mapped on Px ports. I2C Bus Interface UART Interface ADC IO Channels 11 ADC0 AI INPUT. Analog to Digital Converter input 0. Mapped on P0_1. 12 ADC1 AI INPUT. Analog to Digital Converter input 1. Mapped on P0_2. 22 ADC2 AI INPUT. Analog to Digital Converter input 2. Mapped on P0_6. 15 ADC3 AI INPUT. Analog to Digital Converter input 3. Mapped on P0_7. Radio Transceiver 1 RFIOp AIO RF input/output. Impedance 50 Ω 18 RFIOm AIO RF ground. 19 GND_RF1 AIO RF ground. 2 GND_RF2 AIO RF ground. Miscellaneous 10 RST DIO INPUT. Reset signal (active high). Mapped on P0_0 (by default). 6 LX AIO INPUT/OUTPUT. Connection for the external DC-DC converter inductor. Datasheet CFR0011-120-00 Revision 3.0 27 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Pin Pin Name no. Type Reset Description State Power and Ground 23 VSS AIO Digital ground. 20 GND AIO Analog ground. 7 VBAT_HIGH AIO INPUT/OUTPUT. Battery connection or DCDC output in BUCK/BOOST mode, respectively. IO supply. 5 VBAT_LOW AIO INPUT/OUTPUT. Battery connection or DCDC output in BOOST/BUCK mode, respectively. System supply. 21 GND_DCDC AIO DCDC ground. Note 1 Data input only. MOSI in SPI slave mode and MISO in SPI master mode. Note 2 Data output only. MISO in SPI slave mode and MOSI in SPI master mode. Note 3 The differences between Type A and Type B GPIO pads are presented in Types of GPIO Pads. 3 Specifications All MIN/MAX specification limits are guaranteed by design, production testing and/or statistical characterization. Typical values are based on characterization results at default measurement conditions and are informative only. Default measurement conditions (unless otherwise specified): VBAT_HIGH = 3.0 V (buck mode), VBAT_LOW = 1.5 V (boost mode), TA = 25 oC. All radio measurements are performed with standard RF measurement equipment providing a source/load impedance of 50 Ω. All listed currents involving any radio operation have been conducted without the external CLC filter. Due to the voltage dependent capacitance of MLCC capacitors the specified capacitor values at VBAT_HIGH and VBAT_LOW are effective capacitances. Datasheet CFR0011-120-00 Revision 3.0 28 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 1 . u C 10uF BT1 1. 5V G1 G3 G5 C1 1uF p F 0 0 0 0 0/ ST 1 /S C 5/ S D TA 3 1 1 m 1 TA 3 DA 1 531 all CS G D F1 A5 0 B 0 3 3 . 6 G D F G D DCDC 3 . 0000 E1 m 0 3/ TA 3 p VSS 3 1. pF 1 1. pF A3 D p 0 / TA 3 m lcsp1 1. 3. 3n A1 1 F E5 C5 D 0 0 0 1 0 0 5 F 3 VBAT VBAT G A T1 C1 F C3 E3 .0 Figure 5: Boost configuration system diagram 1 . u A T1 0 6 0 0 0 10 11 1 15 1 16 p F 0 0 0 0 0/ ST 1 /S C 5 1 TA 3 p 0 10/ S D 0 11 0 13 0 3 3 . 6 G DF G D F1 G D DCDC 1 1 1 G D VSS 3. 0 0 . 3 m 0 3/ TA 3 p 3 qf n 3 1. pF 3 . 0000 TA 3 0 / TA 3 m 0 10 0 11 1 1. pF 1 1 DA1 531 pin FCG F 0 6 0 0 0 m 3. 3n 1 1 0 0 0 1 0 0 5 F 3 VBAT VBAT G 6 C 1uF 5 C1 10uF BT1 3. 0V Figure 6: Buck configuration system diagram Datasheet CFR0011-120-00 Revision 3.0 29 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 3.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit VBAT_LIM_LOW limiting supply voltage Battery voltage in boost configuration, supply voltage in buck configuration -0.2 3.6 V VBAT_LIM_HIG Battery voltage in buck configuration, supply voltage in boost configuration -0.2 3.6 V -0.2 3.6 V electrostatic discharge voltage (Human Body Model) 4 kV electrostatic discharge voltage (Human Body Model) 2 kV electrostatic discharge voltage (Charged Device Model) 500 V VESD_CDM_WL electrostatic discharge voltage (Charged Device Model) CSP17 500 V -50 150 °C Typ Max Unit 50 μA 1.1 3.3 V 1.1 3.3 V 2.25 3.3 V VBAT_HIGH_OT Voltage range for OTP reading. P_Read 1.62 3.3 V VPIN_default -0.2 VBAT _HIGH +0.2 V limiting supply voltage H VPIN_LIM_defau limiting voltage on a pin lt VESD_HBM_FC GQFN24 VESD_HBM_WL CSP17 VESD_CDM_FC GQFN24 TSTG 3.2 storage temperature Recommended Operating Conditions Table 4: Recommended Operating Conditions Parameter Description Conditions IL_VBAT_HIGH_ Maximum external DC load current on VBAT_HIGH rail during booting in boost mode Boost mode booting sequence active VBAT_HIGH Supply voltage. Buck/Bypass: battery voltage Boost: DCDC output For OTP functionality refer to VBAT_HIGH_OTP_Program/Read VBAT_LOW Supply voltage. Boost/Bypass: battery voltage Buck: DCDC or LDO_LOW output BOOTING VBAT_HIGH_OT Voltage range for OTP programming. P_Program Required temperature for programming is between 20oC and 85oC voltage on a pin Datasheet CFR0011-120-00 Revision 3.0 30 of 374 Min 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Parameter Description TA ambient temperature 3.3 Conditions Min Typ -40 Max Unit 85 °C Max Unit DC Characteristics Table 5: DC Characteristics Parameter Description Conditions IBAT_HIGH_HIB battery supply current Hibernation mode, no RAM retained, no oscillator running Note 1 270 nA battery supply current Hibernation mode, 48kB RAM retained, no oscillator running 750 nA battery supply current Hibernation mode, no RAM retained, no oscillator running Note 2 240 nA battery supply current Hibernation mode at 5 0C, 0kB RAM retained, no oscillator running 150 nA battery supply current Hibernation mode, 48kB RAM retained, no oscillator running 700 nA battery supply current Deep-sleep with 0 kB RAM retained, running on RCX 0.9 μA battery supply current Extended-sleep with 20 kB RAM retained, running on RCX 1.2 μA battery supply current Extended-sleep with 48 kB RAM retained, running on RCX 1.6 μA battery supply current Deep-sleep with no RAM retained, running on RCX 1 μA battery supply current Extended-sleep mode with 20 kB RAM retained, running on RCX 1.2 μA battery supply current Extended-sleep mode with 48 kB RAM retained, running on RCX 1.6 μA battery supply current Application with Receiver Active, CPU idle at 16MHz, DCDC off 5 mA ERN_0kB IBAT_HIGH_HIB ERN_48kB IBAT_LOW_HIB ERN_0kB IBAT_LOW_HIB ERN_0kB_5DEG IBAT_LOW_HIB ERN_48kB IBAT_LOW_DP_ SLP_0kB IBAT_LOW_EX_ SLP_20kB IBAT_LOW_EX_ SLP_48kB IBAT_HIGH_DP_ SLP_0kB IBAT_HIGH_EX_ SLP_20kB IBAT_HIGH_EX_ SLP_48kB IBAT_LOW_ACT _RX Datasheet CFR0011-120-00 Revision 3.0 31 of 374 Min Typ 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Parameter Description Conditions IBAT_LOW_ACT battery supply current Application with Pout = 0dBm, Power setting 9, Transmit continuous unmodulated output power, CPU idle at 16MHz, DCDC off 8 mA IBAT_HIGH_ACT battery supply current Application with Receiver Active, CPU idle at 16MHz, DCDC on 2.2 mA Application with Pout = 0dBm,Power setting 9, Transmit continuous unmodulated output power, CPU idle at 16MHz, DCDC on 3.5 mA battery supply current CPU executing code from RAM running on XTAL32M oscillator at 16MHz, DCDC off 830 μA battery supply current CPU executing code from RAM running on XTAL32M oscillator at 16MHz 380 μA battery supply current CPU in Wait-for-Interrupt (WFI) state running on XTAL32M oscillator at 16MHz 230 μA IBAT_LOW_IDLE battery supply current CPU in Wait-for-Interrupt (WFI) state running on XTAL32M oscillator at 16MHz, DCDC off 460 μA IBAT_HIGH_RST battery supply current Reset pin asserted, buck configuration, VBAT_HIGH = 3.0 V, at 25°C 200 μA IBAT_LOW_RST Reset pin asserted, boost configuration, VBAT_LOW = 1.5 V, at 25°C 200 μA _TX _RX IBAT_HIGH_ACT battery supply current _TX IBAT_LOW_RUN _16MHz IBAT_HIGH_RU N_16MHz IBAT_HIGH_IDL E_16MHz _16MHz battery supply current Note 1 IBAT_HIGH is Buck configuration at VBAT = 3 V, at 25 °C Note 2 IBAT_LOW is Boost configuration at VBAT = 1.5 V, at 25 °C Datasheet CFR0011-120-00 Revision 3.0 32 of 374 Min Typ Max Unit 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 3.4 Timing Characteristics Table 6: Timing Characteristics Parameter Description Conditions tSTA_HIBER startup time Time from hibernation to the first executed code instruction. Applies to both buck or boost modes, excludes capacitors charging time. Assumes VBAT_LOW=VBAT_HIGH with use of the resistive switch so no charging of the respective rail is needed. tSTA_SLP_Buck startup time Time from GPIO toggle to the first executed code instruction. Applicable for both deep and extended sleep mode. Application in buck configuration at 3V battery voltage, excluding capacitor charging. tSTA_SLP_Boost startup time Time from GPIO toggle to the first executed code instruction. Applicable for both deep and extended sleep mode. Application in boost configuration at 1.5V battery voltage, excluding capacitor charging. 3.5 Min Typ Max Unit 0.2 0.4 ms 0.86 1.2 ms 0.83 1.1 ms Typ Max Unit 100 500 ppm RCX Oscillator Table 7: RCX Oscillator - Timing Characteristics Parameter Description Conditions ΔfRC RCX oscillator frequency drift 100ms time slot ΔfRC/ΔV_VBA Supply voltage dependency (VBAT_HIGH) -500 80 500 ppm/V Supply voltage dependency (VBAT_LOW) -500 200 3000 ppm/V T_LOW fRCX RCX oscillator frequency at target fixed trim setting 13 15 17 kHz ΔfRC/ΔT_1 Temperature dependency temperature range -40°C to 85°C, RCX_BIAS at preferred value -125 125 ppm/d eg ΔfRC/ΔT_2 Temperature dependency temperature range -40°C to 105°C, RCX_BIAS at preferred value -200 200 ppm/d eg T_HIGH ΔfRC/ΔV_VBA Datasheet CFR0011-120-00 Revision 3.0 33 of 374 Min 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 3.6 XTAL32MHz Oscillator Table 8: XTAL32MHz Oscillator - Recommended Operating Conditions Parameter Description Conditions Min Typ Max Unit PDRV_MAX maximum drive power Note 1 100 μ VCLK_EXT external clock voltage In case of external clock source on XTAL32Mp (XTAL32Mm floating or connected to mid-level 0.6 V) φN_EXT_32M phase noise fC = 50 kHz; in case of external clock source ΔfXTAL_TRIM crystal frequency trim 2 ppm fXTAL_32M crystal oscillator frequency 32 MHz ΔfXTAL crystal frequency tolerance After optional trimming; including aging and temperature drift Note 2 -20 20 ppm ΔfXTAL_UNT crystal frequency tolerance Untrimmed; including aging and temperature drift Note 3 -40 40 ppm ESR_1pF equivalent series resistance C01.8V POR HIGH AIRCR = 0x05FA0004) and the SYS_CTRL_REG[SW_RESET] bit. It is mainly used to reboot the system after the base address has been remapped. The block diagram of the reset block is depicted in Figure 21. Certain registers are reset by POR only, or by POR and the HW reset signal but not by the SW reset. These registers are listed in Table 39. Table 39: Reset Signals and Registers Reset by POR Only Reset by POR or HW Reset Reset by POR, HW Reset, or SW Reset BANDGAP_REG BLE_CNTL2_REG The rest of the Register File POR_PIN_REG CLK_AMBA_REG[OTP_ENABLE] POR_TIMER_REG CLK_FREQ_TRIM_REG HWR_CTRL_REG CLK_RADIO_REG RESET_STAT_REG[PORESET_STAT] CLK_CTRL_REG PAD_LATCH_REG PMU_CTRL_REG POWER_AON_CTARL_REG SYS_CTRL_REG GP_DATA_REG TRIM_CTRL_REG TEST_VDD_REG RAM_PWR_CTRL_REG RTC_CONTROL_REG CLK_RC32K_REG RTC_KEEP_RTC_REG CLK_XTAL32K_REG CLK_RC32M_REG CLK_RCX_REG XTALRDY_CTRL_REG XTAL32M_CTRL0_REG PMU_SLEEP_REG POWER_CTRL_REG POWER_LEVEL_REG DCDC_CTRL_REG RAM_LPMX_REG HIBERN_CTRL_REG CLK_RTCDIV_REG RTC_CONTROL_REG RTC_KEEP_RTC_REG OTPC_*_REG QDEC_*_REG All RF calibration registers Datasheet CFR0011-120-00 Revision 3.0 68 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 5.2.2 POR Functionality The POR functionality is available by two sources: ● RST Pad: the RST pad is always capable of producing a POR ● GPIO Pin: a GPIO can be selected by the user application to act as a POR source The time needed for a GPIO pin selected for the POR to be active is stored in the POR_TIMER_REG. The register field POR_TIME is a 7-bit field which holds the time factor by which the total time for POR is calculated. The maximum value of the field is 0x7F. The total time for POR is calculated by the following formula: Total time = POR_TIME × 4096 × RC32k clock period (1) where RC32k clock period = 31.25 µs at 25°C. The maximum time for which a POR can be performed is ~16.2 seconds at 25°C. The RC32k clock frequency depends on temperature, so based on the temperature span of -10°C to 50°C, the clock frequency range is calculated to be 25 kHz to 39 kHz. Then, TPORcold = 13 s TPORhot = 20.8 s 5.2.2.1 POR Timer Clock The POR timer is clocked by the RC32k clock. If a SW application disables the RC32k, the HW takes care of enabling the RC32k clock when a POR source (the RST pad or a selected GPIO pin) is asserted. It should be noted that if the POR is generated from the RST pad, the RC32k will operate with the reset (default) trimming value. If a GPIO pin is used as the POR source, the RC32k clock will be trimmed. The timing difference between both cases is expected to be minor. 5.2.2.2 RST Pad The RST pad will produce a HW reset if the pin active time is less than the programmed value in the POR_TIMER_REG register or a POR if the pin active time is greater than or equal to that value. Reset pad is always Active High. 5.2.2.3 POR from GPIO When a GPIO is used as a POR source, the selected pin retains its capability to act as GPIO. The POR_PIN_REG[PIN_SELECT] field holds the required GPIO pin number. If the value of the PIN_SELECT field equals to 0, the POR triggered by GPIO functionality is disabled. The polarity of the pin can be configured by the POR_PIN_REG [POR_POLARITY] bit, where 0 means Active Low and 1 means Active High. 5.2.3 POR Timing Diagram The operation of the POR triggered by both the RST pad and a selected GPIO pin is depicted in Figure 22. Datasheet CFR0011-120-00 Revision 3.0 69 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC TCLK = 31.25usec RC32k Reset pad =POR Timer >=POR Timer 7 ... ... 2.25pF 2.25pF 1.2pF ... 150fF 75fF Figure 28: XTAL32MHz Oscillator Frequency Trimming 10.2.2 Automated Trimming and Settling Notification There is provision in the DA14531 for automating the actual trimming of the 32 MHz crystal oscillator. This is a special hardware block that realizes the XTAL trimming in a single step. Notification about the XTAL oscillator being settled after applying the trim value is also provided in form of an interrupt, namely, the XTAL32RDY_IRQn line. The automated mechanism for applying the trim value and signaling that the oscillator is settled is described in Figure 29. The XTAL32RDY_IRQn is always triggered as soon as an internal counter reaches the value programmed at XTALRDY_CTRL_REG. This counter runs on the RC32M clock if the system is powering up, or on a selected low power clock if the system is waking up. The enabling of the XTAL32M is always done by HW. There are two sections until the interrupt notifies the software that the XTAL32M can be used: ● The start-up section, where the XTAL32M oscillator is slowly converging towards the initial frequency of the crystal. This section ends with the application of the trim value to achieve a 0.9-0V) 120 kOhm GP_ADC_OFFS_SH_EN 0 1 2 3 4 5 6 7 GP_ADC_ATTN P0 _1 P0 _2 P0 _6 P0 _7 Temp Sens or VBAT _H IG H VBAT _L OW VDD General Purpose ADC GP_ADC_OFFS_CM GP_ADC_SEL_P GP_ADC_OFFS_SH_EN ● ● ● ● ● ● ● ● ● ● ● 1 40 kOhm 0 20 kOhm VBAT _L OW 0.9V LDO GP_ADC_EN GP_ADC_I20U GP_ADC_MINT Vref=0.9V ADC_IRQ GP_ADC_INT 60 kOhm GP_ADC_SE ADC_DMA_REQ GP_ADC_SEL_N 20 kOhm 0 1 2 3 120 kOhm GP_ADC_ATTN 40 kOhm P0 _1 P0 _2 P0 _6 P0 _7 16bit GP_ADC_RESULT_REG GP_ADC_EN GP_ADC_START GP_ADC_SIGN GP_ADC_OFFx GP_ADC_CHOP GP_ADC_MUTE GP_ADC_CONV_NRS GP_ADC_SMPL_TIME 60 kOhm ADC Figure 71: Block Diagram of GPADC Datasheet CFR0011-120-00 Revision 3.0 145 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 26.2 Architecture The ADC architecture shown in Figure 71 has the following sub-blocks: ● Analog to Digital converter (ADC) ○ ADC analog part internally clocked with 100 MHz ○ ADC logic part clocked with the ADC_CLK which is the 16 MHz system clock (sys_clk) ● 0.9 V LDO for the ADC supply with a high PSRR enabled with GP_ADC_CTRL_REG[GP_ADC_EN] ● Configurable attenuator with 1×, 2×, 3×, and 4× attenuation controlled by GP_ADC_CTRL2_REG[GP_ADC_ATTN] ● Input shifter which shifts the battery voltage range from 0.85 V to 1.75 V (with a common mode adjustment) to the ADC input range from 0 V to 0.9 V controlled by GP_ADC_CTRL2_REG[GP_ADC_OFFS_SH_EN] and GP_ADC_CTRL2_REG[GP_ADC_OFFS_CM] ● APB Bus interface clocked with the APB clock. Control and status registers are available through registers GP_ADC_* ● Maskable Interrupt (ADC_IRQ) and DMA request (ADC_DMA_REQ) ● ADC input channel selector. Up to four GPIO ports, the battery and DCDC output (VBAT_HIGH and VBAT_LOW ), the internal VDD, and the analog ground level (AVS) can be measured. 26.2.1 Input Channels Table 51 summarizes the ADC input channels. The GPIO signals at the channels [3:0] can be monitored both single-ended and differentially. The signals at the 4-7 inputs can be monitored singleended or differentially with respect to the GPIOs. Table 51: ADC Input Channels Channel Signal Description 3:0 GPIO [P0_1, P0_,2, P0_6, P0_7] General Purpose Inputs 4 Temperature Sensor Temperature Sensor 5 VBAT_HIGH VBAT_HIGH rail 6 VBAT_LOW VBAT_LOW rail 7 VDD VDD rail for the digital power domain Table 52 summarizes the voltage ranges which can be handled with the single-ended or differential operation for different attenuation values. The single-ended/differential mode is controlled by the bit GP_ADC_CTRL_REG[GP_ADC_SE], and the attenuation is handled by the bit GP_ADC_CTRL2_REG[GP_ADC_ATTN]. Table 52: GPADC External Input Channels and Voltage Range GP_ADC_ATTN GP_ADC_SE Input Scale Input Limits 0 (1 ×) 0 1 -0.9 V to +0.9 V 0 V to +0.9 V -1 V to +1 V -0.1 V to 1V 1 (2 ×) 0 1 -1.8 V to +1.8 V 0 V to +1.8 V -1.9 V to +1.9 V -0.1 V to 1.9 V 2 (3 ×) 0 1 -2.7 V to +2.7 V 0 V to +2.7 V -2.8 V to +2.8 V -0.1 V to 2.8 V 3 (4 ×) 0 1 -3.6 V to +3.6 V 0 V to +3.6 V -3.45 V to +3.45 V -0.1 V to 3.45 V Datasheet CFR0011-120-00 Revision 3.0 146 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 26.2.2 Operating Modes The GPADC operation flow diagram is shown in Figure 72. START GP_ADC_EN=1 cntr = 4*GP_ADC_EN_DEL Yes No cntr ==0 cntr-- ADC_LDO_0V9 start-up GP_ADC_START==1 No Wait for initual Star conv_nr = 2*GP_ADC_CONV_NRS cntr = 8*GP_ADC_SMPL_TIME cntr ==0 Yes No ADC Sample time cntr-- ADC Conversion ADC Conversion cntr = GP_ADC_STORE_DEL Yes cntr ==0 No No ADC_READY cntr ==0 No cntr-- ADC Store delay tmp_result += ADC value Oversampling Mode No conv_nr-- conv_nr==0 Yes Delay = GP_ADC_INTERVAL*1.024 ms GP_ADC_RESULT= average(tmp_result) No ADC_IRQ_EN=1 DMA Request =1 Yes GP_ADC_INTERVAL==0 Continuous Mode No GP_ADC_CONT==0 Yes GP_ADC_START=0 STOP Figure 72: GPADC Operation Flow Diagram Datasheet CFR0011-120-00 Revision 3.0 147 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 26.2.2.1 Enabling the ADC Enabling/disabling of the ADC is triggered by configuring bit GP_ADC_CTRL_REG[GP_ADC_EN]. When the bit is set to 1, first the LDO is enabled. Then after the delay value set in GP_ADC_CTRL3_REG[GP_ADC_EN_DEL] (typically 16 µs to account for the LDO settling time), the ADC will be enabled, and an AD conversion can be started. See Table 53 for recommended values. Table 53: ADC_LDO Start-Up Delay fADC_CLK GP_ADC_EN_DEL τADC_EN_DEL 16 MHz 0x40 16 µs Formula: GP_ADC_EN_DEL = τADC_EN_DEL × fADC_CLK / 4 This value must be rounded up to the nearest integer. The GPADC is a dynamic ADC and consumes no static power, except for the ADC_LDO which consumes approximately 20 µA. Therefore, GP_ADC_EN must be set to 0 if the ADC is not used. 26.2.2.2 Manual Mode An AD conversion can be started by setting GP_ADC_START to 1. While a conversion is active, GP_ADC_START remains 1. When a conversion is finished, the hardware sets GP_ADC_START to 0 and GP_ADC_INT to 1 (interrupt), and GP_ADC_RESULT_REG contains the valid ADC value. While a conversion is active, writing 1 to GP_ADC_START will not start a new conversion. SW should always check that bit GP_ADC_START = 0 before starting a new conversion. 26.2.2.3 Continuous Mode Setting GP_ADC_CTRL_REG[GP_ADC_CONT] to 1 enables the continuous mode, which automatically starts a new AD conversion when the current conversion has been completed. The GP_ADC_START bit is only needed once to trigger the first conversion. As long as the continuous mode is active, GP_ADC_RESULT_REG always contains the latest ADC value. To correctly terminate the continuous mode, it is required to disable the GP_ADC_CONT bit first and then wait until the GP_ADC_START bit is cleared to 0, so the ADC is in a defined state. NOTE Before making any changes to the ADC settings, users must disable the continuous mode by setting bit GP_ADC_CONT to 0 and waiting until bit GP_ADC_START = 0. At full speed the ADC consumes approximately 50 to 60 µA. If the data rate is less than 100 ksample/s, the current consumption will be in the order of 25 µA. The time interval between two successive AD conversions is programmable with GP_ADC_CTRL3_REG[GP_ADC_INTERVAL] in steps of 1.024 ms. If GP_ADC_INTERVAL = 0, the conversion will restart immediately. If GP_ADC_INTERVAL is not zero, the ADC first synchronizes to the delay clock before starting the conversion. This can take up to 1 ms. 26.2.3 Conversion Modes 26.2.3.1 AD Conversion Each AD conversion has three phases: ● Sampling ● Conversion ● Storage Datasheet CFR0011-120-00 Revision 3.0 148 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC The AD conversion starts with the sampling phase. This phase ends after the time set in GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] and triggers the conversion phase. If GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] = 0, handshaking is used, that is, the ADC result is stored when a conversion is finished. Otherwise, a fixed (programmable) delay is used, and the result is stored regardless of whether the conversion is finished or not. The total conversion time of an AD conversion depends on various settings. In short, it is as follows. 𝑇𝐴𝐷𝐶 = 𝑁𝐶𝑂𝑁𝑉 ∙ (𝑁𝐶𝑌𝐶𝐿_𝑆𝑀𝑃𝐿 + 𝑁𝐶𝑌𝐿𝐶_𝑆𝑇𝑂𝑅𝐸 ) 𝑓𝐴𝐷𝐶_𝐶𝐿𝐾 (5) Where ● NCONV = the number of conversions. This is related to the value programmed in GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS], following 2GP_ADC_CONV_NRS. When GP_ADC_CTRL_REG[GP_ADC_CHOP] is set, the minimum value for NCONV is always 2. ● NCYLC_SMPL = the number of ADC_CLK cycles used for sampling, which is 8 × GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME]. ● NCYCL_STORE = the number of ADC_CLK cycles until the result is stored. When GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] = 0, handshaking is used. With handshaking, the number of ADC_CLK cycles is typically three. This value may spread from sample to sample and over temperature, otherwise the number of ADC_CLK cycles is GP_ADC_CTRL2_REG[GP_ADC_STORE_DEL] + 1. Sampling Phase The sampling time can be programmed via GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] and depends on the sampling time constant in combination with the desired sampling accuracy. This sampling time constant, τADC_SMPL (Table 54), then depends on the output impedance of the source, the internal resistive dividers, and the internal sampling capacitor. And the number of required time constants is given by the natural logarithm of the desired accuracy, that is, ln(2^NBIT). For NBIT = 10-bit accuracy, 7 time constants are required. Table 54: ADC Sampling Time Constant (τADC_SMPL) ADC Input τADC_SMPL GPADC0, GPADC1 (GP_ADC_ATTN = 0) ROUT × 0.5 pF (Differential Input) ROUT × 1 pF (Single-Ended Input) GPADC0, GPADC1 (GP_ADC_ATTN = 1) (ROUT + 160 Ω) × 0.5 pF (Differential Input) (ROUT + 160 Ω) × 1 pF (Single-Ended Input) Formula: GP_ADC_SMPL_TIME = ln(2^NBIT) × τADC_SMPL × fADC_CLK / 8 This value must be rounded up to the nearest integer. Conversion and Storage Phase One AD conversion typically takes around 125 ns with a 100 MHz clock. The result can be stored either by handshaking or after a fixed number of cycles (programmable). ● Handshake mode (GP_ADC_STORE_DEL = 0): In handshake mode the conversion result is available in GP_ADC_RESULT_REG after two sampling ADC_CLK cycles plus two conversion ADC_CLK cycles plus two ADC_CLK cycles for synchronization. ● Fixed delay mode (GP_ADC_STORE_DEL > 0): In fixed delay mode the conversion result is available in GP_ADC_RESULT_REG after the programmed storage delay, regardless of whether the conversion is ready or not. Note that when the Datasheet CFR0011-120-00 Revision 3.0 149 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC delay is too short (that is, the conversion is not finished in the allocated time), the old (previous) ADC result is stored. 26.2.3.2 Averaging In order to reduce noise and improve performance, multiple samples can be averaged out (assuming the time average of noise equals zero). This is handled by HW and can be controlled by setting GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] to a non-zero value. The actual number of the consecutive samples taken is by 2GP_ADC_CONV_NRS. Because the internal noise also acts as a form of dither, the actual accuracy can be improved. Therefore, the ADC result is not truncated to 10-bit but stored as 16-bit left aligned, and truncation is left for the user. The expected Effective Number of Bits (ENOB) is shown in Table 55. Table 55: ENOB in Oversampling Mode GP_ADC_CONV_NRS ENOB (Left Aligned) in GP_ADC_RESULT_REG 0 >9 1 >9 2 >9 3 > 10 4 > 10 5 > 10 6 > 11 7 > 11 26.2.3.3 Chopper Mode Inherently, the ADC has a DC offset (EOFS). When GP_ADC_CTRL_REG[GP_ADC_CHOP] is set to 1, the hardware triggers two consecutive AD conversions and flips the sign of the offset inbetween. Summing the two samples effectively cancels out the inherent ADC offset. This method also smooths other non-ideal effects and is recommended for DC and the slowly changing signals. When combined with averaging, every other AD conversion is taken with opposite sign. Without averaging two AD conversions are always triggered. Note that a DC offset causes saturation effects at zero scale or full scale. When chopping is used without offset calibration, non-linear behavior is introduced towards zero scale and full scale. 26.2.4 Additional Settings The hardware also supports pre-ADC attenuation via GP_ADC_CTRL2_REG[GP_ADC_ATTN]: ● ● ● ● Setting 0 disables the attenuator Setting 1 scales the input range by a factor of two Setting 2 scales the input range by a factor of three Setting 3 scales the input range by a factor of four With bit GP_ADC_CTRL_REG[GP_ADC_MUTE] = 1, the input is connected to 0.5 × ADC reference. So, the ideal ADC result should be 511.5. Any deviation from this is the ADC offset. With bit GP_ADC_CTRL_REG[GP_ADC_SIGN] = 1, the sign of the offset is inverted. When chopper is used, the hardware alternates GP_ADC_SIGN = 0 and 1. This bit is typically only used for the offset calibration routine described in section 26.2.6 and has no specific use to the end user. Datasheet CFR0011-120-00 Revision 3.0 150 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 26.2.5 Non-Ideal Effects Besides Differential Non-Linearity (DNL) and Integral Non-Linearity (INL), each ADC has a gain error (linear) and an offset error (linear). The gain error (EG) of the GPADC affects the effective input range. The offset error (EOFS) causes the effective input scale to become non-centered. The offset error can be reduced by chopping and/or by offset calibration. The ADC result will also include some noise. If the input signal itself is noise free (inductive effects included), the average noise level will be ±1 LSB. Reducing noise effects can be done by taking more samples and calculating the average value. This can be done by programming GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] to a non-zero value. With a “perfect” input signal (for example, if a filter capacitor is placed close to the input pin), most of the noise comes from the low-power voltage regulator (LDO) of the ADC. Since the DA14531 is targeted for ultra-compact applications, there is no pin available to add a capacitor at this voltage regulator output. The dynamic current of the ADC causes extra noise at the regulator output. This noise can be reduced by setting bits GP_ADC_CTRL2_REG[GP_ADC_I20U]. Bit GP_ADC_I20U enables a constant 20 µA load current at the regulator output so that the current will not drop to zero. This, obviously, increases power consumption by 20 µA. 26.2.6 Offset Calibration A relative high offset error (EOFS, up to 30 mV, so approximately 30 LSB) is caused by a very small dynamic comparator. This offset error can be cancelled with the chopping function, but it still causes unwanted saturation effects at zero scale or full scale. With GP_ADC_OFFP_REG and GP_ADC_OFFN_REG, the offset error can be compensated in the ADC network itself. To calibrate the ADC, follow the steps in Table 56. In this routine, 0x200 is the target mid-scale of the ADC. Table 56: GPADC Calibration Procedure for Single-Ended and Differential Modes Step Single-Ended Mode (GP_ADC_SE = 1) Differential Mode (GP_ADC_SE = 0) 1 Set GP_ADC_OFFP = GP_ADC_OFFN = 0x200; GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0. Set GP_ADC_OFFP = GP_ADC_OFFN = 0x200; GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0. 2 Start conversion. Start conversion. 3 adc_off_p = GP_ADC_RESULT - 0x200 adc_off_p = GP_ADC_RESULT - 0x200 4 Set GP_ADC_SIGN = 0x1. Set GP_ADC_SIGN = 0x1. 5 Start conversion. Start conversion. 6 adc_off_n = GP_ADC_RESULT - 0x200 adc_off_n = GP_ADC_RESULT - 0x200 7 GP_ADC_OFFP = 0x200 - 2 × adc_off_p GP_ADC_OFFN = 0x200 - 2 × adc_off_n GP_ADC_OFFP = 0x200 - adc_off_p GP_ADC_OFFN = 0x200 - adc_off_n In order to increase the accuracy, it is recommended to set the GP_ADC_CTRL2_REG[GP_ADC_SMPL_TIME] = 2 or 3 and GP_ADC_CTRL2_REG[GP_ADC_CONV_NRS] = 3 or 4 prior to this routine. It is recommended to implement the above calibration routine during the initialization phase of DA14531. To verify the calibration results, check whether the GP_ADC_RESULT value is close to 0x200 while bit GP_ADC_CTRL_REG[GP_ADC_MUTE] = 1. 26.2.7 Zero-Scale Adjustment The GP_ADC_OFFP and GP_ADC_OFFN registers can also be used to set the zero-scale or fullscale input level at a certain target value. For instance, they can be used to calibrate GP_ADC_RESULT to 0x000 at an input voltage of exactly 0.0 V, or to calibrate the zero scale of a sensor. Datasheet CFR0011-120-00 Revision 3.0 151 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 26.2.8 Common Mode Adjustment The common mode level of the differential signal must be 0.45 V = Full Scale/2 (or 1.35 V with GP_ADC_ATTN = 2, that is, 3× attenuation). If the common mode input level of 0.45 V cannot be achieved, the common mode level of the GPADC can be adjusted via GP_ADC_OFFP_REG and GP_ADC_OFFN_REG according to Table 57. The GPADC can tolerate a common mode margin of up to 50 mV. Table 57: Common Mode Adjustment CM Voltage (Vccm) GP_ADC_OFFP = GP_ADC_OFFN 0.225 V 0x300 0.450 V 0x200 0.675 V 0x100 Any other common mode levels between 0.0 V and 0.9 V can be calculated from Table 57. Offset calibration can be combined with common mode adjustment by replacing the 0x200 value in the offset calibration routine with the value required to get the appropriate common mode level. 26.2.9 Input Impedance, Inductance, and Input Settling The GPADC has no input buffer stage. During the sampling phase, a capacitor of 0.5 pF in differential mode or 1 pF in single-ended mode is switched to the input line(s). The pre-charge of this capacitor is at midscale level, so the input impedance is infinite. During the sampling phase, a certain settling time is required. A 10-bit accuracy requires at least seven time constants τADC_SMPL, determined by the output impedance of the input signal source, the internal resistive dividers, and the 0.5 pF or 1 pF sampling capacitor. See Table 54. The inductance from the signal source to the ADC input pin must be very small. Otherwise filter capacitors are required from the input pins to ground (single-ended mode) or from pin to pin (differential mode). 26.3 Programming To program and use the GPADC, follow the simple sequence of steps below: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Enable the GPADC by setting the GP_ADC_CTRL_REG[GP_ADC_EN] bit. Set up the GPIO input (P0_x_MODE_REG[PID] = 15). Select the input channel (GP_ADC_SEL_REG). Select the sampling mode (differential or single ended) by writing the GP_ADC_CTRL_REG[GP_ADC_SE] bit. Select between the manual mode and the continuous mode of sampling (GP_ADC_CTRL_REG[GP_ADC_CONT]. Set up extra options (see GP_ADC_CTRLx_REG description) Start the conversion by setting GP_ADC_CTRL_REG[GP_ADC_START] bit. Wait for GP_ADC_CTRL_REG[GP_ADC_START] to become 0 or interrupt being triggered (when used). Clear the ADC interrupt by writing any value to GP_ADC_CLEAR_INT_REG. Get the ADC result from the GP_ADC_RESULT_REG. Datasheet CFR0011-120-00 Revision 3.0 152 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 27 Real Time Clock (RTC) 27.1 Introduction The DA14531 is equipped with a Real Time Clock (RTC) which provides the complete clock and calendar information with automatic time units adjustment and easy configuration. Features ● Complete time of day clock: 12/24 hour, hours, minutes, seconds, and hundredths of a second ● Calendar function: day of week, date of month, month, year, century, leap year compensation, and year 2000 compliant ● ● ● ● ● Alarm function: month, date, hour, minute, second, and hundredths of a second Event interrupt on any calendar or time unit Available during sleep if the power domain PD_TIM is kept alive Granularity of 10 ms (RTC_CLK) Provides 22 LSB to Timer 1 upon a capture trigger Counters APB32 Bus second 22 time_o minute Synchronizer Timer 1 Register File 1/100th hour date day month RTC_CLK (10ms) AON_PCLK year RTC_IRQn century Figure 73: Real Time Clock Block Diagram 27.2 Architecture The architecture of the RTC is depicted in Figure 73. The RTC supports a year range from 1900 to 2999 as well as full month, date, minute, second, and hundredth of second ranges. It also supports hour ranges of 0 to 23 (24-hour format) or 1 to 12 with a.m./p.m. flag (12-hour format). Alarms can be generated in two ways, as a one-time alarm or as a recurring alarm. In addition to alarms, the RTC can detect when a particular event occurs. Each field of the calendar and time counter can generate an event when it rolls over. For example, an event can be generated every new month, new week, new day, new half day (12-hour mode), new minute, or new second. Both alarms Datasheet CFR0011-120-00 Revision 3.0 153 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC and events can generate an interrupt. All the interrupts can be set, enabled, disabled, or masked at any time. The LSB (22) of the port showing a full of 32-bit information on the current time is latched by Timer 1 (TIMER1_CAPCNT1/2_VALUE_REG) if instructed by Timer 1 configuration. This allows for storing an RTC based snapshot upon an event on a GPIO. 27.3 Programming To configure the RTC, follow the simple sequence of steps below: 1. Configure the 100 Hz RTC granularity if needed: a. Based on the selected LP clock (for example, 32768 kHz), set the CLK_RTCDIV_REG[RTC_DIV_INT] = 327 (= 0x147). This values should be equal to the integer divisor part of the formula FLP_CLK/100 = 327.680. b. Based on the selected LP clock (for example, 32768 kHz), set the CLK_RTCDIV_REG[RTC_DIV_FRAC] = 680 (= 0x2A8). This values should be equal to the fractional divisor part of the formula FLP_CLK/100 = 327.680. c. To achieve a better accuracy of the divisor, configure the denominator for the fractional division accordingly (CLK_RTCDIV_REG[RTC_DIV_DENOM]). d. Enable the 100 Hz RTC granularity by setting the CLK_RTCDIV_REG [RTC_DIV_ENABLE] bit. 2. Enable the time functionality by clearing the RTC_CONTROL_REG[RTC_TIME_DISABLE]. 3. Enable the calendar functionality by clearing the RTC_CONTROL_REG[RTC_CAL_DISABLE]. 4. Choose between 12-hour or 24-hour mode (RTC_HOUR_MODE_REG[RTC_HMS]). 5. Configure the time (RTC_TIME_REG). 6. Configure the date (RTC_CALENDAR_REG). 7. Set up a time alarm if needed (RTC_ALARM_ENABLE_REG). 8. Set up a calendar alarm if needed (RTC_CALENDAR_ALARM_REG). 9. Enable the configured alarms (RTC_ALARM_ENABLE_REG[RTC_ALARM_xxxx_EN]). 10. Configure the interrupt generation when an alarm happens (RTC_INTERRUPT_ENABLE_REG). Disable the interrupt generation with RTC_INTERRUPT_DISABLE_REG. 11. Configure the event flag generation when an alarm happens (RTC_EVENT_FLAGS_REG). 12. Define whether a SW reset resets the RTC (RTC_KEEP_RTC_REG[RTC_KEEP]). Datasheet CFR0011-120-00 Revision 3.0 154 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 28 Power As discussed in section 4.2, the integrated power management unit (PMU) comprises the DCDC converter and various LDOs, the VDD Clamp, and the POR circuitry. The details of these blocks are discussed in the following sections. 28.1 DCDC Converter The DA14531 can be configured in three configurations: buck, boost, and DCDC bypass. The integrated part of the DCDC is the same for all three configurations, that is, the black building blocks in Figure 74 and Figure 75. The buck configuration and the boost configuration are configured on the PCB, distinguished with the red external components in Figure 74 and Figure 75, respectively. In the bypass configuration the VBAT_HIGH and VBAT_LOW rails are connected together, so the DCDC is bypassed. VBAT_HIGH Battery CBAT FSM LEXT LX Controller VBAT_LOW CEXT VREF VSSA_DCDC Figure 74: DCDC Block Diagram - Buck Configuration VBAT_HIGH CEXT FSM LX Controller LEXT VBAT_LOW CBAT Battery VREF VSSA_DCDC Figure 75: DCDC Block Diagram - Boost Configuration ● In buck configuration the battery is connected to VBAT_HIGH, and DCDC supplies power to VBAT_LOW rail ● In boost configuration the battery is connected to VBAT_LOW , and DCDC supplies power to VBAT_HIGH rail ● In DCDC bypass configuration VBAT_HIGH is connected to VBAT_LOW and the battery is connected to both rails. Datasheet CFR0011-120-00 Revision 3.0 155 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC The DCDC level can be programmed by POWER_LEVEL_REG[DCDC_LEVEL] and a fine trimming is available by POWER_LEVEL_REG[DCDC_TRIM]. When the system is allowed to go to sleep, the HW FSM is activated and the DCDC controller is automatically turned off. Upon a wakeup, the DCDC will be enabled by programming DCDC_CTRL_REG[DCDC_ENABLE]. If DCDC_ENABLE is kept set before the system goes to sleep, the DCDC will be started by the HW FSM while waking up. If DCDC_ENABLE is reset before the system goes to sleep, the DCDC can only be started by SW setting this bit after wakeup. For Buck configuration, a typical DCDC efficiency at 25°C as a function of the load current for different battery voltages (VBAT = VBAT_HIGH) is shown in Figure 76. Figure 76: DCDC Efficiency in Buck Configuration For Boost configuration, a typical DCDC efficiency at 25°C as a function of the load current for different battery voltages (VBAT = VBAT_LOW ) is shown in Figure 77. Datasheet CFR0011-120-00 Revision 3.0 156 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Figure 77: DCDC Efficiency in Boost Configuration 28.2 LDOs Several LDOs are used in the DA14531 to provide a stable power supply to the rails and the building blocks. ● VDD_Clamp generates a trimmable ~0.75 V VDD supply voltage for the AON (always on) DCORE power domain from VBAT_HIGH or VBAT_LOW when the system is in the hibernation mode ● LDO_LOW provides power to the VBAT_LOW rail in the buck configuration with a typical output voltage of 1.1 V. This LDO is used during start-up and can also be used after start-up. Alternatively, it can be disabled and the VBAT_LOW rail can be supplied by the DCDC converter. The LDO has a low power setting which is used to maintain the VBAT_LOW rail during sleep mode. See section 4.2.3 for more details. ● LDO_CORE supplies the internal VDD from VBAT_LOW . In the active mode it generates 0.9 V and in the sleep mode 0.75 V ● LDOs for the RF and the analog building blocks generate 0.9 V when the particular blocks are active. When the blocks are switched off, the LDOs are disabled. 28.3 POR Circuit The POR_LOW circuit issues a POR when the VBAT_LOW voltage is below the threshold voltage VIL for more than 50 µs. The POR is cleared when the battery voltage is above VIH for at least 25 µs. The threshold levels of the POR circuit are summarized in section 3.12. The POR_HIGH circuit issues a POR when the VBAT_HIGH voltage is below the VIL for more than 50 µs. The POR is cleared when the battery voltage is above VIH for at least 25 µs. The threshold levels of the POR circuit are summarized in section 3.12. Datasheet CFR0011-120-00 Revision 3.0 157 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 29 BLE Core The Bluetooth Low Energy (BLE) core used in the DA14531 is a qualified Bluetooth 5.1 baseband controller compatible with the BLE specification and it is in charge of packet encoding/decoding and frame scheduling. The block diagram of BLE core is presented in Figure 78. Features ● Compliant with Bluetooth Core Specification, v5.1, Bluetooth SIG ○ Dual topology ○ Low duty cycle advertising ○ L2CAP connection-oriented channels ● All device classes support (Broadcaster, Central, Observer, and Peripheral) ● All packet types (Advertising, Data, and Control) ● Dedicated Encryption (AES/CCM) ● Bit stream processing (CRC and Whitening) ● FDMA/TDMA/events formatting and synchronization ● Frequency hopping calculation ● Operating clock 16 MHz or 8 MHz ● Low power modes supporting 32.0 kHz, 32.768 kHz, or 15 kHz ● Supports powerdown of the baseband during the protocol’s idle periods BLE Timer Radio AHB Slave AHB Master BLE Core Test MUXes Registers Bus Interface Control Radio Controller Frequency Selection Interrupt Generator AES CCM Memory Controller BLE_EM _BASE_ REG Data Whitening CRC Packet Controller Event Controller White List Search Event Scheduler Figure 78: BLE Core Block Diagram 29.1 Architecture 29.1.1 Exchange Memory The BLE Core requires access to a memory space named "Exchange Memory" to store control structures and frame buffers. The access to Exchange Memory is performed via the AHB Master interface. The base address of the Exchange Memory is programmable by means of the BLE_EM_BASE register. Datasheet CFR0011-120-00 Revision 3.0 158 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 29.2 Programming 29.2.1 Wake-Up IRQ Once the BLE core switches to "BLE Deep Sleep mode", the only way to correctly exit from this state is by generating initially the BLE_WAKEUP_LP_IRQ and consecutively the BLE_SLP_IRQ. This sequence must be followed regardless of the cause of the termination of the "BLE Deep Sleep mode", that is, regardless of whether the BLE Timer has expired or BLE Timer has been stopped due to the assertion of BLE_WAKEUP_REQ. The assertion and de-assertion of BLE_WAKEUP_LP_IRQ is fully controlled via the BLE_ENBPRESET_REG bit fields. A detailed description is as follows: ● TWIRQ_SET: it defines the number of "ble_lp_clk" cycles before the expiration of the BLE Timer when the BLE_WAKEUP_LP_IRQ must be asserted. It is recommended to select a TWIRQ_SET value larger than the amount of time that is required to finish trimming the XTAL 32 MHz (refer to XTAL32M_TRIM_READY) plus the execution time of the IRQ Handler. If the programmed value of TWIRQ_SET is less than the minimum recommended value, the system will wake up but the actual BLE sleep duration (refer to BLE_DEEPSLSTAT_REG) will be larger than the programmed sleep duration (refer to BLE_DEEPSLWKUP_REG) ● TWIRQ_RESET: it defines the number of "ble_lp_clk" cycles before the expiration of the sleep period when the BLE_WAKEUP_LP_IRQ will be de-asserted. It is recommended to always set its value to "1" ● TWEXT: it determines the high period of BLE_WAKEUP_LP_IRQ, if an external wake-up event (refer to GP_CONTROL_REG[BLE_WAKEUP_REQ]) occurs. Its minimum value is "TWIRQ_RESET + X", where X is the number of "ble_lp_clk" clock cycles that BLE_WAKEUP_LP_IRQ will be held high. The recommended value is "TWIRQ_RESET + 1". Note that as soon as GP_CONTROL_REG[BLE_WAKEUP_REQ] is set to "1", the BLE_WAKEUP_LP_IRQ will be asserted ● Minimum BLE Sleep Duration: The minimum value of BLE_DEEPSLWKUP_REG[DEEPSLTIME] bit, measured in "ble_lp_clk" cycles, is the higher value between (a) "TWIRQ_SET + 1" and (b) the SW execution time from setting BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] up to preparing CPU to accept the BLE_WAKEUP_LP_IRQ (for example, to call the Cortex instruction WFI). If the programmed DEEPSLTIME is less than the minimum value of BLE_DEEPSLWKUP_REG[DEEPSLTIME], the BLE_WAKEUP_LP_IRQ Handler may execute sooner than the call of the Cortex WFI instruction in the example and cause SW instability 29.2.2 Switch from BLE Active Mode to BLE Deep Sleep Mode Software can set the BLE core into the "BLE Deep Sleep mode" by first programming the timing of BLE_WAKEUP_LP_IRQ generation, then programming the desired sleep duration at BLE_DEEPSLWKUP_REG, and finally set the register bit BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON]. During the "BLE Deep Sleep mode", the BLE Core will switch to the "ble_lp_clk" (15kHz, 32.0 kHz, or 32.768 kHz) in order to maintain its internal 6 5 μs timing reference. SW must poll the state of BLE_CNTL2_REG[RADIO_PWRDN_ALLOW] to detect the completion of this mode transition. Once the "ble_lp_clk" is used for base time reference, SW must disable the BLE clocks ("ble_master1_clk", "ble_master2_clk", and "ble_crypt_clk") by setting the CLK_RADIO_REG[BLE_ENABLE] register bit to "0". Finally, SW can optionally power down the Radio Subsystem by using the PMU_CTRL_REG[RADIO_SLEEP] and the Peripheral and System power domains as well. Figure 79 presents the waveforms when the BLE Deep Sleep mode is entered. In this case, as soon as the SW detects that RADIO_PWRDOWN_ALLOW is "1", it sets the PMU_CTRL_REG[RADIO_SLEEP] to power down the Radio Subsystem. In Figure 79, Figure 80, Figure 81, Figure 82, and Figure 83, the corresponding BLE Core signals are marked with red while Datasheet CFR0011-120-00 Revision 3.0 159 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Radio Subsystem is in power-down state and they remain red-marked during the period when RADIO_SLEEP is set. Figure 79: Entering BLE Deep Sleep mode 29.2.3 Switch from BLE Deep Sleep Mode to BLE Active Mode There are two possibilities for the BLE Core to terminate the BLE Deep Sleep mode: ● Termination at the end of a predetermined time ● Termination on SW wake-up request due to an external event 29.2.3.1 Switching at an Anchor Point Figure 82 shows a typical BLE deep sleep phase that is terminated at a predetermined time. After a configurable time before the scheduled wake-up time (configured via BLE_ENBPRESET_REG register bit fields), the BLE Timer asserts the BLE_WAKEUP_LP_IRQ in order to wake up the CPU (powering up the System Power Domain). The BLE_WAKEUP_LP_IRQ Interrupt Handler will prepare the code environment and the XTAL32M oscillator stabilization (refer to SYS_STAT_REG[XTAL32_SETTLED]) and will decide when the BLE Core is ready to exit the BLE Deep Sleep mode. Once the SW decides that the BLE Core can wake up, it must enable the BLE clocks (via CLK_RADIO_REG[BLE_ENABLE]) and power up the Radio Power Domain (refer to PMU_CTRL_REG[RADIO_SLEEP] and SYS_STAT_REG[RAD_IS_UP]). After the sleep period is expired (as specified in BLE_DEEPSLWKUP_REG[DEEPSLTIME]), the BLE Timer will not exit the BLE Deep Sleep mode until it detects that the BLE Core is powered up. That means, if the SW requires more time to power up the BLE Core, the final sleep duration (provided by BLE_DEEPSLSTAT_REG) will be longer than the preprogrammed value. When the BLE Timer is expired, BLE clocks are enabled, and the BLE Core (Radio Subsystem) is powered up, the BLE Core exists the "BLE Core Deep Sleep mode" and asserts the BLE_SLP_IRQ. Datasheet CFR0011-120-00 Revision 3.0 160 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Figure 80: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom In) Figure 81: Exit BLE Deep Sleep Mode after Predetermined Time (Zoom In) Figure 82: Exit BLE Deep Sleep Mode at Predetermined Time (Zoom Out) Datasheet CFR0011-120-00 Revision 3.0 161 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 29.2.3.2 Switching Due to an External Event Figure 83 shows a wakeup from a BLE deep sleep period forced by the assertion of register bit GP_CONTROL_REG[BLE_WAKEUP_REQ]. Assume that the system is in Extended Sleep state with all power domains switched off and both the wake-up timer and wake-up controller programmed appropriately. Then assume that an event is detected at one of the GPIOs, causing the System Power Domain to wake up due to WKUP_QUADDEC_IRQ. In that case, the SW will decide to wake up the BLE core, then it sets the GP_CONTROL_REG[BLE_WAKEUP_REQ] to 1 in order to force the wake-up sequence. In Figure 83 the BLE_WAKEUP_REQ is raised by the SW as soon as possible, causing BLE_WAKEUP_LP_IRQ Handler to be executed as soon as possible. It is also possible to raise BLE_WAKEUP_REQ after the detection of XTAL16_TRIM_READY, causing both BLE_WAKEUP_LP_IRQ and BLE_SLP_IRQ Handlers to be executed sequentially. The decision depends on the SW structure and the application. Figure 83: Exit BLE Deep Sleep Mode Due to External Event As soon as the bit field BLE_WAKEUP_REQ is set to 1, the BLE_WAKEUP_LP_IRQ will be asserted. In that case, the high period of BLE_WAKEUP_LP_IRQ is controlled via TWEXT. The recommended value of TWEXT is "TWIRQ_RESET + 1", meaning that BLE_WAKEUP_LP_IRQ will remain high for one "ble_lp_clk" period. As long as the BLE_WAKEUP_REQ is high, entering the sleep mode is prohibited. Please note that BLE_WAKEUP_REQ event can be disabled by setting BLE_DEEPSLCNTL_REG[EXTWKUPDSB]. Datasheet CFR0011-120-00 Revision 3.0 162 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 30 Radio 30.1 Introduction The Radio Transceiver implements the RF part of the BLE protocol. Together with the Bluetooth 5.1 PHY layer, it provides up to 93 dB RF link budget for a reliable wireless communication. All RF blocks are supplied by on-chip low-drop out-regulators (LDOs). The bias scheme is programmable per block and optimized for minimum power consumption. The radio block diagram is given in Figure 84. It comprises the Receiver, Transmitter, Synthesizer, Rx/Tx combiner block, and Biasing LDOs. Features Single ended RFIO interface, 50 Ω matched Alignment free operation -90 dBm receiver sensitivity Configurable transmit output power from -19.5 dBm up to +2.5 dBm Ultra-low power consumption Fast frequency tuning minimizes overhead LNA ● ● ● ● ● ● IF Filter I-ADC DEM Q-ADC LLH RFIO SYNTH 32 MHz XO MOD PA Figure 84: Bluetooth Radio Block Diagram 30.2 Architecture 30.2.1 Receiver The RX frontend consists of a selective matching network, a low noise amplifier (LNA), and an image rejection down conversion mixer. The intermediate frequency (IF) part of the receiver comprises a filter with a programmable gain. The LNA and IF Filter gains are controlled by the Automatic Gain Control (AGC). This provides the necessary signal conditioning prior to digitalization. The digital demodulator block (DEM) provides a synchronous bit stream. Datasheet CFR0011-120-00 Revision 3.0 163 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 30.2.2 Synthesizer The RF Synthesizer generates the quadrature LO signal for the mixer, but also generates the modulated TX output signal. The Digitally Controlled Oscillator (DCO) runs at twice the required frequency and a dedicated divide-by-2 circuit generates the 2.4 GHz signals in the required phase relations. The reference frequency is the 32 MHz crystal clock. The modulation of the TX frequency is performed by 2-point modulation. 30.2.3 Transmitter The RF power amplifier (RFPA) is an extremely efficient Class-D structure, providing typically the power ranging from -19.5 dBm to +2.5 dBm to the antenna. It is fed by the DC ’s divide-by-2 circuit and delivers its TX power to the antenna pin through the combined RX/TX matching circuit. 30.2.4 RFIO The RX/TX combiner block is a unique feature of the DA14531. It makes sure that the received power is applied to the LNA with minimum losses towards the RFPA. In TX mode, the LNA poses a minimal load for the RFPA and its input pins are protected from the RFPA. In both modes, the single ended RFIO port is matched to a resistor of 50 Ω in order to provide the simplest possible interfacing to the antenna on the printed circuit board. 30.2.5 Biasing All RF blocks are supplied by on-chip LDOs. The bias scheme is programmable and optimized for minimum power consumption. 30.2.6 RF Monitoring The Radio is equipped with a monitoring block whose responsibility is to acquire the data provided by the RF Unit and other analog resources, to combine them in words of 32 bits (when necessary), and to store them in system’s memory. Data can be the output of the Demodulator (I and Q) or be provided by the GPADC. With the monitoring block, production tests of the corresponding block can be achieved. Datasheet CFR0011-120-00 Revision 3.0 164 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31 Registers This section contains a detailed view of the DA14531 registers. It is organized as follows: an overview table is presented initially, which depicts all register names, addresses, and descriptions. A detailed bit level description of each register follows. The register file of the Arm Cortex-M0+ can be found in the following documents available on the website: Devices Generic User Guide: https://developer.arm.com/docs/238818831/10/getting-started-with-cortex-m0-cortex-m0-cortex-m3and-cortex-m4-full-licensee-bundles Technical Reference Manual: https://developer.arm.com/docs/ddi0484/c/preface These documents contain the register descriptions for the Nested Vectored Interrupt Controller (NVIC), the System Control Block (SCB), and the System Timer (SysTick). 31.1 Analog Miscellaneous Registers Table 58: Register map anamisc2632_bif_00 Address Register Description 0x50001600 CLK_REF_SEL_REG Select clock for oscillator calibration 0x50001602 CLK_REF_CNT_REG Count value for oscillator calibration 0x50001604 CLK_REF_VAL_L_RE G XTAL32M reference cycles, lower 16 bits 0x50001606 CLK_REF_VAL_H_RE G XTAL32M reference cycles, higher 16 bits Table 59: CLK_REF_SEL_REG (0x50001600) Bit Mode Symbol Description Reset 3 R/W EXT_CNT_EN_SEL 0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL. 1 : Enable XTAL_CNT counter from an external input. 0x0 2 R/W REF_CAL_START Writing a '1' starts a calibration of the clock selected by CLK_REF_SEL_REG[REF_CLK_SEL]. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready. 0x0 1:0 R/W REF_CLK_SEL Select clock input for calibration: 0x0 : RC32K 0x1 : RC32M 0x2 : XTAL32K 0x3 : RCX 0x0 Datasheet CFR0011-120-00 Revision 3.0 165 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 60: CLK_REF_CNT_REG (0x50001602) Bit Mode Symbol Description Reset 15:0 R/W REF_CNT_VAL Indicates the calibration time, with a decrement counter to 1. 0x0 Table 61: CLK_REF_VAL_L_REG (0x50001604) Bit Mode Symbol Description Reset 15:0 R XTAL_CNT_VAL Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL 0x0 Table 62: CLK_REF_VAL_H_REG (0x50001606) Bit Mode Symbol Description Reset 15:0 R XTAL_CNT_VAL Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL 0x0 Datasheet CFR0011-120-00 Revision 3.0 166 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.2 BLE Core Registers Table 63: Register map BLE Address Register Description 0x40000000 BLE_RWBLECNTL_R EG BLE Control register 0x40000004 BLE_VERSION_REG Version register 0x40000008 BLE_RWBLECONF_R EG Configuration register 0x4000000C BLE_INTCNTL_REG Interrupt controller register 0x40000010 BLE_INTSTAT_REG Interrupt status register 0x40000014 BLE_INTRAWSTAT_R EG Interrupt raw status register 0x40000018 BLE_INTACK_REG Interrupt acknowledge register 0x4000001C BLE_BASETIMECNT_ REG Base time reference counter 0x40000020 BLE_FINETIMECNT_ REG Fine time reference counter 0x40000024 BLE_BDADDRL_REG BLE device address LSB register 0x40000028 BLE_BDADDRU_REG BLE device address MSB register 0x4000002C BLE_CURRENTRXDE SCPTR_REG Rx Descriptor Pointer for the Receive Buffer Chained List 0x40000030 BLE_DEEPSLCNTL_R EG Deep-Sleep control register 0x40000034 BLE_DEEPSLWKUP_ REG Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device 0x40000038 BLE_DEEPSLSTAT_R EG Duration of the last deep sleep phase register 0x4000003C BLE_ENBPRESET_R EG Time in low power oscillator cycles register 0x40000040 BLE_FINECNTCORR_ REG Phase correction value register 0x40000044 BLE_BASETIMECNTC ORR_REG Base Time Counter 0x40000050 BLE_DIAGCNTL_REG Diagnostics Register 0x40000054 BLE_DIAGSTAT_REG Debug use only 0x40000058 BLE_DEBUGADDMAX _REG Upper limit for the memory zone 0x4000005C BLE_DEBUGADDMIN _REG Lower limit for the memory zone 0x40000060 BLE_ERRORTYPEST AT_REG Error Type Status registers 0x40000064 BLE_SWPROFILING_ REG Software Profiling register Datasheet CFR0011-120-00 Revision 3.0 167 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Address Register Description 0x40000074 BLE_RADIOCNTL1_R EG Radio interface control register 0x40000080 BLE_RADIOPWRUPD N_REG RX/TX power up/down phase register 0x40000090 BLE_ADVCHMAP_RE G Advertising Channel Map 0x400000A0 BLE_ADVTIM_REG Advertising Packet Interval 0x400000A4 BLE_ACTSCANSTAT _REG Active scan register 0x400000B0 BLE_WLPUBADDPTR _REG Start address of public devices list 0x400000B4 BLE_WLPRIVADDPT R_REG Start address of private devices list 0x400000B8 BLE_WLNBDEV_REG Devices in white list 0x400000C0 BLE_AESCNTL_REG Start AES register 0x400000C4 BLE_AESKEY31_0_R EG AES encryption key 0x400000C8 BLE_AESKEY63_32_ REG AES encryption key 0x400000CC BLE_AESKEY95_64_ REG AES encryption key 0x400000D0 BLE_AESKEY127_96 _REG AES encryption key 0x400000D4 BLE_AESPTR_REG Pointer to the block to encrypt/decrypt 0x400000D8 BLE_TXMICVAL_REG AES / CCM plain MIC value 0x400000DC BLE_RXMICVAL_REG AES / CCM plain MIC value 0x400000E0 BLE_RFTESTCNTL_R EG RF Testing Register 0x400000E4 BLE_RFTESTTXSTAT _REG RF Testing Register 0x400000E8 BLE_RFTESTRXSTAT _REG RF Testing Register 0x400000F0 BLE_TIMGENCNTL_R EG Timing Generator Register 0x400000F4 BLE_GROSSTIMTGT _REG Gross Timer Target value 0x400000F8 BLE_FINETIMTGT_R EG Fine Timer Target value 0x400000FC BLE_SAMPLECLK_R EG Samples the Base Time Counter 0x40000100 BLE_COEXIFCNTL0_ REG Coexistence interface Control 0 Register 0x40000104 BLE_COEXIFCNTL1_ REG Coexistence interface Control 1 Register 0x40000108 BLE_BLEMPRIO0_RE G Coexistence interface Priority 0 Register Datasheet CFR0011-120-00 Revision 3.0 168 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Address Register Description 0x4000010C BLE_BLEMPRIO1_RE G Coexistence interface Priority 1 Register 0x40000200 BLE_CNTL2_REG BLE Control Register 2 0x40000208 BLE_EM_BASE_REG Exchange Memory Base Register 0x4000020C BLE_DIAGCNTL2_RE G Debug use only 0x40000210 BLE_DIAGCNTL3_RE G Debug use only Table 64: BLE_RWBLECNTL_REG (0x40000000) Bit Mode Symbol Description Reset 31 R0/W MASTER_SOFT_R ST Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 30 R0/W MASTER_TGSOFT _RST Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 29 R/W REG_SOFT_RST Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that INT STAT will not be cleared, so the user should also write to BLE_INTACK_REG after the SW Reset 0x0 28 R0/W SWINT_REQ Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 26 R0/W RFTEST_ABORT Abort the current RF Testing defined as per CSFORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested: 1) In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2) In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. 0x0 25 R0/W ADVERT_ABORT Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 24 R0/W SCAN_ABORT Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 Datasheet CFR0011-120-00 Revision 3.0 169 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 22 R/W MD_DSB 0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are. value forced by SW from Tx Descriptor value just saved in Rx Descriptor during reception 0x0 21 R/W SN_DSB 0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptor value ignored in Rx, where no SN error reported. 0x0 20 R/W NESN_DSB 0: Normal operation of Acknowledge 1: Acknowledge scheme disabled: value forced by SW from Tx Descriptor value ignored in Rx, where no NESN error reported. 0x0 19 R/W CRYPT_DSB 0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data. 0x0 18 R/W WHIT_DSB 0: Normal operation. Whitening enabled. 1: Whitening disabled. 0x0 17 R/W CRC_DSB 0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx. 0x0 16 R/W HOP_REMAP_DSB 0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled 0x0 13:12 R/W - 9 R/W ADVERTFILT_EN Advertising Channels Error Filtering Enable control 0: BLE Core reports all errors to RW-BLE Software 1: BLE Core reports only correctly received packet, without error to RW-BLE Software 0x0 8 R/W RWBLE_EN 0: Disable BLE Core Exchange Table pre-fetch mechanism. 1: Enable BLE Core Exchange table pre-fetch mechanism. 0x0 7:4 R/W RXWINSZDEF Default Rx Window size in us. Used when device: is master connected performs its second receipt. 0 is not a valid value. Recommended value is 10 (in decimal). 0x0 Datasheet CFR0011-120-00 0x0 Revision 3.0 170 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2:0 R/W SYNCERR Indicates the maximum number of errors allowed to recognize the synchronization word. 0x0 Table 65: BLE_VERSION_REG (0x40000004) Bit Mode Symbol Description Reset 31:24 R TYP BLE Core Type 0x7 23:16 R REL BLE Core version Major release number. 0x1 15:8 R UPG BLE Core upgrade Upgrade number. 0x0 7:0 R BUILD BLE Core Build Build number. 0x0 Table 66: BLE_RWBLECONF_REG (0x40000008) Bit Mode Symbol Description Reset 29:24 R ADD_WIDTH Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary. 0xF 22:16 R RFIF Radio Interface ID 0x2 13:8 R CLK_SEL Operating Frequency (in MHz) 0x0 6 R DECIPHER 0: AES deciphering not present 0x0 5 R DMMODE 0: BLE Core is used as a standalone BLE device 0x0 4 R INTMODE 1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement 0x1 3 R COEX 1: WLAN Coexistence mechanism present 0x1 2 R USEDBG 1: Diagnostic port instantiated 0x1 1 R USECRYPT 1: AES-CCM Encryption block present 0x1 0 R BUSWIDTH Processor bus width: 1: 32 bits 0x1 Table 67: BLE_INTCNTL_REG (0x4000000C) Bit Mode Symbol Description Reset 15 R/W CSCNTDEVMSK CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e. advertising, scanning, initiating, and connection) 0: CSCNT Interrupt not generated during events. 1: CSCNT Interrupt generated during events. 0x1 14:10 R - 9 R/W SWINTMSK Datasheet CFR0011-120-00 0x0 SW triggered interrupt Mask 0: Interrupt not generated 1: Interrupt generated Revision 3.0 171 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 8 R/W EVENTAPFAINTMS K End of event / anticipated pre-fetch abort interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x1 7 R/W FINETGTIMINTMSK Fine Target Timer Mask 0: Interrupt not generated 1: Interrupt generated 0x0 6 R/W GROSSTGTIMINTM SK Gross Target Timer Mask 0: Interrupt not generated 1: Interrupt generated 0x0 5 R/W ERRORINTMSK Error Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x0 4 R/W CRYPTINTMSK Encryption engine Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x1 3 R/W EVENTINTMSK End of event Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x1 2 R/W SLPINTMSK Sleep Mode Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x1 1 R/W RXINTMSK Rx Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x1 0 R/W CSCNTINTMSK 625us Base Time Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0x1 Table 68: BLE_INTSTAT_REG (0x40000010) Bit Mode Symbol Description Reset 9 R SWINTSTAT SW triggered interrupt status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending 0x0 8 R EVENTAPFAINTST AT End of event / Anticipated Pre-Fetch Abort interrupt status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. 0x0 7 R FINETGTIMINTSTA T Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. 0x0 Datasheet CFR0011-120-00 Revision 3.0 172 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 6 R GROSSTGTIMINTS TAT Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. 0x0 5 R ERRORINTSTAT Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending. 0x0 4 R CRYPTINTSTAT Masked Encryption engine interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. 0x0 3 R EVENTINTSTAT Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. 0x0 2 R SLPINTSTAT Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. 0x0 1 R RXINTSTAT Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending. 0x0 0 R CSCNTINTSTAT Masked 625us base time reference interrupt status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending. 0x0 Table 69: BLE_INTRAWSTAT_REG (0x40000014) Bit Mode Symbol Description Reset 9 R SWINTRAWSTAT SW triggered interrupt raw status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending. 0x0 8 R EVENTAPFAINTRA WSTAT End of event / Anticipated Pre-Fetch Abort interrupt raw status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. 0x0 7 R FINETGTIMINTRA WSTAT Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. 0x0 6 R GROSSTGTIMINTR AWSTAT Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. 0x0 5 R ERRORINTRAWST AT Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending. 0x0 Datasheet CFR0011-120-00 Revision 3.0 173 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R CRYPTINTRAWST AT Encryption engine interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. 0x0 3 R EVENTINTRAWST AT End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. 0x0 2 R SLPINTRAWSTAT Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. 0x0 1 R RXINTRAWSTAT Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending. 0x0 0 R CSCNTINTRAWST AT 625us base time reference interrupt raw status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending. 0x0 Table 70: BLE_INTACK_REG (0x40000018) Bit Mode Symbol Description Reset 9 R0/W SWINTACK SW triggered interrupt acknowledgement bit Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. Resets at 0 when action is performed 0x0 8 R0/W EVENTAPFAINTAC K End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt. This bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. Resets at 0 when action is performed 0x0 7 R0/W FINETGTIMINTACK Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags. Resets at 0 when action is performed 0x0 6 R0/W GROSSTGTIMINTA CK Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. Resets at 0 when action is performed 0x0 5 R0/W ERRORINTACK Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. Resets at 0 when action is performed 0x0 Datasheet CFR0011-120-00 Revision 3.0 174 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R0/W CRYPTINTACK Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. Resets at 0 when action is performed 0x0 3 R0/W EVENTINTACK End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed 0x0 2 R0/W SLPINTACK End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed 0x0 1 R0/W RXINTACK Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. Resets at 0 when action is performed 0x0 0 R0/W CSCNTINTACK 625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. Resets at 0 when action is performed 0x0 Table 71: BLE_BASETIMECNT_REG (0x4000001C) Bit Mode Symbol Description Reset 26:0 R BASETIMECNT Value of the 625us base time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW 0x0 Table 72: BLE_FINETIMECNT_REG (0x40000020) Bit Mode Symbol Description Reset 9:0 R FINECNT Value of the current s fine time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration 0x0 Datasheet CFR0011-120-00 Revision 3.0 175 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 73: BLE_BDADDRL_REG (0x40000024) Bit Mode Symbol Description Reset 31:0 R/W BDADDRL Bluetooth Low Energy Device Address. LSB part. 0x0 Table 74: BLE_BDADDRU_REG (0x40000028) Bit Mode Symbol Description Reset 16 R/W PRIV_NPUB Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address 0x0 15:0 R/W BDADDRU Bluetooth Low Energy Device Address. MSB part. 0x0 Table 75: BLE_CURRENTRXDESCPTR_REG (0x4000002C) Bit Mode Symbol Description Reset 31:16 R/W ETPTR Exchange Table Pointer that determines the starting point of the Exchange Table 0x0 14:0 R/W CURRENTRXDESC PTR Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List 0x0 Table 76: BLE_DEEPSLCNTL_REG (0x40000030) Bit Mode Symbol Description Reset 31 R/W EXTWKUPDSB External Wake-Up disable 0: RW-BLE Core can be woken by external wakeup 1: RW-BLE Core cannot be woken up by external wake-up 0x0 15 R DEEP_SLEEP_STA T Indicator of current Deep Sleep clock mux status: 0: RW-BLE Core is not yet in Deep Sleep Mode 1: RW-BLE Core is in Deep Sleep Mode (only low_power_clk is running) 0x0 4 R/W SOFT_WAKEUP_R EQ Wake Up Request from BLE Software. Applies when system is in Deep Sleep Mode. It wakes up the BLE Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 3 R0/W DEEP_SLEEP_CO RR_EN 625us base time reference integer and fractional part correction. Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0x0 Datasheet CFR0011-120-00 Revision 3.0 176 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2 R0/W DEEP_SLEEP_ON 0: BLE Core in normal active mode 1: Request RW-BLE Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge. 0x0 1:0 R/W DEEP_SLEEP_IRQ _EN Always set to "3" when DEEP_SLEEP_ON is set to "1". It controls the generation of BLE_WAKEUP_LP_IRQ. 0x0 Table 77: BLE_DEEPSLWKUP_REG (0x40000034) Bit Mode Symbol Description Reset 31:0 R/W DEEPSLTIME Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz 0x0 Table 78: BLE_DEEPSLSTAT_REG (0x40000038) Bit Mode Symbol Description Reset 31:0 R DEEPSLDUR Actual duration of the last deep sleep phase measured in low_power_clk clock cycle. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low_power_clk clock cycle until the end of the deep sleep phase. 0x0 Table 79: BLE_ENBPRESET_REG (0x4000003C) Bit Mode Symbol Description Reset 31:21 R/W TWEXT Minimum and recommended value is "TWIRQ_RESET + 1". In the case of wake-up due to an external wake-up request, TWEXT specifies the time delay in low power oscillator cycles to deassert BLE_WAKEUP_LP_IRQ. Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ]. Range is [0...64 ms] for 32kHz; [0...62.5 ms] for 32.768kHz 0x0 Datasheet CFR0011-120-00 Revision 3.0 177 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 20:10 R/W TWIRQ_SET Minimum value is "TWIRQ_RESET + 1". Time in low power oscillator cycles to set BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...64 ms] for 32kHz; [0...62.5 ms] for 32.768kHz 0x0 9:0 R/W TWIRQ_RESET Recommended value is 1. Time in low power oscillator cycles to reset BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...32 ms] for 32kHz; [0...31.25 ms] for 32.768kHz. 0x0 Table 80: BLE_FINECNTCORR_REG (0x40000040) Bit Mode Symbol Description Reset 9:0 R/W FINECNTCORR Phase correction value for the 625us reference counter (i.e. Fine Counter) in us. 0x0 Table 81: BLE_BASETIMECNTCORR_REG (0x40000044) Bit Mode Symbol Description Reset 26:0 R/W BASETIMECNTCO RR Base Time Counter correction value. 0x0 Table 82: BLE_DIAGCNTL_REG (0x40000050) Bit Mode Symbol Description Reset 31 R/W DIAG3_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 29:24 R/W DIAG3 Only relevant when DIAG3_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG3. 0x0 23 R/W DIAG2_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 21:16 R/W DIAG2 Only relevant when DIAG2_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG2. 0x0 Datasheet CFR0011-120-00 Revision 3.0 178 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 15 R/W DIAG1_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 13:8 R/W DIAG1 Only relevant when DIAG1_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG1. 0x0 7 R/W DIAG0_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 5:0 R/W DIAG0 Only relevant when DIAG0_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG0. 0x0 Table 83: BLE_DIAGSTAT_REG (0x40000054) Bit Mode Symbol Description Reset 31:24 R DIAG3STAT Directly connected to ble_dbg3[7:0] output. Debug use only. 0x0 23:16 R DIAG2STAT Directly connected to ble_dbg2[7:0] output. Debug use only. 0x0 15:8 R DIAG1STAT Directly connected to ble_dbg1[7:0] output. Debug use only. 0x0 7:0 R DIAG0STAT Directly connected to ble_dbg0[7:0] output. Debug use only. 0x0 Table 84: BLE_DEBUGADDMAX_REG (0x40000058) Bit Mode Symbol Description Reset 31:16 R/W REG_ADDMAX Upper limit for the Register zone indicated by the reg_inzone flag 0x0 15:0 R/W EM_ADDMAX Upper limit for the Exchange Memory zone indicated by the em_inzone flag 0x0 Table 85: BLE_DEBUGADDMIN_REG (0x4000005C) Bit Mode Symbol Description Reset 31:16 R/W REG_ADDMIN Lower limit for the Register zone indicated by the reg_inzone flag 0x0 15:0 R/W EM_ADDMIN Lower limit for the Exchange Memory zone indicated by the em_inzone flag 0x0 Datasheet CFR0011-120-00 Revision 3.0 179 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 86: BLE_ERRORTYPESTAT_REG (0x40000060) Bit Mode Symbol Description Reset 17 R CONCEVTIRQ_ER ROR Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the BLE Software. 0: No error 1: Error occurred 0x0 16 R RXDATA_PTR_ER ROR Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure. 0: No error 1: Error occurred 0x0 15 R TXDATA_PTR_ERR OR Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events, or during Master / Slave connections with non-null packet length: this is a major programming failure. 0: No error 1: Error occurred 0x0 14 R RXDESC_EMPTY_ ERROR Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure. 0: No error 1: Error occurred 0x0 13 R TXDESC_EMPTY_ ERROR Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure. 0: No error 1: Error occurred 0x0 12 R CSFORMAT_ERRO R Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred 0x0 11 R LLCHMAP_ERROR Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred 0x0 10 R ADV_UNDERRUN Indicates Advertising Interval Under run, occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than the expected value. 0: No error 1: Error occurred 0x0 Datasheet CFR0011-120-00 Revision 3.0 180 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 9 R IFS_UNDERRUN Indicates Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred 0x0 8 R WHITELIST_ERRO R Indicates White List Timeout error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred 0x0 7 R EVT_CNTL_APFM_ ERROR Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured 0x0 6 R EVT_SCHDL_APF M_ERROR Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured 0x0 5 R EVT_SCHDL_ENTR Y_ERROR Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) 0: No error 1: Error occurred 0x0 4 R EVT_SCHDL_EMA CC_ERROR Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read 0: No error 1: Error occurred 0x0 3 R RADIO_EMACC_E RROR Indicates Radio Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and data are corrupted. 0: No error 1: Error occurred 0x0 2 R PKTCNTL_EMACC _ERROR Indicates Packet Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred 0x0 Datasheet CFR0011-120-00 Revision 3.0 181 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 1 R RXCRYPT_ERROR Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller 0: No error 1: Error occurred 0x0 0 R TXCRYPT_ERROR Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 0: No error 1: Error occurred 0x0 Table 87: BLE_SWPROFILING_REG (0x40000064) Bit Mode Symbol Description Reset 31:0 R/W SWPROFVAL Software Profiling register: used by BLE Software for profiling purpose: this value is copied on Diagnostic port 0x0 Table 88: BLE_RADIOCNTL1_REG (0x40000074) Bit Mode Symbol 31:21 - - 20:16 R/W XRFSEL Description Reset 0x0 Extended radio selection field, Must be set to "2". 0x0 Table 89: BLE_RADIOPWRUPDN_REG (0x40000080) Bit Mode Symbol Description Reset 30:24 R/W RTRIP_DELAY Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in usec. 0x0 23:16 R/W RXPWRUP This register holds the length in s of the RX power up phase for the current radio device. Default value is 210 usec (reset value). Operating range depends on the selected radio. 0xD2 Datasheet CFR0011-120-00 Revision 3.0 182 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 11:8 R/W TXPWRDN This register extends the length in s of the TX power down phase for the current radio device. Default value is 3 usec (reset value). Operating range depends on the selected radio. 0x3 7:0 R/W TXPWRUP This register holds the length in s of the TX power up phase for the current radio device. Default value is 210 usec (reset value). Operating range depends on the selected radio. 0xD2 Table 90: BLE_ADVCHMAP_REG (0x40000090) Bit Mode Symbol Description Reset 2:0 R/W ADVCHMAP Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37. 0x7 Table 91: BLE_ADVTIM_REG (0x400000A0) Bit Mode Symbol Description Reset 13:0 R/W ADVINT Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in us. Value to program depends on the used Advertising Packet type and the device filtering policy. 0x0 Table 92: BLE_ACTSCANSTAT_REG (0x400000A4) Bit Mode Symbol Description Reset 24:16 R BACKOFF Active scan mode back-off counter initialization value. 0x1 8:0 R UPPERLIMIT Active scan mode upper limit counter value. 0x1 Table 93: BLE_WLPUBADDPTR_REG (0x400000B0) Bit Mode Symbol Description Reset 15:0 R/W WLPUBADDPTR Start address pointer of the public devices white list. 0x0 Datasheet CFR0011-120-00 Revision 3.0 183 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 94: BLE_WLPRIVADDPTR_REG (0x400000B4) Bit Mode Symbol Description Reset 15:0 R/W WLPRIVADDPTR Start address pointer of the private devices white list. 0x0 Table 95: BLE_WLNBDEV_REG (0x400000B8) Bit Mode Symbol Description Reset 15:8 R/W NBPRIVDEV Number of private devices in the white list. 0x0 7:0 R/W NBPUBDEV Number of public devices in the white list. 0x0 Table 96: BLE_AESCNTL_REG (0x400000C0) Bit Mode Symbol Description Reset 1 R/W AES_MODE 0: Cipher mode 1: Decipher mode 0x0 0 R0/W AES_START Writing a 1 starts AES-128 ciphering/deciphering process. This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked) 0x0 Table 97: BLE_AESKEY31_0_REG (0x400000C4) Bit Mode Symbol Description Reset 31:0 R/W AESKEY31_0 AES encryption 128-bit key. Bit 31 down to 0 0x0 Table 98: BLE_AESKEY63_32_REG (0x400000C8) Bit Mode Symbol Description Reset 31:0 R/W AESKEY63_32 AES encryption 128-bit key. Bit 63 down to 32 0x0 Table 99: BLE_AESKEY95_64_REG (0x400000CC) Bit Mode Symbol Description Reset 31:0 R/W AESKEY95_64 AES encryption 128-bit key. Bit 95 down to 64 0x0 Datasheet CFR0011-120-00 Revision 3.0 184 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 100: BLE_AESKEY127_96_REG (0x400000D0) Bit Mode Symbol Description Reset 31:0 R/W AESKEY127_96 AES encryption 128-bit key. Bit 127 down to 96 0x0 Table 101: BLE_AESPTR_REG (0x400000D4) Bit Mode Symbol Description Reset 15:0 R/W AESPTR Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored. 0x0 Table 102: BLE_TXMICVAL_REG (0x400000D8) Bit Mode Symbol Description Reset 31:0 R TXMICVAL AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx) 0x0 Table 103: BLE_RXMICVAL_REG (0x400000DC) Bit Mode Symbol Description Reset 31:0 R RXMICVAL AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet. 0x0 Table 104: BLE_RFTESTCNTL_REG (0x400000E0) Bit Mode Symbol Description Reset 31 R/W INFINITERX Applicable in RF Test Mode only 0: Normal mode of operation 1: Infinite Rx window 0x0 27 R/W RXPKTCNTEN Applicable in RF Test Mode only 0: Rx packet count disabled 1: Rx packet count enabled, and reported in CSRXCCMPKTCNT and BLE_RFTESTRXSTAT_REG[RXPKTCNT] on RF abort command 0x0 15 R/W INFINITETX Applicable in RF Test Mode only 0: Normal mode of operation. 1: Infinite Tx packet / Normal start of a packet but endless payload 0x0 Datasheet CFR0011-120-00 Revision 3.0 185 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 14 R/W TXLENGTHSRC Applicable only in Tx/Rx RF Test mode 0: Normal mode of operation: TxDESCTXADVLEN controls the Tx packet payload size 1: Uses BLE_RFTESTCNTL_REG[TXLENGTH] packet length (can support up to 512 bytes transmit) 0x0 13 R/W PRBSTYPE Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload are PRBS9 type 1: Tx Packet Payload are PRBS15 type 0x0 12 R/W TXPLDSRC Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload source is the Control Structure 1: Tx Packet Payload are PRBS generator 0x0 11 R/W TXPKTCNTEN Applicable in RF Test Mode only 0: Tx packet count disabled 1: Tx packet count enabled, and reported in CSTXCCMPKTCNT and BLE_RFTESTTXSTAT_REG[TXPKTCNT] on RF abort command 0x0 8:0 R/W TXLENGTH Applicable only for Tx/Rx RF Test mode, and valid when BLE_RFTESTCNTL_REG[TXLENGTHSRC] =1 Tx packet length in number of byte 0x0 Table 105: BLE_RFTESTTXSTAT_REG (0x400000E4) Bit Mode Symbol Description Reset 31:0 R TXPKTCNT Reports number of transmitted packet during Test Modes. Value is valid if BLE_RFTESTCNTL_REG[TXPKTCNTEN] is set 0x0 Table 106: BLE_RFTESTRXSTAT_REG (0x400000E8) Bit Mode Symbol Description Reset 31:0 R RXPKTCNT Reports number of correctly received packet during Test Modes (no sync error, no CRC error). Value is valid if BLE_RFTESTCNTL_REG[RXPKTCNTEN] is set 0x0 Datasheet CFR0011-120-00 Revision 3.0 186 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 107: BLE_TIMGENCNTL_REG (0x400000F0) Bit Mode Symbol Description Reset 31 R/W APFM_EN Controls the Anticipated pre-Fetch Abort mechanism 0: Disabled 1: Enabled 0x1 25:16 R/W PREFETCHABORT _TIME Defines the instant in usec at which immediate abort is required after anticipated pre-fetch abort. 0x1FE 8:0 R/W PREFETCH_TIME Defines Exchange Table pre-fetch instant in us 0x96 Table 108: BLE_GROSSTIMTGT_REG (0x400000F4) Bit Mode Symbol Description Reset 22:0 R/W GROSSTARGET Gross Timer Target value on which a ble_grosstgtim_irq must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET[22:0] = BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0. 0x0 Table 109: BLE_FINETIMTGT_REG (0x400000F8) Bit Mode Symbol Description Reset 26:0 R/W FINETARGET Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625 usec: interrupt is generated only when FINETARGET = BASETIMECNT 0x0 Table 110: BLE_SAMPLECLK_REG (0x400000FC) Bit Mode Symbol 31:1 - - 0 R0/W SAMP Datasheet CFR0011-120-00 Description Reset 0x0 Writing a 1 samples the Base Time Counter value in BASETIMECNT register. Resets at 0 when action is performed. Revision 3.0 187 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 111: BLE_COEXIFCNTL0_REG (0x40000100) Bit Mode Symbol Description Reset 21:20 R/W WLCRXPRIOMODE Defines Bluetooth Low Energy packet ble_rx mode behavior. 00: Rx indication excluding Rx Power up delay (starts when correlator is enabled) 01: Rx indication including Rx Power up delay 10: Rx High priority indicator 11: n/a 0x0 17:16 R/W WLCTXPRIOMODE Defines Bluetooth Low Energy packet ble_tx mode behavior 00: Tx indication excluding Tx Power up delay 01: Tx indication including Tx Power up delay 10: Tx High priority indicator 11: n/a 0x0 7:6 R/W WLANTXMSK Determines how wlan_tx impact BLE Tx and Rx 00: wlan_tx has no impact (default mode) 01: wlan_tx can stop BLE Tx, no impact on BLE Rx 10: wlan_tx can stop BLE Rx, no impact on BLE Tx 11: wlan_tx can stop both BLE Tx and BLE Rx 0x0 5:4 R/W WLANRXMSK Determines how wlan_rx impact BLE Tx and Rx 00: wlan_rx has no impact 01: wlan_rx can stop BLE Tx, no impact on BLE Rx (default mode) 10: wlan_rx can stop BLE Rx, no impact on BLE Tx 11: wlan_rx can stop both BLE Tx and BLE Rx 0x1 1 R/W SYNCGEN_EN Determines whether ble_sync is generated or not. 0: ble_sync pulse not generated 1: ble_sync pulse generated 0x0 0 R/W COEX_EN Enable / Disable control of the MWS/WLAN Coexistence control 0: Coexistence interface disabled 1: Coexistence interface enabled 0x0 Table 112: BLE_COEXIFCNTL1_REG (0x40000104) Bit Mode Symbol Description Reset 28:24 R/W WLCPRXTHR Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines the threshold for Rx priority setting. If ble_pti[3:0] output value is greater than WLCPRXTHR, then Rx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface 0x0 Datasheet CFR0011-120-00 Revision 3.0 188 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 20:16 R/W WLCPTXTHR Applies on ble_tx if WLCTXPRIOMODE equals 10 Determines the threshold for priority setting. If ble_pti[3:0] output value is greater than WLCPTXTHR, then Tx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface 0x0 14:8 R/W WLCPDURATION Applies on ble_tx if WLCTXPRIOMODE equals 10 Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines how many s the priority information must be maintained Note that if WLCPDURATION = 0x00, then Tx/Rx priority levels are maintained till Tx/Rx EN are deasserted. 0x0 6:0 R/W WLCPDELAY Applies on ble_tx if WLCTXPRIOMODE equals 10. Applies on ble_rx if WLCRXPRIOMODE equals 10. Determines the delay (in us) in Tx/Rx enables rises the time Bluetooth Low energy Tx/Rx priority has to be provided . 0x0 Table 113: BLE_BLEMPRIO0_REG (0x40000108) Bit Mode Symbol Description Reset 31:28 R/W BLEM7 Set Priority value for Passive Scanning 0x3 27:24 R/W BLEM6 Set Priority value for Non-Connectable Advertising 0x4 23:20 R/W BLEM5 Set Priority value for Connectable Advertising BLE message 0x8 19:16 R/W BLEM4 Set Priority value for Active Scanning BLE message 0x9 15:12 R/W BLEM3 Set Priority value for Initiating (Scanning) BLE message 0xA 11:8 R/W BLEM2 Set Priority value for Data Channel transmission BLE message 0xD 7:4 R/W BLEM1 Set Priority value for LLCP BLE message 0xE 3:0 R/W BLEM0 Set Priority value for Initiating (Connection Request Response) BLE message 0xF Table 114: BLE_BLEMPRIO1_REG (0x4000010C) Bit Mode Symbol Description Reset 31:28 R/W BLEMDEFAULT Set default priority value for other BLE message than those defined above 0x3 Datasheet CFR0011-120-00 Revision 3.0 189 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 115: BLE_CNTL2_REG (0x40000200) Bit Mode Symbol 31:25 R - 0x0 24 R/W BLE_PHY_ERR_M SK_N 0x0 23 R/W BLE_ARP_ERR_M SK_N When cleared to "0" then it masks the BLE_ARP_ERR_STAT in order to not trigger a BLE_ERROR_IRQ. 0x0 22 RW1C BLE_ARP_PHY_ER R_STAT When set to "1" then an error occured in BLE ARP sub-block and the BLE_GEN_IRQ will be aserted. It will be set if the ARP_ERROR or PHY_ERROR will be asserted and if the BLE_ARP_ERR_MSK is set to "1". Writing the value "1" will acknowledge and clear this field. 0x0 21 R/W BLE_RSSI_SEL 0: (default) Select Peak-hold RSSI value during the SYNC_FOUND event: CS->RXRSSI[7:0] = RF_RSSI_RESULT_REG>RSSI_LATCHED_RD[9:2]. 1: Select the Average RSSI value during the SYNC_FOUND event: CS->RXRSSI[7:0] = RF_RSSI_RESULT_REG>RSSI_AVG_RD[9:2]. 0x0 20 R WAKEUPLPSTAT The status of the BLE_WAKEUP_LP_IRQ. The Interrupt Service Routine of BLE_WAKEUP_LP_IRQ should return only when the WAKEUPLPSTAT is cleared. Note that BLE_WAKEUP_LP_IRQ is automatically acknowledged after the power up of the Radio Subsystem, plus one Low Power Clock period. 0x0 19 R/W SW_RPL_SPI Keep to 0. 0x0 18 R/W BB_ONLY Keep to 0. 0x0 17 R/W BLE_PTI_SOURCE _SEL 0: Provide to COEX block the PTI value indicated by the Control Structure. Recommended value is "0". 1: Provide to COEX block the PTI value generated dynamically by the BLE core, which is based on the PTI of the Control Structure. 0x0 16:15 R - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 190 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 14:9 R/W BLE_CLK_SEL BLE Clock Select. Specifies the BLE master clock absolute frequency in MHz. Typical values are 16 and 8. Value depends on the selected XTAL frequency and the value of CLK_RADIO_REG[BLE_DIV] bitfield. For example, if XTAL oscillates at 16MHz and CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE master clock frequency is 8MHz and BLE_CLK_SEL should be set to value 8. The selected BLE master clock frequency (affected by BLE_DIV and BLE_CLK_SEL) must be modified and set only during the initialization time, i.e. before setting BLE_RWBLECNTL_REG[RWBLE_EN] to 1. Refer also to BLE_RWBLECONF_REG[CLK_SEL]. 0x0 8 R RADIO_PWRDN_A LLOW This active high signal indicates when it is allowed for the BLE core (embedded in the Radio subSystem power domain) to be powered down. After the assertion of the BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware sequence based on the Low Power clock will cause the assertion of RADIO_PWRDN_ALLOW. The RADIO_PWRDN_ALLOW will be cleared to "0" when the BLE core exits from the sleep state, i.e. when the BLE_SLP_IRQ will be asserted. 0x0 7 R MON_LP_CLK The SW can only write a "0" to this bit. Whenever a positive edge of the low power clock used by the BLE Timers is detected, then the HW will automatically set this bit to "1". This functionality will not work if BLE Timer is in reset state (refer to CLK_RADIO_REG[BLE_LP_RESET]). This bit can be used for SW synchronization, to debug the low power clock, etc. 0x0 6 R BLE_CLK_STAT 0: BLE uses low power clock 1: BLE uses master clock 0x0 5:4 R/W - 3 R/W BLE_DIAG_OVR 1: Overrule BLE_DIAG. 0: BLE_DIAG is not overruled. 0x0 2 R/W EMACCERRMSK Exchange Memory Access Error Mask: When cleared to "0" the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt. When set to "1" an BLE_ERROR_IRQ will be generated as long as EM_ACC_ERR is "1". 0x1 1 R0/W EMACCERRACK Exchange Memory Access Error Acknowledge. When the SW writes a "1" to this bit then the EMACCERRSTAT bit will be cleared. When the SW writes "0" it will have no affect. The read value is always "0". 0x0 Datasheet CFR0011-120-00 0x0 Revision 3.0 191 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R EMACCERRSTAT Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a "1" at EMACCERRACK bitfield. This bit will be set to "1" by the hardware when the controller will access an EM page that is not mapped according to the EM_MAPPING value. When this bit is "1" then the BLE_ERROR_IRQ will be asserted as long as EMACCERRMSK is "1". 0x0 Table 116: BLE_EM_BASE_REG (0x40000208) Bit Mode Symbol 31:17 R - 16:10 R/W BLE_EM_BASE_16 _10 9:0 R - Description Reset 0x0 The physical address on the system memory map of the base of the Exchange Memory. 0x0 0x0 Table 117: BLE_DIAGCNTL2_REG (0x4000020C) Bit Mode Symbol Description Reset 31 R/W DIAG7_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 30 R - 29:24 R/W DIAG7 Only relevant when DIAG7_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG7. 0x0 23 R/W DIAG6_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 22 R - 21:16 R/W DIAG6 Only relevant when DIAG6_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG6. 0x0 15 R/W DIAG5_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 14 R - 13:8 R/W DIAG5 Only relevant when DIAG5_EN= 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG5. 0x0 7 R/W DIAG4_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 0x0 Datasheet CFR0011-120-00 0x0 0x0 0x0 Revision 3.0 192 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol 6 R - 5:0 R/W DIAG4 Description Reset 0x0 Only relevant when DIAG4_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG4. 0x0 Table 118: BLE_DIAGCNTL3_REG (0x40000210) Bit Mode Symbol Description Reset 31 R/W DIAG7_INV If set, then the specific diagnostic bit will be inverted. 0x0 30:28 R/W DIAG7_BIT Selects which bit from the DIAG7 word will be forwarded to bit 7 of the BLE DIagnostic Port. 0x0 27 R/W DIAG6_INV If set, then the specific diagnostic bit will be inverted. 0x0 26:24 R/W DIAG6_BIT Selects which bit from the DIAG6 word will be forwarded to bit 6 of the BLE DIagnostic Port. 0x0 23 R/W DIAG5_INV If set, then the specific diagnostic bit will be inverted. 0x0 22:20 R/W DIAG5_BIT Selects which bit from the DIAG5 word will be forwarded to bit 5 of the BLE DIagnostic Port. 0x0 19 R/W DIAG4_INV If set, then the specific diagnostic bit will be inverted. 0x0 18:16 R/W DIAG4_BIT Selects which bit from the DIAG4 word will be forwarded to bit 4 of the BLE DIagnostic Port. 0x0 15 R/W DIAG3_INV If set, then the specific diagnostic bit will be inverted. 0x0 14:12 R/W DIAG3_BIT Selects which bit from the DIAG3 word will be forwarded to bit 3 of the BLE DIagnostic Port. 0x0 11 R/W DIAG2_INV If set, then the specific diagnostic bit will be inverted. 0x0 10:8 R/W DIAG2_BIT Selects which bit from the DIAG2 word will be forwarded to bit 2 of the BLE DIagnostic Port. 0x0 7 R/W DIAG1_INV If set, then the specific diagnostic bit will be inverted. 0x0 6:4 R/W DIAG1_BIT Selects which bit from the DIAG1 word will be forwarded to bit 1 of the BLE DIagnostic Port. 0x0 3 R/W DIAG0_INV If set, then the specific diagnostic bit will be inverted. 0x0 2:0 R/W DIAG0_BIT Selects which bit from the DIAG0 word will be forwarded to bit 0 of the BLE DIagnostic Port. 0x0 Datasheet CFR0011-120-00 Revision 3.0 193 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.3 Clock Generation and Reset Registers Table 119: Register map CRG Address Register Description 0x50000000 CLK_AMBA_REG HCLK, PCLK, divider and clock gates 0x50000002 CLK_FREQ_TRIM_RE G Xtal frequency trimming register 0x50000004 CLK_PER_REG Peripheral divider register 0x50000008 CLK_RADIO_REG Radio PLL control register 0x5000000A CLK_CTRL_REG Clock control register 0x50000010 PMU_CTRL_REG Power Management Unit control register 0x50000012 SYS_CTRL_REG System Control register 0x50000014 SYS_STAT_REG System status register 0x50000016 TRIM_CTRL_REG Control trimming of the XTAL32M 0x50000018 RAM_PWR_CTRL_RE G Control power state of System RAMS 0x50000020 CLK_RC32K_REG 32 kHz RC oscillator register 0x50000022 CLK_XTAL32K_REG 32 kHz XTAL oscillator register 0x50000024 CLK_RC32M_REG Fast RC control register 0x50000026 CLK_RCX_REG RCX-oscillator control register 0x50000028 BANDGAP_REG Bandgap trimming 0x5000002A ANA_STATUS_REG Status bit of analog (power management) circuits 0x50000030 XTAL32M_START_RE G Trim values for XTAL32M 0x50000032 XTAL32M_TRSTAT_R EG Read back value of current XTAL trimming 0x50000034 XTALRDY_CTRL_RE G Control register for XTALRDY IRQ 0x50000038 XTAL32M_CTRL0_RE G Control bits for XTAL32M 0x50000040 POR_PIN_REG Selects a GPIO pin for POR generation 0x50000042 POR_TIMER_REG Time for POR to happen 0x50000050 PMU_SLEEP_REG Bandgap refresh interval during sleep 0x50000052 POWER_CTRL_REG Power management control 0x50000054 POWER_LEVEL_REG Power management level and trim settings Table 120: CLK_AMBA_REG (0x50000000) Bit Mode Symbol Description Reset 7 R/W OTP_ENABLE Clock enable for OTP controller 0x0 6 R/W - Datasheet CFR0011-120-00 0x0 Revision 3.0 194 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 5:4 R/W PCLK_DIV APB interface clock (PCLK). Divider is cascaded with HCLK_DIV. PCLK is HCLK divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0x0 3:2 R/W - 1:0 R/W HCLK_DIV 0x0 AHB interface and microprocessor clock (HCLK). HCLK is source clock divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0x0 Table 121: CLK_FREQ_TRIM_REG (0x50000002) Bit Mode Symbol Description Reset 7:0 R/W XTAL32M_TRIM Xtal frequency fine trimming register. 0x00: highest frequency 0xFF: lowest frequency 0x80 Table 122: CLK_PER_REG (0x50000004) Bit Mode Symbol Description Reset 11 R/W QUAD_ENABLE Enable the Quadrature clock 0x1 10 R/W SPI_ENABLE Enable SPI clock 0x0 9:8 R/W - 7 R/W UART1_ENABLE Enable UART1 clock 0x0 6 R/W UART2_ENABLE Enable UART2 clock 0x0 5 R/W I2C_ENABLE Enable I2C clock 0x0 4 R/W WAKEUPCT_ENAB LE Enable Wakeup CaptureTimer clock 0x0 3 R/W TMR_ENABLE Enable TIMER0 and TIMER2 clock 0x0 2 R/W - 1:0 R/W TMR_DIV Datasheet CFR0011-120-00 0x0 0x0 Division factor for TIMER0 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 Revision 3.0 195 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 123: CLK_RADIO_REG (0x50000008) Bit Mode Symbol Description Reset 15:8 - - 7 R/W BLE_ENABLE Enable the BLE core clocks 0x0 6 R/W BLE_LP_RESET Reset for the BLE LP timer 0x1 5:4 R/W BLE_DIV Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL]. 0x0 3 R/W RFCU_ENABLE Enable the RF control Unit clock 0x0 2 R/W - 0x0 1:0 R/W - 0x0 0x0 Table 124: CLK_CTRL_REG (0x5000000A) Bit Mode Symbol Description Reset 7 R RUNNING_AT_XTA L32M Indicates that the XTAL32M clock is used as clock, and may not be switched off 0x0 6 R RUNNING_AT_RC3 2M Indicates that the RC32M clock is used as clock 0x1 5 R RUNNING_AT_LP_ CLK Indicates that either the LP_CLK is being used as system clock 0x0 4:3 R/W LP_CLK_SEL Sets the clock source of the LowerPower clock 0x0: RC32K 0x1: RCX 0x2: XTAL32K through the oscillator with an external Crystal. 0x3: XTAL32K through an external square wave generator (set PID of P0[3] to FUNC_GPIO) Change this setting before using this clock, and while RUNNING_AT_LP_CLK == 0. 0x0 2 R/W XTAL32M_DISABL E Setting this bit instantaneously disables the 32 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when "RUNNING_AT_XTAL32M is '1' to prevent deadlock. After resetting this bit, wait for XTAL32M_SETTLED or XTAL32M_TRIM_READY to become '1' before switching to XTAL32M clock source. 0x0 Datasheet CFR0011-120-00 Revision 3.0 196 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 1:0 R/W SYS_CLK_SEL Selects the clock source. 0x0: XTAL32M (check the XTAL32M_SETTLED and XTAL32M_TRIM_READY bits!!) 0x1: RC32M 0x2/0x3: LP_CLK 0x1 Table 125: PMU_CTRL_REG (0x50000010) Bit Mode Symbol Description Reset 6 R/W MAP_BANDGAP_E N Enable wakeup diagnostics mapping. When set, these functions are mapped (please set direction to output) P0[2]: BANDGAP_ENABLE P0[1]: Power WOKENUP Note: P0[2] assigned also to SWD_CLK, thus the debugger must be detached before entering into sleep mode with MAP_BANDGAP_EN=1. Refer also to SYS_STAT_REG->DBG_IS_UP. 0x0 5:4 R/W OTP_COPY_DIV Sets the HCLK division during OTP mirroring 0x0 3 R/W - 2 R/W RADIO_SLEEP Put the digital part of the radio in powerdown 0x1 1 R/W TIM_SLEEP Put PD_TIM in powerdown 0x1 0 R/W RESET_ON_WAKE UP Perform a Hardware Reset after waking up. Booter will be started. 0x0 0x0 Table 126: SYS_CTRL_REG (0x50000012) Bit Mode Symbol Description Reset 15 W SW_RESET Writing a '1' to this bit will reset the device, except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG ... 0x0 10 R/W TIMEOUT_DISABL E Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG. 0x0 9 R/W - 8:7 R/W DEBUGGER_ENAB LE Datasheet CFR0011-120-00 0x0 Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports. 0x0: no debugger enabled. 0x1: SW_CLK = P0[2], SW_DIO=P0[5] 0x2: SW_CLK = P0[2], SW_DIO=P0[1] 0x3: SW_CLK = P0[2], SW_DIO=P0[10] Revision 3.0 197 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 6 R/W OTPC_RESET_RE Q Reset request for the OTP controller. 0x0 5 R/W - 4 R/W OTP_COPY 3 R/W - 2 R/W DEV_PHASE 0x1 Enables OTP to SysRAM copy action after waking up PD_SYS 0x0 0x0 Sets the development phase mode. 0x0 If this bit is set, in combination with the OTP_COPY bit, the OTP DMA will emulate the OTP mirroring to System RAM. No actual writing to RAM is done, but the exact same amount of time is spend as if the mirroring would take place. This is to mimic the behavior as if the System Code is already in OTP, and the mirroring takes place after waking up, but the (development) code still resides in an external source. If this bit is set to '0' and OTP_COPY='1', then the OTP DMA will actually do the OTP mirroring at wakeup. 1:0 R/W REMAP_ADR0 Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: RAM (SysRAM1) 0x3: RAM (SysRAM3, 28 kBytes offset) This bitfield only takes affect after a Software Reset. 0x0 Table 127: SYS_STAT_REG (0x50000014) Bit Mode Symbol Description Reset 7 R XTAL32M_SETTLE D Indicates that XTAL32M has had its settle time, as defined by TRIM_CTRL_REG[XTAL_SETTLE_N] 0x0 6 R XTAL32M_TRIM_R EADY Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG. 0x1 5 R - 4 R DBG_IS_UP Indicates that the SW debugger is attached and in connection with the Cortex. 0x0 3 R TIM_IS_UP Indicates that PD_TIM is functional 0x0 2 R TIM_IS_DOWN Indicates that PD_TIM is in power down 0x1 1 R RAD_IS_UP Indicates that PD_RAD is functional 0x0 0 R RAD_IS_DOWN Indicates that PD_RAD is in power down 0x1 Datasheet CFR0011-120-00 0x0 Revision 3.0 198 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 128: TRIM_CTRL_REG (0x50000016) Bit Mode Symbol Description Reset 13:8 R/W XTAL_SETTLE_N Designates that the XTAL can be safely used as the CPU clock. When XTAL_CLK_CNT reases this value, the signal XTAL32M_SETTLED bit in the SYS_STAT_REG will be set. Counts in steps of 64 xtal clock-cycles. 0x3F 7:6 R/W XTAL_TRIM_SELE CT Select which source controls the XTAL trimming 0b00: xtal counter. Starts XTAL32M_START_REG[XTAL32M_START] after COUNT_N * 32 xtal pulses trim is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b01: xtal OK filter. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START], when xtal amplitude is ramping is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b10: statically forced off. Only uses CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b11: xtal OK filter, 2 stage. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START] switches to CLK_FREQ_TRIM_REG[XTAL32M_RAMP] after timeout (32us), and switches to CLK_FREQ_TRIM_REG[XTAL32M_TRIM] when xtal amplitude is ramping up. 0x0 5:0 R/W XTAL_COUNT_N Defines the number of XTAL cycles to be counted, before the xtal trimming is applied, in steps of 64 cycles. 0x01: 64 0x02: 128 0x3f: 4032 0x22 Table 129: RAM_PWR_CTRL_REG (0x50000018) Bit Mode Symbol Description Reset 5:4 R/W RAM3_PWR_CTRL See description of RAM1_PWR_CTRL. 0x0 3:2 R/W RAM2_PWR_CTRL See description of RAM1_PWR_CTRL. 0x0 1:0 R/W RAM1_PWR_CTRL Power state control of the individual RAMs. May only change when the memory isn't accessed. When in Active or Sleep mode: 0x0: Normal operation 0x1: Normal operation 0x2: Retained (no access possible) 0x3: Off (memory content corrupted) When in Extended Sleep, Deep Sleep or Hibernation mode 0x0: Retained 0x1: Off (memory content corrupted) 0x2: Retained 0x3: Off (memory content corrupted) 0x0 Datasheet CFR0011-120-00 Revision 3.0 199 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 130: CLK_RC32K_REG (0x50000020) Bit Mode Symbol Description Reset 4:1 R/W RC32K_TRIM 0000 = lowest frequency 0111 = default 1111 = highest frequency 0x7 0 R/W RC32K_DISABLE Instantly disables the 32kHz RC oscillator Sleep cycles cannot happen with this clock disabled. 0x0 Table 131: CLK_XTAL32K_REG (0x50000022) Bit Mode Symbol Description Reset 8 - - 7 R/W XTAL32K_DISABLE _AMPREG Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock to XTAL32Kp Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km 0x0 6:3 R/W XTAL32K_CUR Bias current for the 32kHz XTAL oscillator. 0000 is minimum, 1111 is maximum, 0011 is default. For each application there is an optimal setting for which the start-up behavior is optimal 0x5 2:1 R/W XTAL32K_RBIAS Setting for the bias resistor. 00 is maximum, 11 is minimum. Prefered setting will be provided by Dialog 0x3 0 R/W XTAL32K_ENABLE Enables the 32kHz XTAL oscillator. Also set GP_DATA_REG[P03_P04_FILT_DIS] = 1 for lowest current consumption. 0x0 0x0 Table 132: CLK_RC32M_REG (0x50000024) Bit Mode Symbol Description Reset 10:7 R/W RC32M_COSC C-adjust of RC-oscillator A higher value of COSC results in a lower frequency 0xF 6:5 R/W RC32M_RANGE Coarse adjust A higher value of RANGE results in a higher frequency, values 2 and 3 are equal 0x0 4:1 R/W RC32M_BIAS Bias adjustment 0x7 0 R/W RC32M_DISABLE Instantly disables the 32MHz RC oscillator Disabling of the oscillator during sleep happens automatically. 0x0 Datasheet CFR0011-120-00 Revision 3.0 200 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 133: CLK_RCX_REG (0x50000026) Bit Mode Symbol Description Reset 11:8 R/W RCX_BIAS LDO bias current. 0x0: minimum 0xF: maximum 0xA 7 R/W RCX_C0 Add unit capacitance to RC-time delay. 0x1 6:2 R/W RCX_CADJUST Adjust capacitance part of RC-time delay. 0x00: minimum capacitance 0x1F: maximum capacitance 0x1F 1 R/W RCX_RADJUST Adjust resistance part of RC-time delay. Lower resistance increases power consumption. 0x0: maximum resistance 0x1: minimum resistance 0x0 0 R/W RCX_ENABLE Enable the RCX oscillator 0x0 Table 134: BANDGAP_REG (0x50000028) Bit Mode Symbol Description Reset 9:5 R/W BGR_ITRIM Trim setting for bandgap bias current 10000 -> -25% .... 11111 -> ~0% 00000 -> ~0% (typ) ... 01111 -> +32% 0x0 4:0 R/W BGR_TRIM Trim setting for bandgap voltage 10000 -> -6.4% .... 11111 -> ~0% 00000 -> ~0% (typ) ... 01111 -> +5.8% 0x0 Table 135: ANA_STATUS_REG (0x5000002A) Bit Mode Symbol Description Reset 12 R CLKLESS_WAKEU P_STAT Indicates the output of the Clockless wakeup XOR tree. If this signal is '0', the chip will wake up. Use the HIBERN_WKUP_POLARITY bit to set the value to '1' before going into hibernation mode. 0x0 11 - - 10 R LDO_GPADC_OK Indicates that LDO_GPADC output is OK 0x0 9 R LDO_XTAL_OK Indicates that LDO_XTAL output is OK 0x0 Datasheet CFR0011-120-00 0x0 Revision 3.0 201 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 8 R BOOST_SELECTE D 0: Buck mode detected 1: Boost mode detected 0x0 7 R POR_VBAT_HIGH Output of VBAT_HIGH supply rail voltage monitoring circuit. 0: Voltage level on VBAT_HIGH is lower than POR VBAT_HIGH threshold VTH_L (rail not ok, will result in reset if not masked) 1: Voltage level on VBAT_HIGH is higher than POR VBAT_HIGH threshold VTH_H (rail ok, reset released) 0x0 6 R POR_VBAT_LOW Output of VBAT_LOW supply rail voltage monitoring circuit. 0: Voltage level on VBAT_LOW is lower than POR VBAT_LOW threshold VTH_L (rail not ok, will result in reset if not masked) 1: Voltage level on VBAT_LOW is higher than POR VBAT_LOW threshold VTH_H (rail ok, reset released) 0x0 5 R BANDGAP_OK Indicates that BANDGAP is OK 0x0 4 R COMP_VBAT_HIG H_NOK Indicates that VBAT_HIGH < VBAT_LOW -50 mV 0x0 3 R COMP_VBAT_HIG H_OK Indicates that VBAT_HIGH > VBAT_LOW +50 mV 0x0 2 R DCDC_OK Indicates that VBAT_LOW (buck mode) or VBAT_HIGH (boost mode) is OK 0x0 1 R LDO_LOW_OK Indicates that LDO_LOW output is OK (only valid for high current mode) 0x0 0 R LDO_CORE_OK Indicates that LDO_CORE output is OK 0x0 Table 136: XTAL32M_START_REG (0x50000030) Bit Mode Symbol Description Reset 15:8 R/W XTAL32M_RAMP Xtal frequency trimming register. 0x00 : highest frequency 0xFF :lowest frequency 0x0 7:0 R/W XTAL32M_START Xtal frequency trimming register. 0x0 = highest frequency 0xF = lowest frequency. 0xAA Table 137: XTALRDY_CTRL_REG (0x50000034) Bit Mode Symbol Description Reset 7:0 R/W XTALRDY_CNT Number of 32kHz cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. 0x00: no interrupt 0x0 Datasheet CFR0011-120-00 Revision 3.0 202 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 138: XTAL32M_CTRL0_REG (0x50000038) Bit Mode Symbol Description Reset 9:8 - - 7:5 R/W CORE_AMPL_TRIM Core amplitude trimming 0x0 4:2 R/W CORE_CUR_SET Core current trim setting 0x5 1 R/W CORE_AMPL_REG _NULLBIAS Keep bias in ampl detector alive, even when there is a large drive 0x0 0 R/W DCBLOCK_ENABL E Enable dcblock/high pass filter circuit 0x1 0x0 Table 139: POR_PIN_REG (0x50000040) Bit Mode Symbol Description Reset 7 R/W POR_PIN_POLARI TY 0: Active Low 1: Active High Note: This applies only for the GPIO pin. Reset pad has a fixed polarity 0x0 6:4 R/W - 3:0 R/W POR_PIN_SELECT 0x0 Selects the GPIO which is used for POR generation. 0x0: GPIO pin POReset disabled 0x1: P0_0 0x2: P0_1 ... 0xB: P0_10 0xC: P0_11 0xD - 0xF: reserved 0x0 Table 140: POR_TIMER_REG (0x50000042) Bit Mode Symbol Description Reset 6:0 R/W POR_TIME Time for the POReset to happen. Formula: Time = POR_TIME x 4096 x RC32k clock period Default value: ~3 seconds When set to 0x00, the POR TIMER is disabled. 0x18 Datasheet CFR0011-120-00 Revision 3.0 203 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 141: PMU_SLEEP_REG (0x50000050) Bit Mode Symbol Description Reset 11:0 R/W BG_REFRESH_INT ERVAL Defines the refresh interval of reference voltages (bandgap activation and sampling), in units of 2ms. 0x80 Table 142: POWER_CTRL_REG (0x50000052) Bit Mode Symbol Description Reset 15 R/W VBAT_HL_CONNE CT_MODE Sets the control mode fo the switch between VBAT_HIGH and VBAT_LOW 0: Manual (default) 1: Automatic (boost mode only) 0x0 14 R/W POR_VBAT_HIGH_ HYST_DIS 0: Hysteresis enabled 1: Hysteresis disabled 0x1 13 R/W POR_VBAT_HIGH_ HYST_SEL 0: Low level selected 1: High level selected 0x0 12 R/W POR_VBAT_HIGH_ DISABLE Disable por_vbat_high circuit 0x0 11 R/W POR_VBAT_LOW_ HYST_DIS 0: Hysteresis enabled 1: Hysteresis disabled 0x0 10 R/W POR_VBAT_LOW_ HYST_SEL 0: Low level selected 1: High level selected 0x0 9 R/W POR_VBAT_LOW_ DISABLE Disable por_vbat_low circuit 0x0 8 R/W CP_DISABLE Disables LDO_CORE charge-pump circuit 0x0 7 R/W LDO_VREF_HOLD_ FORCE Forces LDO references in HOLD mode 0x0 6:5 R/W LDO_LOW_CTRL_ REG 00: High-current mode in active, LDO_LOW OFF in sleep 01: LDO_LOW OFF 10: Low-current mode in active, Low-current mode in sleep 11: High-current mode in active, Low-current mode in sleep 0x0 4 R/W LDO_CORE_DISAB LE Disables LDO_CORE 0x0 3 R/W LDO_CORE_RET_ ENABLE LDO_CORE_RETENTION 0: Disabled 1: Enabled 0x0 2 R/W VBAT_HL_CONNE CT Switch between VBAT_HIGH and VBAT_LOW 0: Open 1: Closed 0x0 1 R/W CMP_VBAT_HIGH_ OK_ENABLE Enable cmp_vbat_high_ok 0x0 Datasheet CFR0011-120-00 Revision 3.0 204 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W CMP_VBAT_HIGH_ NOK_ENABLE Enable cmp_vbat_high_nok 0x0 Table 143: POWER_LEVEL_REG (0x50000054) Bit Mode Symbol Description Reset 13:11 R/W DCDC_TRIM Delta from DCDC_LEVEL nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV 0x3 10:9 R/W DCDC_LEVEL 00: 1.1 V 01: 1.8 V (default) 10: 2.5 V 11: 3.0 V 0x1 8:7 - - 6:4 R/W LDO_XTAL_TRIM Delta from 0.9 V nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV 0x3 3:1 R/W LDO_LOW_TRIM Delta from 1.1 V nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV (coldboot) 0x7 0 - - 0x0 0x0 Table 144: XTAL32M_TRSTAT_REG (0x50000032) Bit Mode Symbol Description Reset 7:0 R XTAL32M_TRSTAT Reads value of the current XTAL trimming 0x0 Datasheet CFR0011-120-00 Revision 3.0 205 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 145: Register map crg2632_preg_tim_00 Address Register Description 0x5000424C CLK_RTCDIV_REG Divisor for RTC 100Hz clock Table 146: CLK_RTCDIV_REG (0x5000424C) Bit Mode Symbol Description Reset 21 R/W RTC_RESET_REQ Reset request for the RTC module 0x0 20 R/W RTC_DIV_ENABLE Enable for the 100 Hz generation for the RTC block 0x0 19 R/W RTC_DIV_DENOM Selects the denominator for the fractional division: 0b0: 1000 0b1: 1024 0x0 18:10 R/W RTC_DIV_INT Integer divisor part for RTC 100Hz generation 0x147 9:0 R/W RTC_DIV_FRAC Fractional divisor part for RTC 100Hz generation. if RTC_DIV_DENOM=1, out of 1024 cycles will divide by , the rest is If RTC_DIV_DENOM=0, out of 1000 cycles will divide by , the rest is 0x2A8 Datasheet CFR0011-120-00 Revision 3.0 206 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.4 DCDC Converter Registers Table 147: Register map crg2632_dcdc_dig_00 Address Register 0x50000080 DCDC_CTRL_REG Description Table 148: DCDC_CTRL_REG (0x50000080) Bit Mode Symbol Description Reset 15:12 R/W DCDC_ILIM_MAX Maximum value for automatic inductor peak current limit control. 0x0: 6 mA 0x1: 12 mA 0x2: 18 mA 0x3: 24 mA 0x4: 30 mA 0x5: 36 mA 0x6: 42 mA 0x7: 48 mA 0x8: 54 mA (default, limits inrush current) 0x9: 60 mA 0xA: 66 mA 0xB: 72 mA 0xC: 78 mA 0xD: 84 mA 0xE: 90 mA 0xF: 96 mA (set as default for low-ohmic batteries) 0x8 11:8 R/W DCDC_ILIM_MIN Minimum value for automatic inductor peak current limit control. 0x0: 6 mA 0x1: 12 mA 0x2: 18 mA 0x3: 24 mA 0x4: 30 mA (default) 0x5: 36 mA 0x6: 42 mA 0x7: 48 mA 0x8: 54 mA 0x9: 60 mA 0xA: 66 mA 0xB: 72 mA 0xC: 78 mA 0xD: 84 mA 0xE: 90 mA 0xF: 96 mA 0x4 Datasheet CFR0011-120-00 Revision 3.0 207 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:6 R/W DCDC_OK_CLR_C NT Number of subsequent V_NOK events needed to reset VDCD_OK. 0x0: 2 0x1: 4 0x2: 8 (deafult) 0x3: 15 0x2 5:3 R/W DCDC_TIMEOUT Switch timeout, go to next state if either switch is active for longer than this setting. 0x0: Disabled 0 1: 0. 5 μs 0 : 0.50 μs 0x3: 0. 5 μs 0 : 1.00 μs (default) 0 5: 1. 5 μs 0 6: 1.50 μs 0x7: 1. 5 μs 0x4 2:1 R/W DCDC_CLK_DIV Idle clock divider, sets rate at which the output is monitored when the converter is idle. 0x0: Divide by 4 0x1: Divide by 8 0x2: Divide by 16 0x3: Divide by 32 0x1 0 R/W DCDC_ENABLE Enables hardware control of the DCDC converter. 0: DCDC converter disabled 1: DCDC converter under hardware control 0x0 Datasheet CFR0011-120-00 Revision 3.0 208 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.5 DMA Controller Registers Table 149: Register map DMA Address Register Description 0x50003600 DMA0_A_STARTL_R EG Start address Low A of DMA channel 0 0x50003602 DMA0_A_STARTH_R EG Start address High A of DMA channel 0 0x50003604 DMA0_B_STARTL_R EG Start address Low B of DMA channel 0 0x50003606 DMA0_B_STARTH_R EG Start address High B of DMA channel 0 0x50003608 DMA0_INT_REG DMA receive interrupt register channel 0 0x5000360A DMA0_LEN_REG DMA receive length register channel 0 0x5000360C DMA0_CTRL_REG Control register for the DMA channel 0 0x5000360E DMA0_IDX_REG Index value of DMA channel 0 0x50003610 DMA1_A_STARTL_R EG Start address Low A of DMA channel 1 0x50003612 DMA1_A_STARTH_R EG Start address High A of DMA channel 1 0x50003614 DMA1_B_STARTL_R EG Start address Low B of DMA channel 1 0x50003616 DMA1_B_STARTH_R EG Start address High B of DMA channel 1 0x50003618 DMA1_INT_REG DMA receive interrupt register channel 1 0x5000361A DMA1_LEN_REG DMA receive length register channel 1 0x5000361C DMA1_CTRL_REG Control register for the DMA channel 1 0x5000361E DMA1_IDX_REG Index value of DMA channel 1 0x50003620 DMA2_A_STARTL_R EG Start address Low A of DMA channel 2 0x50003622 DMA2_A_STARTH_R EG Start address High A of DMA channel 2 0x50003624 DMA2_B_STARTL_R EG Start address Low B of DMA channel 2 0x50003626 DMA2_B_STARTH_R EG Start address High B of DMA channel 2 0x50003628 DMA2_INT_REG DMA receive interrupt register channel 2 0x5000362A DMA2_LEN_REG DMA receive length register channel 2 0x5000362C DMA2_CTRL_REG Control register for the DMA channel 2 0x5000362E DMA2_IDX_REG Index value of DMA channel 2 0x50003630 DMA3_A_STARTL_R EG Start address Low A of DMA channel 3 0x50003632 DMA3_A_STARTH_R EG Start address High A of DMA channel 3 Datasheet CFR0011-120-00 Revision 3.0 209 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Address Register Description 0x50003634 DMA3_B_STARTL_R EG Start address Low B of DMA channel 3 0x50003636 DMA3_B_STARTH_R EG Start address High B of DMA channel 3 0x50003638 DMA3_INT_REG DMA receive interrupt register channel 3 0x5000363A DMA3_LEN_REG DMA receive length register channel 3 0x5000363C DMA3_CTRL_REG Control register for the DMA channel 3 0x5000363E DMA3_IDX_REG Index value of DMA channel 3 0x50003680 DMA_REQ_MUX_RE G DMA channel assignments 0x50003682 DMA_INT_STATUS_R EG DMA interrupt status register 0x50003684 DMA_CLEAR_INT_RE G DMA clear interrupt register Table 150: DMA0_A_STARTL_REG (0x50003600) Bit Mode Symbol Description Reset 15:0 R/W DMA0_A_STARTL Source start address, lower 16 bits 0x0 Table 151: DMA0_A_STARTH_REG (0x50003602) Bit Mode Symbol Description Reset 15:0 R/W DMA0_A_STARTH Source start address, upper 16 bits 0x0 Table 152: DMA0_B_STARTL_REG (0x50003604) Bit Mode Symbol Description Reset 15:0 R/W DMA0_B_STARTL Destination start address, lower 16 bits 0x0 Table 153: DMA0_B_STARTH_REG (0x50003606) Bit Mode Symbol Description Reset 15:0 R/W DMA0_B_STARTH Destination start address, upper 16 bits 0x0 Datasheet CFR0011-120-00 Revision 3.0 210 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 154: DMA0_INT_REG (0x50003608) Bit Mode Symbol Description Reset 15:0 R/W DMA0_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bitfield IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0x0 Table 155: DMA0_LEN_REG (0x5000360A) Bit Mode Symbol Description Reset 15:0 R/W DMA0_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0x0 Table 156: DMA0_CTRL_REG (0x5000360C) Bit Mode Symbol 15:14 R - 13 R/W REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 0x0 12 R/W DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 0x0 11 R/W DMA_IDLE 0 = Blocking mode, the DMA performs a fast backto-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 211 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 10:8 R/W DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 0x0 7 R/W CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 0x0 6 R/W AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 5 R/W BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 4 R/W DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 0x0 3 R/W IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 0x0 2:1 R/W BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 0x0 0 R/W DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0x0 Datasheet CFR0011-120-00 Revision 3.0 212 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 157: DMA0_IDX_REG (0x5000360E) Bit Mode Symbol Description Reset 15:0 R DMA0_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0x0 Table 158: DMA1_A_STARTL_REG (0x50003610) Bit Mode Symbol Description Reset 15:0 R/W DMA1_A_STARTL Source start address, lower 16 bits 0x0 Table 159: DMA1_A_STARTH_REG (0x50003612) Bit Mode Symbol Description Reset 15:0 R/W DMA1_A_STARTH Source start address, upper 16 bits 0x0 Table 160: DMA1_B_STARTL_REG (0x50003614) Bit Mode Symbol Description Reset 15:0 R/W DMA1_B_STARTL Destination start address, lower 16 bits 0x0 Table 161: DMA1_B_STARTH_REG (0x50003616) Bit Mode Symbol Description Reset 15:0 R/W DMA1_B_STARTH Destination start address, upper 16 bits 0x0 Table 162: DMA1_INT_REG (0x50003618) Bit Mode Symbol Description Reset 15:0 R/W DMA1_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bitfield IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0x0 Datasheet CFR0011-120-00 Revision 3.0 213 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 163: DMA1_LEN_REG (0x5000361A) Bit Mode Symbol Description Reset 15:0 R/W DMA1_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0x0 Table 164: DMA1_CTRL_REG (0x5000361C) Bit Mode Symbol 15:14 R - 13 R/W REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 0x0 12 R/W DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 0x0 11 R/W DMA_IDLE 0 = Blocking mode, the DMA performs a fast backto-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 0x0 10:8 R/W DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 214 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7 R/W CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 0x0 6 R/W AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 5 R/W BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 4 R/W DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 0x0 3 R/W IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 0x0 2:1 R/W BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 0x0 0 R/W DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0x0 Datasheet CFR0011-120-00 Revision 3.0 215 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 165: DMA1_IDX_REG (0x5000361E) Bit Mode Symbol Description Reset 15:0 R DMA1_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0x0 Table 166: DMA2_A_STARTL_REG (0x50003620) Bit Mode Symbol Description Reset 15:0 R/W DMA2_A_STARTL Source start address, lower 16 bits 0x0 Table 167: DMA2_A_STARTH_REG (0x50003622) Bit Mode Symbol Description Reset 15:0 R/W DMA2_A_STARTH Source start address, upper 16 bits 0x0 Table 168: DMA2_B_STARTL_REG (0x50003624) Bit Mode Symbol Description Reset 15:0 R/W DMA2_B_STARTL Destination start address, lower 16 bits 0x0 Table 169: DMA2_B_STARTH_REG (0x50003626) Bit Mode Symbol Description Reset 15:0 R/W DMA2_B_STARTH Destination start address, upper 16 bits 0x0 Table 170: DMA2_INT_REG (0x50003628) Bit Mode Symbol Description Reset 15:0 R/W DMA2_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bitfield IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0x0 Datasheet CFR0011-120-00 Revision 3.0 216 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 171: DMA2_LEN_REG (0x5000362A) Bit Mode Symbol Description Reset 15:0 R/W DMA2_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0x0 Table 172: DMA2_CTRL_REG (0x5000362C) Bit Mode Symbol 15:14 R - 13 R/W REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 0x0 12 R/W DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 0x0 11 R/W DMA_IDLE 0 = Blocking mode, the DMA performs a fast backto-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 0x0 10:8 R/W DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 0x0 7 R/W CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 217 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 6 R/W AINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 5 R/W BINC Enable increment of destination address 0 = do not increment 1 = increment according value of BW 0x0 4 R/W DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 0x0 3 R/W IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 0x0 2:1 R/W BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 0x0 0 R/W DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0x0 Table 173: DMA2_IDX_REG (0x5000362E) Bit Mode Symbol Description Reset 15:0 R DMA2_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0x0 Table 174: DMA3_A_STARTL_REG (0x50003630) Bit Mode Symbol Description Reset 15:0 R/W DMA3_A_STARTL Source start address, lower 16 bits 0x0 Datasheet CFR0011-120-00 Revision 3.0 218 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 175: DMA3_A_STARTH_REG (0x50003632) Bit Mode Symbol Description Reset 15:0 R/W DMA3_A_STARTH Source start address, upper 16 bits 0x0 Table 176: DMA3_B_STARTL_REG (0x50003634) Bit Mode Symbol Description Reset 15:0 R/W DMA3_B_STARTL Destination start address, lower 16 bits 0x0 Table 177: DMA3_B_STARTH_REG (0x50003636) Bit Mode Symbol Description Reset 15:0 R/W DMA3_B_STARTH Destination start address, upper 16 bits 0x0 Table 178: DMA3_INT_REG (0x50003638) Bit Mode Symbol Description Reset 15:0 R/W DMA3_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bitfield IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0x0 Table 179: DMA3_LEN_REG (0x5000363A) Bit Mode Symbol Description Reset 15:0 R/W DMA3_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0x0 Table 180: DMA3_CTRL_REG (0x5000363C) Bit Mode Symbol 15:14 R - 13 R/W REQ_SENSE Datasheet CFR0011-120-00 Description Reset 0x0 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests Revision 3.0 219 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 12 R/W DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 0x0 11 R/W DMA_IDLE 0 = Blocking mode, the DMA performs a fast backto-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 0x0 10:8 R/W DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 0x0 7 R/W CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 0x0 6 R/W AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 5 R/W BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bitfield (by 1, when BW="00" ; by 2, when BW="01" ; by 4, when BW="10") 0x0 4 R/W DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 0x0 Datasheet CFR0011-120-00 Revision 3.0 220 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R/W IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 0x0 2:1 R/W BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 0x0 0 R/W DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0x0 Table 181: DMA3_IDX_REG (0x5000363E) Bit Mode Symbol Description Reset 15:0 R DMA3_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0x0 Table 182: DMA_REQ_MUX_REG (0x50003680) Bit Mode Symbol 15:12 R/W - 0xF 11:8 R/W - 0xF 7:4 R/W DMA23_SEL Datasheet CFR0011-120-00 Description Reset Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Hence, the first DMA request (peripheral-tomemory) is mapped on channel 2 and the second (memory-to-peripheral) on channel 3. See also the description of DMA01_SEL bit-field of this register for the supported peripherals. Revision 3.0 221 of 374 0xF 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3:0 R/W DMA01_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Hence, the first DMA request (peripheral-tomemory) is mapped on channel 0 and the second (memory-to-peripheral) on channel 1. 0x0: SPI_rx / SPI_tx 0x1: Reserved 0x2: UART_rx / UART_tx 0x3: UART2_rx / UART2_tx 0x4: I2C_rx / I2C_tx 0x5: GP_ADC (Rx only) 0x6-0xE: Reserved 0xF: None 0xF Note: If any of the two available peripheral selector fields (DMA01_SEL, DMA23_SEL) have the same value, the lesser significant selector has higher priority and will control the dma acknowledge. Hence, if DMA01_SEL = DMA23_SEL, the channels 0 and 1 will generate the DMA acknowledge signals for the selected peripheral. Consequently, it is suggested to assign the intended peripheral value to a unique selector field. Table 183: DMA_INT_STATUS_REG (0x50003682) Bit Mode Symbol 15:8 R - 0x0 7 R - 0x0 6 R - 0x0 5 R - 0x0 4 R - 0x0 3 R DMA_IRQ_CH3 0: IRQ on channel 3 is not set 1: IRQ on channel 3 is set 0x0 2 R DMA_IRQ_CH2 0: IRQ on channel 2 is not set 1: IRQ on channel 2 is set 0x0 1 R DMA_IRQ_CH1 0: IRQ on channel 1 is not set 1: IRQ on channel 1 is set 0x0 0 R DMA_IRQ_CH0 0: IRQ on channel 0 is not set 1: IRQ on channel 0 is set 0x0 Datasheet CFR0011-120-00 Description Revision 3.0 222 of 374 Reset 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 184: DMA_CLEAR_INT_REG (0x50003684) Bit Mode Symbol 15:8 R - 0x0 7 R - 0x0 6 R - 0x0 5 R - 0x0 4 R - 0x0 3 R0/W DMA_RST_IRQ_CH 3 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 ; writing a 0 will have no effect 0x0 2 R0/W DMA_RST_IRQ_CH 2 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 ; writing a 0 will have no effect 0x0 1 R0/W DMA_RST_IRQ_CH 1 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 ; writing a 0 will have no effect 0x0 0 R0/W DMA_RST_IRQ_CH 0 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 ; writing a 0 will have no effect 0x0 Datasheet CFR0011-120-00 Description Revision 3.0 223 of 374 Reset 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.6 General Purpose ADC Registers Table 185: Register map GPADC Address Register Description 0x50001500 GP_ADC_CTRL_REG General Purpose ADC Control Register 0x50001502 GP_ADC_CTRL2_RE G General Purpose ADC Second Control Register 0x50001504 GP_ADC_CTRL3_RE G General Purpose ADC Third Control Register 0x50001506 GP_ADC_SEL_REG General Purpose ADC Input Selection Register 0x50001508 GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register 0x5000150A GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register 0x5000150C GP_ADC_TRIM_REG General Purpose ADC Trim Register 0x5000150E GP_ADC_CLEAR_INT _REG General Purpose ADC Clear Interrupt Register 0x50001510 GP_ADC_RESULT_R EG General Purpose ADC Result Register Table 186: GP_ADC_CTRL_REG (0x50001500) Bit Mode Symbol Description Reset 12 R/W DIE_TEMP_EN Enables the die-temperature sensor. Output can be measured on GPADC input 4. 0x0 11 - - 10 R/W GP_ADC_LDO_HO LD 0: GPADC LDO tracking bandgap reference 1: GPADC LDO hold sampled bandgap reference 0x0 9 R/W GP_ADC_CHOP 0: Chopper mode off 1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC; Highly recommended for DC-measurements. 0x0 8 R/W GP_ADC_SIGN 0: Default 1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency 0x0 7 R/W GP_ADC_MUTE 0: Normal operation 1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC). 0x0 6 R/W GP_ADC_SE 0: Differential mode 1: Single ended mode 0x0 5 R/W GP_ADC_MINT 0: Disable (mask) GP_ADC_INT. 1: Enable GP_ADC_INT to ICU. 0x0 Datasheet CFR0011-120-00 0x0 Revision 3.0 224 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R GP_ADC_INT 1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG. 0x0 3 R/W GP_ADC_DMA_EN 0: DMA functionality disabled 1: DMA functionality enabled 0x0 2 R/W GP_ADC_CONT 0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit. 1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL. 0x0 1 R/W GP_ADC_START 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero. 0x0 0 R/W GP_ADC_EN 0: LDO is off and ADC is disabled.. 1: LDO is turned on and afterwards the ADC is enabled. 0x0 Table 187: GP_ADC_CTRL2_REG (0x50001502) Bit Mode Symbol Description Reset 15:13 R/W GP_ADC_STORE_ DEL 0: Data is stored after handshake synchronisation 1: Data is stored 2 ADC_CLK cycles after internal start trigger 7: Data is stored 8 ADC_CLK cycles after internal start trigger 0x0 12:9 R/W GP_ADC_SMPL_TI ME 0: The sample time (switch is closed) is two ADC_CLK cycles 1: The sample time is 1*8 ADC_CLK cycles 2: The sample time is 2*8 ADC_CLK cycles 15: The sample time is 15*8 ADC_CLK cycles 0x1 8:6 R/W GP_ADC_CONV_N RS 0: 1 sample is taken or 2 in case ADC_CHOP is active. 1: 2 samples are taken. 2: 4 samples are taken. 7: 128 samples are taken. 0x0 5:4 R/W GP_ADC_OFFS_S H_CM Common mode adjust for offset shifter. Input range is CM +/- 450mV. 0: CM = 1.25V (Input range 0.80 - 1.70) 1: CM = 1.30V (Input range 0.85 - 1.75) (default) 2: CM = 1.35V (Input range 0.90 - 1.80) 3: CM = 1.40V (input range 0.95 - 1.85) 0x1 3 R/W GP_ADC_OFFS_S H_EN 0: Disable input shifter 1: Enable input shifter (900mV - 1800mV shifted to 0mV - 900mV) 0x0 Datasheet CFR0011-120-00 Revision 3.0 225 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2 R/W GP_ADC_I20U 1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC. 0x0 1:0 R/W GP_ADC_ATTN 0: No attenuator (input voltages up to 0.9V allowed) 1: Enabling 2x attenuator (input voltages up to 1.8V allowed) 2: Enabling 3x attenuator (input voltages up to 2.7V allowed) 3: Enabling 4x attenuator (input voltages up to 3.6V allowed) Enabling the attenuator requires a longer sampling time. 0x0 Table 188: GP_ADC_CTRL3_REG (0x50001504) Bit Mode Symbol Description Reset 15:8 R/W GP_ADC_INTERVA L Defines the interval between two ADC conversions in case GP_ADC_CONT is set. 0: No extra delay between two conversions. 1: 1.024 ms interval between two conversions. 2: 2.048 ms interval between two conversions. 255: 261.12 ms interval between two conversions. 0x0 7:0 R/W GP_ADC_EN_DEL Defines the delay for enabling the ADC after enabling the LDO. 0: Not allowed 1: 4x ADC_CLK period. n: n*4x ADC_CLK period. 0x40 Table 189: GP_ADC_OFFP_REG (0x50001508) Bit Mode Symbol Description Reset 9:0 R/W GP_ADC_OFFP Offset adjust of 'positive' array of ADC-network (effective if "GP_ADC_SE=0", or "GP_ADC_SE=1 AND GP_ADC_SIGN=0 OR GP_ADC_CHOP=1") 0x200 Table 190: GP_ADC_OFFN_REG (0x5000150A) Bit Mode Symbol Description Reset 9:0 R/W GP_ADC_OFFN Offset adjust of 'negative' array of ADC-network (effective if "GP_ADC_SE=0", or "GP_ADC_SE=1 AND GP_ADC_SIGN=1 OR GP_ADC_CHOP=1") 0x200 Datasheet CFR0011-120-00 Revision 3.0 226 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 191: GP_ADC_TRIM_REG (0x5000150C) Bit Mode Symbol Description Reset 6:4 R/W GP_ADC_LDO_LEV EL GPADC LDO level 0: 825mV 1: 850mV 2: 875mV 3: 900mV (reset) 4: 925mV (default) 5: 950mV 6: 975mV 7:1000mV 0x3 3:0 R/W GP_ADC_OFFS_S H_VREF Offset Shifter common-mode reference fine trimming: 2mV/LSB Default = mid-scale at 1000 0x8 Table 192: GP_ADC_CLEAR_INT_REG (0x5000150E) Bit Mode Symbol Description Reset 15:0 R0/W GP_ADC_CLR_INT Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0. 0x0 Table 193: GP_ADC_RESULT_REG (0x50001510) Bit Mode Symbol Description Reset 15:0 R GP_ADC_VAL Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits. 0x0 Table 194: GP_ADC_SEL_REG (0x50001506) Bit Mode Symbol 7 - - 6:4 R/W GP_ADC_SEL_P Datasheet CFR0011-120-00 Description Reset 0x0 ADC positive input selection. 0: ADC0 (P0[1]) 1: ADC1 (P0[2]) 2: ADC2 (P0[6]) 3: ADC3 (P0[7]) 4: Temperature Sensor 5: VBAT_HIGH 6: VBAT_LOW 7: VDDD Revision 3.0 227 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol 3 - - 2:0 R/W GP_ADC_SEL_N Datasheet CFR0011-120-00 Description Reset 0x0 ADC negative input selection. Differential only (GP_ADC_SE=0). 0: ADC0 (P0[1]) 1: ADC1 (P0[2]) 2: ADC2 (P0[6]) 3: ADC3 (P0[7]) All other combinations are reserved. Revision 3.0 228 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.7 General Purpose I/O Registers Table 195: Register map GPIO Address Register Description 0x50003000 P0_DATA_REG P0 Data input/output Register 0x50003002 P0_SET_DATA_REG P0 Set port pins Register 0x50003004 P0_RESET_DATA_RE G P0 Reset port pins Register 0x50003006 P00_MODE_REG P00 Mode Register 0x50003008 P01_MODE_REG P01 Mode Register 0x5000300A P02_MODE_REG P02 Mode Register 0x5000300C P03_MODE_REG P03 Mode Register 0x5000300E P04_MODE_REG P04 Mode Register 0x50003010 P05_MODE_REG P05 Mode Register 0x50003012 P06_MODE_REG P06 Mode Register 0x50003014 P07_MODE_REG P07 Mode Register 0x50003016 P08_MODE_REG P08 Mode Register 0x50003018 P09_MODE_REG P09 Mode Register 0x5000301A P010_MODE_REG P010 Mode Register 0x5000301C P011_MODE_REG P011 Mode Register 0x5000301E PAD_WEAK_CTRL_R EG Pad driving strength control Register Table 196: P0_DATA_REG (0x50003000) Bit Mode Symbol 15:12 - - 11:0 R/W P0_DATA Description Reset 0x0 Sets P0 output register when written ; Returns the value of P0 port when read 0x0 Table 197: P0_SET_DATA_REG (0x50003002) Bit Mode Symbol 15:12 - - 11:0 R0/W P0_SET Datasheet CFR0011-120-00 Description Reset 0x0 Writing a 1 to P0[x] sets P0[x] to 1. Writing 0 is discarded, reading returns 0 Revision 3.0 229 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 198: P0_RESET_DATA_REG (0x50003004) Bit Mode Symbol 15:12 - - 11:0 R0/W P0_RESET Description Reset 0x0 Writing a 1 to P0[x] sets P0[x] to 0. Writing 0 is discarded, reading returns 0. 0x0 Table 199: P00_MODE_REG (0x50003006) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - Datasheet CFR0011-120-00 Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 0x0 Revision 3.0 230 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = GPIO (pin direction determined by "PUPD" field) 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SYS_CLK 6 = LP_CLK 7 = Reserved 8 = Reserved 9 = I2C_SCL 10 = I2C_SDA 11 = PWM5 12 = PWM6 13 = PWM7 14 = Reserved 15 = ADC (only for P0_1, P0_2, P0_6 and P0_7) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (signals mapped to P0[3:0] are also mapped to P0[11:8]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = Reserved 22 = Reserved 23 = PWM2 24 = PWM3 25 = PWM4 26 = SPI_DI 27 = SPI_DO 28 = SPI_CLK 29 = SPI_CSN0 30 = SPI_CSN1 31 = Reserved Note: When a certain input function (like SPI_DI) is selected on more than 1 pins, the pin of the lowest index has the highest priority. 0x0 Table 200: P01_MODE_REG (0x50003008) Bit Mode Symbol 15:10 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 231 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - 4:0 R/W PID 0x0 See P00_MODE_REG[PID] 0x0 Table 201: P02_MODE_REG (0x5000300A) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 202: P03_MODE_REG (0x5000300C) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 203: P04_MODE_REG (0x5000300E) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD Datasheet CFR0011-120-00 Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected Revision 3.0 232 of 374 0x2 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol 7:5 - - 4:0 R/W PID Description Reset 0x0 See P00_MODE_REG[PID] 0x0 Table 204: P05_MODE_REG (0x50003010) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 205: P06_MODE_REG (0x50003012) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 206: P07_MODE_REG (0x50003014) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Datasheet CFR0011-120-00 Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 See P00_MODE_REG[PID] Revision 3.0 233 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 207: P08_MODE_REG (0x50003016) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 208: P09_MODE_REG (0x50003018) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 209: P010_MODE_REG (0x5000301A) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - 4:0 R/W PID Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 See P00_MODE_REG[PID] 0x0 Table 210: P011_MODE_REG (0x5000301C) Bit Mode Symbol 15:10 - - 9:8 R/W PUPD 7:5 - - Datasheet CFR0011-120-00 Description Reset 0x0 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 0x2 0x0 Revision 3.0 234 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4:0 R/W PID See P00_MODE_REG[PID] 0x0 Table 211: PAD_WEAK_CTRL_REG (0x5000301E) Bit Mode Symbol 15:12 - - 11:0 R/W PAD_LOW_DRV Datasheet CFR0011-120-00 Description Reset 0x0 0 = Normal operation 1 = Reduces the driving strength of P0_x pad. Bit x controls the driving strength of P0_x, x=0, 1,..., 11. Revision 3.0 235 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.8 General Purpose Registers Table 212: Register map GPREG Address Register Description 0x50003300 SET_FREEZE_REG Controls freezing of various timers/counters. 0x50003302 RESET_FREEZE_RE G Controls unfreezing of various timers/counters. 0x50003304 DEBUG_REG Various debug information register. 0x50003306 GP_STATUS_REG General purpose system status register. 0x50003308 GP_CONTROL_REG General purpose system control register. 0x5000330A BLE_TIMER_REG BLE FINECNT sampled value while in deep sleep state. Table 213: SET_FREEZE_REG (0x50003300) Bit Mode Symbol Description Reset 15:5 - - 4 R/W FRZ_DMA If '1', the DMA is frozen, '0' is discarded. 0x0 3 R/W FRZ_WDOG If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function. 0x0 2 R/W FRZ_BLETIM If '1', the BLE master clock is frozen, '0' is discarded. 0x0 1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) is frozen, '0' is discarded. 0x0 0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer is frozen, '0' is discarded. 0x0 0x0 Table 214: RESET_FREEZE_REG (0x50003302) Bit Mode Symbol 15:5 - - 4 R/W FRZ_DMA If '1', the DMA continues, '0' is discarded. 0x0 3 R/W FRZ_WDOG If '1', the watchdog timer continues, '0' is discarded. 0x0 2 R/W FRZ_BLETIM If '1', the the BLE master clock continues, '0' is discarded. 0x0 1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) continues, '0' is discarded. 0x0 0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer continues, '0' is discarded. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 236 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 215: DEBUG_REG (0x50003304) Bit Mode Symbol 15:1 R/W - 0 R/W DEBUGS_FREEZE _EN Description Reset 0x0 Default '1', freezing of the on-chip timers is enabled when the Cortex is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex is halted in DEBUG State. 0x1 Table 216: GP_STATUS_REG (0x50003306) Bit Mode Symbol Description Reset 15:2 - - 0x0 1 R/W - 0x0 0 R/W CAL_PHASE If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured. 0x0 Table 217: GP_CONTROL_REG (0x50003308) Bit Mode Symbol Description Reset 15:7 - - 6:5 R/W BLE_TIMER_DATA _CTRL Refer to BLE_TIMER_REG. 0x0 4 R/W CPU_DMA_BUS_P RIO Controls the CPU DMA system bus priority: If '0', the CPU has highest priority. If '1', the DMA has highest priority. 0x0 3 - - 2 R BLE_WAKEUP_LP_ IRQ 1 - - 0 R/W BLE_WAKEUP_RE Q 0x0 0x0 The current value of the BLE_WAKEUP_LP_IRQ interrupt request. 0x0 0x0 If '1', the BLE wakes up. Must be kept high at least for 1 low power clock period. If the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles. 0x0 Table 218: BLE_TIMER_REG (0x5000330A) Bit Mode Symbol 15:10 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 237 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 9:0 R/W BLE_TIMER_DATA Operation depends on GP_CONTROL_REG>BLE_TIMER_DATA_CTRL. If BLE_TIMER_DATA_CTRL = 0 then: This register is located at the Always On Power Domain and it holds the automatically sampled value of the BLE FINECNT timer The HW automatically samples the value into this register during the sequence of "BLE Sleep On" and restores automatically the value during the BLE Wake up sequence. The Software may read and modify the value while the BLE is in Sleep state. While the BLE is awake, the value of the register has no meaning, while changing the value by writing another one will have no effect in the operation of the BLE core. There is a constraint when the SW performs an write-read sequence where it has to inject a one cycle delay in between (e.g. write-NOP-read) in order to read back the correct value. If BLE_TIMER_DATA_CTRL is non 0 then write operations have the same effect as when BLE_TIMER_DATA_CTRL=0, while for read operations: BLE_TIMER_DATA_CTRL= 1: then reading BLE_TIMER_REG returns "deepsldur[9:0]". BLE_TIMER_DATA_CTRL= 2: then reading BLE_TIMER_REG returns "deepsltime_samp[9:0]". BLE_TIMER_DATA_CTRL= 3: then reading BLE_TIMER_REG returns "{deep_sleep_stat_monitor, deepsltime_samp[18:10]}. . 0x0 Datasheet CFR0011-120-00 Revision 3.0 238 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.9 I2C Interface Registers Table 219: Register map I2C Address Register Description 0x50001300 I2C_CON_REG I2C Control Register 0x50001304 I2C_TAR_REG I2C Target Address Register 0x50001308 I2C_SAR_REG I2C Slave Address Register 0x50001310 I2C_DATA_CMD_RE G I2C Rx/Tx Data Buffer and Command Register 0x50001314 I2C_SS_SCL_HCNT_ REG Standard Speed I2C Clock SCL High Count Register 0x50001318 I2C_SS_SCL_LCNT_ REG Standard Speed I2C Clock SCL Low Count Register 0x5000131C I2C_FS_SCL_HCNT_ REG Fast Speed I2C Clock SCL High Count Register 0x50001320 I2C_FS_SCL_LCNT_ REG Fast Speed I2C Clock SCL Low Count Register 0x5000132C I2C_INTR_STAT_REG I2C Interrupt Status Register 0x50001330 I2C_INTR_MASK_RE G I2C Interrupt Mask Register 0x50001334 I2C_RAW_INTR_STA T_REG I2C Raw Interrupt Status Register 0x50001338 I2C_RX_TL_REG I2C Receive FIFO Threshold Register 0x5000133C I2C_TX_TL_REG I2C Transmit FIFO Threshold Register 0x50001340 I2C_CLR_INTR_REG Clear Combined and Individual Interrupt Register 0x50001344 I2C_CLR_RX_UNDER _REG Clear RX_UNDER Interrupt Register 0x50001348 I2C_CLR_RX_OVER_ REG Clear RX_OVER Interrupt Register 0x5000134C I2C_CLR_TX_OVER_ REG Clear TX_OVER Interrupt Register 0x50001350 I2C_CLR_RD_REQ_R EG Clear RD_REQ Interrupt Register 0x50001354 I2C_CLR_TX_ABRT_ REG Clear TX_ABRT Interrupt Register 0x50001358 I2C_CLR_RX_DONE_ REG Clear RX_DONE Interrupt Register 0x5000135C I2C_CLR_ACTIVITY_ REG Clear ACTIVITY Interrupt Register 0x50001360 I2C_CLR_STOP_DET _REG Clear STOP_DET Interrupt Register 0x50001364 I2C_CLR_START_DE T_REG Clear START_DET Interrupt Register 0x50001368 I2C_CLR_GEN_CALL _REG Clear GEN_CALL Interrupt Register Datasheet CFR0011-120-00 Revision 3.0 239 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Address Register Description 0x5000136C I2C_ENABLE_REG I2C Enable Register 0x50001370 I2C_STATUS_REG I2C Status Register 0x50001374 I2C_TXFLR_REG I2C Transmit FIFO Level Register 0x50001378 I2C_RXFLR_REG I2C Receive FIFO Level Register 0x5000137C I2C_SDA_HOLD_REG I2C SDA Hold Time Length Register 0x50001380 I2C_TX_ABRT_SOUR CE_REG I2C Transmit Abort Source Register 0x50001388 I2C_DMA_CR_REG DMA Control Register 0x5000138C I2C_DMA_TDLR_REG DMA Transmit Data Level Register 0x50001390 I2C_DMA_RDLR_RE G I2C Receive Data Level Register 0x50001394 I2C_SDA_SETUP_RE G I2C SDA Setup Register 0x50001398 I2C_ACK_GENERAL_ CALL_REG I2C ACK General Call Register 0x5000139C I2C_ENABLE_STATU S_REG I2C Enable Status Register 0x500013A0 I2C_IC_FS_SPKLEN_ REG I2C SS and FS spike suppression limit Size Table 220: I2C_CON_REG (0x50001300) Bit Mode Symbol 15:7 - - 6 R/W I2C_SLAVE_DISAB LE Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'. 0x1 5 R/W I2C_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable 0x1 4 R/W I2C_10BITADDR_M ASTER Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing 0x1 3 R/W I2C_10BITADDR_S LAVE When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing 0x1 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 240 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2:1 R/W I2C_SPEED These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s) Note: The actuall speed depends on the pcb traces capacitance as well as on the values of the external pull-up resistorts. For an exact speed match, trimming might be required, by adjusting the values of I2C_SS_SCL_HCNT_REG, I2C_SS_SCL_LCNT_REG, I2C_FS_SCL_HCNT_REG, I2C_FS_SCL_LCNT_REG registers. The reset values of those registers were calculated with the assumption of 4.3kOhms external pull-up resistors. 0x2 0 R/W I2C_MASTER_MOD E This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x1 Description Reset Table 221: I2C_TAR_REG (0x50001304) Bit Mode Symbol 15:12 - - 11 R/W SPECIAL This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit 0x0 10 R/W GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE 0x0 Datasheet CFR0011-120-00 0x0 Revision 3.0 241 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 9:0 R/W IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave 0x55 Description Reset Table 222: I2C_SAR_REG (0x50001308) Bit Mode Symbol 15:10 - - 9:0 R/W IC_SAR 0x0 The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. 0x55 Table 223: I2C_DATA_CMD_REG (0x50001310) Bit Mode Symbol 15:11 - - 10 R/W I2C_RESTART Datasheet CFR0011-120-00 Description Reset 0x0 This bit controls whether a RESTART is issued before the byte is sent or received. If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0 Revision 3.0 242 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 9 R/W I2C_STOP This bit controls whether a STOP is issued after the byte is sent or received. STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 0x0 8 R/W I2C_CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a "don't care" because writes to this register are not required. In slave-transmitter mode, a "0" indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a "1" is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt 0x0 7:0 R/W DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface. 0x0 Datasheet CFR0011-120-00 Revision 3.0 243 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 224: I2C_SS_SCL_HCNT_REG (0x50001314) Bit Mode Symbol Description Reset 15:0 R/W IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock highperiod count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. 0x48 Table 225: I2C_SS_SCL_LCNT_REG (0x50001318) Bit Mode Symbol Description Reset 15:0 R/W IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. 0x4F Table 226: I2C_FS_SCL_HCNT_REG (0x5000131C) Bit Mode Symbol Description Reset 15:0 R/W IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock highperiod count for fast speed. It is used in highspeed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. 0x8 Datasheet CFR0011-120-00 Revision 3.0 244 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 227: I2C_FS_SCL_LCNT_REG (0x50001320) Bit Mode Symbol Description Reset 15:0 R/W IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed. 0x17 Table 228: I2C_INTR_STAT_REG (0x5000132C) Bit Mode Symbol 15:12 - - 11 R R_GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer. 0x0 10 R R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 9 R R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 8 R R_ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0 7 R R_RX_DONE When the controller is acting as a slavetransmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 245 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 6 R R_TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a "transmit abort". When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0 5 R R_RD_REQ This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 0x0 4 R R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 0x0 3 R R_TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 0x0 2 R R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0 1 R R_RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 Datasheet CFR0011-120-00 Revision 3.0 246 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 Table 229: I2C_INTR_MASK_REG (0x50001330) Bit Mode Symbol Description Reset 15:12 - - 11 R/W M_GEN_CALL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 10 R/W M_START_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x0 9 R/W M_STOP_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x0 8 R/W M_ACTIVITY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x0 7 R/W M_RX_DONE These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 6 R/W M_TX_ABRT These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 5 R/W M_RD_REQ These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 4 R/W M_TX_EMPTY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 3 R/W M_TX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 2 R/W M_RX_FULL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 1 R/W M_RX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 0 R/W M_RX_UNDER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 0x0 Table 230: I2C_RAW_INTR_STAT_REG (0x50001334) Bit Mode Symbol 15:12 - - 11 R GEN_CALL Datasheet CFR0011-120-00 Description Reset 0x0 Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer. Revision 3.0 247 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 10 R START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 9 R STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 8 R ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0 7 R RX_DONE When the controller is acting as a slavetransmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0 6 R TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a "transmit abort". When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0 5 R RD_REQ This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 0x0 Datasheet CFR0011-120-00 Revision 3.0 248 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 0x0 3 R TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 0x0 2 R RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0 1 R RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 0 R RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 Table 231: I2C_RX_TL_REG (0x50001338) Bit Mode Symbol 15:5 - - 4:0 R/W RX_TL Datasheet CFR0011-120-00 Description Reset 0x0 Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries. Revision 3.0 249 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 232: I2C_TX_TL_REG (0x5000133C) Bit Mode Symbol 15:5 - - 4:0 R/W RX_TL Description Reset 0x0 Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries.. 0x0 Table 233: I2C_CLR_INTR_REG (0x50001340) Bit Mode Symbol 15:1 - - 0 R CLR_INTR Description Reset 0x0 Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE 0x0 Table 234: I2C_CLR_RX_UNDER_REG (0x50001344) Bit Mode Symbol 15:1 - - 0 R CLR_RX_UNDER Description Reset 0x0 Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register. 0x0 Table 235: I2C_CLR_RX_OVER_REG (0x50001348) Bit Mode Symbol 15:1 - - 0 R CLR_RX_OVER Datasheet CFR0011-120-00 Description Reset 0x0 Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register. Revision 3.0 250 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 236: I2C_CLR_TX_OVER_REG (0x5000134C) Bit Mode Symbol 15:1 - - 0 R CLR_TX_OVER Description Reset 0x0 Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register. 0x0 Table 237: I2C_CLR_RD_REQ_REG (0x50001350) Bit Mode Symbol 15:1 - - 0 R CLR_RD_REQ Description Reset 0x0 Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register. 0x0 Table 238: I2C_CLR_TX_ABRT_REG (0x50001354) Bit Mode Symbol 15:1 - - 0 R CLR_TX_ABRT Description Reset 0x0 Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. 0x0 Table 239: I2C_CLR_RX_DONE_REG (0x50001358) Bit Mode Symbol 15:1 - - 0 R CLR_RX_DONE Description Reset 0x0 Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register. 0x0 Table 240: I2C_CLR_ACTIVITY_REG (0x5000135C) Bit Mode Symbol 15:1 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 251 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register 0x0 Table 241: I2C_CLR_STOP_DET_REG (0x50001360) Bit Mode Symbol 15:1 - - 0 R CLR_STOP_DET Description Reset 0x0 Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0 0x0 Table 242: I2C_CLR_START_DET_REG (0x50001364) Bit Mode Symbol 15:1 - - 0 R CLR_START_DET Description Reset 0x0 Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. 0x0 Table 243: I2C_CLR_GEN_CALL_REG (0x50001368) Bit Mode Symbol 15:1 - - 0 R CLR_GEN_CALL Description Reset 0x0 Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register. 0x0 Table 244: I2C_ENABLE_REG (0x5000136C) Bit Mode Symbol 15:2 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 252 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 1 R/W I2C_ABORT 0= ABORT not initiated or ABORT done 1= ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 0x0 0 R/W CTRL_ENABLE Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller 0x0 Table 245: I2C_STATUS_REG (0x50001370) Bit Mode Symbol 15:7 - - 6 R SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active 0x0 5 R MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 253 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full 0x0 3 R RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty 0x0 2 R TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty 0x1 1 R TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full 0x1 0 R I2C_ACTIVITY I2C Activity Status. 0x0 Table 246: I2C_TXFLR_REG (0x50001374) Bit Mode Symbol 15:6 - - 5:0 R TXFLR Description Reset 0x0 Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value 0x0 Table 247: I2C_RXFLR_REG (0x50001378) Bit Mode Symbol 15:6 - - 5:0 R RXFLR Description Reset 0x0 Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value 0x0 Table 248: I2C_SDA_HOLD_REG (0x5000137C) Bit Mode Symbol Description Reset 15:0 R/W IC_SDA_HOLD SDA Hold time 0x1 Datasheet CFR0011-120-00 Revision 3.0 254 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 249: I2C_TX_ABRT_SOURCE_REG (0x50001380) Bit Mode Symbol Description Reset 15 R ABRT_SLVRD_INT X 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register 0x0 14 R ABRT_SLV_ARBLO ST 1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never "owns" the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus. 0x0 13 R ABRT_SLVFLUSH_ TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. 0x0 12 R ARB_LOST 1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. 0x0 11 R ABRT_MASTER_DI S 1: User tries to initiate a Master operation with the Master mode disabled. 0x0 10 R ABRT_10B_RD_NO RSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode. 0x0 9 R ABRT_SBYTE_NO RSTRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. 0x0 8 R ABRT_HS_NORST RT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode 0x0 7 R ABRT_SBYTE_ACK DET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). 0x0 6 R ABRT_HS_ACKDE T 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). 0x0 Datasheet CFR0011-120-00 Revision 3.0 255 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 5 R ABRT_GCALL_REA D 1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). 0x0 4 R ABRT_GCALL_NO ACK 1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call. 0x0 3 R ABRT_TXDATA_N OACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). 0x0 2 R ABRT_10ADDR2_N OACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. 0x0 1 R ABRT_10ADDR1_N OACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. 0x0 0 R ABRT_7B_ADDR_N OACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. 0x0 Table 250: I2C_DMA_CR_REG (0x50001388) Bit Mode Symbol Description Reset 1 R/W TDMAE Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled 0x0 0 R/W RDMAE Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0 = Receive DMA disabled 1 = Receive DMA enabled 0x0 Table 251: I2C_DMA_TDLR_REG (0x5000138C) Bit Mode Symbol Description Reset 4:0 R/W DMATDL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. 0x0 Datasheet CFR0011-120-00 Revision 3.0 256 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 252: I2C_DMA_RDLR_REG (0x50001390) Bit Mode Symbol Description Reset 4:0 R/W DMARDL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. 0x0 Table 253: I2C_SDA_SETUP_REG (0x50001394) Bit Mode Symbol 15:8 - - 7:0 R/W SDA_SETUP Description Reset 0x0 SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0. 0x64 Table 254: I2C_ACK_GENERAL_CALL_REG (0x50001398) Bit Mode Symbol 15:1 - - 0 R/W ACK_GEN_CALL Description Reset 0x0 ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts. 0x0 Table 255: I2C_ENABLE_STATUS_REG (0x5000139C) Bit Mode Symbol 15:3 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 257 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2 R SLV_RX_DATA_LO ST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 0x0 1 R SLV_DISABLED_W HILE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 0x0 0 R IC_EN ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). 0x0 Datasheet CFR0011-120-00 Revision 3.0 258 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 256: I2C_IC_FS_SPKLEN_REG (0x500013A0) Bit Mode Symbol 15:8 - - 7:0 R/W IC_FS_SPKLEN Datasheet CFR0011-120-00 Description Reset 0x0 This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. Revision 3.0 259 of 374 0x1 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.10 Keyboard Registers Table 257: Register map KBRD Address Register Description 0x50001400 GPIO_IRQ0_IN_SEL_ REG GPIO interrupt selection for GPIO_IRQ0 0x50001402 GPIO_IRQ1_IN_SEL_ REG GPIO interrupt selection for GPIO_IRQ1 0x50001404 GPIO_IRQ2_IN_SEL_ REG GPIO interrupt selection for GPIO_IRQ2 0x50001406 GPIO_IRQ3_IN_SEL_ REG GPIO interrupt selection for GPIO_IRQ3 0x50001408 GPIO_IRQ4_IN_SEL_ REG GPIO interrupt selection for GPIO_IRQ4 0x5000140C GPIO_DEBOUNCE_R EG debounce counter value for GPIO inputs 0x5000140E GPIO_RESET_IRQ_R EG GPIO interrupt reset register 0x50001410 GPIO_INT_LEVEL_CT RL_REG high or low level select for GPIO interrupts 0x50001412 KBRD_IRQ_IN_SEL0_ REG GPIO interrupt selection for KBRD_IRQ for P0 0x50001414 KBRD_CTRL_REG GPIO Kbrd control register Table 258: GPIO_IRQ0_IN_SEL_REG (0x50001400) Bit Mode Symbol 15:6 - - 3:0 R/W KBRD_IRQ0_SEL Datasheet CFR0011-120-00 Description Reset 0x0 input selection that can generate a GPIO interrupt 1: P0[0] is selected 2: P0[1] is selected 3: P0[2] is selected 4: P0[3] is selected 5: P0[4] is selected 6: P0[5] is selected 7: P0[6] is selected 8: P0[7] is selected 9: P0[8] is selected 10: P0[9] is selected 11: P0[10] is selected 12: P0[11] is selected all others: no input selected Revision 3.0 260 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 259: GPIO_IRQ1_IN_SEL_REG (0x50001402) Bit Mode Symbol 15:6 - - 3:0 R/W KBRD_IRQ1_SEL Description Reset 0x0 see KBRD_IRQ0_SEL 0x0 Table 260: GPIO_IRQ2_IN_SEL_REG (0x50001404) Bit Mode Symbol 15:6 - - 3:0 R/W KBRD_IRQ2_SEL Description Reset 0x0 see KBRD_IRQ0_SEL 0x0 Table 261: GPIO_IRQ3_IN_SEL_REG (0x50001406) Bit Mode Symbol 15:6 - - 3:0 R/W KBRD_IRQ3_SEL Description Reset 0x0 see KBRD_IRQ0_SEL 0x0 Table 262: GPIO_IRQ4_IN_SEL_REG (0x50001408) Bit Mode Symbol 15:6 - - 3:0 R/W KBRD_IRQ4_SEL Description Reset 0x0 see KBRD_IRQ0_SEL 0x0 Table 263: GPIO_DEBOUNCE_REG (0x5000140C) Bit Mode Symbol Description Reset 11 R/W DEB_ENABLE_KBR D enables the debounce counter for the KBRD interface 0x0 10 R/W DEB_ENABLE4 enables the debounce counter for GPIO IRQ4 0x0 9 R/W DEB_ENABLE3 enables the debounce counter for GPIO IRQ3 0x0 8 R/W DEB_ENABLE2 enables the debounce counter for GPIO IRQ2 0x0 7 R/W DEB_ENABLE1 enables the debounce counter for GPIO IRQ1 0x0 6 R/W DEB_ENABLE0 enables the debounce counter for GPIO IRQ0 0x0 5:0 R/W DEB_VALUE Keyboard debounce time if enabled. Generate KEYB_INT after specified time. Debounce time: N*1 ms. N =0..63 0x0 Datasheet CFR0011-120-00 Revision 3.0 261 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 264: GPIO_RESET_IRQ_REG (0x5000140E) Bit Mode Symbol Description Reset 15:6 - - 5 R0/W RESET_KBRD_IRQ writing a 1 to this bit will reset the KBRD IRQ. Reading returns 0. 0x0 4 R0/W RESET_GPIO4_IR Q writing a 1 to this bit will reset the GPIO4 IRQ. Reading returns 0. 0x0 3 R0/W RESET_GPIO3_IR Q writing a 1 to this bit will reset the GPIO3 IRQ. Reading returns 0. 0x0 2 R0/W RESET_GPIO2_IR Q writing a 1 to this bit will reset the GPIO2 IRQ. Reading returns 0. 0x0 1 R0/W RESET_GPIO1_IR Q writing a 1 to this bit will reset the GPIO1 IRQ. Reading returns 0. 0x0 0 R0/W RESET_GPIO0_IR Q writing a 1 to this bit will reset the GPIO0 IRQ. Reading returns 0. 0x0 0x0 Table 265: GPIO_INT_LEVEL_CTRL_REG (0x50001410) Bit Mode Symbol Description Reset 9 R/W EDGE_LEVELn4 see EDGE_LEVELn0, but for GPIO IRQ4 0x0 8 R/W EDGE_LEVELn3 see EDGE_LEVELn0, but for GPIO IRQ3 0x0 7 R/W EDGE_LEVELn2 see EDGE_LEVELn0, but for GPIO IRQ2 0x0 6 R/W EDGE_LEVELn1 see EDGE_LEVELn0, but for GPIO IRQ1 0x0 5 R/W EDGE_LEVELn0 0: do not wait for key release after interrupt was reset for GPIO IRQ0, so a new interrupt can be initiated immediately 1: wait for key release after interrupt was reset for IRQ0 0x0 4 R/W INPUT_LEVEL4 see INPUT_LEVEL0, but for GPIO IRQ4 0x0 3 R/W INPUT_LEVEL3 see INPUT_LEVEL0, but for GPIO IRQ3 0x0 2 R/W INPUT_LEVEL2 see INPUT_LEVEL0, but for GPIO IRQ2 0x0 1 R/W INPUT_LEVEL1 see INPUT_LEVEL0, but for GPIO IRQ1 0x0 0 R/W INPUT_LEVEL0 0 = selected input will generate GPIO IRQ0 if that input is high. 1 = selected input will generate GPIO IRQ0 if that input is low. 0x0 Table 266: KBRD_IRQ_IN_SEL0_REG (0x50001412) Bit Mode Symbol Description Reset 11 R/W KBRD_P11_EN enable P0[11] for the keyboard interrupt 0x0 10 R/W KBRD_P10_EN enable P0[10] for the keyboard interrupt 0x0 Datasheet CFR0011-120-00 Revision 3.0 262 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 9 R/W KBRD_P09_EN enable P0[9] for the keyboard interrupt 0x0 8 R/W KBRD_P08_EN enable P0[8] for the keyboard interrupt 0x0 7 R/W KBRD_P07_EN enable P0[7] for the keyboard interrupt 0x0 6 R/W KBRD_P06_EN enable P0[6] for the keyboard interrupt 0x0 5 R/W KBRD_P05_EN enable P0[5] for the keyboard interrupt 0x0 4 R/W KBRD_P04_EN enable P0[4] for the keyboard interrupt 0x0 3 R/W KBRD_P03_EN enable P0[3] for the keyboard interrupt 0x0 2 R/W KBRD_P02_EN enable P0[2] for the keyboard interrupt 0x0 1 R/W KBRD_P01_EN enable P0[1] for the keyboard interrupt 0x0 0 R/W KBRD_P00_EN enable P0[0] for the keyboard interrupt 0x0 Table 267: KBRD_CTRL_REG (0x50001414) Bit Mode Symbol Description Reset 7 R/W KBRD_REL 0 = No interrupt on key release 1 = Interrupt also on key release (also debouncing if enabled) 0x0 6 R/W KBRD_LEVEL 0 = enabled input will generate KBRD IRQ if that input is high. 1 = enabled input will generate KBRD IRQ if that input is low. 0x0 5:0 R/W KEY_REPEAT While key is pressed, automatically generate repeating KEYB_INT after specified time unequal to 0. Repeat time: N*1 ms. N =1..63, N=0 disables the timer. 0x0 Datasheet CFR0011-120-00 Revision 3.0 263 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.11 Miscellaneous Registers Table 268: Register map crg2632_preg_aon_00 Address Register Description 0x50000300 HWR_CTRL_REG Hardware Reset control register 0x50000304 RESET_STAT_REG Reset status register 0x50000308 RAM_LPMX_REG 0x5000030C PAD_LATCH_REG Control the state retention of the GPIO ports 0x50000310 HIBERN_CTRL_REG Hibernation control register 0x50000320 POWER_AON_CTRL_ REG 0x50000324 GP_DATA_REG Table 269: HWR_CTRL_REG (0x50000300) Bit Mode Symbol Description Reset 0 R/W DISABLE_HWR Disables the RST functionality on P00 0x0 Table 270: RESET_STAT_REG (0x50000304) Bit Mode Symbol Description Reset 3 R/W WDOGRESET_STA T Indicates that a Watchdog has happened. This bit is also set with a PowerOn Reset 0x1 2 R/W SWRESET_STAT Indicates that a SW Reset has been requested. The SW reset is requested by SYS_CTRL_REG[SW_RESET] or SCB->AIRCR inside the Cortex. This bit is also set with a PowerOn Reset 0x1 1 R/W HWRESET_STAT Indicates that a HW Reset has happened This bit is also set with a PowerOn Reset 0x1 0 R/W PORESET_STAT Indicates that a PowerOn Reset has happened 0x1 Table 271: RAM_LPMX_REG (0x50000308) Bit Mode Symbol Description Reset 2:0 R/W RAMx_LPMX RAM[3:1] Transparent Light Sleep (TLS) Core Enable for System RAMs. Assert low to enable the TLS core feature, which will result in lower leakage current. In case VDD is below 0.81V, it is necessary to hold this pin high to maintain data retention. 0x7 Datasheet CFR0011-120-00 Revision 3.0 264 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 272: PAD_LATCH_REG (0x5000030C) Bit Mode Symbol Description Reset 0 R/W PAD_LATCH_EN Controls the state retention of the pads. 0: latches are closed, pads retain their state. 1: latches are open, new control values have immediate effect 0x1 Table 273: HIBERN_CTRL_REG (0x50000310) Bit Mode Symbol Description Reset 6:2 R/W HIBERN_WKUP_M ASK Selects which pin to wakeup from 0x0 1 R/W HIBERN_WKUP_P OLARITY Selects the polarity of the wakeup source. The polarity must be chosen such that the ANA_STATUS_REG[CLKLESS_WAKEUP_STAT] is '1'. Any change on the selected GPIOs will make the CLKLESS_WAKEUP_STAT go to '0', and wakeup the system from hibernation. 0x0 0 R/W HIBERNATION_EN ABLE Enables the hibernation mode when sleeping 0: deep sleep mode, PD_SLP remains on 1: hibernation mode, PD_SLP goes off. REMAP_ADR0 needs to be set to the correct source to boot from before going to sleep. 0x0 Table 274: POWER_AON_CTRL_REG (0x50000320) Bit Mode Symbol 14 - - 13:10 R/W LDO_RET_TRIM VDD clamp level setting for hibernation mode 0x0 9 R/W CMP_VCONT_SLP _DISABLE Disable vcont comparator in SLP 0x0 8:7 R/W BOOST_MODE_FO RCE 0x:automatic selection of boost mode 11: force boost mode 10: force buck mode 0x0 6 R/W CHARGE_VBAT_DI SABLE Do not charge vbat high in boost mode 0x0 5 - - 0x0 4 - - 0x0 3 R/W POR_VBAT_HIGH_ RST_MASK Mask rst from por_vbat_high 0x1 2 R/W POR_VBAT_LOW_ RST_MASK Mask rst from por_vbat_low 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 265 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 1:0 R/W VBAT_HL_CONNE CT_RES_CTRL 00: OFF 01: Forced ON 10: Active: automatic control, Sleep: forced ON 11: Automatic control 0x0 Table 275: GP_DATA_REG (0x50000324) Bit Mode Symbol Description Reset 7 R/W P03_P04_FILT_DIS 0: RC filtered input enabled for P0_3 and P0_4 (e.g. when used for wakeup) 1: RC filtered input disabled for P0_3 and P0_4 (e.g. when used for external clk or XTAL32k) 0x0 6 R/W FORCE_RCX_VDD 0: RCX bias supply open (see FORCE_RCX_VREF) 1: RCX bias supply connected to VDD (use for sleep) 0x0 5 R/W FORCE_RCX_VRE F 0: RCX bias supply connected to clamp and VDD via 400k resistor (old situation) 1: RCX bias supply connected to vref_0v75_0 (use for calibration) 0x0 4 - - 0x0 3:0 R/W SW_GP_DATA 0x0 Datasheet CFR0011-120-00 Revision 3.0 266 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.12 OTP Controller Registers Table 276: Register map OTPC Address Register Description 0x07F40000 OTPC_MODE_REG Mode register 0x07F40004 OTPC_STAT_REG Status register 0x07F40008 OTPC_PADDR_REG The address of the word that will be programmed, when the PROG mode is used. 0x07F4000C OTPC_PWORD_REG The 32-bit word that will be programmed, when the PROG mode is used. 0x07F40010 OTPC_TIM1_REG Various timing parameters of the OTP cell. 0x07F40014 OTPC_TIM2_REG Various timing parameters of the OTP cell. 0x07F40018 OTPC_AHBADR_REG AHB master start address 0x07F4001C OTPC_CELADR_REG OTP cell start address 0x07F40020 OTPC_NWORDS_RE G Number of words Table 277: OTPC_MODE_REG (0x07F40000) Bit Mode Symbol 31:8 - - 7:6 R/W OTPC_MODE_PRG _SEL Defines the part of the OTP cell that is programmed by the controller during the PROG mode, for each program request that is applied. 0x0 : Both normal and redundancy arrays are programmed. This is the normal way of programming. 0x1 : Only the normal array is programmed. 0x2 : Only the redundancy array is programmed. 0x3 : Reserved The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The setting will take effect when will be enabled again the PROG mode. 0x0 5 R/W OTPC_MODE_HT_ MARG_EN Defines the temperature condition under which is performed a margin read. It affects only the initial margin read (RINI mode) and the programming verification margin read (PVFY). 0 : Regular temperature condition (less than 85°C) 1 : High temperature condition (85°C or more) The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The selection will take effect at the next PVFY or RINI mode that will be enabled. The READ mode is not affected by the setting of this configuration bit. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 267 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R/W OTPC_MODE_USE _TST_ROW Selects the memory area of the OTP cell that will be used. 0 - Uses the main memory area of the OTP cell 1 - Uses the test row of the OTP cell The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The selection will take effect at the next programming or reading mode that will be enabled. 0x0 3 - - 2:0 R/W OTPC_MODE_MO DE 0x0 Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 0x0: DSTBY. The OTP memory is in deep standby mode (power supply ON and internal LDO OFF). 0x1: STBY. The OTP memory is powered (power supply ON and internal LDO ON, but is not selected). 0x2: READ. The OTP memory is in the normal read mode. 0x3: PROG. The OTP memory is in programming mode. 0x4: PVFY. The OTP memory is in programming verification mode (margin read after programming). 0x5: RINI. The OTP memory is in initial read mode (initial margin read). 0x6: AREAD. Copying of data from the OTP memory to a system RAM by using the internal DMA. See also the registers OTPC_AHBADR_REG, OTPC_CELADR_REG and OTPC_NWORDS_REG. 0x0 Whenever the OTPC_MODE_REG[MODE] is changing, the status bit OTPC_STAT_REG[OTPC_STAT_MRDY] gets the value zero. The new mode will be ready for use when the OTPC_STAT_MRDY become again 1. During the mode transition the OTPC_MODE_REG[MODE] become read only. Do not try to use or change any function of the controller until the OTPC_STAT_MRDY bit to become equal to 1. The data transferring that is performed by using the AREAD mode is completed when OTPC_STAT_MRDY becomes again 1. The mode change automatically to DSTBY with the completion of the transfer. Table 278: OTPC_STAT_REG (0x07F40004) Bit Mode Symbol 31:3 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 268 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2 R OTPC_STAT_MRD Y Indicates the progress of the transition from a mode of operation to a new mode of operation. 0 : There is a transition in progress in a new mode of operation . Wait until the transition to be completed. 1 : The transition to the new mode of operation has been completed. The function that has been enabled by the new mode can be used. A new mode can be applied. This status bit gets the value zero every time where the OTPC_MODE_REG[MODE] is changing. Do not try to use or change any function of the controller until this status bit to become equal to 1. 0x1 1 R OTPC_STAT_PBUF _EMPTY Indicates the status of the programming buffer (PBUF). 0 : The PBUF contains the address and the data of a programming request. The OTPC_PADDR_REG and the OTPC_PWORD_REG should not be written as long as this status bit is zero. 1 : The PBUF is empty and a new programming request can be registered in the PBUF by using the OTPC_PADDR_REG and the OTPC_PWORD_REG registers. This status bit gets the value zero every time where a programming is triggered by the OTPC_PADDR_REG (only if the PROG mode is active). 0x1 0 R OTPC_STAT_PRD Y Indicates the state of the programming process. 0: The controller is busy. A programming is in progress. 1: The logic which performs programming is idle. 0x1 Table 279: OTPC_PADDR_REG (0x07F40008) Bit Mode Symbol 31:13 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 269 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 12:0 R/W OTPC_PADDR The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory. The OTPC_PADDR_REG refers to a word address. The OTPC_PADDR_REG has to be writen after the OTP_PWORD_REG and only if the OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY] =1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY ]=0). A writting to the OTPC_PADDR_REG triggers the controller to start the programming procedure (only if the PROG mode is active). 0x0 Table 280: OTPC_PWORD_REG (0x07F4000C) Bit Mode Symbol Description Reset 31:0 R/W OTPC_PWORD The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP memory, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory. The OTP_PWORD_REG must be written before the OTPC_PADDR_REG and only if OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY] = 1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY ]=0). 0x0 Table 281: OTPC_TIM1_REG (0x07F40010) Bit Mode Symbol 31 - - 30:24 R/W OTPC_TIM1_US_T _CSP Datasheet CFR0011-120-00 Description Reset 0x0 The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for programming. It must be : - at least 10us - no more than 100us Revision 3.0 270 of 374 0x9 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 23:20 R/W OTPC_TIM1_US_T _CS The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for any kind of read. It must be at least 10us. 0x9 19:16 R/W OTPC_TIM1_US_T _PL The number of microseconds (minus one) that are required until to be enabled the LDO of the OTP. It must be at least 10us. 0x9 15 - - 14:12 R/W OTPC_TIM1_CC_T _RD 11:10 - - 9:8 R/W OTPC_TIM1_CC_T _20NS 7 - - 6:0 R/W OTPC_TIM1_CC_T _1US 0x0 The number of hclk_c clock periods (minus one) that give a time interval at least higher than 60ns. This timing parameter refers to the access time of the OTP memory. 0x0 0x0 The number of hclk_c clock periods (minus one) that give a time interval that is at least higher than 20 ns. 0x0 0x0 The number of hclk_c clock periods (minus one) that give a time interval equal to 1us. This setting affects all the timing parameters that refer to microseconds, due to that defines the correspondence of a microsecond to a number of hclk_c clock cycles. 0xF Table 282: OTPC_TIM2_REG (0x07F40014) Bit Mode Symbol Description Reset 31 R/W OTPC_TIM2_US_A DD_CC_EN Adds an additional hclk_c clock cycle at all the time intervals that count in microseconds. 0 : The extra hclk_c clock cycle is not applied 1 : The extra hclk_c clock cycle is applied 0x1 30:29 R/W OTPC_TIM2_US_T _SAS The number of microseconds (minus one) that are required after the exit from the deep sleep standby mode and before to become ready to enter in an active mode (reading or programming). It must be at least 2us. 0x1 28:24 R/W OTPC_TIM2_US_T _PPH The number of microseconds (minus one) that are required after the last programming pulse and before to be disabled the programming mode in the OTP memory. It must be: - at least 5us - no more than 20us 0x4 23:21 R/W OTPC_TIM2_US_T _VDS The number of microseconds (minus one) that are required after the enabling of the power supply of the OTP memory and before to become ready for the enabling of the internal LDO. It must be at least 1us. 0x0 Datasheet CFR0011-120-00 Revision 3.0 271 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 20:16 R/W OTPC_TIM2_US_T _PPS The number of microseconds (minus one) that are required after the enabling of the programming in the OTP memory and before to be applied the first programming pulse. It must be : - at least 5us - no more than 20us 0x4 15 - - 14:8 R/W OTPC_TIM2_US_T _PPR The number of microseconds (minus one) for recovery after a programming sequence. It must be : - at least 5us - no more than 100us 0x4 7:5 R/W OTPC_TIM2_US_T _PWI The number of microseconds (minus one) between two consecutive programming pulses. It must be : - at least 1us - no more than 5us 0x0 4:0 R/W OTPC_TIM2_US_T _PW The number of microseconds (minus one) that lasts the programming of each bit. It must be : - at least 10us - no more than 20us 0x9 0x0 Table 283: OTPC_AHBADR_REG (0x07F40018) Bit Mode Symbol 31:16 - - 15:2 R/W OTPC_AHBADR 1:0 - - Description Reset 0x0 It is the AHB address used by the AHB master interface of the controller (the bits [15:2]). The bits [1:0] of the address are considered always as equal to zero. The value of the register remains unchanged, by the internal logic of the controller. 0x0 0x0 Table 284: OTPC_CELADR_REG (0x07F4001C) Bit Mode Symbol 31:13 - - 12:0 R/W OTPC_CELADR Datasheet CFR0011-120-00 Description Reset 0x0 Defines a word address inside the OTP cell that will be used during the AREAD mode and the OTP mirroring. Revision 3.0 272 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 285: OTPC_NWORDS_REG (0x07F40020) Bit Mode Symbol 31:13 - - 12:0 R/W OTPC_NWORDS Datasheet CFR0011-120-00 Description Reset 0x0 The number of words (minus one) that will be copied by the AREAD mode. During mirroring, this register reflects the amount of data that will be copied. Revision 3.0 273 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.13 Quadrature Decoder Registers Table 286: Register map QDEC Address Register Description 0x50000200 QDEC_CTRL_REG Quad Decoder control register 0x50000202 QDEC_XCNT_REG Counter value of the X Axis 0x50000204 QDEC_YCNT_REG Counter value of the Y Axis 0x50000206 QDEC_CLOCKDIV_R EG Clock divider register 0x50000208 QDEC_CTRL2_REG Quad Decoder port selection register 0x5000020A QDEC_ZCNT_REG Counter value of the Z Axis 0x5000020C QDEC_EVENT_CNT_ REG Event counter register Table 287: QDEC_CTRL_REG (0x50000200) Bit Mode Symbol Description Reset 10:3 R/W QDEC_IRQ_THRES Defines the number of events on either counter (X or Y or Z) that need to be reached before an interrupt is generated. Events are equal to QDEC_IRQ_THRES+1. 0x2 2 R/W QDEC_IRQ_STATU S 1 = Interrupt is occured. 0 = No interrupt pending Write 1 will clear the pending interrupt 0x0 1 R0/WC QDEC_EVENT_CN T_CLR Writing 1 QDEC_EVENT_CNT_REG is cleared 0x0 0 R/W QDEC_IRQ_ENABL E 0 = interrupt is masked 1 = interrupt is enabled 0x1 Table 288: QDEC_XCNT_REG (0x50000202) Bit Mode Symbol Description Reset 15:0 R QDEC_X_CNT Contains a signed value of the events. Zero when channel is disabled 0x0 Table 289: QDEC_YCNT_REG (0x50000204) Bit Mode Symbol Description Reset 15:0 R QDEC_Y_CNT Contains a signed value of the events. Zero when channel is disabled 0x0 Datasheet CFR0011-120-00 Revision 3.0 274 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 290: QDEC_CLOCKDIV_REG (0x50000206) Bit Mode Symbol Description Reset 10 R/W QDEC_PRESCALE R_EN 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2 0x0 9:0 R/W QDEC_CLOCKDIV Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK 0x3E7 Table 291: QDEC_CTRL2_REG (0x50000208) Bit Mode Symbol Description Reset 11 R/W QDEC_CHZ_EVEN T_MODE 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1) 0x1 10 R/W QDEC_CHY_EVEN T_MODE 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1) 0x1 9 R/W QDEC_CHX_EVEN T_MODE 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1) 0x1 8:6 R/W QDEC_CHZ_PORT _SEL Defines which GPIOs are mapped on Channel Z 0: none 1: P0[2] -> CHZ_A, P0[5] -> CHZ_B 2: P0[1] -> CHZ_A, P0[4] -> CHZ_B 3: P0[3] -> CHZ_A, P0[10] -> CHZ_B 4: P0[6] -> CHZ_A, P0[7] -> CHZ_B 5: P0[8] -> CHZ_A, P0[9] -> CHZ_B 6: P0[0] -> CHZ_A, P0[11] -> CHZ_B 7: none 3 5:3 R/W QDEC_CHY_PORT _SEL Defines which GPIOs are mapped on Channel Y 0: none 1: P0[2] -> CHY_A, P0[5] -> CHY_B 2: P0[1] -> CHY_A, P0[4] -> CHY_B 3: P0[3] -> CHY_A, P0[10] -> CHY_B 4: P0[6] -> CHY_A, P0[7] -> CHY_B 5: P0[8] -> CHY_A, P0[9] -> CHY_B 6: P0[0] -> CHY_A, P0[11] -> CHY_B 7: none 2 Datasheet CFR0011-120-00 Revision 3.0 275 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2:0 R/W QDEC_CHX_PORT _SEL Defines which GPIOs are mapped on Channel X 0: none 1: P0[2] -> CHX_A, P0[5] -> CHX_B 2: P0[1] -> CHX_A, P0[4] -> CHX_B 3: P0[3] -> CHX_A, P0[10] -> CHX_B 4: P0[6] -> CHX_A, P0[7] -> CHX_B 5: P0[8] -> CHX_A, P0[9] -> CHX_B 6: P0[0] -> CHX_A, P0[11] -> CHX_B 7: none 1 Table 292: QDEC_ZCNT_REG (0x5000020A) Bit Mode Symbol Description Reset 15:0 R QDEC_Z_CNT Contains a signed value of the events. Zero when channel is disabled 0 Table 293: QDEC_EVENT_CNT_REG (0x5000020C) Bit Mode Symbol Description Reset 7:0 R QDEC_EVENT_CN T Gives the number of events at all channels. 0x0 Datasheet CFR0011-120-00 Revision 3.0 276 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.14 Real Time Clock Registers Table 294: Register map rtc2632_00 Address Register Description 0x50004100 RTC_CONTROL_REG RTC Control Register 0x50004104 RTC_HOUR_MODE_ REG RTC Hour Mode Register 0x50004108 RTC_TIME_REG RTC Time Register 0x5000410C RTC_CALENDAR_RE G RTC Calendar Register 0x50004110 RTC_TIME_ALARM_R EG RTC Time Alarm Register 0x50004114 RTC_CALENDAR_AL ARM_REG RTC Calendar Alram Register 0x50004118 RTC_ALARM_ENABL E_REG RTC Alarm Enable Register 0x5000411C RTC_EVENT_FLAGS _REG RTC Event Flags Register 0x50004120 RTC_INTERRUPT_EN ABLE_REG RTC Interrupt Enable Register 0x50004124 RTC_INTERRUPT_DI SABLE_REG RTC Interrupt Disable Register 0x50004128 RTC_INTERRUPT_M ASK_REG RTC Interrupt Mask Register 0x5000412C RTC_STATUS_REG RTC Status Register 0x50004130 RTC_KEEP_RTC_RE G RTC Keep RTC Register Table 295: RTC_CONTROL_REG (0x50004100) Bit Mode Symbol Description Reset 1 R/W RTC_CAL_DISABL E When this field is set high the RTC stops incrementing the calendar value. 0x1 0 R/W RTC_TIME_DISABL E When this field is set high the RTC stops incrementing the time value. 0x1 Table 296: RTC_HOUR_MODE_REG (0x50004104) Bit Mode Symbol Description Reset 0 R/W RTC_HMS When this field is set high the RTC operates in 12 hour clock mode; otherwise, times are in 24 hour clock format. 0x0 Datasheet CFR0011-120-00 Revision 3.0 277 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 297: RTC_TIME_REG (0x50004108) Bit Mode Symbol Description Reset 31 R/W RTC_TIME_CH The value in this register has altered since last read. Read and clear. 0x0 30 R/W RTC_TIME_PM In 12 hour clock mode, indicates PM when set. 0x0 29:28 R/W RTC_TIME_HR_T Hours tens. Represented in BCD digit (0-2). 0x0 27:24 R/W RTC_TIME_HR_U Hours units. Represented in BCD digit (0-9). 0x0 23 - - 22:20 R/W RTC_TIME_M_T Minutes tens. Represented in BCD digit (0-5). 0x0 19:16 R/W RTC_TIME_M_U Minutes units. Represented in BCD digit (0-9). 0x0 15 - - 14:12 R/W RTC_TIME_S_T Seconds tens. Represented in BCD digit (0-9). 0x0 11:8 R/W RTC_TIME_S_U Seconds units. Represented in BCD digit (0-9). 0x0 7:4 R/W RTC_TIME_H_T Hundredths of a second tens. Represented in BCD digit (0-9). 0x0 3:0 R/W RTC_TIME_H_U Hundredths of a second units. Represented in BCD digit (0-9). 0x0 0x0 0x0 Table 298: RTC_CALENDAR_REG (0x5000410C) Bit Mode Symbol Description Reset 31 R/W RTC_CAL_CH The value in this register has altered since last read. Read and clear 0x0 30 - - 29:28 R/W RTC_CAL_C_T Century tens. Represented in BCD digit (1-2). 0x2 27:24 R/W RTC_CAL_C_U Century units. Represented in BCD digit (0-9). 0x0 23:20 R/W RTC_CAL_Y_T Year tens. Represented in BCD digit (0-9). 0x0 19:16 R/W RTC_CAL_Y_U Year units. Represented in BCD digit (0-9). 0x0 15:14 - - 13:12 R/W RTC_CAL_D_T Date tens. Represented in BCD digit (0-3). 0x0 11:8 R/W RTC_CAL_D_U Date units. Represented in BCD digit (0-9). 0x1 7 R/W RTC_CAL_M_T Month tens. Represented in BCD digit (0-1). 0x0 6:3 R/W RTC_CAL_M_U Month units. Represented in BCD digit (0-9). 0x1 2:0 R/W RTC_DAY Day of the week (arbitrary) units. Represented in BCD digit (0-7). 0x7 0x0 0x0 Table 299: RTC_TIME_ALARM_REG (0x50004110) Bit Mode Symbol 31 - - 30 R/W RTC_TIME_PM Datasheet CFR0011-120-00 Description Reset 0x0 In 12 hour clock mode, indicates PM when set. Revision 3.0 278 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 29:28 R/W RTC_TIME_HR_T Hours tens. Represented in BCD digit (0-2). 0x0 27:24 R/W RTC_TIME_HR_U Hours units. Represented in BCD digit (0-9). 0x0 23 - - 22:20 R/W RTC_TIME_M_T Minutes tens. Represented in BCD digit (0-5). 0x0 19:16 R/W RTC_TIME_M_U Minutes units. Represented in BCD digit (0-9). 0x0 15 - - 14:12 R/W RTC_TIME_S_T Seconds tens. Represented in BCD digit (0-9). 0x0 11:8 R/W RTC_TIME_S_U Seconds units. Represented in BCD digit (0-9). 0x0 7:4 R/W RTC_TIME_H_T Hundredths of a second tens. Represented in BCD digit (0-9). 0x0 3:0 R/W RTC_TIME_H_U Hundredths of a second units. Represented in BCD digit (0-9). 0x0 0x0 0x0 Table 300: RTC_CALENDAR_ALARM_REG (0x50004114) Bit Mode Symbol Description Reset 31:14 R/W - 13:12 R/W RTC_CAL_D_T Date tens. Represented in BCD digit (0-3). 0x0 11:8 R/W RTC_CAL_D_U Date units. Represented in BCD digit (0-9). 0x0 7 R/W RTC_CAL_M_T Month tens. Represented in BCD digit (0-1). 0x0 6:3 R/W RTC_CAL_M_U Month units. Represented in BCD digit (0-9). 0x0 2:0 - - 0x0 0x0 Table 301: RTC_ALARM_ENABLE_REG (0x50004118) Bit Mode Symbol Description Reset 5 R/W RTC_ALARM_MNT H_EN Alarm on month enable. Enable to trigger alarm when data specified in Calendar Alarm Register (M_T and M_U) has been reached. 0x0 4 R/W RTC_ALARM_DAT E_EN Alarm on date enable. Enable to trigger alarm when data specified in Calendar Alarm Register (D_T and D_U) has been reached. 0x0 3 R/W RTC_ALARM_HOU R_EN Alarm on hour enable. Enable to trigger alarm when data specified in Time Alarm Register (PM, HR_T and HR_U) has been reached. 0x0 2 R/W RTC_ALARM_MIN_ EN Alarm on minute enable. Enable to trigger alarm when data specified in Time Alarm Register (M_T and M_U) has been reached. 0x0 1 R/W RTC_ALARM_SEC _EN Alarm on second enable. Enable to trigger alarm when data specified in Time Alarm Register (S_T and S_U) has been reached. 0x0 Datasheet CFR0011-120-00 Revision 3.0 279 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W RTC_ALARM_HOS _EN Alarm on hundredths of a second enable. Enable to trigger alarm when data specified in Time Alarm Register (H_T and H_U) has been reached. 0x0 Table 302: RTC_EVENT_FLAGS_REG (0x5000411C) Bit Mode Symbol Description Reset 6 R RTC_EVENT_ALR M Alarm event flag. Indicate that alarm event occurred since the last reset. 0x0 5 R RTC_EVENT_MNT H Month rolls over event flag. Indicate that month rolls over event occurred since the last reset. 0x0 4 R RTC_EVENT_DATE Date rolls over event flag. Indicate that date rolls over event occurred since the last reset. 0x0 3 R RTC_EVENT_HOU R Hour rolls over event flag. Indicate that hour rolls over event occurred since the last reset. 0x0 2 R RTC_EVENT_MIN Minute rolls over event flag. Indicate that minute rolls over event occurred since the last reset. 0x0 1 R RTC_EVENT_SEC Second rolls over event flag. Indicate that second rolls over event occurred since the last reset. 0x0 0 R RTC_EVENT_HOS Hundredths of a second event flag. Indicate that hundredths of a second rolls over event occurred since the last reset. 0x0 Table 303: RTC_INTERRUPT_ENABLE_REG (0x50004120) Bit Mode Symbol Description Reset 6 W RTC_ALRM_INT_E N Interrupt on alarm enable. Enable to issue the interrupt when alarm event occurred. 0x0 5 W RTC_MNTH_INT_E N Interrupt on month enable. Enable to issue the interrupt when month event occurred. 0x0 4 W RTC_DATE_INT_E N Interrupt on date enable. Enable to issue the interrupt when date event occurred. 0x0 3 W RTC_HOUR_INT_E N Interrupt on hour enable. Enable to issue the interrupt when hour event occurred. 0x0 2 W RTC_MIN_INT_EN Interrupt on minute enable. Enable to issue the interrupt when minute event occurred. 0x0 1 W RTC_SEC_INT_EN Interrupt on second enable. Enable to issue the interrupt when second event occurred. 0x0 0 W RTC_HOS_INT_EN Interrupt on hundredths of a second enable. Enable to issue the interrupt when hundredths of a second event occurred. 0x0 Datasheet CFR0011-120-00 Revision 3.0 280 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 304: RTC_INTERRUPT_DISABLE_REG (0x50004124) Bit Mode Symbol Description Reset 6 W RTC_ALRM_INT_DI S Interrupt on alarm disable. Disable to issue the interrupt when alarm event occurred. 0x0 5 W RTC_MNTH_INT_D IS Interrupt on month disable. Disable to issue the interrupt when month event occurred. 0x0 4 W RTC_DATE_INT_DI S Interrupt on date disable. Disable to issue the interrupt when date event occurred. 0x0 3 W RTC_HOUR_INT_D IS IInterrupt on hour disable. Disable to issue the interrupt when hour event occurred. 0x0 2 W RTC_MIN_INT_DIS Interrupt on minute disable. Disable to issue the interrupt when minute event occurred. 0x0 1 W RTC_SEC_INT_DIS Interrupt on second disable. Disable to issue the interrupt when second event occurred. 0x0 0 W RTC_HOS_INT_DIS Interrupt on hundredths of a second disable. Disable to issue the interrupt when hundredths of a second event occurred. 0x0 Table 305: RTC_INTERRUPT_MASK_REG (0x50004128) Bit Mode Symbol Description Reset 6 R RTC_ALRM_INT_M SK Mask alarm interrupt. It can be cleared (set) by setting corresponding bit (ALRM) in Interrupt Enable Register (Interrupt Disable Register). 0x1 5 R RTC_MNTH_INT_M SK Mask month interrupt. It can be cleared (set) by setting corresponding bit (MNTH) in Interrupt Enable Register (Interrupt Disable Register). 0x1 4 R RTC_DATE_INT_M SK Mask date interrupt. It can be cleared (set) by setting corresponding bit (DATE) in Interrupt Enable Register (Interrupt Disable Register). 0x1 3 R RTC_HOUR_INT_M SK Mask hour interrupt. It can be cleared (set) by setting corresponding bit (HOUR) in Interrupt Enable Register (Interrupt Disable Register). 0x1 2 R RTC_MIN_INT_MS K Mask minute interrupt. It can be cleared (set) by setting corresponding bit (MIN) in Interrupt Enable Register (Interrupt Disable Register). 0x1 1 R RTC_SEC_INT_MS K Mask second interrupt. It can be cleared (set) by setting corresponding bit (SEC) in Interrupt Enable Register (Interrupt Disable Register). 0x1 0 R RTC_HOS_INT_MS K Mask hundredths of a second interrupt. It can be cleared (set) by setting corresponding bit (HOS) in Interrupt Enable Register (Interrupt Disable Register). 0x1 Datasheet CFR0011-120-00 Revision 3.0 281 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 306: RTC_STATUS_REG (0x5000412C) Bit Mode Symbol Description Reset 3 R RTC_VALID_CAL_ ALM Valid Calendar Alarm. If cleared then indicates that invalid entry occurred when writing to Calendar Alarm Register. 0x1 2 R RTC_VALID_TIME_ ALM Valid Time Alarm. If cleared then indicates that invalid entry occurred when writing to Time Alarm Register. 0x1 1 R RTC_VALID_CAL Valid Calendar. If cleared then indicates that invalid entry occurred when writing to Calendar Register. 0x1 0 R RTC_VALID_TIME Valid Time. If cleared then indicates that invalid entry occurred when writing to Time Register. 0x1 Table 307: RTC_KEEP_RTC_REG (0x50004130) Bit Mode Symbol Description Reset 0 R/W RTC_KEEP Keep RTC. When high, the time and calendar registers and any other registers which directly affect or are affected by the time and calendar registers are NOT reset when software reset is applied. When low, the software reset will reset every register except the keep RTC and control registers. 0x1 Datasheet CFR0011-120-00 Revision 3.0 282 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.15 SPI Interface Registers Table 308: Register map SPI Address Register Description 0x50001200 SPI_CTRL_REG Spi control register 0x50001204 SPI_CONFIG_REG Spi control register 0x50001208 SPI_CLOCK_REG Spi clock register 0x5000120C SPI_FIFO_CONFIG_R EG Spi fifo configuration register 0x50001210 SPI_IRQ_MASK_REG Spi interrupt mask register 0x50001214 SPI_STATUS_REG Spi status register 0x50001218 SPI_FIFO_STATUS_R EG SPI RX/TX fifo status register 0x5000121C SPI_FIFO_READ_RE G Spi RX fifo read register 0x50001220 SPI_FIFO_WRITE_RE G Spi TX fifo wtite register 0x50001224 SPI_CS_CONFIG_RE G Spi cs configuration register 0x50001228 SPI_FIFO_HIGH_REG Spi TX/RX High 16bit word 0x5000122C SPI_TXBUFFER_FOR CE_L_REG SPI TX buffer force low value 0x50001230 SPI_TXBUFFER_FOR CE_H_REG SPI TX buffer force high value Table 309: SPI_CTRL_REG (0x50001200) Bit Mode Symbol Description Reset 7 R/W SPI_SWAP_BYTES 0 = normal operation 1 = LSB and MSB are swaped in APB interface In case of 8bit spi interface, DMA/SPI can be configured in 16bit mode to off load the bus. Enabling SPI_SWAP_BYTES bytes will read/wrte correctly 0x0 6 R/W SPI_CAPTURE_AT _NEXT_EDGE 0 = SPI captures data at correct clock edge 1 = SPI captures data at next clock edge. (only for Master mode and high clock) 0x0 5 R/W SPI_FIFO_RESET 0 = Fifo normal operation 1 = Fifo in reset state 0x0 4 R/W SPI_DMA_RX_EN applicable only when SPI_RX_EN=1 0 = No DMA request for RX 1 = DMA request when SPI_STATUS_RX_FULL='1' 0x0 Datasheet CFR0011-120-00 Revision 3.0 283 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R/W SPI_DMA_TX_EN applicable only when SPI_TX_EN=1 0 = No DMA request for TX 1 = DMA request when SPI_STATUS_TX_EMPTY='1' 0x0 2 R/W SPI_RX_EN 0 = RX path is disabled 1 = RX path is enabled Note: if master clk async or spi mode=1 or spi mode=3 readonly is not supported 0x0 1 R/W SPI_TX_EN 0 = TX path is disabled 1 = TX path is enabled 0x0 0 R/W SPI_EN 0 = SPI module is disable 1 = SPI module is enable 0x0 Table 310: SPI_CONFIG_REG (0x50001204) Bit Mode Symbol Description Reset 7 R/W SPI_SLAVE_EN 0 = SPI module master mode 1 = SPI module slave mode 0x0 6:2 R/W SPI_WORD_LENG TH Define the spi word length = 1+ SPI_WORD_LENGTH (range 4 to 32) 0x0 1:0 R/W SPI_MODE Define the spi mode (CPOL, CPHA) 0 = new data on falling, capture on rising, clk low in idle state 1 = new data on rising, capture on falling, Clk low in idle state 2 = new data on rising, capture on falling, Clk high in idle state 3 = new data on falling, capture on rising Clk high in idle state 0x0 Table 311: SPI_CLOCK_REG (0x50001208) Bit Mode Symbol Description Reset 7 R/W SPI_MASTER_CLK _MODE Should be always 1 0x0 Datasheet CFR0011-120-00 Revision 3.0 284 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 6:0 R/W SPI_CLK_DIV Applicable only in master mode Defines the spi clock frequency in master only mode SPI_CLK = module_clk / 2*(SPI_CLK_DIV+1) when SPI_CLK_DIV not 0x7F if SPI_CLK_DIV=0x7F then SPI_CLK=module_clk 0x0 Table 312: SPI_FIFO_CONFIG_REG (0x5000120C) Bit Mode Symbol Description Reset 7:4 R/W SPI_RX_TL Receive FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the RX_FULL interrupt. IRQ is occurred when fifo level is more or equal to SPI_RX_TL+1. Fifo level is from 0 to 4 0x0 3:0 R/W SPI_TX_TL Transmit FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the TX_EMPTY interrupt. IRQ is occurred when fifo level is less or equal to SPI_TX_TL. Fifo level is from 0 to 4 0x0 Table 313: SPI_IRQ_MASK_REG (0x50001210) Bit Mode Symbol Description Reset 1 R/W SPI_IRQ_MASK_R X_FULL 0 = FIFO RX full irq is masked 1 = FIFO RX full irq is enabled 0x0 0 R/W SPI_IRQ_MASK_TX _EMPTY 0 = FIFO TX empty irq is masked 1 = FIFO TX empy irq is enabled 0x0 Table 314: SPI_STATUS_REG (0x50001214) Bit Mode Symbol Description Reset 1 R SPI_STATUS_RX_ FULL Auto clear 0 = RX fifo level is less than SPI_RX_TL+1 1 = RX fifo level is more or equal to SPI_RX_TL+1 0x0 0 R SPI_STATUS_TX_E MPTY Auto clear 0 = TX fifo level is larger than SPI_TX_TL 1 = TX fifo level is less or equal to SPI_TX_TL 0x1 Datasheet CFR0011-120-00 Revision 3.0 285 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 315: SPI_FIFO_STATUS_REG (0x50001218) Bit Mode Symbol Description Reset 15 R SPI_TRANSACTIO N_ACTIVE In master mode 0 = spi transaction is inactive 1 = spi transaction is active 0x0 14 R SPI_RX_FIFO_OVF L When 1, receive data is not written to fifo because fifo was full and interrupt is generated. It clears with SPI_CTRL_REG.SPI_FIFO_RESET 0x0 13 R SPI_STATUS_TX_F ULL 0 = TX fifo is not full 1 = TX fifo is full 0x0 12 R SPI_STATUS_RX_ EMPTY 0 = RX fifo is not empty 1 = RX fifo is empty 0x1 11:6 R SPI_TX_FIFO_LEV EL Gives the number of bytes in TX fifo 0x0 5:0 R SPI_RX_FIFO_LEV EL Gives the number of bytes in RX fifo 0x0 Table 316: SPI_FIFO_READ_REG (0x5000121C) Bit Mode Symbol Description Reset 15:0 R SPI_FIFO_READ Read from RX fifo. Read access is permit only if SPI_STATUS_RX_EMPTY=0. Returns the 16 LSb 0x0 Table 317: SPI_FIFO_WRITE_REG (0x50001220) Bit Mode Symbol Description Reset 15:0 R0/W SPI_FIFO_WRITE Write to TX fifo. Write access is permit only if SPI_STATUS_TX_FULL is 0 0x0 Table 318: SPI_CS_CONFIG_REG (0x50001224) Bit Mode Symbol Description Reset 2:0 R/W SPI_CS_SELECT Control the cs output in master mode 0 = none slave device selected 1 = selected slave device connected to GPIO with FUNC_MODE=SPI_CS0 2 = selected slave device connected to GPIO with FUNC_MODE=SPI_CS1 4 = selected slave device connected to GPIO with FUNC_MODE=GPIO 0x0 Datasheet CFR0011-120-00 Revision 3.0 286 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 319: SPI_FIFO_HIGH_REG (0x50001228) Bit Mode Symbol Description Reset 15:0 R/W SPI_FIFO_HIGH RX/TX fifo data. 16 MSb when spi word is larger than 16bits This register has to be written before the SPI_FIFO_WRITE_REG This register has to be read after the SPI_FIFO_READ_REG 0x0 Table 320: SPI_TXBUFFER_FORCE_L_REG (0x5000122C) Bit Mode Symbol Description Reset 15:0 W SPI_TXBUFFER_F ORCE_L Write directly the tx buffer (2 LSB). It must to be used only in slave mode 0x0 Table 321: SPI_TXBUFFER_FORCE_H_REG (0x50001230) Bit Mode Symbol Description Reset 15:0 W SPI_TXBUFFER_F ORCE_H Write directly the tx buffer (2 MSB). It must to be used only in slave mode. This register has to be written before the SPI_FIFO_WRITE_REG 0x0 Datasheet CFR0011-120-00 Revision 3.0 287 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.16 Timer and Triple PWM Registers Table 322: Register map Timer+3PWM Address Register Description 0x50003400 TIMER0_CTRL_REG Timer0 control register 0x50003402 TIMER0_ON_REG Timer0 on control register 0x50003404 TIMER0_RELOAD_M_ REG 16 bits reload value for Timer0 0x50003406 TIMER0_RELOAD_N_ REG 16 bits reload value for Timer0 0x50003408 TRIPLE_PWM_FREQ UENCY Frequency for PWM 2,3,4,5,6 and 7 0x5000340A PWM2_START_CYCL E Defines start Cycle for PWM2 0x5000340C PWM3_START_CYCL E Defines start Cycle for PWM3 0x5000340E PWM4_START_CYCL E Defines start Cycle for PWM4 0x50003410 PWM5_START_CYCL E Defines start Cycle for PWM5 0x50003412 PWM6_START_CYCL E Defines start Cycle for PWM6 0x50003414 PWM7_START_CYCL E Defines start Cycle for PWM7 0x50003416 PWM2_END_CYCLE Defines end Cycle for PWM2 0x50003418 PWM3_END_CYCLE Defines end Cycle for PWM3 0x5000341A PWM4_END_CYCLE Defines end Cycle for PWM4 0x5000341C PWM5_END_CYCLE Defines end Cycle for PWM5 0x5000341E PWM6_END_CYCLE Defines end Cycle for PWM6 0x50003420 PWM7_END_CYCLE Defines end Cycle for PWM7 0x50003422 TRIPLE_PWM_CTRL_ REG PWM 2,3,4,5,6,7 Control Table 323: TIMER0_CTRL_REG (0x50003400) Bit Mode Symbol 15:4 - - 3 R/W PWM_MODE Datasheet CFR0011-120-00 Description Reset 0x0 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz. Revision 3.0 288 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2 R/W TIM0_CLK_DIV 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter. 0x0 1 R/W TIM0_CLK_SEL 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses LP clock 0x0 0 R/W TIM0_CTRL 0 = Timer0 is off and in reset state. 1 = Timer0 is running. 0x0 Table 324: TIMER0_ON_REG (0x50003402) Bit Mode Symbol Description Reset 15:0 R/W TIM0_ON Timer0 On reload value: If read the actual ON-counter value is returned 0x0 Table 325: TIMER0_RELOAD_M_REG (0x50003404) Bit Mode Symbol Description Reset 15:0 R/W TIM0_M Timer0 'high' reload value If read the actual T0-counter value is returned 0x0 Table 326: TIMER0_RELOAD_N_REG (0x50003406) Bit Mode Symbol Description Reset 15:0 R/W TIM0_N Timer0 'low' reload value: If read the actual T0-counter value is returned 0x0 Table 327: TRIPLE_PWM_FREQUENCY (0x50003408) Bit Mode Symbol Description Reset 13:0 R/W PWM_FREQ Defines the frequeancy of PWM 2,3,4,5,,6 and 7. pwm freq = module Frequency / (value+1) module frequency is the LP_CLK when TRIPLE_PWM_CLK_SEL=0 else is the sys_clk divided by TMR_DIV 0x0 Datasheet CFR0011-120-00 Revision 3.0 289 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 328: PWM2_START_CYCLE (0x5000340A) Bit Mode Symbol Description Reset 13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0x0 Table 329: PWM3_START_CYCLE (0x5000340C) Bit Mode Symbol Description Reset 13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0x0 Table 330: PWM4_START_CYCLE (0x5000340E) Bit Mode Symbol Description Reset 13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0x0 Table 331: PWM5_START_CYCLE (0x50003410) Bit Mode Symbol Description Reset 13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0x0 Table 332: PWM6_START_CYCLE (0x50003412) Bit Mode Symbol Description Reset 13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0x0 Table 333: PWM7_START_CYCLE (0x50003414) Bit Mode Symbol Description Reset 13:0 R/W START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0x0 Datasheet CFR0011-120-00 Revision 3.0 290 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 334: PWM2_END_CYCLE (0x50003416) Bit Mode Symbol Description Reset 13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0x0 Table 335: PWM3_END_CYCLE (0x50003418) Bit Mode Symbol Description Reset 13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0x0 Table 336: PWM4_END_CYCLE (0x5000341A) Bit Mode Symbol Description Reset 13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0x0 Table 337: PWM5_END_CYCLE (0x5000341C) Bit Mode Symbol Description Reset 13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0x0 Table 338: PWM6_END_CYCLE (0x5000341E) Bit Mode Symbol Description Reset 13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0x0 Table 339: PWM7_END_CYCLE (0x50003420) Bit Mode Symbol Description Reset 13:0 R/W END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0x0 Datasheet CFR0011-120-00 Revision 3.0 291 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 340: TRIPLE_PWM_CTRL_REG (0x50003422) Bit Mode Symbol Description Reset 3 R/W TRIPLE_PWM_CLK _SEL 1 = Timer2 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer2 uses LP clock 0x0 2 R/W HW_PAUSE_EN '1' = HW can pause PWM 2,3,4,5,6,7 0x1 1 R/W SW_PAUSE_EN '1' = PWM 2 3 4 5 6 7 are paused 0x0 0 R/W TRIPLE_PWM_ENA BLE '1' = enable PWM 2 3 4 5 6 7 0x0 Datasheet CFR0011-120-00 Revision 3.0 292 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.17 Timer1 Registers Table 341: Register map Timer1 Address Register Description 0x50004000 TIMER1_CTRL_REG Timer1 control register 0x50004004 TIMER1_CAPTURE_R EG Timer1 Capture control register 0x50004008 TIMER1_STATUS_RE G Timer1 counter value 0x5000400C TIMER1_CAPCNT1_V ALUE_REG Timer1 value for event on GPIO1 0x50004010 TIMER1_CAPCNT2_V ALUE_REG Timer1 value for event on GPIO2 0x50004014 TIMER1_CLR_EVENT _REG Clear event register Table 342: TIMER1_CTRL_REG (0x50004000) Bit Mode Symbol Description Reset 16 R/W TIMER1_CLK_EN 0 = timer1 clock is disabled 1 = timer1 clock is enabled 0x0 15 R/W TIMER1_USE_SYS _CLK 0 = Timer1 use the clock LP clock 1 = Timer1 use the system clock 0x0 14 R/W TIMER1_FREE_RU N_MODE_EN Applicable when timer counts up 1 = timer1 goes to zero when it reaches the max value. 0 = timer1 goes to zero when it reaches the reload value. 0x0 13 R/W TIMER1_IRQ_EN 0 = timer1 IRQ masked 1 = timer1 IRQ unmasked 0x0 12 R/W TIMER1_COUNT_D OWN_EN 0 = timer1 counts up 1 = timer1 counts down 0x0 11 R/W TIMER1_ENABLE 0 = Timer1 disabled 1 = Timer1 enabled 0x0 10:0 R/W TIMER1_RELOAD Reload or max value in timer mode. Actual delay is the register value plus synchronization time (3 clock cycles) 0x0 Table 343: TIMER1_CAPTURE_REG (0x50004004) Bit Mode Symbol Description Reset 27 R/W TIMER1_IN2_STAM P_TYPE 0 = On each event store the counter value 1 = On each event store the RTC time stamp 0x0 Datasheet CFR0011-120-00 Revision 3.0 293 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 26:21 R/W TIMER1_IN2_PERI OD_MAX Gives the number of periods +1 of IN2, in which module counts 0x0 20 R/W TIMER1_IN2_IRQ_ EN 1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN2_PERIOD_MAX 0 = Interrupt is masked 0x0 19 R/W TIMER1_IN2_COU NT_EN 0 = Capture mode 1 = Count mode 0x0 18 R/W TIMER1_IN2_EVEN T_FALL_EN 0 = Rising edge event 1 = Falling edge event it should be written when TIMER1_GPIO2_CONF=0 to prevent false events 0x0 17:14 R/W TIMER1_GPIO2_C ONF 0,13,14,15 = IN2 is not used 1..12 = Defines the P0 pin (0..11) module will use as IN2 0x0 13 R/W TIMER1_IN1_STAM P_TYPE 0 = On each event store the counter value 1 = On each event store the RTC time stamp 0x0 12:7 R/W TIMER1_IN1_PERI OD_MAX Gives the number of periods +1 of IN1, in which module counts 0x0 6 R/W TIMER1_IN1_IRQ_ EN 1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN1_PERIOD_MAX 0 = Interrupt is masked 0x0 5 R/W TIMER1_IN1_COU NT_EN 0 = Capture mode 1 = Count mode 0x0 4 R/W TIMER1_IN1_EVEN T_FALL_EN 0 = Rising edge event 1 = Falling edge event it should be written when TIMER1_GPIO1_CONF=0 to prevent false events 0x0 3:0 R/W TIMER1_GPIO1_C ONF 0,13,14,15 = IN1 is not used 1..12 = Defines the P0 pin (0..11) module will use as IN1 0x0 Table 344: TIMER1_STATUS_REG (0x50004008) Bit Mode Symbol Description Reset 15 R TIMER1_IN2_OVRF LW 1 = New IN2 event occurred while Interrupt was pending. TIMER1_CAPCNT2_VALUE_REG gives the time stamp of the first event. 0x0 14 R TIMER1_IN1_OVRF LW 1 = New IN1 event occurred while Interrupt was pending. TIMER1_CAPCNT1_VALUE_REG gives the time stamp of the first event. 0x0 13 R TIMER1_IN2_EVEN T 1 = Pending Capture 2 interrupt. It has be clear writing 1 to TIMER1_CLR_IN2_EVENT 0x0 Datasheet CFR0011-120-00 Revision 3.0 294 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 12 R TIMER1_IN1_EVEN T 1 = Pending Capture 1 interrupt. It has be clear writing 1 to TIMER1_CLR_IN1_EVENT 0x0 11 R TIMER1_TIMER_E VENT 1 = Pending Timer interrupt. it has be clear writing 1' to TIMER1_CLR_TIMER_EVENT 0x0 10:0 R TIMER1_TIMER_V ALUE Gives the current timer value 0x0 Table 345: TIMER1_CAPCNT1_VALUE_REG (0x5000400C) Bit Mode Symbol Description Reset 21:11 R TIMER1_CAPCNT1 _RTC_HIGH In Counter mode : Not used In Capture mode: Gives the RTC time stamp (high part) when an IN1 event was occurred 0x0 10:0 R TIMER1_CAPCNT1 _VALUE In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN1_PERIOD_MAX periods of IN1 In Capture mode (TIMER1_IN1_STAMP_TYPE=0) : Gives the Counter value when an IN1 event was occurred In Capture mode (TIMER1_IN1_STAMP_TYPE=1) : Gives the RTC time stamp (low part) when an IN1 event was occurred 0x0 Table 346: TIMER1_CAPCNT2_VALUE_REG (0x50004010) Bit Mode Symbol Description Reset 21:11 R TIMER1_CAPCNT2 _RTC_HIGH In Counter mode : Not used In Capture mode: Gives the RTC time stamp (high part) when an IN2 event was occurred 0x0 10:0 R TIMER1_CAPCNT2 _VALUE In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN2_PERIOD_MAX periods of IN2 In Capture mode (TIMER1_IN2_STAMP_TYPE=0) : Gives the Counter value when an IN2 event was occurred In Capture mode (TIMER1_IN2_STAMP_TYPE=1) : Gives the RTC time stamp (low part) when an IN2 event was occurred 0x0 Table 347: TIMER1_CLR_EVENT_REG (0x50004014) Bit Mode Symbol Description Reset 2 R0/WC TIMER1_CLR_IN2_ EVENT Write 1 to clear the TIMER1_IN2_EVENT and TIMER1_IN2_OVRFLW 0x0 Datasheet CFR0011-120-00 Revision 3.0 295 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 1 R0/WC TIMER1_CLR_IN1_ EVENT Write 1 to clear the TIMER1_IN1_EVENT and TIMER1_IN1_OVRFLW 0x0 0 R0/WC TIMER1_CLR_TIME R_EVENT Write 1 to clear the TIMER1_TIMER_EVENT 0x0 Datasheet CFR0011-120-00 Revision 3.0 296 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.18 UART Interface Registers Table 348: Register map UART Address Register Description 0x50001000 UART_RBR_THR_DL L_REG Receive Buffer Register/Transmit Holding Register/Divisor Latch Low 0x50001004 UART_IER_DLH_REG Interrupt Enable Register/Divisor Latch High 0x50001008 UART_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x5000100C UART_LCR_REG Line Control Register 0x50001010 UART_MCR_REG Modem Control Register 0x50001014 UART_LSR_REG Line Status Register 0x50001018 UART_MSR_REG Modem Status Register 0x5000101C UART_SCR_REG Scratchpad Register 0x50001030 UART_SRBR_STHR0 _REG Shadow Receive/Transmit Buffer Register 0x50001034 UART_SRBR_STHR1 _REG Shadow Receive/Transmit Buffer Register 0x50001038 UART_SRBR_STHR2 _REG Shadow Receive/Transmit Buffer Register 0x5000103C UART_SRBR_STHR3 _REG Shadow Receive/Transmit Buffer Register 0x50001040 UART_SRBR_STHR4 _REG Shadow Receive/Transmit Buffer Register 0x50001044 UART_SRBR_STHR5 _REG Shadow Receive/Transmit Buffer Register 0x50001048 UART_SRBR_STHR6 _REG Shadow Receive/Transmit Buffer Register 0x5000104C UART_SRBR_STHR7 _REG Shadow Receive/Transmit Buffer Register 0x50001050 UART_SRBR_STHR8 _REG Shadow Receive/Transmit Buffer Register 0x50001054 UART_SRBR_STHR9 _REG Shadow Receive/Transmit Buffer Register 0x50001058 UART_SRBR_STHR1 0_REG Shadow Receive/Transmit Buffer Register 0x5000105C UART_SRBR_STHR1 1_REG Shadow Receive/Transmit Buffer Register 0x50001060 UART_SRBR_STHR1 2_REG Shadow Receive/Transmit Buffer Register 0x50001064 UART_SRBR_STHR1 3_REG Shadow Receive/Transmit Buffer Register 0x50001068 UART_SRBR_STHR1 4_REG Shadow Receive/Transmit Buffer Register 0x5000106C UART_SRBR_STHR1 5_REG Shadow Receive/Transmit Buffer Register Datasheet CFR0011-120-00 Revision 3.0 297 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Address Register Description 0x50001070 UART_FAR_REG FIFO Access Register 0x5000107C UART_USR_REG UART Status Register 0x50001080 UART_TFL_REG Transmit FIFO Level 0x50001084 UART_RFL_REG Receive FIFO Level 0x50001088 UART_SRR_REG Software Reset Register. 0x5000108C UART_SRTS_REG Shadow Request to Send 0x50001090 UART_SBCR_REG Shadow Break Control Register 0x50001094 UART_SDMAM_REG Shadow DMA Mode 0x50001098 UART_SFE_REG Shadow FIFO Enable 0x5000109C UART_SRT_REG Shadow RCVR Trigger 0x500010A0 UART_STET_REG Shadow TX Empty Trigger 0x500010A4 UART_HTX_REG Halt TX 0x500010A8 UART_DMASA_REG DMA Software Acknowledge 0x500010C0 UART_DLF_REG Divisor Latch Fraction Register 0x500010F8 UART_UCV_REG Component Version 0x500010FA UART_UCV_HIGH_R EG Component Version 0x500010FC UART_CTR_REG Component Type Register 0x500010FE UART_CTR_HIGH_R EG Component Type Register 0x50001100 UART2_RBR_THR_D LL_REG Receive Buffer Register/Transmit Holding Register/Divisor Latch Low 0x50001104 UART2_IER_DLH_RE G Interrupt Enable Register/Divisor Latch High 0x50001108 UART2_IIR_FCR_RE G Interrupt Identification Register/FIFO Control Register 0x5000110C UART2_LCR_REG Line Control Register 0x50001110 UART2_MCR_REG Modem Control Register 0x50001114 UART2_LSR_REG Line Status Register 0x5000111C UART2_SCR_REG Scratchpad Register 0x50001130 UART2_SRBR_STHR 0_REG Shadow Receive/Transmit Buffer Register 0x50001134 UART2_SRBR_STHR 1_REG Shadow Receive/Transmit Buffer Register 0x50001138 UART2_SRBR_STHR 2_REG Shadow Receive/Transmit Buffer Register 0x5000113C UART2_SRBR_STHR 3_REG Shadow Receive/Transmit Buffer Register 0x50001140 UART2_SRBR_STHR 4_REG Shadow Receive/Transmit Buffer Register 0x50001144 UART2_SRBR_STHR 5_REG Shadow Receive/Transmit Buffer Register Datasheet CFR0011-120-00 Revision 3.0 298 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Address Register Description 0x50001148 UART2_SRBR_STHR 6_REG Shadow Receive/Transmit Buffer Register 0x5000114C UART2_SRBR_STHR 7_REG Shadow Receive/Transmit Buffer Register 0x50001150 UART2_SRBR_STHR 8_REG Shadow Receive/Transmit Buffer Register 0x50001154 UART2_SRBR_STHR 9_REG Shadow Receive/Transmit Buffer Register 0x50001158 UART2_SRBR_STHR 10_REG Shadow Receive/Transmit Buffer Register 0x5000115C UART2_SRBR_STHR 11_REG Shadow Receive/Transmit Buffer Register 0x50001160 UART2_SRBR_STHR 12_REG Shadow Receive/Transmit Buffer Register 0x50001164 UART2_SRBR_STHR 13_REG Shadow Receive/Transmit Buffer Register 0x50001168 UART2_SRBR_STHR 14_REG Shadow Receive/Transmit Buffer Register 0x5000116C UART2_SRBR_STHR 15_REG Shadow Receive/Transmit Buffer Register 0x50001170 UART2_FAR_REG FIFO Access Register 0x5000117C UART2_USR_REG UART Status Register 0x50001180 UART2_TFL_REG Transmit FIFO Level 0x50001184 UART2_RFL_REG Receive FIFO Level 0x50001188 UART2_SRR_REG Software Reset Register. 0x50001190 UART2_SBCR_REG Shadow Break Control Register 0x50001194 UART2_SDMAM_REG Shadow DMA Mode 0x50001198 UART2_SFE_REG Shadow FIFO Enable 0x5000119C UART2_SRT_REG Shadow RCVR Trigger 0x500011A0 UART2_STET_REG Shadow TX Empty Trigger 0x500011A4 UART2_HTX_REG Halt TX 0x500011A8 UART2_DMASA_REG DMA Software Acknowledge 0x500011C0 UART2_DLF_REG Divisor Latch Fraction Register 0x500011F8 UART2_UCV_REG Component Version 0x500011FA UART2_UCV_HIGH_R EG Component Version 0x500011FC UART2_CTR_REG Component Type Register 0x500011FE UART2_CTR_HIGH_R EG Component Type Register Datasheet CFR0011-120-00 Revision 3.0 299 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 349: UART_RBR_THR_DLL_REG (0x50001000) Bit Mode Symbol 15:8 - - 7:0 R/W RBR_THR_DLL Description Reset 0x0 Receive Buffer Register: (RBR). This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: (THR) This register contains data to be transmitted on the serial output port (sout) in UART mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, 16 number of characters of data may be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): (DLL) This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the Divisor Latch is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. For the Divisor Latch (High) bits, see register UART_IER_DLH_REG. 0x0 Table 350: UART_IER_DLH_REG (0x50001004) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 300 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7 R/W PTIME_dlh7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled. Divisor Latch (High): DLH7, Bit 7 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 6:4 R/W dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set, otherwise, this field is reserved. See register UART_RBR_THR_DLL_REG. 0x0 3 R/W EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH3, Bit 3 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 2 R/W ELSI_dhl2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH2, Bit 2 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 1 R/W ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH1, Bit 1 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 Datasheet CFR0011-120-00 Revision 3.0 301 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): DLH0, Bit 0 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 Table 351: UART_IIR_FCR_REG (0x50001008) Bit Mode Symbol Description Reset 7:6 R/W UART_FIFOSE_RT On read FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. On write RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be deasserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full 0x0 5:4 R0/W UART_TET On read reserved On Write TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full 0x0 Datasheet CFR0011-120-00 Revision 3.0 302 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R/W UART_IID3_DMAM On Read (Bit3) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0x0 2 R/W UART_IID2_XFIFO R On Read (Bit2) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0x0 1 R/W UART_IID1_RFIFO E On Read (Bit1) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0x0 Datasheet CFR0011-120-00 Revision 3.0 303 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W UART_IID0_FIFOE On Read (Bit0) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset 0x1 Table 352: UART_LCR_REG (0x5000100C) Bit Mode Symbol 15:8 - - 7 R/W UART_DLAB Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero). This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 0x0 6 R/W UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 0x0 5 - - 4 R/W UART_EPS Datasheet CFR0011-120-00 Description Reset 0x0 0x0 Even Parity Select. Writeable only when UART is not busy (USR[0] is zero). This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. Revision 3.0 304 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R/W UART_PEN Parity Enable. Writeable only when UART is not busy (USR[0] is zero) This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 0x0 2 R/W UART_STOP Number of stop bits.Writeable only when UART is not busy (USR[0] is zero). This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 0x0 1:0 R/W UART_DLS Data Length Select.Writeable only when UART is not busy (USR[0] is zero). This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0x0 Table 353: UART_MCR_REG (0x50001010) Bit Mode Symbol 15:7 - - 0x0 6 - - 0x0 5 R/W UART_AFCE Datasheet CFR0011-120-00 Description Reset Auto Flow Control Enable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled Revision 3.0 305 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R/W UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 0x0 3 - - 0x0 2 - - 0x0 1 R/W UART_RTS 0 - - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. 0x0 0x0 Table 354: UART_LSR_REG (0x50001014) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 306 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7 R UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 0x0 6 R UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register(THR) and the Transmitter Shift Register are both empty. 0x1 5 R UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 0x1 4 R UART_BI Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 0x0 Datasheet CFR0011-120-00 Revision 3.0 307 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 0x0 2 R UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 0x0 1 R UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 0x0 Datasheet CFR0011-120-00 Revision 3.0 308 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in nonFIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0x0 Table 355: UART_MSR_REG (0x50001018) Bit Mode Symbol Description Reset 15:5 - - 4 R UART_CTS 3:1 - - 0x0 0 - - 0x0 0x0 Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). 0x1 Table 356: UART_SCR_REG (0x5000101C) Bit Mode Symbol 15:8 - - 7:0 R/W UART_SCRATCH_ PAD Description Reset 0x0 This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0x0 Table 357: UART_SRBR_STHR0_REG (0x50001030) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 309 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 358: UART_SRBR_STHR1_REG (0x50001034) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 310 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 359: UART_SRBR_STHR2_REG (0x50001038) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 311 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 360: UART_SRBR_STHR3_REG (0x5000103C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 312 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 361: UART_SRBR_STHR4_REG (0x50001040) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 313 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 362: UART_SRBR_STHR5_REG (0x50001044) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 314 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 363: UART_SRBR_STHR6_REG (0x50001048) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 315 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 364: UART_SRBR_STHR7_REG (0x5000104C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 316 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 365: UART_SRBR_STHR8_REG (0x50001050) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 317 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 366: UART_SRBR_STHR9_REG (0x50001054) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 318 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 367: UART_SRBR_STHR10_REG (0x50001058) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 319 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 368: UART_SRBR_STHR11_REG (0x5000105C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 320 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 369: UART_SRBR_STHR12_REG (0x50001060) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 321 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 370: UART_SRBR_STHR13_REG (0x50001064) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 322 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 371: UART_SRBR_STHR14_REG (0x50001068) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 323 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 372: UART_SRBR_STHR15_REG (0x5000106C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 324 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 373: UART_FAR_REG (0x50001070) Bit Mode Symbol Description Reset 0 R UART_FAR Description: Writes will have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are implemented and enabled. When FIFO's are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. 0x0 Datasheet CFR0011-120-00 Revision 3.0 325 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 374: UART_USR_REG (0x5000107C) Bit Mode Symbol 15:5 - - 4 R UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 0x0 3 R UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 0x0 2 R UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 0x1 1 R UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 0x1 0 R UART_BUSY UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 326 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 375: UART_TFL_REG (0x50001080) Bit Mode Symbol Description Reset 4:0 R UART_TRANSMIT_ FIFO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0x0 Table 376: UART_RFL_REG (0x50001084) Bit Mode Symbol Description Reset 4:0 R UART_RECEIVE_FI FO_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0x0 Table 377: UART_SRR_REG (0x50001088) Bit Mode Symbol Description Reset 15:3 - - 2 W UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 1 W UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 0 W UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0x0 0x0 Table 378: UART_SRTS_REG (0x5000108C) Bit Mode Symbol 15:1 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 327 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_R EQUEST_TO_SEN D Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. 0x0 Table 379: UART_SBCR_REG (0x50001090) Bit Mode Symbol 15:1 - - 0 R/W UART_SHADOW_B REAK_CONTROL Description Reset 0x0 Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. 0x0 Table 380: UART_SDMAM_REG (0x50001094) Bit Mode Symbol 15:1 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 328 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_D MA_MODE Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0x0 Table 381: UART_SFE_REG (0x50001098) Bit Mode Symbol 15:1 - - 0 R/W UART_SHADOW_F IFO_ENABLE Description Reset 0x0 Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. 0x0 Table 382: UART_SRT_REG (0x5000109C) Bit Mode Symbol 15:2 - - 1:0 R/W UART_SHADOW_R CVR_TRIGGER Datasheet CFR0011-120-00 Description Reset 0x0 Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full Revision 3.0 329 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 383: UART_STET_REG (0x500010A0) Bit Mode Symbol 15:2 - - 1:0 R/W UART_SHADOW_T X_EMPTY_TRIGGE R Description Reset 0x0 Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full 0x0 Table 384: UART_HTX_REG (0x500010A4) Bit Mode Symbol 15:1 - - 0 R/W UART_HALT_TX Description Reset 0x0 This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0x0 Table 385: UART_DMASA_REG (0x500010A8) Bit Mode Symbol Description Reset 0 W DMASA This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'selfclearing' and it is not necessary to clear this bit. 0x0 Datasheet CFR0011-120-00 Revision 3.0 330 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 386: UART_DLF_REG (0x500010C0) Bit Mode Symbol Description Reset 3:0 R/W UART_DLF The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16 0x0 Table 387: UART_UCV_REG (0x500010F8) Bit Mode Symbol Description Reset 15:0 R UCV Component Version 0x352A Table 388: UART_UCV_HIGH_REG (0x500010FA) Bit Mode Symbol Description Reset 15:0 R UCV Component Version 0x3331 Table 389: UART_CTR_REG (0x500010FC) Bit Mode Symbol Description Reset 15:0 R CTR Component Type Register 0x110 Table 390: UART_CTR_HIGH_REG (0x500010FE) Bit Mode Symbol Description Reset 15:0 R CTR Component Type Register 0x4457 Table 391: UART2_RBR_THR_DLL_REG (0x50001100) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 331 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W RBR_THR_DLL Receive Buffer Register: (RBR). This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: (THR) This register contains data to be transmitted on the serial output port (sout) in UART mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, 16 number of characters of data may be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): (DLL) This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the Divisor Latch is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. For the Divisor Latch (High) bits, see register UART_IER_DLH_REG. 0x0 Table 392: UART2_IER_DLH_REG (0x50001104) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 332 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7 R/W PTIME_dlh7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled. Divisor Latch (High): DLH7, Bit 7 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 6:4 R/W dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set, otherwise, this field is reserved. See register UART_RBR_THR_DLL_REG. 0x0 3 R/W EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH3, Bit 3 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 2 R/W ELSI_dhl2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH2, Bit 2 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 1 R/W ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH1, Bit 1 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 Datasheet CFR0011-120-00 Revision 3.0 333 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): DLH0, Bit 0 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0x0 Table 393: UART2_IIR_FCR_REG (0x50001108) Bit Mode Symbol Description Reset 7:6 R/W UART_FIFOSE_RT On read FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. On write RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be deasserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full 0x0 5:4 R0/W UART_TET On read reserved On Write TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full 0x0 Datasheet CFR0011-120-00 Revision 3.0 334 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R/W UART_IID3_DMAM On Read (Bit3) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0x0 2 R/W UART_IID2_XFIFO R On Read (Bit2) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0x0 1 R/W UART_IID1_RFIFO E On Read (Bit1) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0x0 Datasheet CFR0011-120-00 Revision 3.0 335 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W UART_IID0_FIFOE On Read (Bit0) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset 0x1 Table 394: UART2_LCR_REG (0x5000110C) Bit Mode Symbol 15:8 - - 7 R/W UART_DLAB Divisor Latch Access Bit.Writeable only when UART is not busy (USR[0] is zero). This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 0x0 6 R/W UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 0x0 5 - - 4 R/W UART_EPS Datasheet CFR0011-120-00 Description Reset 0x0 0x0 Even Parity Select. Writeable only when UART is not busy (USR[0] is zero). This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. Revision 3.0 336 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 3 R/W UART_PEN Parity Enable. Writeable only when UART is not busy (USR[0] is zero) This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 0x0 2 R/W UART_STOP Number of stop bits. Writeable only when UART is not busy (USR[0] is zero). This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 0x0 1:0 R/W UART_DLS Data Length Select.Writeable only when UART is not busy (USR[0] is zero). This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0x0 Table 395: UART2_MCR_REG (0x50001110) Bit Mode Symbol 15:5 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 337 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 4 R/W UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 0x0 3:0 - - 0x0 Table 396: UART2_LSR_REG (0x50001114) Bit Mode Symbol 15:8 - - 7 R UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 0x0 6 R UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register(THR) and the Transmitter Shift Register are both empty. 0x1 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 338 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 5 R UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 0x1 4 R UART_BI Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 0x0 3 R UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 0x0 Datasheet CFR0011-120-00 Revision 3.0 339 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 2 R UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 0x0 1 R UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 0x0 0 R UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in nonFIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0x0 Table 397: UART2_SCR_REG (0x5000111C) Bit Mode Symbol 15:8 - - 7:0 R/W UART_SCRATCH_ PAD Datasheet CFR0011-120-00 Description Reset 0x0 This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. Revision 3.0 340 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 398: UART2_SRBR_STHR0_REG (0x50001130) Bit Mode Symbol 15:8 - - 7:0 R/W SRBR_STHRx Description Reset 0x0 Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 399: UART2_SRBR_STHR1_REG (0x50001134) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 341 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 400: UART2_SRBR_STHR2_REG (0x50001138) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 342 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 401: UART2_SRBR_STHR3_REG (0x5000113C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 343 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 402: UART2_SRBR_STHR4_REG (0x50001140) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 344 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 403: UART2_SRBR_STHR5_REG (0x50001144) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 345 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 404: UART2_SRBR_STHR6_REG (0x50001148) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 346 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 405: UART2_SRBR_STHR7_REG (0x5000114C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 347 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 406: UART2_SRBR_STHR8_REG (0x50001150) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 348 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 407: UART2_SRBR_STHR9_REG (0x50001154) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 349 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 408: UART2_SRBR_STHR10_REG (0x50001158) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 350 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 409: UART2_SRBR_STHR11_REG (0x5000115C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 351 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 410: UART2_SRBR_STHR12_REG (0x50001160) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 352 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 411: UART2_SRBR_STHR13_REG (0x50001164) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 353 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 412: UART2_SRBR_STHR14_REG (0x50001168) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 354 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 413: UART2_SRBR_STHR15_REG (0x5000116C) Bit Mode Symbol 15:8 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 355 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 7:0 R/W SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0x0 Table 414: UART2_FAR_REG (0x50001170) Bit Mode Symbol Description Reset 0 R UART_FAR Description: Writes will have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are implemented and enabled. When FIFO's are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. 0x0 Datasheet CFR0011-120-00 Revision 3.0 356 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 415: UART2_USR_REG (0x5000117C) Bit Mode Symbol 15:5 - - 4 R UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 0x0 3 R UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 0x0 2 R UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 0x1 1 R UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 0x1 0 R UART_BUSY UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock. 0x0 Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 357 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 416: UART2_TFL_REG (0x50001180) Bit Mode Symbol Description Reset 4:0 R UART_TRANSMIT_ FIFO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0x0 Table 417: UART2_RFL_REG (0x50001184) Bit Mode Symbol Description Reset 4:0 R UART_RECEIVE_FI FO_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0x0 Table 418: UART2_SRR_REG (0x50001188) Bit Mode Symbol Description Reset 15:3 - - 2 W UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 1 W UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 0 W UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0x0 0x0 Table 419: UART2_SBCR_REG (0x50001190) Bit Mode Symbol 15:1 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 358 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_B REAK_CONTROL Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. 0x0 Table 420: UART2_SDMAM_REG (0x50001194) Bit Mode Symbol 15:1 - - 0 R/W UART_SHADOW_D MA_MODE Description Reset 0x0 Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0x0 Table 421: UART2_SFE_REG (0x50001198) Bit Mode Symbol 15:1 - - 0 R/W UART_SHADOW_F IFO_ENABLE Datasheet CFR0011-120-00 Description Reset 0x0 Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. Revision 3.0 359 of 374 0x0 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 422: UART2_SRT_REG (0x5000119C) Bit Mode Symbol 15:2 - - 1:0 R/W UART_SHADOW_R CVR_TRIGGER Description Reset 0x0 Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full 0x0 Table 423: UART2_STET_REG (0x500011A0) Bit Mode Symbol 15:2 - - 1:0 R/W UART_SHADOW_T X_EMPTY_TRIGGE R Description Reset 0x0 Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full 0x0 Table 424: UART2_HTX_REG (0x500011A4) Bit Mode Symbol 15:1 - - Datasheet CFR0011-120-00 Description Reset 0x0 Revision 3.0 360 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W UART_HALT_TX This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0x0 Table 425: UART2_DMASA_REG (0x500011A8) Bit Mode Symbol Description Reset 0 W DMASA This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'selfclearing' and it is not necessary to clear this bit. 0x0 Table 426: UART2_DLF_REG (0x500011C0) Bit Mode Symbol Description Reset 3:0 R/W UART_DLF The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16 0x0 Table 427: UART2_UCV_REG (0x500011F8) Bit Mode Symbol Description Reset 15:0 R UCV Component Version 0x352A Table 428: UART2_UCV_HIGH_REG (0x500011FA) Bit Mode Symbol Description Reset 15:0 R UCV Component Version 0x3331 Table 429: UART2_CTR_REG (0x500011FC) Bit Mode Symbol Description Reset 15:0 R CTR Component Type Register 0x110 Datasheet CFR0011-120-00 Revision 3.0 361 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 430: UART2_CTR_HIGH_REG (0x500011FE) Bit Mode Symbol Description Reset 15:0 R CTR Component Type Register 0x4457 Datasheet CFR0011-120-00 Revision 3.0 362 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.19 Chip Version Registers Table 431: Register map Version Address Register Description 0x50003200 CHIP_ID1_REG Chip identification register 1. 0x50003204 CHIP_ID2_REG Chip identification register 2. 0x50003208 CHIP_ID3_REG Chip identification register 3. 0x5000320C CHIP_ID4_REG Chip identification register 4. Table 432: CHIP_ID1_REG (0x50003200) Bit Mode Symbol Description Reset 7:0 R CHIP_ID1 First character of device type "2632" in ASCII. 0x32 Table 433: CHIP_ID2_REG (0x50003204) Bit Mode Symbol Description Reset 7:0 R CHIP_ID2 Second character of device type "2632" in ASCII. 0x36 Table 434: CHIP_ID3_REG (0x50003208) Bit Mode Symbol Description Reset 7:0 R CHIP_ID3 Third character of device type "2632" in ASCII. 0x33 Table 435: CHIP_ID4_REG (0x5000320C) Bit Mode Symbol Description Reset 7:0 R CHIP_ID4 Fourth character of device type "2632" in ASCII. 0x32 Datasheet CFR0011-120-00 Revision 3.0 363 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.20 Wake-Up Registers Table 436: Register map WKUP Address Register Description 0x50000100 WKUP_CTRL_REG Control register for the wakeup counter 0x50000102 WKUP_COMPARE_R EG Number of events before wakeup interrupt 0x50000104 WKUP_IRQ_STATUS _REG Reset wakeup interrupt 0x50000106 WKUP_COUNTER_R EG Actual number of events of the wakeup counter 0x50000108 WKUP_SELECT_GPI O_REG Select which inputs from P0 port can trigger wkup counter 0x5000010A WKUP2_SELECT_GPI O_REG Select which inputs from P1 port can trigger wkup counter 0x5000010C WKUP_POL_GPIO_R EG Select the sensitivity polarity for each P0 input 0x5000010E WKUP2_POL_GPIO_ REG Select the sensitivity polarity for each P1 input Table 437: WKUP_CTRL_REG (0x50000100) Bit Mode Symbol Description Reset 8 R/W WKUP2_ENABLE_I RQ 0 = no interrupt will be generated 1 = if the event counter2 reaches the value set by WKUP_COMPARE_REG an IRQ will be generated 0x0 7 R/W WKUP_ENABLE_IR Q 0 = no interrupt will be generated 1 = if the event counter reaches the value set by WKUP_COMPARE_REG an IRQ will be generated 0x0 6 R/W WKUP_SFT_KEYHI T 0 = no effect 1 = emulate key hit. The event counter and counter2 will increment by 1 (after debouncing if enabled). First make this bit 0 before any new key hit can be sensed. 0x0 5:0 R/W WKUP_DEB_VALU E Keyboard debounce time (N*1 ms with N = 1 to 63). 0x0: no debouncing 0x1 to 0x3F: 1 ms to 63 ms debounce time 0x0 Datasheet CFR0011-120-00 Revision 3.0 364 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 438: WKUP_COMPARE_REG (0x50000102) Bit Mode Symbol Description Reset 7:0 R/W WKUP_COMPARE Defines the number of events -1 that have to be counted before the wakeup interrupt will be given. value 0 means one event. 0x0 Table 439: WKUP_IRQ_STATUS_REG (0x50000104) Bit Mode Symbol Description Reset 3 R0/W WKUP2_CNTR_RS T writing 1 will reset the event2 counter 0x0 2 R0/W WKUP_CNTR_RST writing 1 will reset the event counter 0x0 1 R/W WKUP2_IRQ_STAT US Gives 1 when there is a wkup2 pending IRQ. Writing 1 will reset the interrupt. 0x0 0 R/W WKUP_IRQ_STATU S Gives 1 when there is a wkup pending IRQ. Writing 1 will reset the interrupt. 0x0 Table 440: WKUP_COUNTER_REG (0x50000106) Bit Mode Symbol Description Reset 15:8 R EVENT2_VALUE This value represents the number of events that have been counted so far. It will be reset by writting to the WKUP_CNTR_RST bit field of the WKUP_IRQ_STATUS_REG 0x0 7:0 R EVENT_VALUE This value represents the number of events that have been counted so far. It will be reset by writting to the WKUP_CNTR_RST bit field of the WKUP_IRQ_STATUS_REG. 0x0 Table 441: WKUP_SELECT_GPIO_REG (0x50000108) Bit Mode Symbol Description Reset 11:0 R/W WKUP_SELECT_G PIO 0 = input P0x is not enabled for wakeup event counter 1 = input P0x is enabled for wakeup event counter 0x0 Table 442: WKUP2_SELECT_GPIO_REG (0x5000010A) Bit Mode Symbol Description Reset 11:0 R/W WKUP2_SELECT_ GPIO 0 = input P0x is not enabled for wakeup event counter 1 = input P0x is enabled for wakeup event counter 0x0 Datasheet CFR0011-120-00 Revision 3.0 365 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Table 443: WKUP_POL_GPIO_REG (0x5000010C) Bit Mode Symbol Description Reset 11:0 R/W WKUP_POL_GPIO 0 = the enabled input P0x increments the event counter if that input goes high 1 = the enabled input P0x increments the event counter if that input goes low 0x0 Table 444: WKUP2_POL_GPIO_REG (0x5000010E) Bit Mode Symbol Description Reset 11:0 R/W WKUP2_POL_GPIO 0 = the enabled input P0x increments the event2 counter if that input goes high 1 = the enabled input P0x increments the event2 counter if that input goes low 0x0 Datasheet CFR0011-120-00 Revision 3.0 366 of 374 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC 31.21 Watchdog Registers Table 445: Register map WDOG Address Register Description 0x50003100 WATCHDOG_REG Watchdog timer register. 0x50003102 WATCHDOG_CTRL_ REG Watchdog control register. Table 446: WATCHDOG_REG (0x50003100) Bit Mode Symbol Description Reset 15:9 R0/W WDOG_WEN 0000.000 = Write enable for Watchdog timer else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away. 0x0 8 R/W WDOG_VAL_NEG 0 = Watchdog timer value is positive. 1 = Watchdog timer value is negative. 0x0 7:0 R/W WDOG_VAL Write: Watchdog timer reload value. Note that all bits 15-9 must be 0 to reload this register. Read: Actual Watchdog timer value. Decremented by 1 every 10.24 msec. Bit 8 indicates a negative counter value. 2, 1, 0, 1FF16, 1FE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions: If WATCHDOG_CTRL_REG[NMI_RST] = 0 then If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt) if WDOG_VAL = 1F016 -> WDOG reset -> reload FF16 If WATCHDOG_CTRL_REG[NMI_RST] = 1 then if WDOG_VAL WDOG reset -> reload FF16 0xFF Table 447: WATCHDOG_CTRL_REG (0x50003102) Bit Mode Symbol 15:2 - - 0x0 1 R/W - 0x0 Datasheet CFR0011-120-00 Description Revision 3.0 367 of 374 Reset 12-Mar-2020 © 2020 Dialog Semiconductor DA14531 Final Ultra Low Power Bluetooth 5.1 SoC Bit Mode Symbol Description Reset 0 R/W NMI_RST 0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at