NSI8140W0

NSi8140/NSi8141/NSi8142: High Reliabilit y Quad-Channel Digital Isolators NOVOSENSE Datasheet (EN) 1.4 Product Overview The NSi814x devices are high reliability quad-channel digital isolators. The NSi814x device is safety certified by UL1577 support several insulation withstand voltages (3.75kVrms, 5kVrms), while providing high electromagnetic immunity and low emissions at low power consumption. The data rate of the NSi814x is up to 150Mbps, and the common-mode transient immunity (CMTI) is up to 150kV/us. The NSi814x device provides digital channel direction configuration and the default output level configuration when the input power is lost. Wide supply voltage of the NSi814x device support to connect with most digital interface directly, easy to do the level shift. High system level EMC performance enhance reliability and stability of use. AEC-Q100 (Grade 1) option is provided for all devices. Key Features  Up to 5000Vrms Insulation voltage  Date rate: DC to 150Mbps  Power supply voltage: 2.5V to 5.5V  AEC-Q100 Grade 1 available for all devices  High CMTI: 150kV/us  Chip level ESD: HBM: ±6kV Safety Regulatory Approvals  UL recognition: up to 5000Vrms for 1 minute per UL1577  CQC certification per GB4943.1-2011  CSA component notice 5A  DIN VDE V 0884-11:2017-01 Applications  Industrial automation system  Isolated SPI, RS232, RS485  General-purpose multichannel isolation  Motor control Functional Block Diagrams  High system level EMC performance: Enhanced system level ESD, EFT, Surge immunity  Default output high level or low level option  Isolation barrier life: >60 years  Low power consumption: 1.5mA/ch (1 Mbps)  Low propagation delay: 400 Ⅱ Material Group 3.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 INSULATION CHARATERISTICS Description Test Condition Symbol Value NB-SOIC16 Unit WB-SOIC16 Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150Vrms Ⅰto Ⅳ Ⅰto Ⅳ For Rated Mains Voltage ≤ 300Vrms Ⅰto Ⅲ Ⅰto Ⅳ Copyright © 2019, NOVOSENSE Page 12 NSi8140/NSi8141/NSi8142 For Rated Mains Voltage ≤ 400Vrms Ⅰto Ⅲ Climatic Classification 10/105/2 1 Pollution Degree per DIN VDE 0110, 2 Ⅰto Ⅳ 10/105/2 1 2 Table 1 Maximum repetitive peak isolation voltage Maximum working isolation voltage AC voltage VIORM 565 1166 Vpeak VIOWM 400 824 VRMS 565 1166 Vpeak V pd (m) 847 1749 Vpeak DC voltage Input to Output Test Voltage, Method B1 V IORM × 1. 5 = V pd (m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pC Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 V IORM × 1.2 = V pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pC V pd (m) 678 1399 Vpeak After Input and /or Safety Test Subgroup 2 and Subgroup 3 V IORM × 1.2= V pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pC V pd (m) 678 1399 Vpeak t = 60 sec VIOTM 5300 7000 Vpeak Test method per IEC60065,1.2/50us waveform, VTEST=VIOSM×1.3 VIOSM 5384 5384 Vpeak VIO =500V RIO >109 >109 Ω f = 1MHz CIO 0.6 0.6 pF Input capacitance CI 2 2 pF Total Power Dissipation at 25℃ Ps 1499 W Maximum transient isolation voltage Maximum Surge Isolation Voltage Isolation resistance Isolation capacitance θJA = 140 °C/W, V I = 5.5 V, T J = 150 °C, T A = 25 °C Safety input, output, or supply current 160 Is θJA = 84 °C/W, V I = 5.5 V, T J = 150 °C, T A = 25 °C Case Temperature Copyright © 2019, NOVOSENSE mA Ts 150 237 mA 150 ℃ Page 13 Saftey Limiting Current (mA) NSi8140/NSi8141/NSi8142 180 160 140 120 100 80 60 40 20 0 0 50 100 150 200 Case Temperature (℃) Saftey Limiting Current (mA) Figure 3.1 NSi8140N/NSi8141N/NSi8142N Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11 250 200 150 100 50 0 0 50 100 150 200 Case Temperature (℃) Figure 3.2 NSi8140W/NSi8141W/NSi8142W Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11 3.3. REGULATORY INFORMATION The NSi8140N/NSi8141N/NSi8142N are approved or pending approval by the organizations listed in table. CUL UL 1577 Component Recognition Program1 Single Protection, 3750Vrms Isolation voltage Approved under CSA Component Acceptance Notice 5A CQC DIN VDE V 088411(VDE V 088411):2017-012 Certified by CQC11471543-2012 Single Protection, 3750Vrms Isolation voltage Basic Insulation 565Vpeak, VIOSM=5384Vpeak Basic insulation at 400Vrms (565Vpeak) File (E500602) File (5024579-48800001) File (E500602) 1 VDE GB4943.1-2011 File (pending) In accordance with UL 1577, each NSi8140N/NSi8141N/NSi8142N is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 sec. 2 In accordance with DIN VDE V 0884-11, each NSi8140N/NSi8141N/NSi8142N is proof tested by applying an insulation test voltage ≥ 847 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval. The NSi8140W/NSi8141W/NSi8142W are approved or pending approval by the organizations listed in table. CUL UL 1577 Component Recognition Program1 Copyright © 2019, NOVOSENSE VDE Approved under CSA Component Acceptance Notice 5A DIN VDE V 088411(VDE V 088411):2017-012 CQC Certified by CQC11471543-2012 GB4943.1-2011 Page 14 NSi8140/NSi8141/NSi8142 Single Protection, 5000Vrms Isolation voltage Single Protection, 5000Vrms Isolation voltage File (E500602) 1 Basic Insulation 1166Vpeak, VIOSM=5384Vpeak File (E500602) File (5024579-48800001) Basic insulation at 824VRMS (1166Vpeak) Reinforced insulation at 400VRMS (565Vpeak) File (pending) In accordance with UL 1577, each NSi8140W/NSi8141W/NSi8142W is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec. 2 In accordance with DIN VDE V 0884-11, each NSi8140W/NSi8141W/NSi8142W is proof tested by applying an insulation test voltage ≥ 1749 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval. 4.0 FUNCTION DESCRIPTION The NSi814x is a Quad-channel digital isolator based on a capacitive isolation barrier technique. The digital signal is modulated with RF carrier generated by the internal oscillator at the Transmitter side. Then it is transferred through the capacitive isolation barrier and demodulated at the Receiver side. The NSi814x devices are high reliability quad-channel digital isolator with AEC-Q100 qualified. The NSi814x device is safety certified by UL1577 support several insulation withstand voltages (3.75kVrms, 5kVrms), while providing high electromagnetic immunity and low emissions at low power consumption. The data rate of the NSi814x is up to 150Mbps, and the common-mode transient immunity (CMTI) is up to 150kV/us. The NSi814x device provides digital channel direction configuration and the default output level configuration when the input power is lost. Wide supply voltage of the NSi814x device support to connect with most digital interface directly, easy to do the level shift. High system level EMC performance enhance reliability and stability of use. The NSi814x has a default output status when VDDIN is unready and VDDOUT is ready as shown in Table 4.1, which helps for diagnosis when power is missing at the transmitter side. The output B follows the same status with the input A within 60us after powering up. Isolation barrier VIN TX signal cinditioning PWM RX signal cinditioning envelope detection VOUT EN OSC Figure 4.1 Simplified Channel Diagram Table 4.1 Output status vs. power status Input ENX VDD1 status VDD2 status Output Comment H H or NC Ready Ready H Normal operation. L H or NC Ready Ready L X L Ready Ready Z Output Disabled, the output is high impedance X H or NC Unready Ready L H The output follows the same status with the input within 60us after input side VDD1 is powered on. X L Unready Ready Z Output Disabled, the output is high impedance X X Ready Unready X The output follows the same status with the input within 60us after output side VDD2 is powered on. Copyright © 2019, NOVOSENSE Page 15 NSi8140/NSi8141/NSi8142 5.0 APPLICATION NOTE 5.1. PCB LAYOUT The NSi814x requires a 0.1 µF bypass capacitor between VDD1 and GND1, VDD2 and GND2. The capacitor should be placed as close as possible to the package. Figure 5.1 show the recommended schematic diagram , Figure 5.2 to Figure 5.3 show the recommended PCB layout, make sure the space under the chip should keep free from planes, traces, pads and via. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series with the inputs and outputs if the system is excessively noisy. The series resistors also improve the system reliability such as latch-up immunity. The typical output impedance of an isolator driver channel is approximately 50 Ω, ±40%. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. VDD1 VDD2 1 VDD1 VDD2 16 2 GND1 GND2 15 100nF 100nF A2 14 B1 B2 13 C1 C2 12 D1 D2 11 3 A1 4 5 6 50R 50R 7 EN1 8 GND1 EN2 10 GND2 9 Figure5.1 Recommended schematic diagram Figure5.2 Recommended PCB Layout — Top Layer Figure5.3 Recommended PCB Layout — Bottom Layer 5.2. HIGH SPEED PERFORMANCE Figure 5.4 shows the eye diagram of NSi814x at 200Mbps data rate output. The result shows a typical measurement on the NSi814x with 350ps p-p jitter. Copyright © 2019, NOVOSENSE Page 16 NSi8140/NSi8141/NSi8142 Figure5.4 NSi814x Eye Diagram 5.3. TYPICAL SUPPLY CURRENT EQUATIONS The typical supply current of NSi814x can be calculated using below equations. IDD1 and IDD2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive load measured in pF NSi8140: IDD1 = 0.19 *a1+1.45*b1+0.82*c1. IDD2 = 1.36+ VDD1*f* CL *c1*10-9 When a1 is the channel number of low input at side 1, b1 is the channel number of high input at side 1, c1 is the channel number of switch signal input at side 1. NSi8141: IDD1 = 0.87 +1.26*b1+0.63*c1+ VDD1*f* CL *c2*10-9 IDD2 = 0.87 +1.26*b2+0.63*c2+ VDD1*f* CL *c1*10-9 When b1 is the channel number of high input at side 1, c1 is the channel number of switch signal input at side 1, b2 is the channel number of high input at side 2, c2 is the channel number of switch signal input at side 2. NSi8142: IDD1 = 0.87 +1.26*b1+0.63*c1+ VDD1*f* CL *c2*10-9 IDD2 = 0.87 +1.26*b2+0.63*c2+ VDD1*f* CL *c1*10-9 When b1 is the channel number of high input at side 1, c1 is the channel number of switch signal input at side 1, b2 is the channel number of high input at side 2, c2 is the channel number of switch signal input at side 2. Copyright © 2019, NOVOSENSE Page 17 NSi8140/NSi8141/NSi8142 6.0 PACKAGE INFORMATION VDD1 1 16 VDD2 VDD1 1 16 VDD2 VDD1 1 16 VDD2 GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2 INA 3 14 OUTA INA 3 14 OUTA INA 3 14 OUTA INB 4 13 OUTB INB 4 13 OUTB INB 4 13 OUTB INC 5 12 OUTC INC 5 12 OUTC OUTC 5 12 INC IND 6 11 OUTD OUTD 6 11 IND OUTD 6 11 IND EN1 7 10 EN2 EN1 7 10 EN2 10 EN2 NC 7 GND1 8 NSi8140 9 GND2 GND1 8 Figure 6.1 NSi8140N Package NSi8141 9 GND2 Figure 6.2 NSi8141N Package GND1 8 NSi8142 9 GND2 Figure 6.3 NSi8142N Package Figure 6.4 NB SOIC16 Package Shape and Dimension in millimeters (inches) Table6.1 NSi8140N/ NSi8141N/ NSi8142N Pin Configuration and Description NSi8140N PIN NO. NSi8141N PIN NO. NSi8142N PIN NO. SYMBOL FUNCTION 1 1 1 VDD1 Power Supply for Isolator Side 1 2 2 2 GND1 Ground 1, the ground reference for Isolator Side 1 Copyright © 2019, NOVOSENSE Page 18 NSi8140/NSi8141/NSi8142 3 3 3 INA Logic Input A 4 4 4 INB Logic Input B 5 5 12 INC Logic Input C 6 11 11 IND Logic Input D 7 7 7 NC/ EN1 No Connection. or Output Enable 1. Active high logic input. When EN1 is high or NC, the output of Side 1 are enabled. When EN1 is low, the output of Side 1 are disabled to high impedance state. 8 8 8 GND1 Ground 1, the ground reference for Isolator Side 1 9 9 9 GND2 Ground 2, the ground reference for Isolator Side 2 10 10 10 EN2 Output Enable 2. Active high logic input. When EN2 is high or NC, the output of Side 2 are enabled. When EN2 is low, the output of Side 2 are disabled to high impedance state. 11 6 6 OUTD Logic Output D 12 12 5 OUTC Logic Output C 13 13 13 OUTB Logic Output B 14 14 14 OUTA Logic Output A 15 15 15 GND2 Ground 2, the ground reference for Isolator Side 2 16 16 16 VDD2 Power Supply for Isolator Side 2 VDD1 1 16 VDD 2 GND 1 2 15 GND 2 VDD1 1 GND1 2 16 VDD2 VDD1 1 16 VDD 2 15 GND2 GND 1 2 15 GND 2 14 OUTA 13 OUTB INA 3 14 OUTA INA 3 14 OUTA INA 3 INB 4 13 OUTB INB 4 13 OUTB INB 4 INC 5 12 OUTC INC 5 12 OUTC OUTC 5 12 INC IND 6 11 OUTD OUTD 6 11 IND OUTD 6 11 IND EN1 7 10 EN2 EN 1 7 10 EN 2 10 EN2 NC 7 GND 1 8 NSi8140 9 GND2 Figure 6.5 NSi8140W Package Copyright © 2019, NOVOSENSE GND1 8 NSi8141 9 GND 2 Figure 6.6 NSi8141W Package GND1 8 NSi8142 9 GND2 Figure 6.7 NSi8142W Package Page 19 NSi8140/NSi8141/NSi8142 Figure 6.8 WB SOIC16 Package Shape and Dimension in millimeters and (inches) Table 6.2 NSi8140W/ NSi8141W/ NSi8142W Pin Configuration and Description NSi8140W PIN NO. NSi8141W PIN NO. NSi8142W PIN NO. SYMBOL FUNCTION 1 1 1 VDD1 Power Supply for Isolator Side 1 2 2 2 GND1 Ground 1, the ground reference for Isolator Side 1 3 3 3 INA Logic Input A 4 4 4 INB Logic Input B 5 5 12 INC Logic Input C 6 11 11 IND Logic Input D 7 7 7 NC/ EN1 No Connection. or Output Enable 1. Active high logic input. When EN1 is high or NC, the output of Side 1 are enabled. When EN1 is low, the output of Side 1 are disabled to high impedance state. 8 8 8 GND1 Ground 1, the ground reference for Isolator Side 1 9 9 9 GND2 Ground 2, the ground reference for Isolator Side 2 10 10 10 EN2 Output Enable 2. Active high logic input. When EN2 is high or NC, the output of Side 2 are enabled. When EN2 is low, the output of Side 2 are disabled to high impedance state. 11 6 6 OUTD Logic Output D Copyright © 2019, NOVOSENSE Page 20 NSi8140/NSi8141/NSi8142 7.0 12 12 5 OUTC Logic Output C 13 13 13 OUTB Logic Output B 14 14 14 OUTA Logic Output A 15 15 15 GND2 Ground 2, the ground reference for Isolator Side 2 16 16 16 VDD2 Power Supply for Isolator Side 2 ORDER INFORMATION Part No. Isolati on Rating (kV) Numb er of side 1 inputs Numb er of side 2 inputs Max Data Rate (Mbps) Default Output State MSL level Temperature Auto moti ve Package Qty Package NSi8140N0 3.75 4 0 150 Low 1 -40 to 125℃ NO 2500 NB SOIC16 NSi8140N1 3.75 4 0 150 High 1 -40 to 125℃ NO 2500 NB SOIC16 NSi8141N0 3.75 3 1 150 Low 1 -40 to 125℃ NO 2500 NB SOIC16 NSi8141N1 3.75 3 1 150 High 1 -40 to 125℃ NO 2500 NB SOIC16 NSi8142N0 3.75 2 2 150 Low 1 -40 to 125℃ NO 2500 NB SOIC16 NSi8142N1 3.75 2 2 150 High 1 -40 to 125℃ NO 2500 NB SOIC16 NSi8140W0 5 4 0 150 Low 2 -40 to 125℃ NO 1000 WB SOIC16 NSi8140W1 5 4 0 150 High 2 -40 to 125℃ NO 1000 WB SOIC16 NSi8141W0 5 3 1 150 Low 2 -40 to 125℃ NO 1000 WB SOIC16 NSi8141W1 5 3 1 150 High 2 -40 to 125℃ NO 1000 WB SOIC16 NSi8142W0 5 2 2 150 Low 2 -40 to 125℃ NO 1000 WB SOIC16 NSi8142W1 5 2 2 150 High 2 -40 to 125℃ NO 1000 WB SOIC16 NSi8140W0Q 5 4 0 150 Low 2 -40 to 125℃ YES 1000 WB SOIC16 NSi8140W1Q 5 4 0 150 High 1 -40 to 125℃ YES 1000 WB SOIC16 NSi8141W0Q 5 3 1 150 Low 1 -40 to 125℃ YES 1000 WB SOIC16 NSi8141W1Q 5 3 1 150 High 1 -40 to 125℃ YES 1000 WB SOIC16 NSi8142W0Q 5 2 2 150 Low 1 -40 to 125℃ YES 1000 WB SOIC16 NSi8142W1Q 5 2 2 150 High 1 YES 1000 WB SOIC16 -40 to 125℃ NOTE: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. All devices are AEC-Q100 qualified. Part Number Rule: Copyright © 2019, NOVOSENSE Page 21 NSi8140/NSi8141/NSi8142 NSi(81)(4)(1)(N)(1)(Q) Series Number Total Channel Amount: N=N Channels N=1,2,4… N=0: I2C Part Reverse Channel Amount: N=N Channels N=0,1,2… 8.0 Q = Automotive version Fail-Safe Output State: 0 = Logic Low 1 = Logic High Package Type: N= NB SOIC16 W= WB SOIC16 TAPE AND REEL INFORMATION Copyright © 2019, NOVOSENSE Page 22 NSi8140/NSi8141/NSi8142 Figure 8.1 Tape and Reel Information of WB SOIC16 Copyright © 2019, NOVOSENSE Page 23 NSi8140/NSi8141/NSi8142 Figure 8.2 Tape and Reel Information of NB SOIC16 9.0 REVISION HISTORY Revision 1.0 1.1 1.2 1.3 1.4 Description 1.5 Change NSi8140 IDD1(Q0) MAX value Add maximum operation current spec. Change to ordering information Change Certification Information Add Thermal characteristics, MSL level，Recommended schematic diagram，Simplified Channel Diagram; change Package Shape and Dimension in millimeters and (inches) add recommended operation recommEnded operating conditions Copyright © 2019, NOVOSENSE Date 2017/11/15 2018/10/12 2018/12/20 2019/06/17 2020/2/11 2020/4/17 Page 24