RTL8189ES-VB-CG
SINGLE-CHIP IEEE 802.11b/g/n 1T1R WLAN
WITH SDIO INTERFACE
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
25 December 2012
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8189ES-VB
Datasheet
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2012/12/25
Summary
First release
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
ii
Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ............................................................................................................................................... 1
2.
FEATURES .......................................................................................................................................................................... 2
3.
SYSTEM APPLICATIONS ................................................................................................................................................ 3
3.1.
4.
PIN ASSIGNMENTS ........................................................................................................................................................... 4
4.1.
5.
PACKAGE IDENTIFICATION .............................................................................................................................................. 4
PIN DESCRIPTIONS .......................................................................................................................................................... 5
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
6.
SINGLE-BAND 11N (1X1) SOLUTION ............................................................................................................................... 3
SDIO INTERFACE ............................................................................................................................................................ 5
GSPI INTERFACE............................................................................................................................................................. 5
POWER PINS .................................................................................................................................................................... 6
RF INTERFACE ................................................................................................................................................................ 6
LED INTERFACE.............................................................................................................................................................. 6
CLOCK AND OTHER PINS ................................................................................................................................................. 7
ELECTRICAL AND THERMAL CHARACTERISTICS............................................................................................... 8
6.1. TEMPERATURE LIMIT RATINGS ....................................................................................................................................... 8
6.2. TEMPERATURE LIMIT RATINGS ....................................................................................................................................... 8
6.3. DC CHARACTERISTICS .................................................................................................................................................... 8
6.3.1.
Power Supply Characteristics ................................................................................................................................ 8
6.3.2.
Digital IO Pin DC Characteristics ......................................................................................................................... 9
6.4. AC CHARACTERISTICS .................................................................................................................................................... 9
6.4.1.
SDIO/GSPI Interface Timing ................................................................................................................................. 9
6.4.2.
SDIO/GSPI Interface Signal Level ....................................................................................................................... 10
6.4.3.
SDIO Interface Power-On Sequence .................................................................................................................... 10
6.4.4.
GSPI Interface Power-On Sequence .................................................................................................................... 12
7.
MECHANICAL DIMENSIONS ....................................................................................................................................... 14
7.1.
8.
MECHANICAL DIMENSIONS NOTES ............................................................................................................................... 14
ORDERING INFORMATION ......................................................................................................................................... 15
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
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Datasheet
List of Tables
TABLE 1. SDIO INTERFACE ........................................................................................................................................................... 5
TABLE 2. GSPI INTERFACE ............................................................................................................................................................ 5
TABLE 3. POWER PINS ................................................................................................................................................................... 6
TABLE 4. RF INTERFACE ............................................................................................................................................................... 6
TABLE 5. LED INTERFACE............................................................................................................................................................. 6
TABLE 6. CLOCK AND OTHER PINS ................................................................................................................................................ 7
TABLE 7. TEMPERATURE LIMIT RATINGS ...................................................................................................................................... 8
TABLE 8. TEMPERATURE LIMIT RATINGS ...................................................................................................................................... 8
TABLE 9. DC CHARACTERISTICS ................................................................................................................................................... 8
TABLE 10. 3.3V GPIO DC CHARACTERISTICS ................................................................................................................................ 9
TABLE 11. 2.8V GPIO DC CHARACTERISTICS ................................................................................................................................ 9
TABLE 12. 1.8V GPIO DC CHARACTERISTICS ................................................................................................................................ 9
TABLE 13. SDIO/GSPI INTERFACE TIMING PARAMETERS ............................................................................................................ 10
TABLE 14. SDIO INTERFACE POWER-ON TIMING PARAMETERS ................................................................................................... 11
TABLE 15. GSPI INTERFACE POWER-ON TIMING PARAMETERS.................................................................................................... 13
TABLE 16. ORDERING INFORMATION ............................................................................................................................................ 15
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
SINGLE-BAND 11N (1X1) SOLUTION ............................................................................................................................. 3
PIN ASSIGNMENTS......................................................................................................................................................... 4
SDIO/GSPI INTERFACE TIMING ................................................................................................................................... 9
SDIO INTERFACE POWER-ON SEQUENCE ................................................................................................................... 10
GSPI INTERFACE POWER-ON SEQUENCE .................................................................................................................... 12
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with SDIO Interface
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Datasheet
1.
General Description
The Realtek RTL8189ES-VB-CG is a highly integrated single-chip 802.11n Wireless LAN (WLAN)
network SDIO interface (SDIO 1.1/ 2.0/ 3.0 compliant) controller. It is a WLAN MAC, a 1T1R capable
WLAN baseband, and WLAN RF in a single chip. The RTL8189ES-VB provides a complete solution for a
high-throughput performance integrated wireless LAN device.
The RTL8189ES-VB WLAN baseband implements Orthogonal Frequency Division Multiplexing (OFDM)
with 1 transmit and 1 receive path and is compatible with the IEEE 802.11n specification. Features include
one spatial stream transmission, short guard interval (GI) of 400ns, spatial spreading, and transmission over
20MHz and 40MHz bandwidth.
For legacy compatibility, Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK)
and OFDM baseband processing are included to support all IEEE 802.11b and 802.11g data rates.
Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability,
are available, and CCK provides support for legacy data rates, with long or short preamble. The high-speed
FFT/IFFT paths, combined with BPSK, QPSK, 16QAM, and 64QAM modulation of the individual
subcarriers and rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, 3/4, and 5/6,
provide higher data rates of 54Mbps and 150Mbps for IEEE 802.11g and 802.11n OFDM respectively.
The RTL8189ES-VB WLAN Controller builds in an enhanced signal detector, an adaptive frequency
domain equalizer, and a soft-decision Viterbi decoder to alleviate severe multi-path effects and mutual
interference in the reception of multiple streams. Robust interference detection and suppression are
provided to protect against Bluetooth, cordless phone, and microwave oven interference.
Efficient IQ-imbalance, DC offset, phase noise, frequency offset, and timing offset compensations are
provided for the radio frequency front-end. Selectable digital transmit and receive FIR filters are provided
to meet transmit spectrum mask requirements and to reject adjacent channel interference, respectively.
The RTL8189ES-VB WLAN Controller supports fast receiver Automatic Gain Control (AGC) with
synchronous and asynchronous control loops among antennas, antenna diversity functions, and adaptive
transmit power control function to obtain the better performance in the analog portions of the transceiver.
The RTL8189ES-VB WLAN MAC supports 802.11e for multimedia applications, 802.11i for security, and
802.11n for enhanced MAC protocol efficiency. Using packet aggregation techniques such as A-MPDU
with BA and A-MSDU, protocol efficiency is significantly improved. Power saving mechanisms such as
Legacy Power Save, and U-APSD, reduce the power wasted during idle time, and compensates for the extra
power required to transmit OFDM. The RTL8189ES-VB provides simple legacy and 20MHz/40MHz
co-existence mechanisms to ensure backward and network compatibility.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
2. Features
General
WLAN MAC Features
32-pin QFN
Frame aggregation for increased MAC
efficiency (A-MSDU, A-MPDU)
CMOS MAC, Baseband PHY, and RF in a
single chip for IEEE 802.11b/g/n
compatible WLAN
Low latency immediate High-Throughput
Block Acknowledgement (HT-BA)
Complete 802.11n solution for 2.4GHz
band
PHY-level spoofing to enhance legacy
compatibility
72.2Mbps receive PHY rate and 72.2Mbps
transmit PHY rate using 20MHz bandwidth
Power saving mechanism
Channel management and co-existence
Transmit Opportunity (TXOP) Short
Inter-Frame Space (SIFS) bursting for
higher multimedia bandwidth
150Mbps receive PHY rate and 150Mbps
transmit PHY rate using 40MHz bandwidth
Compatible with 802.11n specification
Backward compatible with 802.11b/g
devices while operating in 802.11n mode
IEEE 802.11n OFDM
One Transmit and one Receive path (1T1R)
Complies with SDIO 1.1/ 2.0/ 3.0 for
WLAN with clock rate up to 100MHz
20MHz and 40MHz bandwidth
transmission
GSPI interface for configurable endian for
WLAN
Short Guard Interval (400ns)
DSSS with DBPSK and DQPSK, CCK
modulation with long and short preamble
OFDM with BPSK, QPSK, 16QAM, and
64QAM modulation.
Convolutional Coding Rate: 1/2, 2/3, 3/4,
and 5/6
Maximum data rate 54Mbps in 802.11g and
150Mbps in 802.11n
Switch diversity for DSSS/CCK
Hardware antenna diversity on per packet
base
Host Interface
WLAN PHY Features
Standards Supported
IEEE 802.11b/g/n compatible WLAN
IEEE 802.11e QoS Enhancement (WMM)
802.11i (WPA, WPA2). Open, shared key,
and pair-wise key authentication services
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
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Datasheet
Selectable receiver FIR filters
Programmable scaling in transmitter and
receiver to trade quantization noise against
increased probability of clipping
Peripheral Interfaces
Fast receiver Automatic Gain Control
(AGC)
3.
On-chip ADC and DAC
General Purpose Input/Output (8 pins)
One configurable LED pin
System Applications
3.1. Single-Band 11n (1x1) Solution
RTL8189ES-VB
TX I/Q
.
PA
matching
Transmitter
MAC
Configuration
Control and
Memory
2.4 GHz
Receiver
RX I/Q
SDIO/GSPI
Host Interface
Baseband
( PHY)
SWR/LDO
Regulators
3.3V
Ext
Interface
ADC
Antenna
Balun/
Filter
Circuit
DAC
NV Memory
40 MHz
Crystal
Figure 1. Single-Band 11n (1x1) Solution
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Datasheet
4.
Pin Assignments
Figure 2. Pin Assignments
4.1. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2Figure 2. The version is shown
in the location marked ‘V’, e.g.,.B=Version B.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
5.
Pin Descriptions
The following signal type codes are used in the tables:
I: Input
T/S: Tri-State Bi-Directional Input/Output Pin
O: Output
S/T/S: Sustained Tri-State
O/D: Open Drain
P: Power Pin
5.1. SDIO Interface
Table 1. SDIO Interface
Symbol
Type
Pin No Description
SD_CLK
I
21
SDIO Clock Input
SD_CMD
I/O
22
SDIO Command Input
SD_D0
I/O
19
SDIO Data Line 0
SD_D1
I/O
20
SDIO Data Line 1
SD_D2
I/O
23
SDIO Data Line 2
SD_D3
I/O
24
SDIO Data Line 3
Note: For details of SDIO interface selection, see section 6.4.2 SDIO/GSPI Interface Signal Level, page 10.
5.2. GSPI Interface
Table 2. GSPI Interface
Symbol
Type
Pin No Description
SPI_CLK
I
21
GSPI Clock Input
SPI_MOSI
I
22
GSPI Data Input
SPI_MISO
O
19
GSPI Data Out
SPI_SIRQ
O
23
GSPI Interrupt
SPI_SCSn
I
20
GSPI Chip Select Bar
Note: The GSPI interface pins are shared with the SDIO interface. For details of SDIO interface selection, see section 6.4.2
SDIO/GSPI Interface Signal Level, page 10.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
5.3. Power Pins
Symbol
LX_SPS
VDSPS33
Type
P
P
Pin No
15
16
VD33A
VD33IO
VD33PAD
VD33S
VDIO_SDIO
P
P
P
P
P
11, 17
30
3
8
18
VD12A
VD12D
VD12R
VD12S
GND_SPS
P
P
P
P
P
12
13, 31
6
7
14
Table 3. Power Pins
Description
Switching Regulator Output
Switching Regulator Input or Linear Regulator output from 3.3V to
1.5V
VDD 3.3V for Analog
VDD3.3V for Digital
VDD 3.3V for PAD
VDD 3.3V for Analog
VDD for SDIO Pin. The power supply is the same as the signal level of
SDIO bus (3.3V ~ 1.8V)
VDD 1.2V for Analog
VDD 1.2V for Digital
VDD 1.2V for Analog
VDD 1.2V for Analog
Switching Regulator Ground
5.4. RF Interface
Symbol
RXIN
RXIP
TXPA_ON
TXPA_OP
Type
I
I
O
O
Pin No
5
4
2
1
Table 4. RF Interface
Description
RF RX Negative Signal
RF RX Positive Signal
RF TX Negative Signal
RF TX Positive Signal
5.5. LED Interface
Symbol
LED2
Type
O
Pin No
26
Table 5. LED Interface
Description
LED pin (Active Low).
This pin is shared with GPIO5. It can be selected via the control register
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
5.6. Clock and Other Pins
Symbol
XI
Type
I
XO
PDn
O
I
CLK_REQ
O
GPIO1/(SPS_LDO
_SEL)
IO
GPIO4
GPIO5
IO
IO
GPIO6/(TEST_MODE
_SEL)
IO
GPIO7
IO
Table 6. Clock and Other Pins
Pin No Description
10
OSC Input.
Input of Crystal Clock Reference.
The Crystal Clock can be 40MHz, 13MHz, 19.2MHz, 20MHz, 25MHz,
26MHz, 38.4MHz, 17.664MHz, 16MHz, 14.318MHz, or 12MHz
9
Output of Crystal Clock Reference
25
This pin can Externally Shutdown the RTL8189ES-VB without requiring
an extra power switch
26
This pin is used by the RTL8189ES to request the system clock from the
host. It is shared with GPIO5. It can be selected via the control register
29
.General Purpose Input/Output Pin.
Trap function: weakly pull low to enable the integrated switching regulator;
weakly pull high to enable the integrated linear regulator
28
General Purpose Input/Output Pin
26
General Purpose Input/Output Pin. This pin is shared with CLK_REQ and
LED2.
32
General Purpose Input/Output Pin.
Trap function: weakly pull low to enable the RTL8189ES-VB to enter
normal operation mode.
27
General Purpose Input/Output Pin
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
6.
Electrical and Thermal Characteristics
6.1. Temperature Limit Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Junction Temperature
Table 7. Temperature Limit Ratings
Minimum
Maximum
-55
+125
0
70
0
125
Units
C
C
C
6.2. Temperature Limit Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Junction Temperature
Table 8. Temperature Limit Ratings
Minimum
Maximum
-55
+125
0
70
0
125
Units
C
C
C
6.3. DC Characteristics
6.3.1.
Power Supply Characteristics
Symbol
VD33A, VD33D
VD12A, VD12D
IDD33
Table 9. DC Characteristics
Parameter
Minimum
Typical
3.3V I/O Supply Voltage
3.0
3.3
1.2V Core Supply Voltage
1.10
1.2
3.3V Rating Current
-
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
8
Maximum
3.6
1.32
600
Units
V
V
mA
Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
6.3.2.
Digital IO Pin DC Characteristics
Symbol
VIH
VIL
VOH
VOL
Table 10. 3.3V GPIO DC Characteristics
Parameter
Minimum
Normal
Input High Voltage
2.0
3.3
Input Low Voltage
-0
Output High Voltage
2.97
-Output Low Voltage
0
--
Maximum
3.6
0.9
3.3
0.33
Units
V
V
V
V
Symbol
VIH
VIL
VOH
VOL
Table 11. 2.8V GPIO DC Characteristics
Parameter
Minimum
Normal
Input High Voltage
1.8
2.8
Input Low Voltage
-0
Output High Voltage
2.5
-Output Low Voltage
0
--
Maximum
3.1
0.8
3.1
0.28
Units
V
V
V
V
Symbol
VIH
VIL
VOH
VOL
Table 12. 1.8V GPIO DC Characteristics
Parameter
Minimum
Normal
Input High Voltage
1.7
1.8
Input Low Voltage
-0
Output High Voltage
1.62
-Output Low Voltage
0
--
Maximum
2.0
0.8
1.8
0.18
Units
V
V
V
V
6.4. AC Characteristics
6.4.1.
SDIO/GSPI Interface Timing
Figure 3. SDIO/GSPI Interface Timing
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
Table 13. SDIO/GSPI Interface Timing Parameters
NO
Parameter
fPP
Clock Frequency
TWL
Clock Low Time
TWH
Clock High Time
TISU
Input Setup Time
TIH
Input Hold Time
TODLY Output Delay Time
6.4.2.
Mode
MIN
MAX
Unit
Default
HS
DEF
HS
DEF
HS
DEF
HS
DEF
HS
DEF
HS
0
0
10
7
10
7
5
6
5
2
-
25
50
14
14
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDIO/GSPI Interface Signal Level
The SDIO and GSPI signal level ranges from 1.8V to 3.3V.
The DC characteristics of a typical signal level, 3.3V/2.8V/1.8V are shown in section 6.3.2 Digital IO Pin
DC Characteristics, page 9.
6.4.3.
SDIO Interface Power-On Sequence
After power-on, the SDIO interface is selected by the RTL8189ES-VB automatically when a valid SDIO
command is received. To attain better SDIO host compatibility, the following power-on sequence is
recommended:
T33Ramp'
3.3V
pre-charge
Toff
T33Ramp
formal power up
2.7V
SD_CLK
SD_CMD
CMD5 not ready
CMD5/5/3/7 ready
CMD52/ 53
SDIO_RDY
T12Ramp
Tnon_rdy
VDDON
TPOR
POR
Figure 4. SDIO Interface Power-On Sequence
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
Definitions
T33ramp’: The 3.3V power pre-charge ramp up duration before formal power up. We recommend that a 3.3V
power-on and then power-off sequence is executed by the host controller before the formal power-on
sequence. This procedure can eliminate the host card detection issue when the power ramp up duration is
too long or the system warm reboot fails.
Toff : The duration 3.3V is cut off before formal power up.
T33ramp: The 3.3V main power ramp up duration.
T12ramp: The internal 1.2V ramp up duration.
TPOR: The duration the power-on reset releases, and the power management unit executes power-on tasks.
The power-on reset will detect both 3.3V and 1.2V power ramp up after a predetermined duration.
Tnon_rdy: SDIO not ready duration. In this state the RTL8189ES may respond to commands without the
ready bit set. After the ready bit is set, the host will initiate the full card detection procedure.
Power-On Flow Description
We recommend that the card detection procedures are divided into two phases: a 3.3V power pre-charge
phase and a formal power-up phase.
For the 3.3V power pre-charge phase, the power ramp up duration is not limited. The 3.3V is then cut off
and is turned on after a Toff period. The ramp up time is specified by the T33ramp duration.
After main 3.3V ramp up and 1.2V ramp up, the power management unit will be enabled by the power
ready detection circuit, and will enable the SDIO block. eFUSE is then autoloaded to the SDIO circuits
during the Tnon_rdy duration. After the autoload has completed, the SDIO sets the ready bit. After CMD5/
5/3/7 procedures, card detection is then executed. After the driver has loaded, normal commands 52 and 53
are then used.
A typical timing specification is shown below:
Parameter
T33ramp’
Toff
T33ramp
T12ramp
Tpor
Tnon-rdy
Table 14. SDIO Interface Power-On Timing Parameters
Min
Typical
Max
No Limit
250
500
1000
0.1
0.5
2.5
0.1
0.5
1.5
2
2
8
1
2
10
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
11
Unit
ms
ms
ms
ms
ms
ms
Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
6.4.4.
GSPI Interface Power-On Sequence
The GSPI interface is enabled automatically when a valid GSPI command is first received. The
recommended power-on sequence is as follows:
T33Ramp'
3.3V
pre-charge
Toff
T33Ramp
formal power up
2.7V
SPI_CLK
write register SPI_CFG
SPI_MISO
write cmd+data
read cmd
write cmd+data
SPI_MOSI
status
status+data
status
SPI_SCSn
T12RampTnon_rdy
VDDON
POR
Figure 5. GSPI Interface Power-On Sequence
Definitions
T33ramp’: The 3.3V power pre-charge ramp up duration before formal power up. We recommend that a 3.3V
power-on and then power-off sequence is executed by the host controller before the formal power-on
sequence. This procedure can eliminate the host card detection issue when the power ramp up duration is
too long or the system warm reboot fails.
Toff : The duration 3.3V is cut off before formal power up.
T33ramp: The 3.3V main power ramp up duration.
T12ramp: The internal 1.2V ramp up duration.
Tnon_rdy: The duration of SPI device internal initialization. After Tnon_rdy, the SPI host can then send
commands to write the SPI_CFG register. The SPI_CFG register controls SPI endian and word length.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
Power-On Flow Description
We recommend that the card detection procedures are divided into two phases: a 3.3V power pre-charge
phase and a formal power-up phase.
For the 3.3V power pre-charge phase, the power ramp up duration is not limited. The 3.3V is then cut off
and is turned on after a Toff period. The ramp up time is specified by the T33ramp duration.
After main 3.3V ramp up and 1.2V ramp up, the power management unit will be enabled by the power
ready detection circuit, and will enable the SPI block. eFUSE is then autoloaded to the SPI circuits, and the
internal power circuits are configured during the Tnon_rdy duration.
A typical timing specification is shown below:
Parameter
T33ramp’
Toff
T33ramp
T12ramp
Tnon-rdy
Table 15. GSPI Interface Power-On Timing Parameters
Min
Typical
Max
No Limit
250
500
1000
0.1
0.5
2.5
0.1
0.5
1.5
3
4
18
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
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Unit
ms
ms
ms
ms
ms
Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
7.
Mechanical Dimensions
7.1. Mechanical Dimensions Notes
Symbol
Dimension in mm
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
A3
0.20 REF
A4
0.10 REF
b
0.18
0.25
0.30
D/E
5.00 BSC
D2/E2
3.25
3.50
3.75
e
0.50 BSC
L
0.30
0.40
0.50
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
Min
0.031
0.000
0.007
0.128
0.012
14
Dimension in inch
Nom
0.033
0.001
0.008 REF
0.004 REF
0.010
0.020 BSC
0.138
0.020 BSC
0.016
Max
0.035
0.002
0.012
0.148
0.020
Track ID: JATR-8275-15 Rev. 1.0
RTL8189ES-VB
Datasheet
8.
Ordering Information
Table 16. Ordering Information
Part Number
Package
RTL8189ES-VB-CG
QFN-32, ‘Green’ Package
Note: See page 4 for package identification.
Status
Mass Production
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller
with SDIO Interface
15
Track ID: JATR-8275-15 Rev. 1.0
工商网监
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