RTL8367S-CG

RTL8367S-CG LAYER 2 MANAGED 5+2-PORT 10/100/1000M SWITCH CONTROLLER DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. Pre-0.941 23 Feb 2016 Track ID: xxxx-xxxx-xx Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211 Fax: +886-3-577-6047 www.realtek.com RTL8367S Datasheet COPYRIGHT ©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek RTL8367S IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. REVISION HISTORY Revision Pre-0.9 Pre-0.91 Release Date 2015/08/06 2015/08/18 Pre-0.92 2015/11/18 Summary Preliminary release. 1. Revised Section 6. Pin Assignments 2. Revised Section 6.2. Pin Assignments Table 3. Revised Section 7.3. General Purpose Interfaces 4. Revised Section 7.5. Configuration Strapping Pins 5. Revised Section 7.6. Management 6. Revised Section 7.7. Miscellaneous Pins 1. Revised Section 6. Pin Assignments 2. Revised Section 6.2. Pin Assignments Table 3. Revised Section 7.3. General Purpose Interfaces 4. Revised Section 7.5. Configuration Strapping Pins 5. Revised Section 7.6. Management Interface Pins 6. Revised Section 7.7. Miscellaneous Pins 7. Revised Section 9.19. LED Indicators 8. Revised Section 12.2. Recommended Operating Range 9. Add Section 12.5.7. HSGMII Characteristics 10. Add Section 12.5.8. SGMII Characteristics Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller ii Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Revision Pre-0.93 Release Date 2015/12/30 Pre-0.94 Pre-0.941 2016/01/11 2016/02/23 Summary 1. Revised Section 12.2. Recommended Operating Range 2. Revised Section 12.3.1. Assembly Description 3. Revised Section 12.3.2. Material Properties 4. Revised Section 12.3.3. Simulation Conditions 5. Revised Section 12.3.4. Thermal Performance of LQFP-128 on PCB Under Still Air Convection 6. Delete Section 12.3.5. Thermal Performance of LQFP-128 on PCB Under Forced Convection 1. Revised Section 12.5.2. EEPROM SMI Slave Mode Timing Characteristics 1. Revised Table 10 2. Revised Table 12 3. Revised package type as LQFP-128 or LQFP 128-pin 4. Revised Section 7.4. LED Pins 5. Revised Section 12.3.1. Assembly Description Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller iii Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Table of Contents 1. GENERAL DESCRIPTION ..............................................................................................................................................1 2. FEATURES .........................................................................................................................................................................3 3. SYSTEM APPLICATIONS...............................................................................................................................................5 4. APPLICATION EXAMPLES ...........................................................................................................................................5 4.1. 4.2. 5-PORT 1000BASE-T SWITCH ......................................................................................................................................5 5-PORT 1000BASE-T ROUTER WITH SGMII/HSGMII AND/OR MII/RGMII ................................................................6 5. BLOCK DIAGRAM ...........................................................................................................................................................7 6. PIN ASSIGNMENTS .........................................................................................................................................................8 6.1. 6.2. 7. PACKAGE IDENTIFICATION ...........................................................................................................................................8 PIN ASSIGNMENTS TABLE ............................................................................................................................................9 PIN DESCRIPTIONS.......................................................................................................................................................12 7.1. MEDIA DEPENDENT INTERFACE PINS .........................................................................................................................12 7.2. HIGH SPEED SERIAL INTERFACE PINS ........................................................................................................................13 7.3. GENERAL PURPOSE INTERFACES ................................................................................................................................13 7.3.1. RGMII Pins...........................................................................................................................................................15 7.3.2. MII Pins................................................................................................................................................................16 7.4. LED PINS ...................................................................................................................................................................18 7.5. CONFIGURATION STRAPPING PINS .............................................................................................................................19 7.5.1. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF)......................................................20 7.6. MANAGEMENT INTERFACE PINS ................................................................................................................................21 7.7. MISCELLANEOUS PINS ...............................................................................................................................................21 7.8. TEST PINS ..................................................................................................................................................................23 7.9. POWER AND GND PINS ..............................................................................................................................................23 8. PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................24 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. 8.9. 8.10. 9. MDI INTERFACE ........................................................................................................................................................24 1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................24 1000BASE-T RECEIVE FUNCTION ..............................................................................................................................24 100BASE-TX TRANSMIT FUNCTION...........................................................................................................................24 100BASE-TX RECEIVE FUNCTION .............................................................................................................................25 10BASE-T TRANSMIT FUNCTION ...............................................................................................................................25 10BASE-T RECEIVE FUNCTION ..................................................................................................................................25 AUTO-NEGOTIATION FOR UTP ..................................................................................................................................25 CROSSOVER DETECTION AND AUTO CORRECTION .....................................................................................................26 POLARITY CORRECTION .............................................................................................................................................26 GENERAL FUNCTION DESCRIPTION......................................................................................................................27 9.1. RESET ........................................................................................................................................................................27 9.1.1. Hardware Reset ....................................................................................................................................................27 9.1.2. Software Reset ......................................................................................................................................................27 9.2. IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................27 9.3. HALF DUPLEX FLOW CONTROL .................................................................................................................................28 9.3.1. Back-Pressure Mode ............................................................................................................................................28 9.4. SEARCH AND LEARNING ............................................................................................................................................29 9.5. SVL AND IVL/SVL ...................................................................................................................................................29 9.6. ILLEGAL FRAME FILTERING .......................................................................................................................................29 9.7. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL .............................................................................30 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller iv Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.8. BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................31 9.9. PORT SECURITY FUNCTION ........................................................................................................................................31 9.10. MIB COUNTERS .........................................................................................................................................................31 9.11. PORT MIRRORING ......................................................................................................................................................31 9.12. VLAN FUNCTION ......................................................................................................................................................32 9.12.1. Port-Based VLAN ............................................................................................................................................32 9.12.2. IEEE 802.1Q Tag-Based VLAN.......................................................................................................................32 9.12.3. Protocol-Based VLAN .....................................................................................................................................33 9.12.4. Port VID ..........................................................................................................................................................33 9.13. QOS FUNCTION ..........................................................................................................................................................34 9.13.1. Input Bandwidth Control .................................................................................................................................34 9.13.2. Priority Assignment .........................................................................................................................................34 9.13.3. Priority Queue Scheduling...............................................................................................................................34 9.13.4. IEEE 802.1p/Q and DSCP Remarking ............................................................................................................35 9.13.5. ACL-Based Priority .........................................................................................................................................35 9.14. IGMP & MLD SNOOPING FUNCTION.........................................................................................................................36 9.15. IEEE 802.1X FUNCTION .............................................................................................................................................37 9.15.1. Port-Based Access Control..............................................................................................................................37 9.15.2. Authorized Port-Based Access Control ...........................................................................................................37 9.15.3. Port-Based Access Control Direction..............................................................................................................37 9.15.4. MAC-Based Access Control.............................................................................................................................37 9.15.5. MAC-Based Access Control Direction ............................................................................................................38 9.15.6. Optional Unauthorized Behavior.....................................................................................................................38 9.15.7. Guest VLAN .....................................................................................................................................................38 9.16. IEEE 802.1D FUNCTION ............................................................................................................................................38 9.17. EMBEDDED 8051........................................................................................................................................................38 9.18. REALTEK CABLE TEST (RTCT) .................................................................................................................................39 9.19. LED INDICATORS.......................................................................................................................................................39 9.20. GREEN ETHERNET ......................................................................................................................................................41 9.20.1. Link-On and Cable Length Power Saving .......................................................................................................41 9.20.2. Link-Down Power Saving ................................................................................................................................41 9.21. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ...............................................................................41 9.22. INTERRUPT PIN FOR EXTERNAL CPU .........................................................................................................................41 10. INTERFACE DESCRIPTIONS .................................................................................................................................42 10.1. EEPROM SMI HOST TO EEPROM ...........................................................................................................................42 10.2. EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................43 10.3. GENERAL PURPOSE INTERFACE..................................................................................................................................44 10.3.1. Extension Ports RGMII Mode Interface (1Gbps) ............................................................................................45 10.3.2. Extension Ports MII MAC/PHY Mode Interface (10/100Mbps) ......................................................................45 11. REGISTER DESCRIPTIONS ....................................................................................................................................48 11.1. 11.2. 11.3. 11.4. 11.5. 11.6. 11.7. 11.8. 11.9. 11.10. 11.11. 11.12. 11.13. PCS REGISTER (PHY 0~4).........................................................................................................................................48 REGISTER 0: CONTROL ...............................................................................................................................................49 REGISTER 1: STATUS ..................................................................................................................................................50 REGISTER 2: PHY IDENTIFIER 1 .................................................................................................................................51 REGISTER 3: PHY IDENTIFIER 2 .................................................................................................................................51 REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................51 REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................52 REGISTER 6: AUTO-NEGOTIATION EXPANSION ..........................................................................................................53 REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER ..................................................................................53 REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................54 REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................54 REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................55 REGISTER 15: EXTENDED STATUS .........................................................................................................................55 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller v Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12. ELECTRICAL CHARACTERISTICS......................................................................................................................56 12.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................56 12.2. RECOMMENDED OPERATING RANGE..........................................................................................................................56 12.3. THERMAL CHARACTERISTICS.....................................................................................................................................57 12.3.1. Assembly Description ......................................................................................................................................57 12.3.2. Material Properties .........................................................................................................................................57 12.3.3. Simulation Conditions .....................................................................................................................................57 12.3.4. Thermal Performance of LQFP-128 on PCB Under Still Air Convection.......................................................58 12.4. DC CHARACTERISTICS ...............................................................................................................................................59 12.5. AC CHARACTERISTICS ...............................................................................................................................................60 12.5.1. EEPROM SMI Host Mode Timing Characteristics .........................................................................................60 12.5.2. EEPROM SMI Slave Mode Timing Characteristics ........................................................................................61 12.5.3. MDIO Slave Mode Timing Characteristics .....................................................................................................62 12.5.4. MII MAC Mode Timing ...................................................................................................................................63 12.5.5. MII PHY Mode Timing ....................................................................................................................................64 12.5.6. RGMII Timing Characteristics ........................................................................................................................65 12.5.7. HSGMII Characteristics ..................................................................................................................................67 12.5.8. SGMII Characteristics.....................................................................................................................................69 12.6. POWER AND RESET CHARACTERISTICS ......................................................................................................................71 13. MECHANICAL DIMENSIONS.................................................................................................................................72 14. ORDERING INFORMATION ...................................................................................................................................73 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller vi Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet List of Tables TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................9 TABLE 2. MEDIA DEPENDENT INTERFACE PINS ...........................................................................................................................12 TABLE 3. GENERAL PURPOSE INTERFACES PINS ..........................................................................................................................13 TABLE 4. EXTENSION GMAC2 RGMII PINS ...............................................................................................................................15 TABLE 5. EXTENSION GMAC2 MII PINS (MII MAC MODE OR MII PHY MODE).......................................................................16 TABLE 6. LED PINS .....................................................................................................................................................................18 TABLE 7. CONFIGURATION STRAPPING PINS................................................................................................................................19 TABLE 8. CONFIGURATION STRAPPING PINS (DISAUTOLOAD, DIS_8051, AND EN_SPIF) ......................................................20 TABLE 9. MANAGEMENT INTERFACE PINS ....................................................................................................................................21 TABLE 10. MISCELLANEOUS PINS .................................................................................................................................................21 TABLE 11. TEST PINS ....................................................................................................................................................................23 TABLE 12. POWER AND GND PINS ................................................................................................................................................23 TABLE 13. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................26 TABLE 14. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE .........................................................................................30 TABLE 15. IPV4/IPV6 MULTICAST ROUTING PROTOCOLS .............................................................................................................36 TABLE 16. LED DEFINITIONS........................................................................................................................................................39 TABLE 17. RTL8367S EXTENSION PORT 2 PIN DEFINITIONS ........................................................................................................44 TABLE 18. EXTENSION GMAC2 RGMII PINS ...............................................................................................................................45 TABLE 19. EXTENSION GMAC2 MII PINS ....................................................................................................................................45 TABLE 20. PCS REGISTER (PHY 0~4)...........................................................................................................................................48 TABLE 21. REGISTER 0: CONTROL ................................................................................................................................................49 TABLE 22. REGISTER 1: STATUS....................................................................................................................................................50 TABLE 23. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................51 TABLE 24. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................51 TABLE 25. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ...................................................................................................51 TABLE 26. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................52 TABLE 27. REGISTER 6: AUTO-NEGOTIATION EXPANSION ............................................................................................................53 TABLE 28. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER....................................................................................53 TABLE 29. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ...................................................................54 TABLE 30. REGISTER 9: 1000BASE-T CONTROL REGISTER ...........................................................................................................54 TABLE 31. REGISTER 10: 1000BASE-T STATUS REGISTER ............................................................................................................55 TABLE 32. REGISTER 15: EXTENDED STATUS ...............................................................................................................................55 TABLE 33. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................56 TABLE 34. RECOMMENDED OPERATING RANGE ...........................................................................................................................56 TABLE 35. ASSEMBLY DESCRIPTION .............................................................................................................................................57 TABLE 36. MATERIAL PROPERTIES ...............................................................................................................................................57 TABLE 37. SIMULATION CONDITIONS ...........................................................................................................................................57 TABLE 38. THERMAL PERFORMANCE OF LQFP-128 ON PCB UNDER STILL AIR CONVECTION .....................................................58 TABLE 39. DC CHARACTERISTICS .................................................................................................................................................59 TABLE 40. EEPROM SMI HOST MODE TIMING CHARACTERISTICS .............................................................................................61 TABLE 41. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ...........................................................................................61 TABLE 42. MDIO TIMING CHARACTERISTICS AND REQUIREMENT ...............................................................................................62 TABLE 43. MII MAC MODE TIMING .............................................................................................................................................63 TABLE 44. MII PHY MODE TIMING CHARACTERISTICS ................................................................................................................64 TABLE 45. RGMII TIMING CHARACTERISTICS ..............................................................................................................................66 TABLE 46. HSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS .........................................................................................67 TABLE 47. HSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ...............................................................................................68 TABLE 48. SGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS ............................................................................................69 TABLE 49. SGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ..................................................................................................70 TABLE 50. POWER AND RESET CHARACTERISTICS ........................................................................................................................71 TABLE 51. ORDERING INFORMATION ............................................................................................................................................73 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller vii Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller viii Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet List of Figures FIGURE 1. 5-PORT 1000BASE-T SWITCH .......................................................................................................................................5 FIGURE 2. 5-PORT 1000BASE-T ROUTER WITH SGMII/HSGMII AND/OR MII/RGMII .................................................................6 FIGURE 3. BLOCK DIAGRAM ..........................................................................................................................................................7 FIGURE 4. PIN ASSIGNMENTS (LQFP-128) ....................................................................................................................................8 FIGURE 5. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................26 FIGURE 6. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART ..................................................................................33 FIGURE 7. RTL8367S MAX-MIN SCHEDULING DIAGRAM .........................................................................................................35 FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED...........................................................................40 FIGURE 9. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED...................................................................................40 FIGURE 10. SMI START AND STOP COMMAND ..............................................................................................................................42 FIGURE 11. EEPROM SMI HOST TO EEPROM............................................................................................................................42 FIGURE 12. EEPROM SMI HOST MODE FRAME...........................................................................................................................42 FIGURE 13. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................43 FIGURE 14. EEPROM SMI READ COMMAND FOR SLAVE MODE ..................................................................................................43 FIGURE 15. RGMII MODE INTERFACE SIGNAL DIAGRAM .............................................................................................................45 FIGURE 16. SIGNAL DIAGRAM OF MII PHY MODE INTERFACE (100MBPS)..................................................................................46 FIGURE 17. SIGNAL DIAGRAM OF MII MAC MODE INTERFACE (100MBPS) .................................................................................47 FIGURE 18. EEPROM SMI HOST MODE TIMING CHARACTERISTICS ............................................................................................60 FIGURE 19. SCK/SDA POWER ON TIMING ....................................................................................................................................60 FIGURE 20. EEPROM AUTO-LOAD TIMING..................................................................................................................................60 FIGURE 21. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ..........................................................................................61 FIGURE 22. MDIO SOURCED BY MASTER .....................................................................................................................................62 FIGURE 23. MDIO SOURCED BY RTL8367S (SLAVE)...................................................................................................................62 FIGURE 24. MII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING ......................................................................................63 FIGURE 25. MII MAC MODE INPUT TIMING .................................................................................................................................63 FIGURE 26. MII PHY MODE OUTPUT TIMING ...............................................................................................................................64 FIGURE 27. MII PHY MODE CLOCK OUTPUT TO DATA INPUT DELAY TIMING .............................................................................64 FIGURE 28. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=0) ................................................................65 FIGURE 29. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=2NS) ............................................................65 FIGURE 30. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=0)....................................................................65 FIGURE 31. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=2NS)................................................................66 FIGURE 32. HSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM ..............................................................................................67 FIGURE 33. HSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM ....................................................................................................68 FIGURE 34. SGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM .................................................................................................69 FIGURE 35. SGMII DIFFERENTIAL RECEIVER EYE DIAGRAM .......................................................................................................70 FIGURE 36. POWER AND RESET CHARACTERISTICS .......................................................................................................................71 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller ix Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 1. General Description The RTL8367S-CG is a LQFP-128, high-performance 5+2-port 10/100/1000M Ethernet switch featuring a low-power integrated 5-Port Giga-PHY that supports 1000Base-T, 100Base-TX, and 10Base-T. For specific applications, the RTL8367S supports one extra interface that could be configured as RGMII/MII interfaces. The RTL8367S also supports one Ser-Des interface that could be configured as SGMII/HSGMII interfaces. The RTL8367S integrates all the functions of a high-speed switch system; including SRAM for packet buffering, non-blocking switch fabric, and internal register management into a single CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration. The embedded packet storage SRAM in the RTL8367S features superior memory management technology to efficiently utilize memory space. The RTL8367S integrates a 2K-entry look-up table with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access from the EEPROM Serial Management Interface (SMI), Media Independent Interface Management (MIIM), or SPI Interface. Each of the table entries can be configured as a static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions. The Extension GMAC1 of the RTL8367S implements a SGMII/HSMII interfaces and Extension GMAC2 of the RTL8367S implements a RGMII/MII interfaces. These interfaces could be connected to an external PHY, MAC, CPU, or RISC for specific applications. In router applications, the RTL8367S supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag will be changed to PVID. Note: The RTL8367S Extra Interface (Extension GMAC2) supports: Media Independent Interface (MII) Reduced Gigabit Media Independent Interface (RGMII) The RTL8367S supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. The RTL8367S supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports only. For IP multicast applications, the RTL8367S supports IPv4 IGMPv1/v2/v3 and IPv6 MLDv1/v2 snooping. In order to support flexible traffic classification, the RTL8367S supports 96-entry ACL rule check and multiple actions options. Each port can optionally enable or disable the ACL rule check function. The ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value in 802.1q/Q tag, force output tag format and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps steps). In Bridge operation the RTL8367S supports 16 sets of port configurations: disable, block, learning, and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and management application requirements, the RTL8367S supports IEEE 802.1x Port-based/MAC-based Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8367S provides a Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 1 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics. To improve real-time or multimedia networking applications, the RTL8367S supports eight priority assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or Weighted Fair Queue (WFQ) or mixed. The RTL8367S provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-based VLAN operation to separate logical connectivity from physical connectivity. The RTL8367S supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM SMI Slave after reset. In router applications, the router may want to know the input port of the incoming packet. The RTL8367S supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port. The RTL8367S also provides an option to admit VLAN tagged packet with a specific PVID only. If this function is enabled, the RTL8367S will drop all non-tagged packets and packets with an incorrect PVID. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 2 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 2. Features  Single-chip 5+2-port 10/100/1000M nonblocking switch architecture  Embedded 5-Port 10/100/1000Base-T PHY  Each port supports full duplex 10/100/1000M connectivity (half duplex only supported in 10/100M mode)   Optional setting of per-port action to take when ACL mismatch  Supports IEEE 802.1Q VLAN  Supports 4K VLANs and 32 Extra Enhanced VLANs  Supports Un-tag definition in each VLAN  Supports VLAN policing and VLAN Extra Interface (Extension GMAC1) Supports High Speed Serial Interface (Extension GMAC1) forwarding decision  Port-based, Tag-based, and Protocol-based VLAN  SGMII (1.25GHz) Interface  Up to 4 Protocol-based VLAN entries  High SGMII (3.125GHz) Interface   Per-port and per-VLAN egress VLAN Extra Interface (Extension GMAC2) supports  Media Independent Interface (MII) tagging and un-tagging  Supports IVL, SVL, and IVL/SVL  2K-entry MAC address table with 4-way  Reduced 10/100/1000M Media hash algorithm Independent Interface (RGMII)    Up to 2K-entry L2/L3 Filtering Database Full-duplex and half-duplex operation with IEEE 802.3x flow control and backpressure Supports 9216-byte jumbo packet length forwarding at wire speed  Realtek Cable Test (RTCT) function  Supports 96-entry ACL Rules  Per-port MAC learning limitation  System base MAC learning limitation  Supports Spanning Tree Port Behavior configuration  IEEE 802.1w Rapid Spanning Tree  IEEE 802.1s Multiple Spanning Tree with  Search keys support physical port, Layer2, up to 16 Spanning Tree instances Layer3, and Layer4 information  Actions include mirror, redirect, dropping,  priority adjustment, traffic policing, CVLAN decision, and SVLAN assignment GPIO control, force output tag format, interrupt and logging counter  Port-Based Access Control  MAC-Based Access Control  Guest VLAN  Supports five types of user defined ACL rule format for 96 ACL rules  Supports Auto protection from Denial-ofService attacks  Supports H/W IGMP/MLD Snooping  Optional per-port enable/disable of ACL function Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller Supports IEEE 802.1x Access Control Protocol 3 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet  IGMPv1/v2/v3 and MLD v1/v2  Supports Fast Leave  Supports MAC-based 1:N VLAN  Supports two IEEE 802.3ad Link aggregation port groups  Supports Port Mirror function for one monitor port for multiple mirroring ports  Supports OAM and EEE LLDP (Energy Efficient Ethernet Link Layer Discovery Protocol  Supports Loop Detection  Security Filtering  Static router port configuration  Dynamic router port learning and aging  Supports Quality of Service (QoS)  Supports per port Input Bandwidth Control  Traffic classification based on IEEE 802.1p/Q priority definition, physical Port, IP DSCP field, ACL definition, VLAN based priority, MAC based priority and SVLAN based priority  Disable learning for each port  Eight Priority Queues per port  Disable learning-table aging for each port  Per queue flow control  Drop unknown DA for each port  Min-Max Scheduling  Strict Priority and Weighted Fair Queue  Broadcast/Multicast/Unknown DA storm control protects system from attack by hackers  Supports IEEE 802.3az Energy Efficient Ethernet (EEE)  Supports Realtek Green Ethernet features (WFQ) to provide minimum bandwidth  One leaky bucket to constrain the average packet rate of each queue   Supports rate limiting (32 shared meters, with 8kbps granulation or packets per second configuration)  Link-On Cable Length Power Saving Supports RFC MIB Counter  MIB-II (RFC 1213)  Link-Down Power Saving  Supports one interrupt output to external CPU for notification  Interface Group MIB (RFC 2863)  Each port supports 3 LED outputs  RMON (RFC 2819)  Management Interface Supports  Ethernet-Like MIB (RFC 3635)    Bridge MIB (RFC 1493)  EEPROM SMI Slave interface  Bridge MIB Extension (RFC 2674)  Media Independent Interface Management (MIIM) Supports Stacking VLAN and Port Isolation with eight Enhanced Filtering Databases Supports IEEE 802.1ad Stacking VLAN  SPI Slave Interface  Supports 32K-byte EEPROM space for configuration  Integrated 8051 microprocessor.  25MHz crystal or 3.3V OSC input  Supports 64 SVLANs  Supports 32 L2/IPv4 Multicast mappings to SVLAN Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 4 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet  LQFP 128-pin package 3. System Applications  5-Port 1000Base-T Switch  5-Port 1000Base-T Router with SGMII/HSGMII and/or MII/RGMII 4. Application Examples 4.1. 5-Port 1000Base-T Switch Figure 1. 5-Port 1000Base-T Switch Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 5 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 4.2. 5-Port 1000Base-T Router with SGMII/HSGMII and/or MII/RGMII Figure 2. 5-Port 1000Base-T Router with SGMII/HSGMII and/or MII/RGMII Note: Extra Interface (Extension GMAC1) in SGMII/HSGMII Mode and/or (Extension GMAC2) in MII/RGMII Mode. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 6 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 5. Block Diagram UTP UTP UTP UTP UTP Giga-PHY PCS P0 GMAC Giga-PHY PCS P1 GMAC Giga-PHY PCS P2 GMAC Giga-PHY PCS P3 GMAC Giga-PHY PCS P4 GMAC High-SGMII (3.125GHz) SGMII (1.25GHz) RGMII/MII SRAM Controller Queue Management Packet Buffer SRAM Linking Lists Extension GMAC 1 SerDes 2K MAC Address Table Lookup Engine Extension Extension Interface 2 GMAC 2 4096 VLAN Table GNIC MAC GNIC 8051 I2C Host PLL Management Interface Control Registers + MIB Counter SCK/SDA MDC/MDIO (MMD) 25MHz Crystal Figure 3. Block Diagram Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 7 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GND AVDDL P0MDIBN P0MDIBP P0MDIAN P0MDIAP AVDDH GND GPIO55/SDA/MDIO GPIO54/SCK/MDC/EN_EEE nRESET GND XTALI XTALO AVDDH GP O52/LAN0LED0/LED_CK/SMI_SEL GP O51/LAN0LED1/LED_DA GP O50/LAN1LED0/EN_PHY GPIO49/LAN1LED1 GPIO46/LAN2LED1 GP O45/DISAUTOLOAD GP O44/LAN2LED0/DIS_8051 GP O43/LAN3LED0/EN_SPIF GP O42/EN_PWRLIGHT GPIO41/LAN3LED1 GPIO40/LAN4LED1 GP O39/LAN4LED0/EEPROM_MOD DVDDL GND DVDDIO HV_SWR HV_SWR 6. Pin Assignments 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LX LX GND_SWR GND_SWR EN_SWR DVDDIO_2 DVDDL GND GPIO12/RG2_RXD3/M2M_RXD3/M2P_TXD3 GPIO11/RG2_RXD2/M2M_RXD2/M2P_TXD2 GPIO10/RG2_RXD1/M2M_RXD1/M2P_TXD1/SPIF_CS GPIO09/RG2_RXD0/M2M_RXD0/M2P_TXD0/SPIF_D1 GPIO08/RG2_RXCTL/M2M_RXDV/M2P_TXEN GPIO07/RG2_RXCLK/M2M_RXCLK/M2P_TXCLK GPIO06/RG2_TXCLK/M2M_TXCLK/M2P_RXCLK GPIO05/RG2_TXCTL/M2M_TXEN/M2P_RXDV/SPIF_D0 GPIO04/RG2_TXD0/M2M_TXD0/M2P_RXD0/SPIF_CLK GPIO03/RG2_TXD1/M2M_TXD1/M2P_RXD1 GPIO02/RG2_TXD2/M2M_TXD2/M2P_RXD2/UART_TX GPIO01/RG2_TXD3/M2M_TXD3/M2P_RXD3/UART_RX GND GND DVDDIO_2 SVDDH SGND HSIN HSIP SVDDL HSOP HSON SGND AVDDH GND P3MDIAP P3MDIAN P3MDIBP P3MDIBN AVDDL P3MDICP P3MDICN P3MDIDP P3MDIDN AVDDH AGND MDIREF AVDDL RTT1 RTT2 AVDDH GND INTERRUPT/GPIO57 DVDDL AVDDH P4MDIAP P4MDIAN GND P4MDIBP P4MDIBN AVDDL P4MDICP P4MDICN P4MDIDP P4MDIDN GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0MDICP P0MDICN GND P0MDIDP P0MDIDN AVDDH P1MDIAP P1MDIAN GND P1MDIBP P1MDIBN AVDDL P1MDICP P1MDICN GND P1MDIDP P1MDIDN PLLVDDL PLLGND AVDDH P2MDIAP P2MDIAN GND P2MDIBP P2MDIBN AVDDL P2MDICP P2MDICN GND P2MDIDP P2MDIDN AVDDH LQFP-128 Package Size 14mm x 14mm Figure 4. Pin Assignments (LQFP-128) 6.1. Package Identification Green package is indicated by the ‘G’ in GXXX (Figure 4). Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 8 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 6.2. Pin Assignments Table Upon Reset: Defined as a short time after the end of a hardware reset. After Reset: Defined as the time after the specified ‘Upon Reset’ time. I: Input Pin AI: Analog Input Pin O: Output Pin AO: Analog Output Pin I/O: Bi-Directional Input/Output Pin AI/O: Analog Bi-Directional Input/Output Pin P: Digital Power Pin AP: Analog Power Pin G: Digital Ground Pin AG: Analog Ground Pin IPU: Input Pin With Pull-Up Resistor; OPU: Output Pin With Pull-Up Resistor; (Typical Value = 75K Ohm) (Typical Value = 75K Ohm) IPD: Input Pin With Pull-Down Resistor; (Typical Value = 75K Ohm) OPD: Output Pin With Pull-Down Resistor; (Typical Value = 75K Ohm) IS: Input Pin With Schmitt Trigger Name GND P3MDIAP P3MDIAN P3MDIBP P3MDIBN AVDDL P3MDICP P3MDICN P3MDIDP P3MDIDN AVDDH AGND MDIREF AVDDL RTT1 RTT2 AVDDH GND GPIO57/INTERRUPT DVDDL Table 1. Pin Assignments Table Pin No. Type Name 1 G AVDDH 2 AI/O P4MDIAP 3 AI/O P4MDIAN 4 AI/O GND 5 AI/O P4MDIBP 6 AP P4MDIBN 7 AI/O AVDDL 8 AI/O P4MDICP 9 AI/O P4MDICN 10 AI/O P4MDIDP 11 AP P4MDIDN 12 AG GND 13 AO AVDDH 14 AP SGND 15 AO HSON 16 AO HSOP 17 AP SVDDL 18 G HSIP 19 I/OPD HSIN 20 P SGND Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 9 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Type AP AI/O AI/O G AI/O AI/O AP AI/O AI/O AI/O AI/O G AP AG AO AO AP AI AI AG Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Name Pin No. SVDDH 41 DVDDIO_2 42 GND 43 GND 44 45 GPIO01/RG2_TXD3/M2M_TXD3/ M2P_RXD3/UART_RX 46 GPIO02/RG2_TXD2/M2M_TXD2/ M2P_RXD2/UART_TX 47 GPIO03/RG2_TXD1/M2M_TXD1/ M2P_RXD1 48 GPIO04/RG2_TXD0/M2M_TXD0/ M2P_RXD0/SPIF_CLK 49 GPIO05/RG2_TXCTL/M2M_TXE N/M2P_RXDV/SPIF_D0 50 GPIO06/RG2_TXCLK/M2M_TXC LK/M2P_RXCLK 51 GPIO07/RG2_RXCLK/M2M_RXC LK/M2P_TXCLK 52 GPIO08/RG2_RXCTL/M2M_RXD V/M2P_TXEN 53 GPIO09/RG2_RXD0/M2M_RXD0/ M2P_TXD0/SPIF_D1 54 GPIO10/RG2_RXD1/M2M_RXD1/ M2P_TXD1/SPIF_CS 55 GPIO11/RG2_RXD2/M2M_RXD2/ M2P_TXD2 56 GPIO12/RG2_RXD3/M2M_RXD3/ M2P_TXD3 GND 57 DVDDL 58 DVDDIO_2 59 EN_SWR 60 GND_SWR 61 GND_SWR 62 LX 63 LX 64 HV_SWR 65 HV_SWR 66 DVDDIO 67 GND 68 DVDDL 69 GP O39/LAN4LED0/ 70 EEPROM_MOD GPIO40/LAN4LED1 71 GPIO41/LAN3LED1 72 GP O42/EN_PWRLIGHT 73 Type AP P G G I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O G P P AI AG AG AO AO AP AP P G P I/OPU I/OPU I/OPU I/OPU Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller Name GP O43/LAN3LED0/EN_SPIF GP O44/LAN2LED0/DIS_8051 GP O45/DISAUTOLOAD GPIO46/LAN2LED1 GPIO49/LAN1LED1 GP O50/LAN1LED0/EN_PHY GP O51/LAN0LED1/LED_DA GP O52/LAN0LED0/LED_CK/ SMI_SEL AVDDH XTALO XTALI GND nRESET GPIO54/SCK/MDC/EN_EEE GPIO55/SDA/MDIO GND AVDDH P0MDIAP P0MDIAN P0MDIBP P0MDIBN AVDDL GND P0MDICP P0MDICN GND P0MDIDP P0MDIDN AVDDH P1MDIAP P1MDIAN GND P1MDIBP P1MDIBN AVDDL P1MDICP P1MDICN GND P1MDIDP P1MDIDN PLLVDDL PLLGND AVDDH 10 Pin No. 74 75 76 77 78 79 80 81 Type I/OPU I/OPU I/OPU I/OPU I/OPU I/OPU I/OPU I/OPU 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 AP AO AI G IPU I/O I/O G AP AI/O AI/O AI/O AI/O AP G AI/O AI/O G AI/O AI/O AP AI/O AI/O G AI/O AI/O AP AI/O AI/O G AI/O AI/O AP AG AP Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Name P2MDIAP P2MDIAN GND P2MDIBP P2MDIBN AVDDL Pin No. 117 118 119 120 121 122 Type AI/O AI/O G AI/O AI/O AP Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller Name P2MDICP P2MDICN GND P2MDIDP P2MDIDN AVDDH 11 Pin No. 123 124 125 126 127 128 Type AI/O AI/O G AI/O AI/O AP Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7. Pin Descriptions 7.1. Media Dependent Interface Pins Pin Name P0MDIAP/N P0MDIBP/N P0MDICP/N P0MDIDP/N P1MDIAP/N P1MDIBP/N P1MDICP/N P1MDIDP/N P2MDIAP/N P2MDIBP/N P2MDICP/N P2MDIDP/N P3MDIAP/N P3MDIBP/N P3MDICP/N P3MDIDP/N P4MDIAP/N P4MDIBP/N P4MDICP/N P4MDIDP/N Table 2. Media Dependent Interface Pins Drive Pin No. Type Description (mA) 91 AI/O 10 Port 0 Media Dependent Interface A~D. 92 For 1000Base-T operation, differential data from the media is transmitted and received on all four pairs. For 100Base-TX and 10Base-T operation, 93 only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs 94 MDIAP/N and MDIBP/N. 97 98 100 101 103 104 106 107 109 110 112 113 117 118 120 121 123 124 126 127 2 3 4 5 7 8 9 10 22 23 25 26 28 29 30 31 Each of the differential pairs has an internal 100-ohm termination resistor. AI/O 10 Port 1 Media Dependent Interface A~D. For 1000Base-T operation, differential data from the media is transmitted and received on all four pairs. For 100Base-TX and 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N and MDIBP/N. Each of the differential pairs has an internal 100-ohm termination resistor. AI/O 10 Port 2 Media Dependent Interface A~D. For 1000Base-T operation, differential data from the media is transmitted and received on all four pairs. For 100Base-TX and 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N and MDIBP/N. Each of the differential pairs has an internal 100-ohm termination resistor. AI/O 10 Port 3 Media Dependent Interface A~D. For 1000Base-T operation, differential data from the media is transmitted and received on all four pairs. For 100Base-TX and 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N and MDIBP/N. Each of the differential pairs has an internal 100-ohm termination resistor. AI/O 10 Port 4 Media Dependent Interface A~D. For 1000Base-T operation, differential data from the media is transmitted and received on all four pairs. For 100Base-TX and 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N and MDIBP/N. Each of the differential pairs has an internal 100-ohm termination resistor. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 12 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7.2. High Speed Serial Interface Pins Pin Name Pin No. Type HSOP/N 36 35 38 39 HSIP/N 7.3. AO AI Drive Description (mA) 10 High Speed Serial Output Pins: 1.25GHz/3.125GHz Differential serial interface to transmit data. Keep floating when unused. 10 High Speed Serial Input Pins: 1.25GHz/3.125GHz Differential serial interface to receive data. Keep floating when unused. General Purpose Interfaces The RTL8367S supports multi-function General Purpose Interfaces that can be configured as MII/RGMII mode for extension GMAC interfaces. The RTL8367S supports one digital extension interfaces (Extension GMAC2) for connecting with an external PHY, MAC, or CPU in specific applications. This extension interface supports RGMII, MII MAC mode, or MII PHY mode via register configuration. Table 3. General Purpose Interfaces Pins Pin No. GPIO 19 45 46 47 48 49 50 51 52 53 54 55 56 70 71 72 73 74 75 76 77 78 79 GPIO57 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GP O39 GPIO40 GPIO41 GP O42 GP O43 GP O44 GP O45 GPIO46 GPIO49 GP O50 80 GP O51 81 GP O52 RGMII RG2_TXD3 RG2_TXD2 RG2_TXD1 RG2_TXD0 RG2_TXCTL RG2_TXCLK RG2_RXCLK RG2_RXCTL RG2_RXD0 RG2_RXD1 RG2_RXD2 RG2_RXD3 MII MAC Mode M2M_TXD3 M2M_TXD2 M2M_TXD1 M2M_TXD0 M2M_TXEN M2M_TXCLK M2M_RXCLK M2M_RXDV M2M_RXD0 M2M_RXD1 M2M_RXD2 M2M_RXD3 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller MII PHY Mode M2P_RXD3 M2P_RXD2 M2P_RXD1 M2P_RXD0 M2P_RXDV M2P_RXCLK M2P_TXCLK M2P_TXEN M2P_TXD0 M2P_TXD1 M2P_TXD2 M2P_TXD3 Other function INTERRUPT UART_RX UART_TX SPIF_CLK SPIF_D0 SPIF_D1 SPIF_CS LAN4LED0 LAN4LED1 LAN3LED1 LAN3LED0 LAN2LED0 LAN2LED1 LAN1LED1 LAN1LED0 LAN0LED1/ LED_DA LAN0LED0/ LED_CK 13 Configuration Strapping EEPROM_MOD EN_PWRLIGHT EN_SPIF DIS_8051 DISAUTOLOAD EN_PHY SMI_SEL Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Pin No. GPIO 87 GPIO54 88 GPIO55 RGMII MII MAC Mode Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller MII PHY Mode Other function SCK/ MDC SDA/ MDIO 14 Configuration Strapping EN_EEE Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7.3.1. RGMII Pins The Extension GMAC2 of the RTL8367S supports RGMII interface to connect with an external MAC or PHY device when register configuration is set to RGMII mode interface. Pin Name RG2_TXD3 RG2_TXD2 RG2_TXD1 RG2_TXD0 RG2_TXCTL RG2_TXCLK RG2_RXCLK RG2_RXCTL RG2_RXD0 RG2_RXD1 RG2_RXD2 RG2_RXD3 Table 4. Extension GMAC2 RGMII Pins Drive Pin No. Type Description (mA) 45 O RG2_TXD[3:0] Extension GMAC2 RGMII Transmit Data Output. 46 Transmitted data is sent synchronously to RG2_TXCLK. 47 48 49 O RG2_TXCTL Extension GMAC2 RGMII Transmit Control signal Output. The RG2_TXCTL indicates TX_EN at the rising edge of RG2_TXCLK, and TX_ER at the falling edge of RG2_TXCLK. At the RG2_TXCLK falling edge, RG2_TXCTL= TX_EN (XOR) TX_ER. 50 O RG2_TXCLK Extension GMAC2 RGMII Transmit Clock Output. RG2_TXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and 2.5MHz @ 10Mbps. Used for RG2_TXD[3:0] and RG2_TXCTL synchronization at RG2_TXCLK on both rising and falling edges. 51 I RG2_RXCLK Extension GMAC2 RGMII Receive Clock Input. RG2_RXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and 2.5MHz @ 10Mbps. Used for RG2_RXD[3:0] and RG2_RXCTL synchronization at both RG2_RXCLK rising and falling edges. This pin must be pulled low with a 1K ohm resistor when not used. 52 I RG2_RXCTL Extension GMAC2 RGMII Receive Control signal input. The RG2_RXCTL indicates RX_DV at the rising of RG2_RXCLK and RX_ER at the falling edge of RG2_RXCLK. At RG2_RXCLK falling edge, RG2_RXCTL= RX_DV (XOR) RX_ER. This pin must be pulled low with a 1K ohm resistor when not used. 53 I RG2_RXD[3:0] Extension GMAC2 RGMII Receive Data Input. 54 Received data is received synchronously by RG2_RXCLK. 55 These pins must be pulled low with a 1K ohm resistor when not used. 56 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 15 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7.3.2. MII Pins The Extension GMAC2 of the RTL8367S supports MII interface to connect with an external MAC or PHY device when register configuration is set to MII mode interface. This MII interface can be configured as MII MAC mode or MII PHY mode by register. Pin Name M2M_TXD3/ M2P_RXD3 M2M_TXD2/ M2P_RXD2 M2M_TXD1/ M2P_RXD1 M2M_TXD0/ M2P_RXD0 M2M_TXEN/ M2P_RXDV Table 5. Extension GMAC2 MII Pins (MII MAC Mode or MII PHY Mode) Drive Pin No. Type Description (mA) 45 O M2M_TXD[3:0] Extension GMAC2 MII MAC Mode Transmit Data Output. Transmitted data is sent synchronously at the rising edge of 46 M2M_TXCLK. M2P_RXD[3:0] Extension GMAC2 MII PHY Mode Receive Data 47 Output. Received data is received synchronously at the rising edge of 48 M2P_RXCLK. 49 O - M2M_TXCLK/ M2P_RXCLK 50 I/O - M2M_RXCLK/ M2P_TXCLK 51 I/O - M2M_TXEN Extension GMAC2 MII MAC Mode Transmit Data Enable Output. Transmit enable that is sent synchronously at the rising edge of M2M_TXCLK. M2P_RXDV Extension GMAC2 MII PHY Mode Receive Data Valid Output. Receive Data Valid signal that is sent synchronously at the rising edge of M2P_RXCLK. M2M_TXCLK Extension GMAC2 MII MAC Mode Transmit Clock Input. In MII 100Mbps, M2M_TXCLK is 25MHz Clock Input. In MII 10Mbps, M2M_TXCLK is 2.5MHz Clock Input. Used to synchronize M2M_TXD[3:0] and M2M_TXEN. M2P_RXCLK Extension GMAC2 MII PHY Mode Receive Clock Output. In MII 100Mbps, M2P_RXCLK is 25MHz Clock Output. In MII 10Mbps, M2P_RXCLK is 2.5MHz Clock Output. Used to synchronize M2P_RXD[3:0] and M2P_RXDV. This pin must be pulled low with a 1K ohm resistor when not used. M2M_RXCLK Extension GMAC2 MII MAC Mode Receive Clock Input. In MII 100Mbps, M2M_RXCLK is 25MHz Clock Input. In MII 10Mbps, M2M_RXCLK is 2.5MHz Clock Input. Used to synchronize M2M_RXD[3:0], M2M_RXDV, and M2M_CRS. M2P_TXCLK Extension GMAC2 MII PHY Mode Transmit Clock Output. In MII 100Mbps, M2P_TXCLK is 25MHz Clock Output. In MII 10Mbps, M2P_TXCLK is 2.5MHz Clock Output. Used to synchronize M2P_TXD[3:0] and M2P_TXEN. This pin must be pulled low with a 1K ohm resistor when not used. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 16 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Pin Name Pin No. Type M2M_RXDV/ M2P_TXEN 52 I M2M_RXD0/ M2P_TXD0 M2M_RXD1/ M2P_TXD1 M2M_RXD2/ M2P_TXD2 M2M_RXD3/ M2P_TXD3 53 I 54 55 56 Drive Description (mA) M2M_RXDV Extension GMAC2 MII MAC Mode Receive Data Valid Input. Receive Data Valid sent synchronously at the rising edge of M2M_RXCLK. M2P_TXEN Extension GMAC2 MII PHY Mode Transmit Data Enable Input. Transmit Data Enable is received synchronously at the rising edge of M2P_TXCLK. This pin must be pulled low with a 1K ohm resistor when not used. M2M_RXD[3:0] Extension GMAC2 MII MAC Mode Receive Data Input. Received data that is received synchronously at the rising edge of M2M_RXCLK. M2P_TXD[3:0] Extension GMAC2 MII PHY Mode Transmit Data Input. Transmitted data is received synchronously at the rising edge of M2P_TXCLK. These pins must be pulled low with a 1K ohm resistor when not used. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 17 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7.4. LED Pins The RTL8367S LED Pins can be configured to parallel mode LED or serial mode LED interface via Register configuration. LED0 and LED1 of Port n indicates information that can be defined via register or EEPROM. In parallel mode LED interface, when the LED pin is pulled low, the LED output polarity will be high active. When the LED pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 39 for more details. Pin Name Pin No. Type LAN4LED1 71 I/OPU LAN4LED0/ EEPROM_MOD 70 I/OPU LAN3LED1 72 I/OPU LAN3LED0/ EN_SPIF 74 I/OPU LAN2LED1 77 I/OPU LAN2LED0/ DIS_8051 75 I/OPU LAN1LED1 78 I/OPU LAN1LED0/ EN_PHY 79 I/OPU LAN0LED1/ LED_DA 80 I/OPU LAN0LED0/ LED_CK/ SMI_SEL 81 I/OPU Table 6. LED Pins Drive Description (mA) LAN 4 LED 1 Output Signal. LAN4LED1 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 4 LED 0 Output Signal. LAN4LED0 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 3 LED 1 Output Signal. LAN3LED1 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 3 LED 0 Output Signal. LAN3LED0 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 2 LED 1 Output Signal. LAN2LED1 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 2 LED 0 Output Signal. LAN2LED0 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 1 LED 1 Output Signal. LAN1LED1 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 1 LED 0 Output Signal. LAN1LED0 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 0 LED 1 Output Signal. LAN0LED1 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. LAN 0 LED 0 Output Signal. LAN0LED0 indicates information is defined by register or EEPROM. See section 9.19 LED Indicators, page 39 for more details. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 18 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7.5. Configuration Strapping Pins Pin Name EN_SWR EEPROM_MOD/ LAN4LED0 EN_PWRLIGHT EN_SPIF/ LAN3LED0 DIS_8051/ LAN2LED0 Table 7. Configuration Strapping Pins Pin No. Type Description 60 AI Enable Internal Switching Regulator. Pull Up: Enable Internal Switching Regulator Pull Down: Disable Internal Switching Regulator Note: This pin must be pulled high or low via an external 1k ohm resistor when normal operation. 70 I/OPU EEPROM Mode Selection. Pull Up: EEPROM 24Cxx Size greater than 16Kbits (24C32~24C256) Pull Down: EEPROM 24Cxx Size less than or equal to 16Kbit (24C02~24C16). Note: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. When this pin is pulled low, the LED output polarity will be high active. When this pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 39 for more details. 73 I/OPU Enable Power on Light. Pull Up: Enable Power on Light Pull Down: Disable Power on Light Note: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. When this pin is pulled low, the LED output polarity will be high active. When this pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 39 for more details. 74 I/OPU Enable SPI FLASH Interface. Pull Up: Enable FLASH interface Pull Down: Disable FLASH interface Note 1: The strapping pin DISAUTOLOAD, DIS_8051, and EN_SPIF are for power on or reset initial stage configuration. Refer to Table 8 Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF), page 20 for details. Note 2: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. 75 I/OPU Disable Embedded 8051. Pull Up: Disable embedded 8051 Pull Down: Enable embedded 8051 Note 1: The strapping pin DISAUTOLOAD, DIS_8051, and EN_SPIF are for power on or reset initial stage configuration. Refer to Table 8 Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF), page 20 for details. Note 2: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. When this pin is pulled low, the LED output polarity will be high active. When this pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicator, page 39 for more details. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 19 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Pin Name DISAUTOLOAD EN_PHY/ LAN1LED0 SMI_SEL/ LED_CK/ LAN0LED0 EN_EEE/ GPIO54/ SCK/ MDC 7.5.1. Pin No. Type Description 76 I/OPU Disable EEPROM/FLASH Autoload. Pull Up: Disable EEPROM/FLASH autoload Pull Down: Enable EEPROM/FLASH autoload Note 1: The strapping pin DISAUTOLOAD, DIS_8051, and EN_SPIF are for power on or reset initial stage configuration. Refer to Table 8 Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF), page 20 for details. Note 2: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. When this pin is pulled low, the LED output polarity will be high active. When this pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 39 for more details. 79 I/OPU Enable Embedded PHY. Pull Up: Enable embedded PHY Pull Down: Disable embedded PHY Note: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. When this pin is pulled low, the LED output polarity will be high active. When this pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 39 for more details. 81 I/OPU EEPROM SMI/MII Management Interface Selection. Pull Up: EEPROM SMI interface Pull Down: MII Management interface Note: This pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. When this pin is pulled low, the LED output polarity will be high active. When this pin is pulled high, the LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 39 for more details. 87 I/O Enable IEEE 802.3az Energy Efficient Ethernet (EEE). Pull Up: Enable Energy Efficient Ethernet (EEE) function Pull Down: Disable Energy Efficient Ethernet (EEE) function Note: This pin must be pulled high or low via an external 4.7k ohm resistor upon power on or reset. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF) Table 8. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF) DISAUTOLOAD 0 1 DIS_8051 0 1 Irrelevant Initial Stage (Power On or Reset) Loading Data EN_SPIF 0 1 Must be 0 X From To EEPROM SPI_FLASH EEPROM Do Nothing Embedded 8051 Instruction Memory Embedded 8051 Instruction Memory Register Do Nothing Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 20 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 7.6. Management Interface Pins Pin Name INTERRUPT UART_RX UART_TX SPIF_CLK SPIF_D0 SPIF_D1 SPIF_CS SCK/ MDC SDA/ MDIO 7.7. Pin No. 19 45 46 48 49 53 54 87 88 Table 9. Management Interface Pins Type Description OPD Interrupt output when Interrupt even occurs. Active High by pull-down to GND via a 1K resister. Active Low by pull-up to DVDDIO via a 4.7K resister. I Universal Asynchronous Receiver Pin. O Universal Asynchronous Transmitter Pin. O Serial Clock Output (FLASH Interface). I/O Serial Data I/O 0 (FLASH Interface). I/O Serial Data I/O 1 (FLASH Interface). O Chip Selection (FLASH Interface). I/O EEPROM SMI Interface Clock/MII Management Interface (MMD) Clock (selected via the hardware strapping pin 81, SMI_SEL). I/O EEPROM SMI Interface Data/MII Management Interface (MMD) Data (selected via the hardware strapping pin 81, SMI_SEL). Miscellaneous Pins Pin No. 83 Type AO XTALI 84 AI MDIREF 13 AO nRESET 86 IPU 63, 64 AO 45 I/O Table 10. Miscellaneous Pins Description 25MHz Crystal Clock Output Pin. 25MHz +/-50ppm tolerance crystal output. When using a crystal, series connect a 150 ohm resistor between XTALO and crystal, connect a loading capacitor between crystal pin and ground. 25MHz Crystal Clock Input and Feedback Pin. 25MHz +/-50ppm tolerance crystal reference or oscillator input. When using a crystal, connect a loading capacitor between crystal pin and ground. When either using an oscillator or driving an external 25MHz clock from another device, XTALO should be kept floating. The maximum XTALI input voltage is 3.3V. Reference Resistor. A 2.49K ohm (1%) resistor must be connected between MDIREF and GND. System Reset Input Pin. When low active will reset the RTL8367S. Internal Switching Regulator LX output. Connect to an inductor 2.2uH and capacitor 10uF to generate 1.1V power. General Purpose Input/Output Interface IO01. 46 I/O General Purpose Input/Output Interface IO02. 47 48 I/O I/O General Purpose Input/Output Interface IO03. General Purpose Input/Output Interface IO04. 49 I/O General Purpose Input/Output Interface IO05. Pin Name XTALO LX GPIO01/ UART_RX GPIO02/ UART_TX GPIO03 GPIO04/ SPIF_CLK GPIO05/ SPIF_D0 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 21 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Pin Name GPIO06 GPIO07 GPIO08 GPIO09/ SPIF_D1 GPIO10/ SPIF_CS GPIO11 GPIO12 GP O39/ LAN4LED0/ EEPROM_MOD GPIO40/ LAN4LED1 GPIO41/ LAN3LED1 GP O42/ EN_PWRLIGHT GP O43/ LAN3LED0/ EN_SPIF GP O44/ LAN2LED0/ DIS_8051 GP O45/ DISAUTOLOAD GPIO46/ LAN2LED1 GPIO49/ LAN1LED1 GP O50/ LAN1LED0/ EN_PHY GP O51/ LAN0LED1/ LED_DA GP O52/ LAN0LED0/ LED_CK/ SMI_SEL GPIO54/ SCK/ MDC/ EN_EEE GPIO55/ SDA/ MDIO Pin No. 50 51 52 53 Type I/O I/O I/O I/O Description General Purpose Input/Output Interface IO06. General Purpose Input/Output Interface IO07. General Purpose Input/Output Interface IO08. General Purpose Input/Output Interface IO09. 54 I/O General Purpose Input/Output Interface IO10. 55 56 70 I/O I/O I/OPU General Purpose Input/Output Interface IO11. General Purpose Input/Output Interface IO12. General Purpose Output Interface O39. 71 I/OPU General Purpose Input/Output Interface IO40. 72 I/OPU General Purpose Input/Output Interface IO41. 73 I/OPU General Purpose Output Interface O42. 74 I/OPU General Purpose Output Interface O43. 75 I/OPU General Purpose Output Interface O44. 76 I/OPU General Purpose Output Interface O45. 77 I/OPU General Purpose Input/Output Interface IO46. 78 I/OPU General Purpose Input/Output Interface IO49. 79 I/OPU General Purpose Output Interface O50. 80 I/OPU General Purpose Output Interface O51. 81 I/OPU General Purpose Output Interface O52. 87 I/O General Purpose Input/Output Interface IO54. 88 I/O General Purpose Input/Output Interface IO55. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 22 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Pin Name GPIO57/ INTERRUPT 7.8. Type I/OPD Description General Purpose Input/Output Interface IO57. Type AO AO Table 11. Test Pins Description Reserved for Internal Use. Must be left floating. Reserved for Internal Use. Must be left floating. Test Pins Pin Name RTT1 RTT2 7.9. Pin No. 19 Pin No. 15 16 Power and GND Pins Pin Name DVDDIO DVDDIO_2 DVDDL AVDDH SVDDH HV_SWR AVDDL SVDDL PLLVDDL GND AGND SGND GND_SWR PLLGND Table 12. Power and GND Pins Pin No. Type Description 67 P Digital I/O High Voltage Power for LED, Management Interface, and nRESET. 42, 59 P Digital I/O High Voltage Power for Extension Port 2 General Purpose Interface. 20, 58, 69 P Digital Low Voltage Power. AP Analog High Voltage Power and INTERRUPT. 11, 17, 21, 33, 82, 90, 102, 116, 128 41 AP Ser-Des High Voltage Power. 65, 66 AP Internal Switching Regulator Power, Connect to a bulk capacitor 10uF to GND. AP Analog Low Voltage Power. 6, 14, 27, 95, 108, 122 37 AP Ser-Des Low Voltage Power. 114 AP PLL Low Voltage Power. G GND. 1, 18, 24, 32, 43, 44, 57, 68, 85, 89, 96, 99, 105, 111, 119, 125 12 AG Analog GND. 34, 40 AG Ser-Des GND. 61, 62 AG Internal Switching Regulator GND. 115 AG PLL GND. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 23 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 8. Physical Layer Functional Overview 8.1. MDI Interface The RTL8367S embeds five 10/100/1000M Ethernet PHYs in one chip. Each port uses a single common MDI interface to support 1000Base-T, 100Base-TX, and 10Base-T. This interface consists of four signal pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at the same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For 10/100 links and during auto-negotiation, only pairs A and B are used. 8.2. 1000Base-T Transmit Function The 1000Base-TX transmit function performs 8B/10B coding, scrambling, and 4D-PAM5 encoding. These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are transmitted onto 4-pair CAT5 cable at 125MBaud/s through a D/A converter. 8.3. 1000Base-T Receive Function Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the transmitted signal from the input signal for effective reduction of near-end echo. The received signal is then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the packet buffer manager. 8.4. 100Base-TX Transmit Function The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such that EMI effects can be reduced significantly. The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which also reduces EMI emissions. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 24 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 8.5. 100Base-TX Receive Function The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL circuit. Finally, the converted parallel data is fed into the MAC. 8.6. 10Base-T Transmit Function The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external filter. 8.7. 10Base-T Receive Function The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects the signal level is above squelch level. 8.8. Auto-Negotiation for UTP The RTL8367S obtains the states of duplex, speed, and flow control ability for each port in UTP mode through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During autonegotiation, each port advertises its ability to its link partner and compares its ability with advertisements received from its link partner. By default, the RTL8367S advertises full capabilities (1000Full, 100Full, 100Half, 10Full, 10Half) together with flow control ability. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 25 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 8.9. Crossover Detection and Auto Correction The RTL8367S automatically determines whether or not it needs to crossover between pairs (see Table 13) so that an external crossover cable is not required. When connecting to another device that does not perform MDI crossover, when necessary, the RTL8367S automatically switches its pin pairs to communicate with the remote device. When connecting to another device that does have MDI crossover capability, an algorithm determines which end performs the crossover function. The crossover detection and auto correction function can be disabled via register configuration. The pin mapping in MDI and MDI Crossover mode is given below. Pairs A B C D Table 13. Media Dependent Interface Pin Mapping MDI MDI Crossover 1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX A TX TX B RX B RX RX A TX C Unused Unused D Unused D Unused Unused C Unused 10Base-T RX TX Unused Unused 8.10. Polarity Correction The RTL8367S automatically corrects polarity errors on the receiver pairs in 1000Base-T and 10Base-T modes. In 100Base-TX mode, the polarity is irrelevant. In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes unlocked only when the receiver loses lock. In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The polarity becomes unlocked when the link is down. RTL8367S Link Partner + RX _ + _ TX + TX _ _ + + _ RX Figure 5. Conceptual Example of Polarity Correction Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 26 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9. General Function Description 9.1. 9.1.1. Reset Hardware Reset In a power-on reset, an internal power-on reset pulse is generated and the RTL8367S will start the reset initialization procedures. These are:      Determine various default settings via the hardware strap pins at the end of the nRESET signal Autoload the configuration from EEPROM if EEPROM is detected Complete the embedded SRAM BIST process Initialize the packet buffer descriptor allocation Initialize the internal registers and prepare them to be accessed by the external CPU 9.1.2. Software Reset The RTL8367S supports two software resets; a chip reset and a soft reset. 9.1.2.1 CHIP_RESET When CHIP_RESET is set to 0b1 (write and self-clear), the chip will take the following steps: 1. Download configuration from strap pin and EEPROM 2. Start embedded SRAM BIST (Built-In Self Test) 3. Clear all the Lookup and VLAN tables 4. Reset all registers to default values 5. Restart the auto-negotiation process 9.1.2.2 SOFT_RESET When SOFT_RESET is set to 0b1 (write and self-clear), the chip will take the following steps: 1. Clear the FIFO and re-start the packet buffer link list 2. Restart the auto-negotiation process 9.2. IEEE 802.3x Full Duplex Flow Control The RTL8367S supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be decided in two ways:   When Auto-Negotiation is enabled, flow control depends on the result of NWay When Auto-Negotiation is disabled, flow control depends on register definition Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 27 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.3. Half Duplex Flow Control In half duplex mode, the CSMA/CD media access method is the means by which two or more stations share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If the message collides with that of another station, then each transmitting station intentionally transmits for an additional predefined period to ensure propagation of the collision throughout the system. The station remains silent for a random amount of time (backoff) before attempting to transmit again. When a transmission attempt has terminated due to a collision, it is retried until it is successful. The scheduling of the retransmissions is determined by a controlled randomization process called “Truncated Binary Exponential Backoff”. At the end of enforcing a collision (jamming), the switch delays before attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer ‘r’ in the range: 0 ≤ r < 2k where: k = min (n, backoffLimit). The backoffLimit for the RTL8367S is 9. The half duplex back-off algorithm in the RTL8367S does not have the maximum retry count limitation of 16 (as defined in IEEE 802.3). This means packets in the switch will not be dropped if the back-off retry count is over 16. 9.3.1. Back-Pressure Mode In Back-Pressure mode, the RTL8367S sends a 4-byte jam pattern (data=0xAA) to collide with incoming packets when congestion control is activated. The Jam pattern collides at the fourth byte counted from the preamble. The RTL8367S supports 48PASS1, which receives one packet after 48 consecutive jam collisions (data collisions are not included in the 48). Enable this function to prevent port partition after 63 consecutive collisions (data collisions + consecutive jam collisions). Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 28 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.4. Search and Learning Search When a packet is received, the RTL8367S uses the destination MAC address, Filtering Identifier (FID) and Enhanced Filtering Identifier (EFID) to search the 2K-entry look-up table. The 48-bit MAC address, 4-bit FID and 3-bit EFID use a hash algorithm, to calculate an 11-bit index value. The RTL8367S uses the index to compare the packet MAC address with the entries (MAC addresses) in the look-up table. This is the ‘Address Search’. If the destination MAC address is not found, the switch will broadcast the packet according to VLAN configuration. Learning The RTL8367S uses the source MAC address, FID, and EFID of the incoming packet to hash into a 9-bit index. It then compares the source MAC address with the data (MAC addresses) in this index. If there is a match with one of the entries, the RTL8367S will update the entry with new information. If there is no match and the 2K entries are not all occupied by other MAC addresses, the RTL8367S will record the source MAC address and ingress port number into an empty entry. This process is called ‘Learning’. Address aging is used to keep the contents of the address table correct in a dynamic network topology. The look-up engine will update the time stamp information of an entry whenever the corresponding source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not refreshed by the address learning process during the aging time period. The aging time of the RTL8367S is between 200 and 400 seconds (typical is 300 seconds). 9.5. SVL and IVL/SVL The RTL8367S supports a 16-group Filtering Identifier (FID) for L2 search and learning. In default operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning (SVL). If VLAN entries are configured to different FIDs, then the same source MAC address with multiple FIDs can be learned into different look-up table entries. This is called Independent VLAN Learning and Shared VLAN Learning (IVL/SVL). 9.6. Illegal Frame Filtering Illegal frames such as CRC error packets, runt packets (length maximum length) will be discarded by the RTL8367S. The maximum packet length may be set from 1518 bytes to 16K bytes. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 29 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.7. IEEE 802.3 Reserved Group Addresses Filtering Control The RTL8367S supports the ability to drop/forward IEEE 802.3 specified reserved group MAC addresses: 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01 (802.3x Pause) and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 14 shows the Reserved Multicast Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. Table 14. Reserved Multicast Address Configuration Table Assignment Value Bridge Group Address 01-80-C2-00-00-00 IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation 01-80-C2-00-00-01 IEEE Std 802.3ad Slow Protocols-Multicast Address 01-80-C2-00-00-02 IEEE Std 802.1X PAE Address 01-80-C2-00-00-03 Provider Bridge Group Address 01-80-C2-00-00-08 Undefined 802.1 Address 01-80-C2-00-00-04 ~ 01-80-C2-00-00-07 & 01-80-C2-00-00-09 ~ 01-80-C2-00-00-0C & 01-80-C2-00-00-0F Provider Bridge MVRP Address 01-80-C2-00-00-0D IEEE Std 802.1AB Link Layer Discovery Protocol Address 01-80-C2-00-00-0E All LANs Bridge Management Group Address 01-80-C2-00-00-10 Load Server Generic Address Loadable Device Generic Address Undefined 802.1 Address 01-80-C2-00-00-11 01-80-C2-00-00-12 01-80-C2-00-00-13 ~ 01-80-C2-00-00-17 & 01-80-C2-00-00-19 & 01-80-C2-00-00-1B ~ 01-80-C2-00-00-1F 01-80-C2-00-00-18 01-80-C2-00-00-1a 01-80-C2-00-00-20 01-80-C2-00-00-21 01-80-C2-00-00-22 | 01-80-C2-00-00-2F 01-00-0C-CC-CC-CC 01-00-0C-CC-CC-CD (01:80:c2:00:00:0e or 01:80:c2:00:00:03 or 01:80:c2:00:00:00) && ethertype = 0x88CC Generic Address for All Manager Stations Generic Address for All Agent Stations GMRP Address GVRP Address Undefined GARP Address CDP(Cisco Discovery Protocol) CSSTP(Cisco Shared Spanning Tree Protocol) LLDP Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 30 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.8. Broadcast/Multicast/Unknown DA Storm Control The RTL8367S enables or disables per-port broadcast/multicast/unknown DA storm control by setting registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets exceeds a reference rate (number of Kbps per second or number of packets per second), all other broadcast/multicast/unknown DA packets will be dropped. The reference rate is set via register configuration. 9.9. Port Security Function The RTL8367S supports three types of security function to prevent malicious attacks:    Per-port enable/disable SA auto-learning for an ingress packet Per-port enable/disable look-up table aging update function for an ingress packet Per-port enable/disable drop all unknown DA packets 9.10. MIB Counters The RTL8367S supports a set of counters to support management functions.       MIB-II (RFC 1213) Ethernet-Like MIB (RFC 3635) Interface Group MIB (RFC 2863) RMON (RFC 2819) Bridge MIB (RFC 1493) Bridge MIB Extension (RFC 2674) 9.11. Port Mirroring The RTL8367S supports one set of port mirroring functions for all ports. The TX, or RX, or both TX/RX packets from multiple mirrored port can be mirrored to one monitor port. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 31 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.12. VLAN Function The RTL8367S supports 4K VLAN groups. These can be configured as port-based VLANs, IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering options provide flexible VLAN configuration: Ingress Filtering  The acceptable frame type of the ingress process can be set to ‘Admit All’, ‘Admit only Untagged’ or ‘Admit only Tagged’  ‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set Egress Filtering  ‘Forward’ or ‘Discard’ Leaky VLAN frames between different VLAN domains  ‘Forward’ or ‘Discard’ Multicast VLAN frames between different VLAN domains The VLAN tag can be inserted or removed at the output port. The RTL8367S will insert a Port VID (PVID) for untagged frames, or remove the tag from tagged frames. The RTL8367S also supports a special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and Gateway applications. In router applications, the router may want to know which input port this packet came from. The RTL8367S supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress. Using this function, VID information carried in the VLAN tag will be changed to PVID. The RTL8367S also provides an option to admit VLAN tagged packets with a specific PVID only. If this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID. 9.12.1. Port-Based VLAN This default configuration of the VLAN function can be modified via an attached serial EEPROM or EEPROM SMI Slave interface. The 4K-entry VLAN Table designed into the RTL8367S provides full flexibility for users to configure the input ports to associate with different VLAN groups. Each input port can join with more than one VLAN group. Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to determine their VLAN association. All the packets received on a given input port will be forwarded to this port’s VLAN members. 9.12.2. IEEE 802.1Q Tag-Based VLAN The RTL8367S supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In 802.1Q VLAN mapping, the RTL8367S uses a 12-bit explicit identifier in the VLAN tag to associate received packets with a VLAN. The RTL8367S compares the explicit identifier in the VLAN tag with the 4K VLAN Table to determine the VLAN association of this packet, and then forwards this packet to the member set of that VLAN. Two VIDs are reserved for special purposes. One of them is all 1’s, which is reserved and currently unused. The other is all 0’s, which indicates a priority tag. A priority-tagged frame should be treated as an untagged frame. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 32 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet When ‘802.1Q tag aware VLAN’ is enabled, the RTL8367S performs 802.1Q tag-based VLAN mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q tag aware VLAN’ is disabled, the RTL8367S performs only port-based VLAN mapping both on non-tagged and tagged frames. The processing flow when ‘802.1Q tag aware VLAN’ is enabled is illustrated below. Two VLAN ingress filtering functions are supported in registers by the RTL8367S. One is the ‘VLAN tag admit control, which provides the ability to receive VLAN-tagged frames only. Untagged or priority tagged (VID=0) frames will be dropped. The other is ‘VLAN member set ingress filtering’, which will drop frames if the ingress port is not in the member set. 9.12.3. Protocol-Based VLAN The RTL8367S supports a 4-group Protocol-based VLAN configuration. The packet format can be RFC 1042, LLC, or Ethernet, as shown in Figure 6. There are 4 configuration tables to assign the frame type and corresponding field value. Taking IP packet configuration as an example, the user can configure the frame type to be ‘Ethernet’, and value to be ‘0x0800’. Each table will index to one of the entries in the 4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the VLAN member configuration of the indexed entry to forward the packets. Figure 6. Protocol-Based VLAN Frame Format and Flow Chart 9.12.4. Port VID In a router application, the router may want to know which input port this packet came from. The RTL8367S supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged or priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control is enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the RTL8367S will drop non-tagged packets and packets with an incorrect PVID. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 33 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.13. QoS Function The RTL8367S supports 8 priority queues and input bandwidth control. Packet priority selection can depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and ACLbased priority. When multiple priorities are enabled in the RTL8367S, the packet’s priority will be assigned based on the priority selection table. Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as Strict Priority (SP) or Weighted Fair Queue (WFQ) for packet scheduling algorithm. 9.13.1. Input Bandwidth Control Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps). 9.13.2. Priority Assignment Priority assignment specifies the priority of a received packet according to various rules. The RTL8367S can recognize the QoS priority information of incoming packets to give a different egress service priority. The RTL8367S identifies the priority of packets based on several types of QoS priority information:        Port-based priority 802.1p/Q-based priority IPv4/IPv6 DSCP-based priority ACL-based priority VLAN-based priority MAC-based priority SVLAN-based priority 9.13.3. Priority Queue Scheduling The RTL8367S supports MAX-MIN packet scheduling. Packet scheduling offers two modes:   Average Packet Rate (APR) leaky bucket, which specifies the average rate of one queue Weighted Fair Queue (WFQ), which decides which queue is selected in one slot time to guarantee the minimal packet rate of one queue Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 34 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to packet scheduling mode. Figure 7 shows the RTL8367S packet-scheduling diagram. Figure 7. RTL8367S MAX-MIN Scheduling Diagram 9.13.4. IEEE 802.1p/Q and DSCP Remarking The RTL8367S supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point) remarking function. When packets egress from one of the 8 queues, the packet’s 802.1p/Q priority and IP DSCP can optionally be remarked to a configured value. 802.1p/Q priority & IP DSCP value can be remarked based on internal priority or original 802.1p/Q priority & IP DSCP value in packets. 9.13.5. ACL-Based Priority The RTL8367S supports 96-entry ACL (Access Control List) rules. When a packet is received, its physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries. If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is valid, the action bit and priority bit will be applied.     If the action bit is ‘Drop’, the packet will be dropped. If the action bit is ‘CPU’, the packet will be trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules other than the ACL rule) If the action bit is ‘Permit’, ACL rules will override other rules If the action bit is ‘Mirror’, the packet will be forwarded to the mirror port and the L2 lookup result destination port. The mirror port indicates the port configured in the port mirror mechanism The priority bit will take effect only if the action bit is ‘CPU’, ‘Permit’, and ‘Mirror’. The Priority bit is used to determine the packet queue ID according to the priority assignment mechanism Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 35 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.14. IGMP & MLD Snooping Function The RTL8367S supports hardware IGMPv1/v2/v3 and MLDv1/v2 snooping with a maximum of 256 groups (maximum 255 groups per port). These multicast groups are learned and deleted/aged out automatically. For data packets of a known multicast group, the RTL8367S forwards them according to the learned group membership. The RTL8367S checks group membership every 125 seconds (default). If a specified port of the RTL8367S does not receive a report message after 3 (default) consecutive checks, the port is removed from the multicast group. The 125 second interval and the number of consecutive checks before ageing are user configurable default values. IPv4 multicast data packets are forwarded per group IP. IPv6 multicast data packets are forwarded per destination MAC. That is, IPv6 multicast groups that share the same destination MAC are treated as the same group. This is called address ambiguity. Some reserved range IP addresses will always be flooded to all ports. If IGMP or MLD report message requests to join these groups, this request will be ignored silently. These reserved IP addresses could be the following IP addresses and they are configurable. IPv4: 224.0.0.0 ~ 224.0.0.255 IPv4: 224.0.1.0 ~ 224.0.1.255 IPv4: 239.255.255.0 ~ 239.255.255.255 IPv6: 33:33:00:00:00:00 ~ 33:33:00:00:00:FF (forwarded per destination MAC) Due to address ambiguity, some IPv6 multicast addresses that are not reserved for network protocols will be flooded, as the corresponding destination MAC address is inside the reserved IP address range (Corresponding MAC address). The RTL8367S learns the ‘Dynamic Router Port’ automatically by monitoring Query messages (both IGMP & MLD) and multicast routing protocol packets. Table 15 gives the multicast routing protocols that the RTL8367S recognizes. PIMv1 is confirmed by the IGMP header type and the other multicast routing protocols are recognized by the destination IP in the IP header (in both IPv4 and IPv6). IPv4 N/A 224.0.0.13 224.0.0.4 224.0.0.5 224.0.0.6 IPv6 N/A FF02::D FF02::4 FF02::5 FF02::6 Table 15. IPv4/IPv6 Multicast Routing Protocols Multicast Routing Protocol Check IGMP Header Type=0x14 (PIMv1) PIMv2 DVMRP MOSPF MOSPF Users can specify ‘Static Router Ports’ via API. This forces the ports to act as true router ports. All reports and Leave/Done messages will be forwarded to the specified Static Router ports. The RTL8367S supports a ‘Fast Leave’ feature. When enabled, group membership will be removed immediately the RTL8367S receives an IGMPv2 Leave message or MLDv1 Done message. Normally this feature is only enabled when there is only one host. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 36 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet The IGMP/MLD snooping feature is disabled by default. IGMP & MLD messages will be flooded to all ports without any further processing. This feature can be enabled and configured via API. Contact your Realtek support team for configuration details. 9.15. IEEE 802.1x Function The RTL8367S supports IEEE 802.1x Port-based/MAC-based Access Control.        Port-Based Access Control for each port Authorized Port-Based Access Control for each port Port-Based Access Control Direction for each port MAC-Based Access Control for each port MAC-Based Access Control Direction Optional Unauthorized Behavior Guest VLAN 9.15.1. Port-Based Access Control Each port of the RTL8367S can be set to 802.1x port-based authenticated checking function usage and authorized status. Ports with 802.1X unauthorized status will drop received/transmitted frames. 9.15.2. Authorized Port-Based Access Control If a dedicated port is set to 802.1x port-based access control, and passes the 802.1x authorization, then its port authorization status can be set to authorized. 9.15.3. Port-Based Access Control Direction Ports with 802.1X unauthorized status will drop received/transmitted frames only when port authorization direction is ‘BOTH’. If the authorization direction of an 802.1X unauthorized port is IN, incoming frames to that port will be dropped, but outgoing frames will be transmitted. 9.15.4. MAC-Based Access Control MAC-Based Access Control provides authentication for multiple logical ports. Each logical port represents a source MAC address. There are multiple logical ports for a physical port. When a logical port or a MAC address is authenticated, the relevant source MAC address has the authorization to access the network. A frame with a source MAC address that is not authenticated by the 802.1x function will be dropped or trapped to the CPU. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 37 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.15.5. MAC-Based Access Control Direction Unidirectional and Bi-directional control are two methods used to process frames in 802.1x. As the system cannot predict which port the DA is on, a system-wide MAC-based access control direction setup is provided for determining whether receiving or bi-direction should be authorized. If MAC-based access control direction is BOTH, then received frames with unauthenticated SA or unauthenticated DA will be dropped. When MAC-based access control direction is IN, only received frames with unauthenticated SA will be dropped. 9.15.6. Optional Unauthorized Behavior Both in Port-Based Network Access Control and MAC-Based Access Control, a whole system control setup is provided to determine unauthorized frame dropping, trapping to CPU, or tagging as belonging to a Guest VLAN (see the following ‘Guest VLAN’ section). 9.15.7. Guest VLAN When the RTL8367S enables the Port-based or MAC-based 802.1x function, and the connected PC does not support the 802.1x function or does not pass the authentication procedure, the RTL8367S will drop all packets from this port. The RTL8367S also supports one Guest VLAN to allow unauthorized ports or packets to be forwarded to a limited VLAN domain. The user can configure one VLAN ID and member set for these unauthorized packets. 9.16. IEEE 802.1D Function When using IEEE 802.1D, the RTL8367S supports 16 sets and four status’ for each port for CPU implementation 802.1D (STP) and 802.1s (MSTP) function:     Disabled: The port will not transmit/receive packets, and will not perform learning Blocking: The port will only receive BPDU spanning tree protocol packets, but will not transmit any packets, and will not perform learning Learning: The port will receive any packet, including BPDU spanning tree protocol packets, and will perform learning, but will only transmit BPDU spanning tree protocol packets Forwarding: The port will transmit/receive all packets, and will perform learning The RTL8367S also supports a per-port transmission/reception enable/disable function. Users can control the port state via register. 9.17. Embedded 8051 An 8051 MCU is embedded in the RTL8367S to support management functions. The 8051 MCU can access all of the registers in the RTL8367S through the internal bus. With the Network Interface Circuit (NIC) acting as the data path, the 8051 MCU connects to the switch core and can transmit frames to or receive frames from the Ethernet network. The features of the 8051 MCU are listed below: Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 38 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet       256 Bytes fast internal RAM On-chip 48K data memory On-chip 16K code memory Supports code-banking 12KBytes NIC buffer EEPROM read/write ability 9.18. Realtek Cable Test (RTCT) The RTL8367S physical layer transceivers use DSP technology to implement the Realtek Cable Test (RTCT) feature. The RTCT function can be used to detect short, open, or impedance mismatch in each differential pair. The RTL8367S also provides LED support to indicate test status and results. 9.19. LED Indicators The RTL8367S supports parallel LEDs for each port. Each port has two LED indicator pins, LANnLED0 and LANnLED1. Each pin may have different indicator information (defined in Table 16). Refer to section 7.4 LED Pins, page 18 for pin details. Upon reset, the RTL8367S supports chip diagnostics and LED operation test by blinking all LEDs once. LED Statuses LED_Off Dup/Col Link/Act Spd1000 Spd100 Spd10 Spd1000/Act Spd100/Act Spd10/Act Spd100 (10)/Act Act Table 16. LED Definitions Description LED Pin Output Disable. Duplex/Collision Indicator. Blinking when collision occurs. Low for full duplex, and high for half duplex mode. Link, Activity Indicator. Low for link established. Link/Act Blinking when the corresponding port is transmitting or receiving. 1000Mbps Speed Indicator. Low for 1000Mbps. 100Mbps Speed Indicator. Low for 100Mbps. 10Mbps Speed Indicator. Low for 10Mbps. 1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinking when the corresponding port is transmitting or receiving. 100Mbps Speed/Activity Indicator. Low for 100Mbps. Blinking when the corresponding port is transmitting or receiving. 10Mbps Speed/Activity Indicator. Low for 10Mbps. Blinking when the corresponding port is transmitting or receiving. 10/100Mbps Speed/Activity Indicator. Low for 10/100Mbps. Blinking when the corresponding port is transmitting or receiving. Activity Indicator. Act blinking when the corresponding port is transmitting or receiving. The LED pin also supports pin strapping configuration functions. The LANnLED0 and LANnLED1 pins are dual-function pins: input operation for configuration upon reset, and output operation for LED after Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 39 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet reset. When the pin input is pulled high upon reset, the pin output is active low after reset. When the pin input is pulled down upon reset, the pin output is active high after reset. For details refer to Figure 8, page 40, and Figure 9, page 40. Typical values for pull-up/pull-down resistors are 4.7K. The LANnLED1 can be combined with LANnLED0 as a Bi-color LED. LED LANnLED1 should operate with the same polarity as other Bi-color LED pins. For example:   LAN0LED1 should be pulled up upon reset if LAN0LED1 is combined with LAN0LED0 as a Bicolor LED, and LAN0LED0 input is pulled high upon reset. In this configuration, the output of these pins is active low after reset LAN0LED1 should be pulled down upon reset if LAN0LED1 is combined with LAN0LED0 as a Bicolor LED, and LAN0LED0 input is pulled down upon reset. In this configuration, the output of these pins is active high after reset Upon reset, the RTL8367S supports chip diagnostics and LED functions by blinking all LEDs once. This function can be disabled by asserting EN_PWRLIGHT to 0b0 (pull down). Figure 8. Pull-Up and Pull-Down of LED Pins for Single-Color LED Pull-Down Pull-Up SPD 1000 4.7K ohm DVDDIO SPD 100 470ohm 470ohm RTL8367S Yellow SPD100 4.7K ohm Green RTL8367S SPD1000 4.7K ohm LED Pins Output Active Low Green Yellow 4.7K ohm LED Pins Output Active High Figure 9. Pull-Up and Pull-Down of LED Pins for Bi-Color LED Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 40 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 9.20. Green Ethernet 9.20.1. Link-On and Cable Length Power Saving The RTL8367S provides link-on and dynamic detection of cable length and dynamic adjustment of power required for the detected cable length. This feature provides high performance with minimum power consumption. 9.20.2. Link-Down Power Saving The RTL8367S implements link-down power saving on a per-port basis, greatly cutting power consumption when the network cable is disconnected. After it detects an incoming signal, it wakes up from link-down power saving and operates in normal mode. 9.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function The RTL8367S supports IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T and 100Base-TX in full duplex operation. The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access Control (MAC) sub-layer with 100Base-TX and 1000Base-T Physical Layers defined to support operation in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the link can disable portions of the functionality and save power during periods of low link utilization.   1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power Idle 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power Idle The RTL8367S MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner, that a break in the data stream is expected, and components may use this information to enter power saving modes that require additional time to resume normal operation. Similarly, it informs the LPI Client that the link partner has sent such an indication. 9.22. Interrupt Pin for External CPU The RTL8367S provides one Interrupt output pin to interrupt an external CPU. The polarity of the Interrupt output pin can be configured via register access. In configuration registers, each port has link-up and link-down interrupt flags with mask. When port link-up or link-down interrupt mask is enabled, the RTL8367S will raise the interrupt signal to alarm the external CPU. The CPU can read the interrupt flag to determine which port has changed to which status. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 41 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 10. Interface Descriptions 10.1. EEPROM SMI Host to EEPROM The EEPROM interface of the RTL8367S uses the serial bus EEPROM Serial Management Interface (SMI) to read the EEPROM space up to 256K-bits. When the RTL8367S is powered up, it drives SCK and SDA to read the registers from the EEPROM. SCK SDA START STOP Figure 10. SMI Start and Stop Command SCK 1 8 9 DATA IN DATA OUT ACKNOWLEDGE START Figure 11. EEPROM SMI Host to EEPROM Figure 12. EEPROM SMI Host Mode Frame Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 42 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 10.2. EEPROM SMI Slave for External CPU When EEPROM auto-load is complete, the RTL8367S registers can be accessed via SCK and SDA by an external CPU. The device address of the RTL8367S is 0x4. For the start and end of a write/read command, SCK needs one extra clock before/after the start/stop signals. Figure 13. EEPROM SMI Write Command for Slave Mode Figure 14. EEPROM SMI Read Command for Slave Mode Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 43 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 10.3. General Purpose Interface The RTL8367S supports one digital extension interface. The interface function mux is summarized in d Table 17. The Extension GMAC2 of the RTL8367S supports RGMII, MII MAC mode, or MII PHY mode via register configuration. Table 17. RTL8367S Extension Port 2 Pin Definitions Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 Extension Interface E2_DO3 E2_DO2 E2_DO1 E2_DO0 E2_DOEN E2_DOCLK E2_DICLK E2_DIDV E2_DI0 E2_DI1 E2_DI2 E2_DI3 Type RGMII MII MAC Mode MII PHY Mode O O O O O O I I I I I I RG2_TXD3 RG2_TXD2 RG2_TXD1 RG2_TXD0 RG2_TXCTL RG2_TXCLK RG2_RXCLK RG2_RXCTL RG2_RXD0 RG2_RXD1 RG2_RXD2 RG2_RXD3 M2M_TXD3 M2M_TXD2 M2M_TXD1 M2M_TXD0 M2M_TXEN M2M_TXCLK M2M_RXCLK M2M_RXDV M2M_RXD0 M2M_RXD1 M2M_RXD2 M2M_RXD3 M2P_RXD3 M2P_RXD2 M2P_RXD1 M2P_RXD0 M2P_RXDV M2P_RXCLK M2P_TXCLK M2P_TXEN M2P_TXD0 M2P_TXD1 M2P_TXD2 M2P_TXD3 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 44 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 10.3.1. Extension Ports RGMII Mode Interface (1Gbps) The Extension GMAC2 of the RTL8367S supports RGMII interface to an external CPU. The pin numbers and names are shown in Table 18. Figure 15 shows the signal diagram for Extension GMAC2 in RGMII interface. RTL8367S Pin No. 45, 46, 47, 48 49 50 51 52 53, 54, 55, 56 Table 18. Extension GMAC2 RGMII Pins Type Extension Port 2 RGMII O RG2_TXD[3:0] O RG2_TXCTL O RG2_TXCLK I RG2_RXCLK I RG2_RXCTL I RG2_RXD[0:3] Figure 15. RGMII Mode Interface Signal Diagram 10.3.2. Extension Ports MII MAC/PHY Mode Interface (10/100Mbps) The Extension GMAC2 of the RTL8367S supports MII MAC/PHY mode interfaces to an external CPU. The pin numbers and names are shown in Table 19. Figure 16 shows the signal diagram for Extension GMAC2 in MII PHY mode interface, and Figure 17 shows the signal diagram for Extension GMAC2 in MII MAC mode interface. RTL8367S Pin No. 45, 46, 47, 48 49 50 Table 19. Extension GMAC2 MII Pins Extension GMAC 2 Type Type MII MAC Mode O M2M_TXD[3:0] O O M2M_TXEN O I M2M_TXCLK O Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 45 Extension GMAC 2 MII PHY Mode M2P_RXD[3:0] M2P_RXDV M2P_RXCLK Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet RTL8367S Pin No. 51 52 53, 54, 55, 56 Type I I I Extension GMAC 2 MII MAC Mode M2M_RXCLK M2M_RXDV M2M_RXD[0:3] Type O I I Extension GMAC 2 MII PHY Mode M2P_TXCLK M2P_TXEN M2P_TXD[0:3] Figure 16. Signal Diagram of MII PHY Mode Interface (100Mbps) Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 46 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Figure 17. Signal Diagram of MII MAC Mode Interface (100Mbps) Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 47 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367RB-VB Datasheet 11. Register Descriptions In this section the following abbreviations are used: RO: Read Only LH: Latch High until clear RW: Read/Write SC: Self Clearing LL: Latch Low until clear 11.1. PCS Register (PHY 0~4) Register 0 1 2 3 4 5 6 7 8 9 10 11~14 15 16~31 Table 20. PCS Register (PHY 0~4) Register Description Control Register Status Register PHY Identifier 1 PHY Identifier 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Page Transmit Register Auto-Negotiation Link Partner Next Page Register 1000Base-T Control Register 1000Base-T Status Register Reserved Extended Status ASIC Control Register Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 48 Default 0x1140 0x7949 0x001C 0xC980 0x0DE1 0x0000 0x0004 0x2001 0x0000 0x0E00 0x0000 0x0000 0x2000 - Track ID: JATR-3375-16 Rev. 0.1 RTL8367S Datasheet 11.2. Register 0: Control Reg.bit 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6 0.[5:0] Table 21. Register 0: Control Mode Description RW/SC 1: PHY reset 0: Normal operation This bit is self-clearing. Loopback RW 1: Enable loopback. This will loopback TXD to RXD and ignore all activity on the cable media (Digital Loopback) 0: Normal operation This function is usable only when this PHY is operated in 10Base-T full duplex, 100Base-TX full duplex, or 1000Base-T full duplex. Speed Selection[0] RW [0.6, 0.13] Speed Selection[1:0] 11: Reserved 10: 1000Mbps 01: 100Mbps 00: 10Mbps This bit can be set through SMI (Read/Write). RW 1: Enable auto-negotiation process Auto Negotiation Enable 0: Disable auto-negotiation process This bit can be set through SMI (Read/Write). Power Down RW 1: Power down. All functions will be disabled except SMI function 0: Normal operation Isolate RW 1: Electrically isolates the PHY from GMII. The PHY is still able to respond to SMI 0: Normal operation RW/SC 1: Restart Auto-Negotiation process Restart Auto Negotiation 0: Normal operation Duplex Mode RW 1: Full duplex operation 0: Half duplex operation This bit can be set through SMI (Read/Write). Collision Test RO 1: Collision test enabled 0: Normal operation When set, this bit will cause the COL signal to be asserted in response to the assertion of TXEN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the deassertion of TXEN. Speed Selection[1] RW See bit 13 Reserved RO Reserved Name Reset Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 49 Default 0 0 0 1 0 0 0 1 0 1 000000 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 11.3. Register 1: Status Reg.bit 1.15 Name 100Base-T4 Mode RO 1.14 100Base-TX-FD RO 1.13 100Base-TX-HD RO 1.12 10Base-T-FD RO 1.11 10Base-T-HD RO 1.10 100Base-T2-FD RO 1.9 100Base-T2-HD RO 1.8 Extended Status RO 1.7 1.6 Reserved MF Preamble Suppression Auto-negotiate Complete Remote Fault RO RO 1.5 1.4 1.3 RO RO/LH RO 1.2 Auto-Negotiation Ability Link Status RO/LL 1.1 Jabber Detect RO/LH 1.0 Extended Capability RO Table 22. Register 1: Status Description 0: No 100Base-T4 capability The RTL8367S does not support 100Base-T4 mode and this bit should always be 0. 1: 100Base-TX full duplex capable 0: Not 100Base-TX full duplex capable 1: 100Base-TX half duplex capable 0: Not 100Base-TX half duplex capable 1: 10Base-T full duplex capable 0: Not 10Base-T full duplex capable 1: 10Base-T half duplex capable 0: Not 10Base-T half duplex capable 0: Not 100Base-T2 full duplex capable The RTL8367S does not support 100Base-T2 mode and this bit should always be 0. 0: Not 100Base-T2 half duplex capable The RTL8367S does not support 100Base-T2 mode and this bit should always be 0. 1: Extended status information in Register 15 The RTL8367S always supports Extended Status Register. Reserved The RTL8367S will accept management frames with preamble suppressed. 1: Auto-negotiation process completed 0: Auto-negotiation process not completed 1: Remote fault condition detected 0: No remote fault detected This bit will remain set until it is cleared by reading register 1 via the management interface. 1: Auto-negotiation capable (permanently =1) 1: Link is established. If the link fails, this bit will be 0 until after reading this bit again 0: Link has failed since previous read If the link fails, this bit will be set to 0 until bit is read. 1: Jabber detected 0: No Jabber detected Jabber is supported only in 10Base-T mode. 1: Extended register capable (permanently =1) Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 50 Default 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 1 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 11.4. Register 2: PHY Identifier 1 The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this device. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor’s model number, and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. Reg.bit 2.[15:0] Name OUI Table 23. Register 2: PHY Identifier 1 Mode Description RO Composed of the 3rd to 18th bits of the Organizationally Unique Identifier (OUI), respectively. Default 0x001C 11.5. Register 3: PHY Identifier 2 Reg.bit 3.[15:10] 3.[9:4] 3.[3:0] Name OUI Model Number Revision Number Table 24. Register 3: PHY Identifier 2 Mode Description RO Assigned to the 19th through 24th bits of the OUI RO Manufacturer’s model number RO Manufacturer’s revision number Default 110010 011000 0000 11.6. Register 4: Auto-Negotiation Advertisement This register contains the advertisement abilities of this device as they will be transmitted to its Link Partner during Auto-negotiation. Note: Each time the link ability of the RTL8367S is reconfigured, the auto-negotiation process should be executed to allow the configuration to take effect. Reg.bit 4.15 4.14 4.13 4.12 4.11 4.10 4.9 4.8 4.7 Table 25. Register 4: Auto-Negotiation Advertisement Name Mode Description Next Page RO 1: Additional next pages exchange desired 0: No additional next pages exchange desired Acknowledge RO Permanently=0 Remote Fault RW 1: Advertises that the RTL8367S has detected a remote fault 0: No remote fault detected Reserved RO Reserved Reserved RW Reserved Pause RW 1: Advertises that the RTL8367S has flow control capability 0: No flow control capability 100Base-T4 RO 1: 100Base-T4 capable 0: Not 100Base-T4 capable (Permanently =0) 100Base-TX-FD RW 1: 100Base-TX full duplex capable 0: Not 100Base-TX full duplex capable 100Base-TX RW 1: 100Base-TX half duplex capable 0: Not 100Base-TX half duplex capable Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 51 Default 0 0 0 0 0 1 0 1 1 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Reg.bit 4.6 Name 10Base-T-FD Mode RW Description 1: 10Base-T full duplex capable 0: Not 10Base-T full duplex capable 4.5 10Base-T RW 1: 10Base-T half duplex capable 0: Not 10Base-T half duplex capable 4.[4:0] Selector Field RO [00001]=IEEE 802.3 Note 1: The setting of Register 4 has no effect unless auto-negotiation is restarted or the link goes down. Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted. Default 1 1 00001 11.7. Register 5: Auto-Negotiation Link Partner Ability This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after a successful Auto-negotiation. Reg.bit 5.15 5.14 5.13 5.12 5.11 5.10 5.9 5.8 5.7 5.6 5.5 5.[4:0] Table 26. Register 5: Auto-Negotiation Link Partner Ability Mode Description RO 1: Link partner desires Next Page transfer 0: Link partner does not desire Next Page transfer Acknowledge RO 1: Link Partner acknowledges reception of Fast Link Pulse (FLP) words 0: Not acknowledged by Link Partner Remote Fault RO 1: Remote Fault indicated by Link Partner 0: No remote fault indicated by Link Partner Reserved RO Reserved Asymmetric Pause RO 1: Asymmetric Flow control supported by Link Partner 0: No Asymmetric flow control supported by Link Partner When auto-negotiation is enabled, this bit reflects Link Partner ability Pause RO 1: Flow control supported by Link Partner. 0: No flow control supported by Link Partner When auto-negotiation is enabled, this bit reflects Link Partner ability 100Base-T4 RO 1: 100Base-T4 supported by Link Partner 0: 100Base-T4 not supported by Link Partner 100Base-TX-FD RO 1: 100Base-TX full duplex supported by Link Partner 0: 100Base-TX full duplex not supported by Link Partner 100Base-TX RO 1: 100Base-TX half duplex supported by Link Partner 0: 100Base-TX half duplex not supported by Link Partner 10Base-T-FD RO 1: 10Base-T full duplex supported by Link Partner 0: 10Base-T full duplex not supported by Link Partner 10Base-T RO 1: 10Base-T half duplex supported by Link Partner 0: 10Base-T half duplex not supported by Link Partner Selector Field RO [00001]=IEEE 802.3 Name Next Page Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 52 Default 0 0 0 0 0 0 0 0 0 0 0 00000 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 11.8. Register 6: Auto-Negotiation Expansion Reg.bit 6.[15:5] 6.4 6.3 6.2 6.1 6.0 Table 27. Register 6: Auto-Negotiation Expansion Name Mode Description Reserved RO Ignore on read RO/ 1: A fault has been detected via the Parallel Detection function Parallel Detection Fault LH 0: No fault has been detected via the Parallel Detection function RO 1: Link Partner is Next Page able Link Partner Next Page Ability 0: Link Partner is not Next Page able RO Not supported. Permanently =0 Local Next Page Ability Page Received RO/ 1: A New Page has been received LH 0: A New Page has not been received RO If Auto-Negotiation is enabled, this bit means: Link Partner AutoNegotiation 1: Link Partner is Auto-Negotiation able Ability 0: Link Partner is not Auto-Negotiation able Default 0 0 0 1 0 0 11.9. Register 7: Auto-Negotiation Page Transmit Register Reg.bit 7.15 7.14 7.13 7.12 7.11 7.[10:0] Table 28. Register 7: Auto-Negotiation Page Transmit Register Name Mode Description Next Page RW 1: Link partner desires Next Page transfer 0: Link partner does not desire Next Page transfer Reserved RO 1: A fault has been detected via the Parallel Detection function 0: No fault has been detected via the Parallel Detection function Message Page RW 1: Message page 0: No Message page ability Acknowledge 2 RW 1: Local device has the ability to comply with the message received 0: Local device has no ability to comply with the message received Toggle RO Toggle bit RW Content of message/unformatted page Message/ Unformatted Field Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 53 Default 0 0 1 0 0 1 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 11.10. Register 8: Auto-Negotiation Link Partner Next Page Register Reg.bit 8.15 8.14 8.13 8.12 8.11 8.[10:0] Table 29. Register 8: Auto-Negotiation Link Partner Next Page Register Name Mode Description Next Page RO Received Link Code Word Bit 15 Acknowledge RO Received Link Code Word Bit 14 Message Page RO Received Link Code Word Bit 13 Acknowledge 2 RO Received Link Code Word Bit 12 Toggle RO Received Link Code Word Bit 11 RO Received Link Code Word Bit 10:0 Message/ Unformatted Field Default 0 0 0 0 0 0 11.11. Register 9: 1000Base-T Control Register Table 30. Register 9: 1000Base-T Control Register Reg.bit Name Mode Description 9.[15:13] Test Mode RW Test Mode Select. 000: Normal mode 001: Test mode 1 – Transmit waveform test 010: Test mode 2 – Transmit jitter test in MASTER mode 011: Test mode 3 – Transmit jitter test in SLAVE mode 100: Test mode 4 – Transmitter distortion test 101, 110, 111: Reserved 9.12 RW 1: Enable MASTER/SLAVE manual configuration MASTER/SLAVE Manual Configuration 0: Disable MASTER/SLAVE manual configuration Enable 9.11 RW MASTER/SLAVE 1: Configure PHY as MASTER during MASTER/SLAVE Configuration Value negotiation, only when bit 9.12 is set to logical one 0: Configure PHY as SLAVE during MASTER/SLAVE negotiation, only when bit 9.12 is set to logical one 9.10 Port Type RW 1: Multi-port device 0: Single-port device 9.9 1000Base-T Full Duplex RW 1: Advertise PHY is 1000Base-T full duplex capable 0: Advertise PHY is not 1000Base-T full duplex capable 9.8 1000Base-T Half Duplex RW 1: Advertise PHY is 1000Base-T half duplex capable 0: Advertise PHY is not 1000Base-T half duplex capable 9.[7:0] Reserved RW Reserved Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 54 Default 000 0 1 1 1 0 0 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 11.12. Register 10: 1000Base-T Status Register Reg.bit 10.15 10.14 10.13 10.12 10.11 10.10 10.[9:8] 10.[7:0] Table 31. Register 10: 1000Base-T Status Register Name Mode Description MASTER/SLAVE RO/LH/ 1: MASTER/SLAVE configuration fault detected Configuration Fault SC 0: No MASTER/SLAVE configuration fault detected RO 1: Local PHY configuration resolved to MASTER MASTER/SLAVE Configuration Resolution 0: Local PHY configuration resolved to SLAVE Local Receiver Status RO 1: Local receiver OK 0: Local receiver not OK Remote Receiver Status RO 1: Remote receiver OK 0: Remote receiver not OK RO 1: Link partner is capable of 1000Base-T full duplex Link Partner 1000Base-T Full Duplex 0: Link partner is not capable of 1000Base-T full duplex 1000Base-T Half Duplex RO 1: Link partner is capable of 1000Base-T half duplex 0: Link partner is not capable of 1000Base-T half duplex Reserved RO Reserved Idle Error Count RO/SC Idle Error Counter. The counter stops automatically when it reaches 0xFF Default 0 0 0 0 0 0 0 0 11.13. Register 15: Extended Status Table 32. Register 15: Extended Status Reg.bit Name Mode Description 15.15 1000Base-X Full Duplex RO 1: 1000Base-X full duplex capable 0: Not 1000Base-X full duplex capable 15.14 1000Base-X Half Duplex RO 1: 1000Base-X half duplex capable 0: Not 1000Base-X half duplex capable 15.13 1000Base-T Full Duplex RO 1: 1000Base-T full duplex capable 0: Not 1000Base-T full duplex capable 15.12 1000Base-T Half Duplex RO 1: 1000Base-T half duplex capable 0: Not 1000Base-T half duplex capable 15.[11:0] Reserved RO Reserved Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 55 Default 0 0 1 0 0 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12. Electrical Characteristics 12.1. Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified. Table 33. Absolute Maximum Ratings Parameter Min Junction Temperature (Tj) Storage Temperature -45 DVDDIO, DVDDIO_2, AVDDH, SVDDH. HV_SWR, Supply GND-0.3 Referenced to GND, SGND, AGND, and GND_SWR DVDDL, AVDDL, SVDDL, PLLVDDL, Supply Referenced to GND-0.3 GND, AGND, SGND, and PLLGND. Digital Input Voltage GND-0.3 Max +125 +125 Units C C +3.63 V +1.21 V VDDIO+0.3 V 12.2. Recommended Operating Range Table 34. Recommended Operating Range Parameter Min Typical Ambient Operating Temperature (Ta) 0 AVDDH, SVDDH and HV_SWR Supply Voltage Range 3.135 3.3 3.3V 3.135 3.3 DVDDIO Supply Voltage Range 2.5V 2.375 2.5 3.3V 3.135 3.3 DVDDIO_2 Supply Voltage Range 2.5V 2.375 2.5 DVDDL, AVDDL, SVDDL, PLLVDDL Supply Voltage Range 1.045 1.1 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 56 Max 70 3.465 3.465 2.625 3.465 2.625 1.155 Units C V V V V V V Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.3. Thermal Characteristics 12.3.1. Assembly Description Package PCB Table 35. Assembly Description Type LQFP-128 Dimension 14mm×14mm Thickness 1.4mm PCB Dimension 100mm×89mm PCB Thickness 1.6mm 2-Layer: - Top layer (1oz): 40% coverage of Cu - Bottom layer (1oz): 95% coverage of Cu 4-Layer: Number of Cu Layer-PCB - 1st layer (1oz): 40% coverage of Cu - 2nd layer (1oz): 95% coverage of Cu - 3rd layer (1oz): 95% coverage of Cu - 4th layer (1oz): 95% coverage of Cu 12.3.2. Material Properties Table 36. Material Properties Material Thermal Conductivity K (W/m-K) 149 at 25C Die Silicon 107 at 125C Lead Frame C7025 172 Epoxy CRM-1076W 0.9 Molding Compound EME-G631H 0.9 Copper 389 PCB FR-4 0.3 Item Package 12.3.3. Simulation Conditions Table 37. Simulation Conditions 1.765W 2L (2S) / 4L (2S2P) Air Flow = 0 m/s Power Dissipation Test Board (PCB) Control Condition Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 57 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.3.4. Thermal Performance of LQFP-128 on PCB Under Still Air Convection Table 38. Thermal Performance of LQFP-128 on PCB Under Still Air Convection θJA θJB θJC ΨJB 2L PCB 50.08 24.52 10.39 21.69 4L PCB 45.01 25.16 10.35 22.33 Note: θJA: Junction to ambient thermal resistance θJB: Junction to board thermal resistance θJC: Junction to case thermal resistance ΨJB: Junction to bottom surface center of PCB thermal characterization Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 58 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.4. DC Characteristics Table 39. DC Characteristics Parameter SYM Min Typical Max Units IDVDDIO_2 31 mA Power Supply Current for RGMII1 DVDDIO_2 (2.5V) (For General Purpose Interface) System Idle (All UTP Port Link Down, without Extension Ports and LEDs) Power Supply Current for VDDH IDVDDIO, IAVDDH 17 mA Power Supply Current for VDDL IDVDDL, IAVDDL, IPLLVDDL 110 mA 1000M Active (All UTP Ports Link/Active, without Extension Ports and LEDs) Power Supply Current for VDDH IDVDDIO, IAVDDH 221 mA Power Supply Current for VDDL IDVDDL, IAVDDL, IPLLVDDL 710 mA VDDIO=3.3V TTL Input High Voltage Vih 2.0 V TTL Input Low Voltage Vil 0.7 V Output High Voltage Voh 2.7 V Output Low Voltage Vol 0.6 V VDDIO=2.5V TTL Input High Voltage Vih 1.7 V TTL Input Low Voltage Vil 0.6 V Output High Voltage Voh 2.25 V Output Low Voltage Vol 0.4 V Note: ISVDDL, ISVDDH , and IDVDDIO_2 should be added to the total current consumption when the dual extension ports of the RTL8367S are used. Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 59 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.5. AC Characteristics 12.5.1. EEPROM SMI Host Mode Timing Characteristics Figure 18. EEPROM SMI Host Mode Timing Characteristics t9 nRESET SCK SDA Figure 19. SCK/SDA Power on Timing Figure 20. EEPROM Auto-Load Timing Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 60 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 - Table 40. EEPROM SMI Host Mode Timing Characteristics Description Type Min Typical SCK Clock Period O 9.7 10 SCK High Time O 4.2 5 SCK Low Time O 4.2 5 START Condition Setup Time O 4.8 5.04 START Condition Hold Time O 4.8 4.96 Data Hold Time O 2.2 2.52 Data Setup Time O 2.2 2.48 STOP Condition Setup Time O 4.4 5.04 SCK/SDA Active from Reset Ready O 75 78.4 8K-Bits EEPROM Auto-Load Time O 250 278 SCK Rise Time (10% to 90%) O 320 SCK Fall Time (90% to 10%) O 320 Duty Cycle O 48.86 50 Max 51.14 Units µs µs µs µs µs µs µs µs ms ms ns ns % Max - Units µs µs µs µs µs ns ns µs 12.5.2. EEPROM SMI Slave Mode Timing Characteristics Figure 21. EEPROM SMI Slave Mode Timing Characteristics Symbol t1 t2 t3 t4 t5 t6 t7 t8 Table 41. EEPROM SMI Slave Mode Timing Characteristics Description Type Min Typical SCK High Time I 0.25 SCK Low Time I 0.25 START Condition Setup Time I 0.15 START Condition Hold Time I 0.15 Data Hold Time I 0.15 Data Setup Time I 150 Clock to Data Output Delay O 100 STOP Condition Setup Time I 0.15 - Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 61 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.5.3. MDIO Slave Mode Timing Characteristics The RTL8367S supports MDIO (MMD) slave mode. The Master (CPU) can access the Slave (RTL8367S) registers via the MDIO interface. The MDIO is a bi-directional signal that can be sourced by the Master or the Slave. In a write command, the master sources the MDIO signal. In a read command, the slave sources the MDIO signal.   The timing characteristics t1, t2, and t3 (Table 42) of the Master (the RTL8367S link partner CPU) are provided by the Master when the Master sources the MDIO signal (Write command) The timing characteristics t4 (Table 42) of the Slave (RTL8367S) are provided by the RTL8367S when the RTL8367S sources the MDIO signal (Read command) Figure 22. MDIO Sourced by Master Figure 23. MDIO Sourced by RTL8367S (Slave) Table 42. MDIO Timing Characteristics and Requirement Parameter SYM Description/Condition Type Min MDC Clock Period t1 Clock Period I 125 t2 Input Setup Time I 25 MDIO to MDC Rising Setup Time (Write Data) t3 Input Hold Time I 25 MDIO to MDC Rising Hold Time (Write Data) t4 O 0 MDC to MDIO Delay Time Clock (Falling Edge) to Data (Read Data) Delay Time Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 62 Typical - Max - - - 2.8 40 Units ns ns ns ns Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.5.4. MII MAC Mode Timing Figure 24. MII MAC Mode Clock to Data Output Delay Timing Figure 25. MII MAC Mode Input Timing Parameter 100Base-TX MxM_TXCLK and MxM_RXCLK Input Cycle Time 10Base-T MxM_TXCLK and MxM_RXCLK Input Cycle Time MxM_TXCLK to MxM_TXD[3:0] and MxM_TXEN Output Delay Time MxM_RXD[3:0], MxM_RXDV, and MxM_CRS Input Setup Time MxM_RXD[3:0], MxM_RXDV, and MxM_CRS Input Hold Time Table 43. MII MAC Mode Timing SYM Description/Condition TMM_TX_CYC 25MHz Clock Input. TMM_RX_CYC TMM_TX_CYC 2.5MHz Clock Input. TMM_RX_CYC TMM_COD - Type I Min - Typical 40 Max - Units ns I - 400 - ns O 3 5 7 ns TMM_RX_SU - I 10 - - ns TMM_RX_HO - I 10 - - ns Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 63 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.5.5. MII PHY Mode Timing Figure 26. MII PHY Mode Output Timing Figure 27. MII PHY Mode Clock Output to Data Input Delay Timing Table 44. MII PHY Mode Timing Characteristics Parameter SYM Description/Condition Type Min TMP_RX_CYC 25MHz Clock Output. O 100M MxP_RXCLK and MxP_TXCLK Output Cycle Time TMP_TX_CYC TMP_RX_CYC 2.5MHz Clock Output. O 10M MxP_RXCLK and MxP_TXCLK Output Cycle Time TMP_TX_CYC O 14 TMP_RX_SU 100M MxP_RXD[3:0] and MxP_RXDV to MxP_RXCLK Output Setup Time O 16 TMP_RX_HO 100M MxP_RXD[3:0] and MxP_RXDV to MxP_RXCLK Output Hold Time I 0 TMP_COD 100M MxP_TXCLK Clock Output to MxP_TXD[3:0] and MxP_TXEN Input Delay Time Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 64 Typical 40 Max - Units ns 400 - ns 18 - ns 19.5 - ns - 25 ns Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 12.5.6. RGMII Timing Characteristics Figure 28. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=0) Figure 29. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=2ns) Figure 30. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=0) Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 65 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet Figure 31. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=2ns) Table 45. RGMII Timing Characteristics SYM Description/Condition Type TTX_CYC 125MHz Clock Output. O Refer to Figure 28, page 65. TTX_CYC 25MHz Clock Output. O Refer to Figure 28, page 65. TTX_CYC 2.5MHz Clock Output. O Refer to Figure 28, page 65. TskewT Disable Output Clock Delay. O RGx_TXD[3:0] and RGx_TXCTL to RGx_TXCLK Output Skew (RGx_TXCLK_DELAY=0). Refer to Figure 28, page 65. O RGx_TXD[3:0] and RGx_TXCTL to TTX_SU Enable Output Clock Delay. RGx_TXCLK Output Setup Time (RGx_TXCLK_DELAY=1). Refer to Figure 29, page 65. O RGx_TXD[3:0] and RGx_TXCTL to TTX_HO Enable Output Clock Delay. RGx_TXCLK Output Hold Time (RGx_TXCLK_DELAY=1). Refer to Figure 29, page 65. TRX_SU Disable Input Clock Delay. I RGx_RXD[3:0] and RGx_RXCTL to RGx_RXCLK Input Setup Time (RGx_RXCLK_DELAY=0). Refer to Figure 30, page 65. TRX_HO Disable Input Clock Delay. I RGx_RXD[3:0] and RGx_RXCTL to RGx_RXCLK Input Hold Time (RGx_RXCLK_DELAY=0). Refer to Figure 30, page 65. TskewR Enable Input Clock Delay. I RGx_RXD[3:0] and RGx_RXCTL to RGx_RXCLK Input Skew (RGx_RXCLK_DELAY=1). Refer to Figure 31, page 66. Parameter 1000M RGx_TXCLKc Output Cycle Time 100M RGx_TXCLK Output Cycle Time 10M RGx_TXCLK Output Cycle Time Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 66 Min 7.6 Typical Max 8 8.6 Units ns 38 40 42 ns 380 400 420 ns -500 500 ps 1.2 - ns 1.2 - ns 1.0 - - ns 1.0 - - ns -600 - 600 ps Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367RB-VB Datasheet 12.5.7. HSGMII Characteristics Parameter Unit Interval Eye Mask Eye Mask Eye Mask Eye Mask Output Differential Voltage Output Jitter TJ Table 46. HSGMII Differential Transmitter Characteristics SYM Min Typ Max Units Notes UI 319.968 320 320.032 ps 320ps ± 100ppm T_X1 T_X2 T_Y1 T_Y2 VTX-DIFFp-p TTX-JITTER DJ Minimum TX Eye Width Output Rise Time Output Fall Time Differential Resistance AC Coupling Capacitor Transmit Length in PCB TTX-EYE TTX-RISE TTX-FALL RTX CTX LTX 400 500 - 700 - 0.175 0.39 800 1000 0.3 UI UI mV mV mV UI - - 0.165 UI 0.65 0.125 0.125 80 80 - 100 100 - 120 120 10 TTX-JITTER-MAX = 1 - TTX-EYE-MIN = 0.30UI UI UI 20% ~ 80% UI 20% ~ 80% ohm nF inch - Figure 32. HSGMII Differential Transmitter Eye Diagram Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 67 Track ID: JATR-3375-16 Rev. 0.1 RTL8367RB-VB Datasheet Parameter Unit Interval Eye Mask Eye Mask Eye Mask Eye Mask Input Differential Voltage Minimum RX Eye Width Input Jitter Tolerance Differential Resistance Table 47. HSGMII Differential Receiver Characteristics SYM Min Typ Max Units Notes UI 319.968 320 320.032 ps 320ps ± 100ppm R_X1 0.275 UI R_X2 0.4 UI R_Y1 100 mV R_Y2 800 mV VRX-DIFFp-p 200 1200 mV TRX-EYE 0.4 UI TRX-JITTER 0.6 UI TRX-JITTER-MAX = 1 - TRX-EYE-MIN = 0.6UI RRX 80 100 120 ohm - Figure 33. HSGMII Differential Receiver Eye Diagram Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 68 Track ID: JATR-3375-16 Rev. 0.1 RTL8367RB-VB Datasheet 12.5.8. SGMII Characteristics Parameter Unit Interval Eye Mask Eye Mask Eye Mask Eye Mask Output Differential Voltage Minimum TX Eye Width Output Jitter Data dependent jitter Output Rise Time Output Fall Time Output impedance AC Coupling Capacitor Transmit Length in PCB Table 48. SGMII Differential Transmitter Characteristics SYM Min Typ Max Units Notes UI 799.92 800 800.08 ps 800ps ± 100ppm T_X1 T_X2 T_Y1 T_Y2 VTX-DIFFp-p TTX-EYE TTX-JITTER TTX-RISE TTX-FALL RTX CTX LTX 150 300 0.7 100 100 40 80 - 700 70 100 - 0.15 0.4 400 800 0.3 200 200 140 120 10 UI UI mV mV mV UI UI ps ps ps ohm nF inch TTX-JITTER-MAX = 1 - TTX-EYE-MIN = 0.30UI 20% ~ 80% 20% ~ 80% single-end - Figure 34. SGMII Differential Transmitter Eye Diagram Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 69 Track ID: JATR-3375-16 Rev. 0.1 RTL8367RB-VB Datasheet Parameter Unit Interval Eye Mask Eye Mask Eye Mask Input Differential Voltage Minimum RX Eye Width Input Jitter Tolerance Differential Resistance Table 49. SGMII Differential Receiver Characteristics SYM Min Typ Max Units Notes UI 799.92 800 800.08 ps 800ps ± 100ppm T_X1 0.15 UI T_Y1 100 mV T_Y2 600 mV VRX-DIFFp-p 200 1200 mV TRX-EYE 0.4 UI TRX-JITTER 0.6 UI TRX-JITTER-MAX = 1 - TRX-EYE-MIN = 0.6UI RRX 80 100 120 ohm - Figure 35. SGMII Differential Receiver Eye Diagram Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 70 Track ID: JATR-3375-16 Rev. 0.1 RTL8367S Datasheet 12.6. Power and Reset Characteristics t3 t1 DVDDL AVDDL SVDDL DVDDIO DVDDIO_x SVDDH AVDDH t2 t4 nRESET Figure 36. Power and Reset Characteristics Parameter Reset Delay Time Reset Low Time VDDL Power Rise Settling Time VDDH Power Rise Settling Time Table 50. Power and Reset Characteristics SYM Description/Condition Type t1 I The duration from ‘all power steady’ to the reset signal released to high t2 I The duration of reset signal remaining low time before issuing a reset to the RTL8367S t3 I DVDDL, SVDDL and AVDDL power rise settling time t4 I DVDDIO, DVDDIO_x, SVDDH, and AVDDH power rise settling time Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 71 Min 10 Typical - Max - Units ms 10 - - ms 0.5 - - ms 0.5 - - ms Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 13. Mechanical Dimensions Low Profile Plastic Quad Flat Package 128 Leads 14mm×14mm Outline. Symbol Dimension in mm Nom Max A — 1.60 A1 — 0.15 A2 1.40 1.45 b 0.18 0.23 D/E 16.00BSC D1/E1 14.00BSC e 0.40BSC L 0.45 0.60 0.75 L1 1.00 REF Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MS-026. Min — 0.05 1.35 0.13 Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller Min — 0.002 0.053 0.005 0.018 72 Dimension in inch Nom — — 0.055 0.007 0.630BSC 0.551BSC 0.016BSC 0.024 0.039 REF Max 0.063 0.006 0.057 0.09 0.030 Track ID: xxxx-xxxx-xx Rev. Pre-0.941 RTL8367S Datasheet 14. Ordering Information Table 51. Ordering Information Part Number Package RTL8367S-CG LQFP 128-pin ‘Green’ Package Note: See page 8 for package identification. Status - Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller 73 Track ID: xxxx-xxxx-xx Rev. Pre-0.941