GD32F330K8U6

GigaDevice Semiconductor Inc. GD32F330xx ARM® Cortex®-M4 32-bit MCU Datasheet GD32F330xx Datasheet Table of Contents Table of Contents ........................................................................................................... 1 List of Figures ................................................................................................................ 3 List of Tables .................................................................................................................. 4 1 General description ................................................................................................. 6 2 Device overview ....................................................................................................... 7 3 2.1 Device information ...................................................................................................... 7 2.2 Block diagram .............................................................................................................. 8 2.3 Pinouts and pin assignment ....................................................................................... 9 2.4 Memory map .............................................................................................................. 12 2.5 Clock tree ................................................................................................................... 14 2.6 Pin definitions ............................................................................................................ 15 2.6.1 GD32F330Rx LQFP64 pin definitions .................................................................................. 15 2.6.2 GD32F330Cx LQFP48 pin definitions .................................................................................. 18 2.6.3 GD32F330Kx QFN32 pin definitions .................................................................................... 21 2.6.4 GD32F330Gx QFN28 pin definitions .................................................................................... 24 2.6.5 GD32F330Fx TSSOP20 pin definitions ................................................................................ 26 2.6.6 GD32F330xx pin alternate functions .................................................................................... 28 Functional description .......................................................................................... 32 3.1 ARM® Cortex®-M4 core .............................................................................................. 32 3.2 On-chip memory ........................................................................................................ 32 3.3 Clock, reset and supply management ...................................................................... 33 3.4 Boot modes ................................................................................................................ 33 3.5 Power saving modes ................................................................................................. 34 3.6 Analog to digital converter (ADC) ............................................................................ 34 3.7 DMA ............................................................................................................................ 35 3.8 General-purpose inputs/outputs (GPIOs) ................................................................ 35 3.9 Timers and PWM generation..................................................................................... 35 3.10 Real time clock (RTC) ............................................................................................ 36 3.11 Inter-integrated circuit (I2C) .................................................................................. 37 3.12 Serial peripheral interface (SPI) ............................................................................ 37 3.13 Universal synchronous asynchronous receiver transmitter (USART) ............... 38 1 GD32F330xx Datasheet 4 5 3.14 Debug mode ........................................................................................................... 38 3.15 Package and operation temperature ..................................................................... 38 Electrical characteristics ....................................................................................... 39 4.1 Absolute maximum ratings ....................................................................................... 39 4.2 Operating conditions characteristics ....................................................................... 39 4.3 Power consumption .................................................................................................. 41 4.4 EMC characteristics .................................................................................................. 47 4.5 Power supply supervisor characteristics ................................................................ 48 4.6 Electrical sensitivity .................................................................................................. 49 4.7 External clock characteristics .................................................................................. 49 4.8 Internal clock characteristics ................................................................................... 51 4.9 PLL characteristics.................................................................................................... 52 4.10 Memory characteristics ......................................................................................... 53 4.11 NRST pin characteristics ....................................................................................... 53 4.12 GPIO characteristics .............................................................................................. 54 4.13 ADC characteristics ............................................................................................... 55 4.14 Temperature sensor characteristics ..................................................................... 57 4.15 I2C characteristics ................................................................................................. 57 4.16 SPI characteristics ................................................................................................. 58 4.17 USART characteristics ........................................................................................... 59 4.18 TIMER characteristics ............................................................................................ 59 4.19 WDGT characteristics ............................................................................................ 59 4.20 Parameter conditions............................................................................................. 60 Package information.............................................................................................. 61 5.1 LQFP64 package outline dimensions....................................................................... 61 5.2 LQFP48 package outline dimensions....................................................................... 63 5.3 QFN32 package outline dimensions ........................................................................ 64 5.4 QFN28 package outline dimensions ........................................................................ 65 5.5 TSSOP20 package outline dimensions .................................................................... 66 6 Ordering information ............................................................................................. 67 7 Revision history ..................................................................................................... 68 2 GD32F330xx Datasheet List of Figures Figure 2-1. GD32F330xx block diagram ............................................................................................................... 8 Figure 2-2. GD32F330Rx LQFP64 pinouts ........................................................................................................... 9 Figure 2-3. GD32F330Cx LQFP48 pinouts ........................................................................................................... 9 Figure 2-4. GD32F330Kx QFN32 pinouts ........................................................................................................... 10 Figure 2-5. GD32F330Gx QFN28 pinouts........................................................................................................... 10 Figure 2-6. GD32F330Fx TSSOP20 pinouts ...................................................................................................... 11 Figure 2-7. GD32F330xx clock tree ..................................................................................................................... 14 Figure 4-1. Recommended power supply decoupling capacitors (1) (2)....................................................... 39 Figure 4-2. Typical supply current consumption in Run mode ................................................................... 45 Figure 4-3. Typical supply current consumption in Sleep mode ................................................................ 46 Figure 4-4. Recommended external NRST pin circuit .................................................................................... 54 Figure 4-5. I/O port AC characteristics definition............................................................................................ 55 Figure 5-1. LQFP64 package outline .................................................................................................................. 61 Figure 5-2. LQFP48 package outline .................................................................................................................. 63 Figure 5-3. QEN32 package outline .................................................................................................................... 64 Figure 5-4. QFN28 package outline ..................................................................................................................... 65 Figure 5-5. TSSOP20 package outline ................................................................................................................ 66 3 GD32F330xx Datasheet List of Tables Table 2-1. GD32F330xx devices features and peripheral list ......................................................................... 7 Table 2-2. GD32F330xx memory map ................................................................................................................. 12 Table 2-3. GD32F330Rx LQFP64 pin definitions .............................................................................................. 15 Table 2-4. GD32F330Cx LQFP48 pin definitions .............................................................................................. 18 Table 2-5. GD32F330Kx QFP32 pin definitions ................................................................................................ 21 Table 2-6. GD32F330Gx QFN28 pin definitions ................................................................................................ 24 Table 2-7. GD32F330Fx TSSOP20 pin definitions ........................................................................................... 26 Table 2-8. Port A alternate functions summary ............................................................................................... 28 Table 2-9. Port B alternate functions summary ............................................................................................... 29 Table 2-10. Port C alternate functions summary ............................................................................................. 30 Table 2-11. Port D alternate functions summary ............................................................................................. 30 Table 2-12. Port F alternate functions summary ............................................................................................. 31 Table 4-1. Absolute maximum ratings(1) (4) ......................................................................................................... 39 Table 4-2. DC operating conditions..................................................................................................................... 39 Table 4-3. Clock frequency .................................................................................................................................... 40 Table 4-4. Operating conditions at Power up/ Power down(1) ...................................................................... 40 Table 4-5. Start-up timings of Operating conditions (1) (2) (3) ........................................................................... 40 Table 4-6. Power saving mode wakeup timings characteristics(1) (2) .......................................................... 40 Table 4-7.Power consumption characteristics(1) (2) (3) (3) (4) (5) .......................................................................... 41 Table 4-8. Peripheral current consumption characteristics (1) ..................................................................... 46 Table 4-9. EMS characteristics(1) ......................................................................................................................... 47 Table 4-10. Power supply supervisor characteristics .................................................................................... 48 Table 4-11. ESD characteristics (1) ....................................................................................................................... 49 Table 4-12. Static latch-up characteristics (1) .................................................................................................... 49 Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics .. 49 Table 4-14. High speed external user clock characteristics (HXTAL in bypass mode) ......................... 49 Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ... 50 Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode) .......................... 50 Table 4-17. High speed internal clock (IRC8M) characteristics ................................................................... 51 Table 4-18. Low speed internal clock (IRC40K) characteristics .................................................................. 51 Table 4-19. High speed internal clock (IRC28M) characteristics ................................................................. 51 Table 4-20. High speed internal clock (IRC48M) characteristics ................................................................. 52 Table 4-21. PLL characteristics ............................................................................................................................ 52 Table 4-22 Flash memory characteristics.......................................................................................................... 53 Table 4-23. NRST pin characteristics ................................................................................................................. 53 Table 4-24. I/O port DC characteristics .............................................................................................................. 54 Table 4-25. I/O port AC characteristics (1) (2) ....................................................................................................... 55 Table 4-26. ADC characteristics .......................................................................................................................... 55 Table 4-27. ADC RAIN max for fADC = 40 MHz (1).................................................................................................. 56 Table 4-28. ADC dynamic accuracy at fADC = 28 MHz (1) ................................................................................. 56 4 GD32F330xx Datasheet Table 4-29. ADC dynamic accuracy at fADC = 30 MHz Table 4-30.ADC dynamic accuracy at fADC = 36 MHz Table 4-31. ADC static accuracy at fADC = 14 MHz Table 4-32. Temperature sensor characteristics (1) (1) (1) (1) ................................................................................. 57 .................................................................................. 57 ....................................................................................... 57 ......................................................................................... 57 Table 4-33. I2C characteristics (1) (2) (3) ................................................................................................................. 57 Table 4-34. Standard SPI characteristics (1) ...................................................................................................... 58 Table 4-35. USART characteristics (1) ................................................................................................................. 59 Table 4-36. TIMER characteristics (1) ................................................................................................................... 59 Table 4-37. FWDGT min/max timeout period at 40 kHz (IRC40K) (1) ............................................................ 59 Table 4-38. WWDGT min-max timeout value at 84 MHz (fPCLK1) (1) ............................................................... 60 Table 5-1. LQFP64 package dimensions ........................................................................................................... 61 Table 5-2. LQFP48 package dimensions ........................................................................................................... 63 Table 5-3. QFN32 package dimensions .............................................................................................................. 64 Table 5-4. QFN28 package dimensions .............................................................................................................. 65 Table 5-5. TSSOP20 package dimensions ......................................................................................................... 66 Table 6-1. Part ordering code for GD32F330xx devices ................................................................................ 67 Table 7-1. Revision history ................................................................................................................................... 68 5 GD32F330xx Datasheet 1 General description The GD32F330xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best costperformance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a powerful trace technology for enhanced application security and advanced debug support. The GD32F330xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 84 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, up to five general 16-bit timers, a general 32-bit timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F330xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. 6 GD32F330xx Datasheet 2 Device overview 2.1 Device information Table 2-1. GD32F330xx devices features and peripheral list GD32F330xx Part Number F4 F6 F8 G4 G6 G8 K4 K6 K8 C4 C6 C8 CB R8 RB 16 32 64 16 32 64 16 32 64 16 32 64 64 64 64 0 0 0 0 0 0 0 0 0 0 0 0 64 0 64 16 32 64 16 32 64 16 32 64 16 32 64 128 64 128 4 4 8 4 4 8 4 4 8 4 4 8 16 16 16 Genaral timer 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (32-bit) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) Genaral timer 4 4 4 4 4 5 4 4 5 4 4 5 5 5 5 (16-bit) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13-16) (2,13,15,16) (2,13,15,16) (2,13-16) (2,13,15,16) (2,13,15,16) (2,13-16) (2,13-16) (2,13-16) (2,13-16) Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 timer (16-bit) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) SysTick 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 (0) (0-1) (0-1) (0) (0-1) (0-1) (0) (0-1) (0-1) (0) (0-1) (0-1) (0-1) (0-1) (0-1) 1 1 2 1 1 2 1 1 2 1 1 2 2 2 2 (0) (0) (0-1) (0) (0) (0-1) (0) (0) (0-1) (0) (0) (0-1) (0-1) (0-1) (0-1) 1 1 2 1 1 2 1 1 2 1 1 2 2 2 2 (0) (0) (0-1) (0) (0) (0-1) (0) (0) (0-1) (0) (0) (0-1) (0-1) (0-1) (0-1) GPIO 15 15 15 23 23 23 27 27 27 39 39 39 39 55 55 EXTI 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Units 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Channels (External) 9 9 9 10 10 10 10 10 10 10 10 10 10 16 16 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Code area Flash (KB) Data area (KB) Total (KB) Connectivity Timers SRAM (KB) USART I2C ADC SPI Channels (Internal) Package TSSOP20 QFN28 QFN32 LQFP48 LQFP64 7 GD32F330xx Datasheet 2.2 Block diagram Figure 2-1. GD32F330xx block diagram LDO 1.2V TPIU SW AHB Matrix NVIC ICode DCode System ARM Cortex-M4 Processor Fmax: 84MHz AHB2: Fma x = 84MHz IBus GPIO Ports A, B, C, D, F SRAM Controller SRAM Flash Memory Controller Flash Memory POR/PDR LVD PLL Fmax: 84MHz HXTAL 4-32MHz DBus GP DMA 7chs AHB1: Fma x = 84MHz AHB to APB Bridge 2 CRC AHB to APB Bridge 1 IRC8M 8MHz RST/CLK Controller IRC48M 48MHz Powered by LDO (1.2V) PMU EXTI FWDGT 12-bit SAR ADC IRC28M 28MHz ADC RTC I2C0 SPI0 TIMER16 APB1: Fmax = 42MHz TIMER15 APB2: Fmax = 42MHz TIMER14 Powered by V DD/VDDA WWDGT USART0 TIMER0 IRC40K 40KHz I2C1 CTC USART1 SPI1 TIMER1 TIMER2 TIMER13 8 GD32F330xx Datasheet 2.3 Pinouts and pin assignment Figure 2-2. GD32F330Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 PC13 2 47 PF6 PC14-OSC32IN 3 46 PA13 PC15-OSC32OUT PF0-OSCIN 4 45 PA12 5 44 PA11 PF1-OSCOUT 6 43 PA10 NRST 7 42 PA9 PC0 8 PC1 9 PC2 PC3 VSSA GigaDevice GD32F330Rx LQFP64 PF7 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS VDD PB11 PB10 PB2 PB1 PB0 PC5 PA7 PC4 PA6 PA5 PA4 PF5 PF4 PA3 Figure 2-3. GD32F330Cx LQFP48 pinouts PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 48 47 46 45 44 43 42 41 40 39 38 37 VBAT 1 36 PF7 PC13 2 35 PF6 PC14-OSC32IN 3 34 PA13 PC15-OSC32OUT PF0-OSCIN 4 33 PA12 5 32 PA11 PF1-OSCOUT NRST VSSA 6 31 PA10 30 PA9 8 29 VDDA 9 28 PA8 PB15 PA0 10 27 PB14 PA1 PA2 11 26 PB13 25 PB12 GigaDevice GD32F330Cx LQFP48 7 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD VSS PB11 PB10 PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 9 GD32F330xx Datasheet Figure 2-4. GD32F330Kx QFN32 pinouts PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 VDD 1 32 31 30 29 28 27 26 25 24 PA14 OSCIN/PF0 2 23 PA13 OSCOUT/PF1 NRST 3 22 PA12 21 PA11 VDDA PA0 5 PA1 7 PA2 8 GigaDevice GD32F330Kx QFN32 4 6 VSS, VSSA 20 PA10 19 PA9 18 PA8 17 VDD 9 10 11 12 13 14 15 16 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 Figure 2-5. GD32F330Gx QFN28 pinouts PB3 PA14 PA15 PB4 PB5 PB6 PB7 28 27 26 25 24 23 22 1 21 2 20 PA13 OSCOUT/PF1 NRST 3 19 PA9 18 PA8 VDDA PA0 5 17 VDD 6 16 PA1 7 15 VSS PB1 BOOT0 OSCIN/PF0 GigaDevice GD32F330Gx QFN28 4 8 9 10 11 12 13 14 PA10 PA7 PB0 PA6 PA5 PA4 PA3 PA2 10 GD32F330xx Datasheet Figure 2-6. GD32F330Fx TSSOP20 pinouts 1 20 PA14 OSCIN/PF0 2 19 PA13 OSCOUT/PF1 3 18 PA10 NRST 4 17 PA9 VDDA 5 PA0 6 GigaDevice 16 GD32F330Fx TSSOP20 15 PA1 7 14 PA2 8 13 PA7 PA3 9 12 PA6 PA4 10 11 PA5 BOOT0 VDD Vss PB1 11 GD32F330xx Datasheet 2.4 Memory map Table 2-2. GD32F330xx memory map Pre-defined Address Peripherals 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals External Device 0xA000 0000 - 0xDFFF FFFF Reserved External RAM 0x6000 0000 - 0x9FFF FFFF Reserved 0x5004 0000 - 0x5FFF FFFF Reserved 0x5000 0000 - 0x5003 FFFF Reserved 0x4800 1800 - 0x4FFF FFFF Reserved 0x4800 1400 - 0x4800 17FF GPIOF 0x4800 1000 - 0x4800 13FF Reserved 0x4800 0C00 - 0x4800 0FFF GPIOD 0x4800 0800 - 0x4800 0BFF GPIOC 0x4800 0400 - 0x4800 07FF GPIOB 0x4800 0000 - 0x4800 03FF GPIOA 0x4002 4400 - 0x47FF FFFF Reserved 0x4002 4000 - 0x4002 43FF Reserved 0x4002 3400 - 0x4002 3FFF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1400 - 0x4002 1FFF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0400 - 0x4002 0FFF Reserved 0x4002 0000 - 0x4002 03FF DMA 0x4001 8000 - 0x4001 FFFF Reserved 0x4001 5C00 - 0x4001 7FFF Reserved 0x4001 4C00 - 0x4001 5BFF Reserved 0x4001 4800 - 0x4001 4BFF TIMER16 0x4001 4400 - 0x4001 47FF TIMER15 0x4001 4000 - 0x4001 43FF TIMER14 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF ADC 0x4001 0800 - 0x4001 23FF Reserved 0x4001 0400 - 0x4001 07FF EXTI Regions Bus AHB1 AHB2 AHB1 Peripherals APB2 12 GD32F330xx Datasheet Pre-defined Regions Bus APB1 SRAM Code Address Peripherals 0x4001 0000 - 0x4001 03FF SYSCFG 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF CTC 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF Reserved 0x4000 7000 - 0x4000 73FF PMU 0x4000 6400 - 0x4000 6FFF Reserved 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 4800 - 0x4000 53FF Reserved 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF Reserved 0x4000 3800 - 0x4000 3BFF SPI1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1400 - 0x4000 1FFF Reserved 0x4000 1000 - 0x4000 13FF Reserved 0x4000 0800 - 0x4000 0FFF Reserved 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2000 4000 - 0x3FFF FFFF Reserved 0x2000 0000 - 0x2000 3FFF SRAM 0x1FFF FC00 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF FBFF Option bytes 0x1FFF EC00 - 0x1FFF F7FF System memory 0x0802 0000 - 0x1FFF EBFF Reserved 0x0800 0000 - 0x0801 FFFF Main Flash memory 0x0010 0000 - 0x07FF FFFF Reserved 0x0000 0000 - 0x000F FFFF Aliased to Flash or system memory 13 GD32F330xx Datasheet 2.5 Clock tree Figure 2-7. GD32F330xx clock tree CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable ( by hardware) ( to FMC) HCLK CK_IRC8M 00 8 MHz IRC8M 0 /2 1 ×2,3,4 …,64 PLL CK_PLL 10 AHB enable CK_SYS 84 MHz max AHB Prescaler ÷1,2... 512 ( to AHB bus, Cortex-M4, SRAM, DMA) CK_ CST CK_ AHB ÷8 84 MHz max ( to Cortex-M 4 SysTick) FCLK PLLMF PREDV PLLSEL PLLPRESEL CK_IRC48M 01 1 4- 32 MHz HXTAL Clock Monitor ÷1,2. ..16 0 CK_HXTAL /32 ( free running clock) TIMER1,2,13 APB1 Prescaler ÷1,2,4,8,16 11 CK_TIMERx ÷[APB1 prescaler/2] TIMERx enable to TIMER1,2,13 CK_ APB1 PCLK1 42 MHz max to APB1 peripherals Peripheral enable 32. 768 KHz LXTAL CK_ RTC 01 ( to RTC) 10 40 KHz IRC40K RTCSRC[1:0] CK_FWDGT ( to FWDGT) TIMER0,14,1 5,16 ÷[APB2 prescaler/2] APB2 Prescaler ÷1,2,4,8,16 CK_TIMERx TIMERx enable to TIMER0,14,15,16 CK_ APB2 PCLK2 to APB2 peripherals 42 MHz max Peripheral enable CK_ OUT ÷1,2,4... ,128 CKOUTDIV 0 CK_IRC28M CK_IRC40K CK_ LXTAL CK_ SYS CK_IRC8M CK_ HXTAL /1,2 CK_PLL ADC Prescaler ÷2,3 ...9 1 CK_ ADC to ADC 0 40 MHz max ADCSEL 28 MHz IRC28M ÷1, 2 CK_IRC8M 11 CK_L XTAL 10 CK_ SYS 01 CK_ USART0 to USART0 00 Note: If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1. Otherwise, they are set to the AHB frequency divide by half of APB prescaler. Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC8M: Internal 8M RC oscillators IRC40K: Internal 40K RC oscillator IRC28M: Internal 28M RC oscillators 14 GD32F330xx Datasheet 2.6 Pin definitions 2.6.1 GD32F330Rx LQFP64 pin definitions Table 2-3. GD32F330Rx LQFP64 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins VBAT 1 P 2 I/O 3 I/O 4 I/O 5 I/O Default: VBAT PC13TAMPER- Functions description Default: PC13 Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1 RTC PC14OSC32IN PC15OSC32OUT Default: PC14 Additional: OSC32IN Default: PC15 Additional: OSC32OUT Default: PF0 PF0-OSCIN 5VT Alternate: CTC_SYNC Additional: OSCIN PF1OSCOUT NRST 6 I/O 7 I/O 5VT Default: PF1 Additional: OSCOUT Default: NRST Default: PC0 PC0 8 I/O Alternate: EVENTOUT Additional: ADC_IN10 Default: PC1 PC1 9 I/O Alternate: EVENTOUT Additional: ADC_IN11 Default: PC2 PC2 10 I/O Alternate: EVENTOUT Additional: ADC_IN12 Default: PC3 PC3 11 I/O Alternate: EVENTOUT Additional: ADC_IN13 VSSA 12 P Default: VSSA VDDA 13 P Default: VDDA Default: PA0 PA0-WKUP 14 I/O Alternate: USART1_CTS, TIMER1_CH0, TIMER1_ETI, I2C1_SCL Additional: ADC_IN0, RTC_TAMP1, WKUP0 Default: PA1 PA1 15 I/O Alternate: USART1_RTS, TIMER1_CH1, I2C1_SDA, EVENTOUT Additional: ADC_IN1 PA2 16 I/O Default: PA2 Alternate: USART1_TX, TIMER1_CH2, TIMER14_CH0 15 GD32F330xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Additional: ADC_IN2 Default: PA3 PA3 17 Alternate: USART1_RX, TIMER1_CH3, TIMER14_CH1 I/O Additional: ADC_IN3 PF4 18 I/O 5VT PF5 19 I/O 5VT Default: PF4 Alternate: EVENTOUT Default: PF5 Alternate: EVENTOUT Default: PA4 PA4 20 Alternate: SPI0_NSS, USART1_CK, TIMER13_CH0, I/O SPI1_NSS Additional: ADC_IN4 Default: PA5 PA5 21 Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI I/O Additional: ADC_IN5 Default: PA6 PA6 22 Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, I/O TIMER15_CH0, EVENTOUT Additional: ADC_IN6 Default: PA7 PA7 23 Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, I/O TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 Default: PC4 PC4 24 Alternate: EVENTOUT I/O Additional: ADC_IN14 PC5 25 Default: PC5 I/O Additional: ADC_IN15, WKUP4 Default: PB0 PB0 26 Alternate: TIMER2_CH2, TIMER0_CH1_ON, I/O USART1_RX(4), EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 27 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK Additional: ADC_IN9 PB2 28 I/O 5VT PB10 29 I/O 5VT Default: PB2 Default: PB10 Alternate: I2C1_SCL, TIMER1_CH2, SPI1_IO2 Default: PB11 PB11 30 I/O 5VT Alternate:I2C1_SDA, TIMER1_CH3, EVENTOUT, SPI1_IO3 VSS 31 P Default: VSS VDD 32 P Default: VDD PB12 33 I/O 5VT Default: PB12 16 GD32F330xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: SPI1_NSS, TIMER0_BKIN, I2C1_SMBA, EVENTOUT PB13 34 I/O 5VT Default: PB13 Alternate: SPI1_SCK, TIMER0_CH0_ON Default: PB14 PB14 35 I/O 5VT Alternate: SPI1_MISO, TIMER0_CH1_ON, TIMER14_CH0 Default: PB15 Alternate: SPI1_MOSI, TIMER0_CH2_ON, PB15 36 I/O 5VT TIMER14_CH0_ON, TIMER14_CH1 Additional: RTC_REFIN, WKUP6 PC6 37 I/O 5VT PC7 38 I/O 5VT PC8 39 I/O 5VT PC9 40 I/O 5VT PA8 41 I/O 5VT Default: PC6 Alternate: TIMER2_CH0 Default: PC7 Alternate: TIMER2_CH1 Default: PC8 Alternate: TIMER2_CH2 Default: PC9 Alternate: TIMER2_CH3 Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX, EVENTOUT,CTC_SYNC Default: PA9 PA9 42 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL Default: PA10 PA10 43 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN, I2C0_SDA Default: PA11 PA11 44 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT, SPI1_IO2 Default: PA12 PA12 45 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3 PA13 46 I/O 5VT PF6 47 I/O 5VT PF7 48 I/O 5VT PA14 49 I/O 5VT Default: PA13 Alternate: IFRP_OUT, SWDIO, SPI1_MISO Default: PF6 Alternate: I2C1_SCL Default: PF7 Alternate: I2C1_SDA Default: PA14 Alternate: USART1_TX, SWCLK, SPI1_MOSI Default: PA15 PA15 50 I/O 5VT Alternate: SPI0_NSS , USART1_RX, TIMER1_CH0, TIMER1_ETI, SPI1_NSS, EVENTOUT 17 GD32F330xx Datasheet Pin I/O Type(1) Level(2) 51 I/O 5VT Default: PC10 PC11 52 I/O 5VT Default: PC11 PC12 53 I/O 5VT Default: PC12 PD2 54 I/O 5VT PB3 55 I/O 5VT PB4 56 I/O 5VT Pin Name Pins PC10 Functions description Default: PD2 Alternate: TIMER2_ETI Default: PB3 Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT Default: PB4 Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT Default: PB5 PB5 57 I/O 5VT Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1 Additional:WKUP5 PB6 58 I/O 5VT PB7 59 I/O 5VT BOOT0 60 I PB8 61 I/O Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON Default: BOOT0 5VT Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 Default: PB9 PB9 62 I/O 5VT Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0, EVENTOUT VSS 63 P Default: VSS VDD 64 P Default: VDD Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32F330C4 devices only. (4) Functions are available on GD32F330CB/8/6 devices. (5) Functions are available on GD32F330CB/8 devices. 2.6.2 GD32F330Cx LQFP48 pin definitions Table 2-4. GD32F330Cx LQFP48 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins VBAT 1 P 2 I/O 3 I/O PC13TAMPERRTC PC14OSC32IN Functions description Default: VBAT Default: PC13 Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1 Default: PC14 Additional: OSC32IN 18 GD32F330xx Datasheet Pin Name PC15OSC32OUT Pins 4 Pin I/O Type(1) Level(2) Functions description Default: PC15 I/O Additional: OSC32OUT Default: PF0 PF0-OSCIN 5 I/O 5VT Alternate: CTC_SYNC Additional: OSCIN PF1- I/O NRST 7 I/O VSSA 8 P Default: VSSA VDDA 9 P Default: VDDA OSCOUT 5VT Default: PF1 6 Additional: OSCOUT Default: NRST Default: PA0 PA0-WKUP 10 I/O Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5) Additional: ADC_IN0, RTC_TAMP1, WKUP0 Default: PA1 PA1 11 I/O Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT Additional: ADC_IN1 Default: PA2 PA2 12 I/O Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 Additional: ADC_IN2 Default: PA3 PA3 13 I/O Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1 Additional: ADC_IN3 Default: PA4 PA4 14 I/O Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4 Default: PA5 PA5 15 I/O Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI Additional: ADC_IN5 Default: PA6 PA6 16 I/O Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT Additional: ADC_IN6 Default: PA7 PA7 17 I/O Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 Default: PB0 PB0 18 I/O Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT Additional: ADC_IN8 19 GD32F330xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PB1 PB1 19 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 PB2 20 I/O 5VT PB10 21 I/O 5VT Default: PB2 Default: PB10 Alternate: I2C0_SCL(3),I2C1_SCL(5), TIMER1_CH2, SPI1_IO2(5) Default: PB11 PB11 22 I/O 5VT Alternate: I2C0_SDA(3),I2C1_SDA(5), TIMER1_CH3, EVENTOUT, SPI1_IO3(5) VSS 23 P Default: VSS VDD 24 P Default: VDD Default: PB12 PB12 25 I/O 5VT Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BKIN, I2C1_SMBA(5), EVENTOUT PB13 26 I/O 5VT PB14 27 I/O 5VT Default: PB13 Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON Default: PB14 Alternate: SPI0_MISO(3), SPI1_MISO(5), TIMER0_CH1_ON, TIMER14_CH0 Default: PB15 Alternate: SPI0_MOSI(3), SPI1_MOSI(5), PB15 28 I/O 5VT TIMER0_CH2_ON, TIMER14_CH0_ON, TIMER14_CH1 Additional: RTC_REFIN, WKUP6 Default: PA8 PA8 29 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT,CTC_SYNC Default: PA9 PA9 30 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL Default: PA10 PA10 31 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN, I2C0_SDA Default: PA11 PA11 32 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT, SPI1_IO2(5) Default: PA12 PA12 33 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5) PA13 34 I/O 5VT PF6 35 I/O 5VT Default: PA13 Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5) Default: PF6 Alternate: I2C0_SCL(3), I2C1_SCL(5) 20 GD32F330xx Datasheet Pin Name Pins PF7 36 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PF7 Alternate: I2C0_SDA(3), I2C1_SDA(5) Default: PA14 PA14 37 I/O 5VT Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) Default: PA15 PA15 38 I/O 5VT Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT PB3 39 I/O 5VT PB4 40 I/O 5VT Default: PB3 Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT Default: PB4 Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT Default: PB5 PB5 41 I/O 5VT Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1 Additional:WKUP5 PB6 42 I/O 5VT PB7 43 I/O 5VT BOOT0 44 I PB8 45 I/O Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON Default: BOOT0 5VT Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 Default: PB9 PB9 46 I/O 5VT Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0, EVENTOUT VSS 47 P Default: VSS VDD 48 P Default: VDD Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32F330C4 devices only. (4) Functions are available on GD32F330CB/8/6 devices. (5) Functions are available on GD32F330CB/8 devices. 2.6.3 GD32F330Kx QFN32 pin definitions Table 2-5. GD32F330Kx QFP32 pin definitions Pin Name Pins PF0-OSCIN 2 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PF0 Alternate: CTC_SYNC Additional: OSCIN 21 GD32F330xx Datasheet Pin I/O Type(1) Level(2) 3 I/O 5VT NRST 4 I/O VDDA 5 P Pin Name PF1OSCOUT Pins Functions description Default: PF1 Additional: OSCOUT Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 Alternate: USART0_CTS(3), USART1_CTS(4), I/O TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5) Additional: ADC_IN0, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 Alternate: USART0_RTS(3), USART1_RTS(4), I/O TIMER1_CH1, I2C1_SDA(5), EVENTOUT Additional: ADC_IN1 Default: PA2 PA2 8 Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, I/O TIMER14_CH0 Additional: ADC_IN2 Default: PA3 PA3 9 Alternate: USART0_RX(3), USART1_RX(4), I/O TIMER1_CH3, TIMER14_CH1 Additional: ADC_IN3 Default: PA4 PA4 10 Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), I/O TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4 Default: PA5 PA5 11 Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI I/O Additional: ADC_IN5 Default: PA6 PA6 12 Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, I/O TIMER15_CH0, EVENTOUT Additional: ADC_IN6 Default: PA7 PA7 13 Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, I/O TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 Default: PB0 PB0 14 Alternate: TIMER2_CH2, TIMER0_CH1_ON, I/O USART1_RX(4), EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 15 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 PB2 16 I/O VDD 17 P 5VT Default: PB2 Default: VDD 22 GD32F330xx Datasheet Pin Name Pins PA8 18 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT,CTC_SYNC Default: PA9 PA9 19 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL Default: PA10 PA10 20 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN, I2C0_SDA Default: PA11 PA11 21 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT, SPI1_IO2(5) Default: PA12 PA12 22 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5) PA13 23 I/O 5VT PA14 24 I/O 5VT Default: PA13 Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) Default: PA15 PA15 25 I/O 5VT Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT PB3 26 I/O 5VT PB4 27 I/O 5VT Default: PB3 Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT Default: PB4 Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT Default: PB5 PB5 28 I/O 5VT Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1 Additional:WKUP5 PB6 29 I/O 5VT PB7 30 I/O 5VT BOOT0 31 I PB8 32 I/O VDD 1 P Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON Default: BOOT0 5VT Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 Default: VDD Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32F330K4 devices only. (4) Functions are available on GD32F330KB/8/6 devices. 23 GD32F330xx Datasheet (5) Functions are available on GD32F330KB/8 devices. 2.6.4 GD32F330Gx QFN28 pin definitions Table 2-6. GD32F330Gx QFN28 pin definitions Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PF0 PF0-OSCIN 2 I/O 5VT Alternate: CTC_SYNC Additional: OSCIN PF1- 3 I/O NRST 4 I/O VDDA 5 P OSCOUT 5VT Default: PF1 Additional: OSCOUT Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5) Additional: ADC_IN0, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT Additional: ADC_IN1 Default: PA2 PA2 8 I/O Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 Additional: ADC_IN2 Default: PA3 PA3 9 I/O Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1 Additional: ADC_IN3 Default: PA4 PA4 10 I/O Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4 Default: PA5 PA5 11 I/O Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI Additional: ADC_IN5 Default: PA6 PA6 12 I/O Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT Additional: ADC_IN6 Default: PA7 PA7 13 I/O Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 PB0 14 I/O Default: PB0 Alternate: TIMER2_CH2, TIMER0_CH1_ON, 24 GD32F330xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description USART1_RX, EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 15 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 VSS 16 P Default: VSS VDD 17 P Default: VDD PA8 18 I/O Default: PA8 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX, EVENTOUT,CTC_SYNC Default: PA9 PA9 19 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL Default: PA10 PA10 20 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN, I2C0_SDA PA13 21 I/O 5VT PA14 22 I/O 5VT Default: PA13 Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) Default: PA15 PA15 23 I/O 5VT Alternate: SPI0_NSS , USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT PB3 24 I/O 5VT PB4 25 I/O 5VT Default: PB3 Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT Default: PB4 Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT Default: PB5 PB5 26 I/O 5VT Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1 Additional:WKUP5 PB6 27 I/O 5VT PB7 28 I/O 5VT BOOT0 1 I Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON Default: BOOT0 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32F330G4 devices only. (4) Functions are available on GD32F330GB/8/6 devices. (5) Functions are available on GD32F330GB/8 devices. 25 GD32F330xx Datasheet 2.6.5 GD32F330Fx TSSOP20 pin definitions Table 2-7. GD32F330Fx TSSOP20 pin definitions Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PF0 PF0-OSCIN 2 I/O 5VT Alternate: CTC_SYNC Additional: OSCIN PF1- 3 I/O NRST 4 I/O VDDA 5 P OSCOUT 5VT Default: PF1 Additional: OSCOUT Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, I2C1_SCL(5) Additional: ADC_IN0, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, I2C1_SDA(5), EVENTOUT Additional: ADC_IN1 Default: PA2 PA2 8 I/O Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, TIMER14_CH0 Additional: ADC_IN2 Default: PA3 PA3 9 I/O Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, TIMER14_CH1 Additional: ADC_IN3 Default: PA4 PA4 10 I/O Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4 Default: PA5 PA5 11 I/O Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI Additional: ADC_IN5 Default: PA6 PA6 12 I/O Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, EVENTOUT Additional: ADC_IN6 Default: PA7 PA7 13 I/O Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 Default: PB1 PB1 14 I/O Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 26 GD32F330xx Datasheet Pin I/O Type(1) Level(2) Pin Name Pins Functions description VSS 15 P Default: VSS VDD 16 P Default: VDD PA9 17 I/O Default: PA9 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN , I2C0_SCL Default: PA10 PA10 18 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN, I2C0_SDA PA13 19 I/O 5VT PA14 20 I/O 5VT Default: PA13 Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) BOOT0 1 I Default: BOOT0 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32F330F4 devices only. (4) Functions are available on GD32F330FB/8/6 devices. (5) Functions are available on GD32F330FB/8 devices. 27 GD32F330xx Datasheet 2.6.6 GD32F330xx pin alternate functions Table 2-8. Port A alternate functions summary Pin Name AF0 PA2 PA3 AF2 AF3 USART0_CTS(1) TIMER1_CH0 PA0 PA1 AF1 USART0_RTS(1) USART1_RTS(2) TIMER14_CH USART0_TX(1) 0 USART1_TX(2) TIMER14_CH USART0_RX(1) 1 USART1_RX(2) TIMER1_CH2 TIMER1_CH3 USART0_CK(1) TIMER13_C SPI1_NSS(3 USART1_CK(2) H0 ) SPI0_NSS PA5 SPI0_SCK PA6 SPI0_MISO TIMER2_CH0 TIMER0_BKIN PA7 SPI0_MOSI TIMER2_CH1 PA8 CK_OUT USART0_CK TIMER0_CH0 USART0_TX TIMER0_CH1 I2C0_SCL USART0_RX TIMER0_CH2 I2C0_SDA PA10 TIMER14_BK IN TIMER16_BK IN AF6 I2C1_SDA(3) TIMER1_CH1 PA4 PA9 AF5 I2C1_SCL(3) USART1_CTS(2) TIMER1_ETI EVENTOUT AF4 TIMER1_CH0/ TIMER1_ETI TIMER15 _CH0 TIMER0_CH0_ TIMER13_C TIMER16 ON H0 EVENTOU USART1_TX T (2) _CH0 EVENTOUT EVENTOUT CTC_SYNC PA11 EVENTOUT USART0_CTS TIMER0_CH3 SPI1_IO2(3) PA12 EVENTOUT USART0_RTS SPI1_IO3(3) PA13 SWDIO PA14 SWCLK PA15 SPI0_NSS TIMER0_ETI SPI1_MISO( IFRP_OUT 3) USART0_TX(1) SPI1_MOSI( USART1_TX(2) 3) USART0_RX(1) TIMER1_CH0/ EVENTOU USART1_RX(2) TIMER1_ETI T SPI1_NSS(3 ) 28 GD32F330xx Datasheet Table 2-9. Port B alternate functions summary Pin Name PB0 PB1 AF0 AF1 AF2 AF3 0 AF5 AF6 USART1_ EVENTOUT TIMER2_CH2 TIMER0_CH1_ON TIMER13_CH AF4 RX(2) SPI1_SCK(3 TIMER2_CH3 TIMER0_CH2_ON ) PB2 PB3 SPI0_SCK EVENTOUT TIMER1_CH1 PB4 SPI0_MISO TIMER2_CH0 EVENTOUT PB5 SPI0_MOSI TIMER2_CH1 TIMER15_BKIN TIMER15_CH0_O PB6 USART0_TX I2C0_SCL PB7 USART0_RX I2C0_SDA PB8 I2C0_SCL TIMER15_CH0 I2C0_SDA TIMER16_CH0 PB9 IFRP_OUT I2C0_SCL(1), PB10 I2C1_SCL(3) PB11 EVENTOUT PB12 PB13 PB14 PB15 SPI0_NSS(1) SPI1_NSS(3) SPI0_SCK(1) SPI1_SCK(3) SPI0_MISO(1) SPI1_MISO(3) SPI0_MOSI(1) SPI1_MOSI(3) I2C0_SDA(1), I2C1_SDA(3) EVENTOUT I2C0_SMBA N TIMER16_CH0_O N EVENTOUT TIMER1_CH2 SPI1_IO2(3) TIMER1_CH3 SPI1_IO3(3) I2C1_SM TIMER0_BKIN BA(3) TIMER0_CH0_ON TIMER14_CH0 TIMER0_CH1_ON TIMER14_CH1 TIMER0_CH2_ON TIMER14_CH0 _ON 29 GD32F330xx Datasheet Table 2-10. Port C alternate functions summary Pin Name AF0 PC0 EVENTOUT PC1 EVENTOUT PC2 EVENTOUT PC3 EVENTOUT PC4 EVENTOUT AF1 AF2 AF3 AF4 AF5 AF6 PC5 PC6 TIMER2_CH0 PC7 TIMER2_CH1 PC8 TIMER2_CH2 PC9 TIMER2_CH3 PC10 PC11 PC12 PC13 PC14 PC15 Table 2-11. Port D alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PD0 PD1 PD2 TIMER2_ETI PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 30 GD32F330xx Datasheet Table 2-12. Port F alternate functions summary Pin Name PF0 AF0 AF1 AF2 AF3 AF4 AF5 AF6 CTC_SYNC PF1 PF2 PF3 PF4 EVENTOUT PF5 EVENTOUT PF6 PF7 I2C0_SCL(1) I2C1_SCL(3) I2C0_SDA(1) I2C1_SDA(3) PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 Notes: (1) Functions are available on GD32F330x4 devices only. (2) Functions are available on GD32F330xB/8/6 devices. (3) Functions are available on GD32F330xB/8 devices. 31 GD32F330xx Datasheet 3 Functional description 3.1 ARM® Cortex®-M4 core The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit ARM® Cortex®-M4 processor core  Up to 84 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated DSP instructions  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 128 Kbytes of Flash memory  Up to 16 Kbytes of SRAM with hardware parity checking The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash and 16 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. Table 2-2. GD32F330xx memory map shows the memory map of the GD32F330xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 32 GD32F330xx Datasheet 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 48 MHz RC oscillator  Internal 28 MHz RC oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 84 MHz/42 MHz/42 MHz. See Figure 2-7. GD32F330xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present. 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15). 33 GD32F330xx Datasheet 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, LVD output and USART wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.  Standby mode In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin. 3.6 Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2.86 MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage (VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general level 0 timers (TIMERx,x=1,2) and the advanced timer (TIMER0) with internal connection. The temperature 34 GD32F330xx Datasheet sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7 DMA  7 channel DMA controller  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory. Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.8 General-purpose inputs/outputs (GPIOs)  Up to 55 fast GPIOs, all mappable on 16 external interrupt lines  Analog input/output configurable  Alternate function input/output configurable There are up to 55 general purpose I/O pins (GPIO) in GD32F330xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (pushpull, open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 3.9 Timers and PWM generation  One 16-bit advanced timer (TIMER0), one 32-bit general timer (TIMER1) and five 16-bit general timers (TIMER2, TIMER13 ~ TIMER16)  Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input  16-bit, motor control PWM advanced timer with programmable dead-time generation for output match 35 GD32F330xx Datasheet  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Free watchdog timer and window watchdog timer) The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder. The GD32F330xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below: 3.10  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.  Calendar with subsecond, seconds, minutes, hours, week day, date, year and month 36 GD32F330xx Datasheet automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. 3.11 Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 3.12 Serial peripheral interface (SPI)  Up to two SPI interfaces with a frequency of up to 21 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 37 GD32F330xx Datasheet 3.13 Universal synchronous asynchronous receiver transmitter (USART)  Up to two USARTs with operating frequency up to 5.25 MB/s  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.14 Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.15 Package and operation temperature  LQFP64 (GD32F330Rx), LQFP48 (GD32F330Cx), QFN32 (GD32F330Kx), QFN28 (GD32F330Gx) and TSSOP20 (GD32F330Fx)  Operation temperature range: -40°C to +85°C (industrial level)  Operation temperature range: -20°C to +85°C (commercial level) 38 GD32F330xx Datasheet 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings(1) (4) Symbol Parameter Min Max Unit VDD External voltage range(2) VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V VSS - 0.3 VDD + 3.6 V Input voltage on other I/O VSS - 0.3 3.6 V |ΔVDDx| Variations between different VDD power pins — 50 mV |VSSX −VSS| Variations between different ground pins — 50 mV IIO Maximum current for GPIO pin — ±25 mA TA Operating temperature range -40 +85 °C TSTG Storage temperature range -55 +150 °C TJ Maximum junction temperature — 125 °C VIN Input voltage on 5V tolerant pin (3) (1). Guaranteed by design, not tested in production. (2). All main power and ground pins should be connected to an external power source within the allowable range. (3). VIN maximum value cannot exceed 6.5 V. (4). It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD and VDDA does not exceed 300 mV during power-up and operation. 4.2 Operating conditions characteristics Table 4-2. DC operating conditions Min(1) Typ Max(1) Unit Symbol Parameter Conditions VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 (1). Based on characterization, not tested in production. Figure 4-1. Recommended power supply decoupling capacitors (1) (2) 39 GD32F330xx Datasheet VBAT 100 nF VSS N * VDD 4.7 μF + N * 100 nF VSS VDDA 1 μF VSSA 10 nF (1). The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins are not available and internally connected to VDDA and VSSA pins. (2). All decoupling capacitors need to be as close as possible to the pins on the PCB board. Table 4-3. Clock frequency Symbol Parameter Conditions Min Max Unit fHCLK1 AHB1 clock frequency — 0 84 MHz fHCLK2 AHB2 clock frequency — 0 84 MHz fAPB1 APB1 clock frequency — 0 42 MHz fAPB2 APB2 clock frequency — 0 42 MHz Min Max Unit 0 ∞ 20 ∞ Table 4-4. Operating conditions at Power up/ Power down(1) Symbol tVDD Parameter Conditions VDD rise time rate — VDD fall time rate μs /V (1). Based on characterization, not tested in production. Table 4-5. Start-up timings of Operating conditions (1) (2) (3) Symbol Parameter tstart-up Start-up time Conditions Typ Clock source from HXTAL 37 Clock source from IRC8M 37 Unit ms (1). Based on characterization, not tested in production. (2). After power-up, the start-up time is the time between the rising edge of NRST high and the main function. (3). PLL is off. Table 4-6. Power saving mode wakeup timings characteristics(1) (2) Symbol Parameter Typ tSleep Wakeup from Sleep mode 3.4 Wakeup from Deep-sleep mode（LDO On） 5.3 Wakeup from Deep-sleep mode（LDO in low power mode） 5.3 Wakeup from Standby mode 37.9 tDeep-sleep tStandby Unit μs ms (1). Based on characterization, not tested in production. 40 GD32F330xx Datasheet (2). The wakeup time is measured from the wakeup event to the point at which the application code reads the first instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz. 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 4-7.Power consumption characteristics(1) (2) (3) (3) (4) (5) Symbol Parameter Conditions Min Typ Max Unit — 19.86 — mA — 15.14 — mA — 17.22 — mA — 13.18 — mA — 11.99 — mA — 9.30 — mA — 9.36 — mA — 7.36 — mA — 6.72 — mA — 5.38 — mA — 4.96 — mA VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 84 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 84 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 72 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 72 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 48 MHz, All peripherals enabled IDD + IDDA Supply current (Run mode) VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 48 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 36 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 36 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 24 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 24 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 16 MHz, All peripherals enabled 41 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit — 4.06 — mA — 3.22 — mA — 2.78 — mA — 0.94 — mA — 0.75 — mA — 0.56 — mA — 0.48 — mA — 10.60 — mA — 5.24 — mA — 9.28 — mA — 4.68 — mA — 6.70 — mA — 3.62 — mA — 5.36 — mA VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 16 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 8 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, System clock = 8 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, System clock = 4 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, System clock = 4 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System clock = 2 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, System clock = 2 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 84 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 84 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 72 MHz, All peripherals enabled Supply current (Sleep mode) VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 72 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 48 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 48 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 36 MHz, All peripherals enabled 42 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit — 3.08 — mA — 4.06 — mA — 2.52 — mA — 3.20 — mA — 2.18 — mA — 2.32 — mA — 1.84 — mA — 0.56 — mA — 0.36 — mA — 0.37 — mA — 0.27 — mA VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 36 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 24 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 24 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 16 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 16 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 8 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 8 MHz, CPU clock off, System clock = 8 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, CPU clock off, System clock = 4 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 4 MHz, CPU clock off, System clock = 4 MHz, All peripherals disabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, CPU clock off, System clock = 2 MHz, All peripherals enabled VDD = VDDA = 3.3 V, HXTAL = 2 MHz, CPU clock off, System clock =2 MHz, All peripherals disabled VDD = VDDA = 3.3 V, LDO in run mode, IRC40K off, RTC off, All GPIOs analog — 117.06 330 μA — 91.98 330 μA — 110.78 330 μA mode Supply current VDD = VDDA = 3.3 V, LDO in low power (Deep-sleep mode, IRC40K off, RTC off, All GPIOs mode) analog mode VDD = VDDA = 3.3 V, Main LDO in under drive mode, IRC40K off, RTC off, All GPIOs analog mode 43 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit — 85.92 330 μA — 7.83 12.1 μA — 7.54 12.1 μA — 6.85 12.1 μA — 4.46 12.1 μA — 1.74 — μA — 1.59 — μA — 1.38 — μA — 1.44 — μA — 1.29 — μA — 1.09 — μA — 1.15 — μA — 1.00 — μA — 0.80 — μA — 1.07 — μA — 0.92 — μA VDD = VDDA = 3.3 V, Low Power LDO in under drive mode, IRC40K off, RTC off, All GPIOs analog mode VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, RTC on VDD = VDDA = 3.3 V, LXTAL off, IRC40K on, Supply current RTC off (Standby mode) VDD = VDDA = 3.3 V, LXTAL off, IRC40K off, RTC off, VDDA Monitor on VDD = VDDA = 3.3 V, LXTAL off, IRC40K off, RTC off, VDDA Monitor off VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL High driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL High driving VDD off, VDDA off, VBAT = 2.6 V, LXTAL on with external crystal, RTC on, LXTAL High driving VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL Medium High driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL Medium High driving IBAT Battery supply current VDD off, VDDA off, VBAT = 2.6 V, LXTAL on with external crystal, RTC on, LXTAL Medium High driving VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 2.6 V, LXTAL on with external crystal, RTC on, LXTAL Medium Low driving VDD off, VDDA off, VBAT = 3.6 V, LXTAL on with external crystal, RTC on, LXTAL Low driving VDD off, VDDA off, VBAT = 3.3 V, LXTAL on with external crystal, RTC on, LXTAL Low driving 44 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ — 0.72 Max Unit VDD off, VDDA off, VBAT = 2.6 V, LXTAL on with external crystal, RTC on, LXTAL Low — μA driving (1). Based on characterization, not tested in production. (2). Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value. (3). When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed, no PLL. (4). When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed, using PLL. (5). When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional power consumption should be considered. Figure 4-2. Typical supply current consumption in Run mode 45 GD32F330xx Datasheet Figure 4-3. Typical supply current consumption in Sleep mode Table 4-8. Peripheral current consumption characteristics (1) Peripherials(3) AHB1 AHB2 APB2 APB1 Typical consumption at TA = 25 ℃ （TYP）(1) CRC 0.66 DMA 1.01 GPIOF 0.66 GPIOD 0.66 GPIOC 0.71 GPIOB 0.71 GPIOA 0.71 TIMER16 0.76 TIMER15 0.77 TIMER14 0.86 USART0 0.84 TIMER0 1.15 SPI0 0.70 ADC 1.42 PMU 0.95 I2C1 0.70 I2C0 0.73 USART1 0.68 SPI1 0.63 WWDGT 0.59 TIMER13 0.65 Unit mA 46 GD32F330xx Datasheet Peripherials(3) Typical consumption at TA = 25 ℃ （TYP）(1) TIMER2 0.93 TIMER1 1.01 Unit (1). Based on characterization, not tested in production. (2). System clock = fHCLK = 84 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADCON bit is set to 1. (3). If there is no other description, then HXTAL = 8 MHz, System clock = fHCLK = 84 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK. 4.4 EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in Table 4-9. EMS characteristics, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-9. EMS characteristics(1) Symbol VESD Parameter Voltage applied to all device pins to induce a functional disturbance Fast transient voltage burst applied to VFTB Conditions Level/Class VDD = 3.3 V, TA = 25 °C, LQFP64, fHCLK = 108 MHz 3A conforms to IEC 61000-4-2 VDD = 3.3 V, TA = 25 °C, induce a functional disturbance through LQFP64, fHCLK = 108 MHz 100 pF on VDD and VSS pins conforms to IEC 61000-4-4 3A (1). Measurements were made performed on a similar LQFP64 device GD32F350RxT6. 47 GD32F330xx Datasheet 4.5 Power supply supervisor characteristics Table 4-10. Power supply supervisor characteristics Symbol VLVD(1) VLVDhyst(2) VPOR(1) VPDR(1) Parameter Conditions Min Typ Max Unit LVDT[2:0] = 000, rising edge 3.03 3.11 3.19 V LVDT[2:0] = 000, falling edge 2.94 3.01 3.07 V LVDT[2:0] = 001, rising edge 2.90 2.97 3.04 V LVDT[2:0] = 001, falling edge 2.80 2.87 2.93 V LVDT[2:0] = 010, rising edge 2.76 2.83 2.9 V LVDT[2:0] = 010, falling edge 2.66 2.73 2.79 V LVDT[2:0] = 011, rising edge 2.63 2.69 2.76 V Low Voltage Detector LVDT[2:0] = 011, falling edge 2.53 2.59 2.66 V Threshold LVDT[2:0] = 100, rising edge 2.49 2.55 2.62 V LVDT[2:0] = 100, falling edge 2.39 2.45 2.52 V LVDT[2:0] = 101, rising edge 2.36 2.42 2.47 V LVDT[2:0] = 101, falling edge 2.26 2.32 2.37 V LVDT[2:0] = 110, rising edge 2.22 2.28 2.33 V LVDT[2:0] = 110, falling edge 2.13 2.17 2.22 V LVDT[2:0] = 111, rising edge 2.08 2.14 2.19 V LVDT[2:0] = 111, falling edge 1.99 2.03 2.08 V — — 100 — mV — 2.37 — V — 1.82 — V LVD hysteresis Power on reset threshold Power down reset threshold — VPDRhyst(2) PDR hysteresis — 600 — mV tRSTTEMPO(2) Reset temporization — 2 — ms (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. 48 GD32F330xx Datasheet 4.6 Electrical sensitivity The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up (LU) test is based on the two measurement methods. Table 4-11. ESD characteristics (1) Symbol VESD(HBM) VESD(CDM) Parameter Conditions Electrostatic discharge TA = 25 °C; voltage (human body model) JESD22-A114 Electrostatic discharge TA = 25 °C; voltage (charge device model) JESD22-C101 Min Typ Max Unit — — 6000 V — — 2000 V Min Typ Max Unit — — ±200 mA — — 5.4 V (1). Based on characterization, not tested in production. Table 4-12. Static latch-up characteristics (1) Symbol Parameter Conditions I-test LU TA = 25 °C; JESD78 Vsupply over voltage (1). Based on characterization, not tested in production. 4.7 External clock characteristics Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics Symbol Parameter Conditions Min Typ Max Unit fHXTAL(1) Crystal or ceramic frequency 2.6 V ≤ VDD ≤ 3.6 V 4 8 32 MHz RF(2) Feedback resistor VDD = 3.3 V — 400 — kΩ CHXTAL(2)(3) capacitance on OSCIN and — — 20 30 pF — 30 50 70 % VDD = 3.3 V, TA = 25 °C — 1.3 — mA VDD = 3.3 V, TA = 25 °C — 1.8 — ms Recommended matching OSCOUT Ducy(HXTAL)(2) IDD(HXTAL)(1) tSUHXTAL(1) Crystal or ceramic duty cycle Crystal or ceramic operating current Crystal or ceramic startup time (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. (3). CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. Table 4-14. High speed external user clock characteristics (HXTAL in bypass mode) Symbol Parameter Conditions Min Typ Max Unit fHXTAL_ext(1) External clock source or oscillator VDD = 3.3 V 1 8 50 MHz 49 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit frequency VHXTALH VHXTALL (2) OSCIN input pin high level voltage (2) OSCIN input pin low level voltage tH/L(HXTAL)(2) tR/F(HXTAL) (2) CIN(1) (2) Ducy(HXTAL) VDD = 3.3 V 0.7 VDD — VDD VSS — 0.3 VDD V OSCIN high or low time — 5 — — OSCIN rise or fall time — — — 10 OSCIN input capacitance — — 5 — pF Duty cycle — 30 50 70 % ns (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics Symbol Parameter Conditions Min Typ Max Unit fLXTAL(1) Crystal or ceramic frequency — — 32.768 — kHz — — 15 — pF % Recommended matching CLXTAL (2)(3) capacitance on OSC32IN and OSC32OUT Ducy(LXTAL) (2) IDDLXTAL (1) tSULXTAL(1)(4) — 30 — 70 LXTALDRI[1:0] = 11 — 1.3 — Crystal or ceramic operating LXTALDRI[1:0] = 10 — 1.0 — current LXTALDRI[1:0] = 01 — 0.7 — LXTALDRI[1:0] = 00 — 0.6 — — — 1.8 — Crystal or ceramic duty cycle Crystal or ceramic startup time μA s (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. (3). CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance. (4). tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator stabilization flags is SET. This value varies significantly with the crystal manufacturer. Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode) Symbol fLXTAL_ext VLXTALH(1) VLXTALL (1) Parameter External clock source or oscillator frequency Conditions Min Typ Max Unit — — 32.768 1000 kHz 0.7 VDD — VDD OSC32IN input pin high level voltage OSC32IN input pin low level — VSS voltage tH/L(LXTAL) (1) OSC32IN high or low time V — 450 — 0.3 VDD — — ns tR/F(LXTAL) CIN(1) (1) OSC32IN rise or fall time — — — 50 OSC32IN input capacitance — — 5 — pF 50 GD32F330xx Datasheet Ducy(LXTAL) (1) — Duty cycle 30 50 70 % (1). Guaranteed by design, not tested in production. 4.8 Internal clock characteristics Table 4-17. High speed internal clock (IRC8M) characteristics Symbol Parameter Conditions Min Typ Max Unit VDD = VDDA = 3.3 V — 8 — MHz -4.0 — +5.0 % -2.0 — +2.0 % VDD = VDDA = 3.3 V, TA = 25°C -1.0 — +1.0 % — — 0.5 — % 45 50 55 % — 66 — μA — 2 — μs Min Typ Max Unit 20 40 45 kHz — 0.4 — μA — 110 — μs High Speed Internal fIRC8M Oscillator (IRC8M) frequency VDD = VDDA = 3.3 V, IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M TA = -40 °C ~ +85 °C(1) VDD = VDDA = 3.3 V, TA = 0°C ~ +85°C IRC8M oscillator Frequency accuracy, User trimming step(1) DucyIRC8M(2) IRC8M oscillator duty cycle IDDAIRC8M(1) tSUIRC8M(1) VDD = VDDA = 3.3 V, fIRC8M = 8 MHz IRC8M oscillator operating VDD = VDDA = 3.3 V, current fIRC8M = 8 MHz IRC8M oscillator startup VDD = VDDA = 3.3 V, time fIRC8M = 8 MHz (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. Table 4-18. Low speed internal clock (IRC40K) characteristics Symbol fIRC40K(1) IDDAIRC40K(2) tSUIRC40K(2) Parameter Conditions Low Speed Internal oscillator VDD = VDDA = 3.3 V, (IRC40K) frequency TA = -40 °C ~ +85 °C IRC40K oscillator operating VDD = VDDA = 3.3 V, TA = current 25 °C IRC40K oscillator startup VDD = VDDA = 3.3 V, TA = time 25 °C (1). Guaranteed by design, not tested in production. (2). Based on characterization, not tested in production. Table 4-19. High speed internal clock (IRC28M) characteristics Symbol fIRC28M ACCIRC28M Parameter High Speed Internal Oscillator (IRC28M) frequency Conditions Min Typ Max Unit VDD = VDDA = 3.3 V — 28 — MHz -4.0 — +5.0 % IRC28M oscillator Frequency VDD = VDDA = 3.3 V, accuracy, Factory-trimmed TA = -40 °C ~ +85 °C(2) 51 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit -2.0 — +2.0 % -1.0 — +1.0 % — 0.5 — % 45 50 55 % — 120 — μA — 1.6 — μs Conditions Min Typ Max Unit VDD = VDDA = 3.3 V — 48 — MHz -4.0 — +5.0 % -3.0 — +3.0 % VDD = VDDA = 3.3 V, TA = 25°C -2.0 — +2.0 % — — 0.12 — % 45 50 55 % — 260 — μA — 1.5 — μs VDD = VDDA = 3.3 V, TA = 0°C ~ +85°C VDD = VDDA = 3.3 V, TA = 25°C IRC28M oscillator Frequency — accuracy, User trimming step(1) DIRC28M(2) IRC28M oscillator duty cycle IDDAIRC28M(1) tSUIRC28M(1) VDD = VDDA = 3.3 V, fIRC28M = 28 MHz IRC28M oscillator operating VDD = VDDA = 3.3 V, fIRC28M = current 28 MHz IRC28M oscillator startup time VDD = VDDA = 3.3 V, fIRC28M = 28 MHz (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. Table 4-20. High speed internal clock (IRC48M) characteristics Symbol Parameter High Speed Internal fIRC48M Oscillator (IRC48M) frequency VDD = VDDA = 3.3 V, IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M TA = -40 °C ~+85 °C(1) VDD = VDDA = 3.3 V, TA = 0°C ~ +85°C IRC48M oscillator Frequency accuracy, User trimming step(1) DIRC48M(2) IRC48M oscillator duty cycle IDDAIRC48M(1) tSUIRC48M(1) VDD = VDDA = 3.3 V, fIRC28M = 16 MHz IRC48M oscillator operating VDD = VDDA = 3.3 V, current fIRC28M = 16 MHz IRC48M oscillator startup VDD = VDDA = 3.3 V, time fIRC28M = 16 MHz (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. 4.9 PLL characteristics Table 4-21. PLL characteristics 52 GD32F330xx Datasheet Symbol fPLLIN (1) fPLLOUT Parameter Conditions Min Typ Max Unit PLL input clock frequency — 1 — 25 MHz PLL output clock frequency — 16 — 84 MHz — — — 84 MHz — — — 300 μs VCO freq = 84 MHz — 270 — μA — 32.1 — PLL VCO output clock fVCO frequency tLOCK PLL lock time IDDA(1) (3) Current consumption on VDDA Cycle to cycle Jitter JitterPLL(4) （rms） System clock Cycle to cycle Jitter ps — （peak to peak） 255.6 — (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. (3). System clock = IRC8M = 8 MHz, fPLLOUT = 84 MHz. (4). Value given with main PLL running. 4.10 Memory characteristics Table 4-22 Flash memory characteristics Symbol Parameter Conditions Min(1) Typ(1) Max(2) Unit Number of guaranteed PECYC program /erase cycles — 100 — — kcycles before failure (Endurance) tRET Data retention time — — 20 — years wtPROG Word programming time TA = -40 °C ~ +85 °C — 37.5 86 μs tERASE Page erase time TA = -40 °C ~ +85 °C — 45 300 ms tMERASE(64KB) Mass erase time TA = -40 °C ~ +85 °C — 0.5 1.6 s Min Typ Max -0.5 — 0.3 VDD 0.7 VDD — VDD + 0.5 — 140 — mV — 40 — kΩ (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. 4.11 NRST pin characteristics Table 4-23. NRST pin characteristics Symbol Parameter VIL(NRST) (1) NRST Input low level voltage (1) NRST Input high level voltage VIH(NRST) Vhyst Schmidt trigger Voltage hysteresis Rpu(2) Pull-up equivalent resistor Conditions 2.6 V ≤ VDD = VDDA ≤ 3.6 V — Unit V (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. 53 GD32F330xx Datasheet Figure 4-4. Recommended external NRST pin circuit VDD VDD External reset circuit RPU 10kΩ NRST K 100 nF GND 4.12 GPIO characteristics Table 4-24. I/O port DC characteristics Symbol Parameter Conditions Min Typ Max Unit 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V — — 0.3 VDD V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 0.7 VDD — — V Low level output voltage VDD = 2.6 V — — 0.21 for 8 IO Pins VDD = 3.3 V — — 0.19 (each IIO = +8 mA) VDD = 3.6 V — — 0.18 Low level output voltage VDD = 2.6 V — — 0.54 for 8 IO Pins VDD = 3.3 V — — 0.47 (each IIO = +20 mA) VDD = 3.6 V — — 0.45 High level output voltage VDD = 2.6 V 2.40 — — for 8 IO Pins VDD = 3.3 V 3.10 — — (each IIO = +8 mA) VDD = 3.6 V 3.40 — — High level output voltage VDD = 2.6 V 1.95 — — for 8 IO Pins VDD = 3.3 V 2.73 — — (each IIO = +20 mA) VDD = 3.6 V 3.07 — — Standard IO Low level input VIL voltage 5V-tolerant IO Low level input voltage Standard IO High level VIH input voltage 5V-tolerant IO High level input voltage VOL (1) VOL VOH VOH(1) V V V V 54 GD32F330xx Datasheet Symbol RPU(2) RPD(2) Parameter Conditions Min Typ Max Unit Internal pull- All pins VIN = VSS 30 40 50 kΩ up resistor PA10 — 7.5 10 13.5 kΩ Internal pull- All pins VIN = VDD 30 40 50 kΩ down resistor PA10 — 7.5 10 13.5 kΩ (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. Table 4-25. I/O port AC characteristics (1) (2) GPIOx_OSPD[1:0] bit value(3) Parameter GPIOx_OSPD0->OSPDy[1:0] = X0 Maximum （IO_Speed = 2 MHz） frequency(4) GPIOx_OSPD0->OSPDy[1:0] = 01 Maximum （IO_Speed = 10 MHz） frequency(4) GPIOx_OSPD0->OSPDy[1:0] = 11 Maximum （IO_Speed = 50 MHz） frequency(4) GPIOx_OSPD0->OSPDy[1:0] = 11 and GPIOx_OSPD1->SPDy = 1 （IO_Speed mode = MAX） Maximum Conditions Max VDD = 3.3 V, CL = 10 pF 20 VDD = 3.3 V, CL = 30 pF 10 VDD = 3.3 V, CL = 50 pF 8 VDD = 3.3 V, CL = 10 pF 46 VDD = 3.3 V, CL = 30 pF 40 VDD = 3.3 V, CL = 50 pF 30 VDD = 3.3 V, CL = 10 pF 128 VDD = 3.3 V, CL = 30 pF 120 VDD = 3.3 V, CL = 50 pF 112 VDD = 3.3 V, CL = 10 pF 144 VDD = 3.3 V, CL = 30 pF 128 VDD = 3.3 V, CL = 50 pF 116 Unit MHz MHz MHz MHz frequency(4) (1). Based on characterization, not tested in production. (2). Unless otherwise specified, all test results given for TA = 25 ℃. (3). The I/O speed is configured using the GPIOx_OSPD0->OSPDy [1:0] bits. Refer to the GD32F3x0 user manual which is selected to set the GPIO port output speed. (4). The maximum frequency is defined in Figure 4-5, and maximum frequency cannot exceed 84 MHz. Figure 4-5. I/O port AC characteristics definition 90% EXTERNAL OUTPU T ON 50pF 50% 10% tr(IO)out 10% 50% 90% tr(IO)out If (tr+tf)≤2/3 T,then maximum frequency is achieved . The duty cycle is （45%-55%）when loaded by 50 pF 4.13 ADC characteristics Table 4-26. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA(1) Operating voltage — 2.6 3.3 3.6 V 55 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit VIN(1) ADC input voltage range — 0 — VDDA V fADC(1) ADC clock — 0.1 — 40 MHz 12-bit 0.007 — 2.86 10-bit 0.008 — 3.33 8-bit 0.01 — 4.00 6-bit 0.011 — 5.00 Analog input voltage 16 external; 2 internal 0 — VDDA V External input impedance See Equation 1 — — 24 kΩ — — — 0.2 kΩ — — 5.5 pF fS(1) VAIN(1) (2) RAIN RADC(2) Sampling rate Input sampling switch resistance No pin/pad capacitance MSPS CADC(2) Input sampling capacitance tCAL(2) Calibration time fADC = 40 MHz — 3.12 — μs Sampling time fADC = 40 MHz 0.036 — 5.7 μs 12-bit — 14 — 10-bit — 12 — 8-bit — 10 — 6-bit — 8 — — — — 1 (2) ts included Total conversion tCONV(2) time(including sampling time) tSU(2) Startup time 1/ fADC μs (1). Based on characterization, not tested in production. (2). Guaranteed by design, not tested in production. Equation 1 ：RAIN max formula R AIN < Ts fADC ∗CADC ∗ln(2N+2 ) − R ADC The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 4-27. ADC RAIN max for fADC = 40 MHz (1) Ts(cycles) ts(μs) RAINmax (kΩ) 1.5 0.04 0.47 7.5 0.18 3.15 13.5 0.32 5.82 28.5 0.68 12.55 41.5 0.99 18.35 55.5 1.32 24.55 71.5 1.70 NA 239.5 5.70 NA (1). Based on characterization, not tested in production. Table 4-28. ADC dynamic accuracy at fADC = 28 MHz (1) Symbol Parameter Test conditions Min Typ Max Unit ENOB Effective number of bits fADC = 28 MHz — 10.3 — bits SNDR Signal-to-noise and distortion ratio VDDA = VDD = 3.3 V — 63.8 — SNR Signal-to-noise ratio Input Frequency = 20 kHz — 64.5 — dB 56 GD32F330xx Datasheet Symbol Parameter Test conditions Min Typ THD Total harmonic distortion Temperature = 25℃ — Max Unit — -67.5 (1). Based on characterization, not tested in production. Table 4-29. ADC dynamic accuracy at fADC = 30 MHz (1) Symbol Parameter Test conditions Min Typ Max Unit ENOB Effective number of bits fADC = 30 MHz — 10.3 — SNDR Signal-to-noise and distortion ratio VDDA = VDD = 3.3 V — 63.8 — SNR Signal-to-noise ratio Input Frequency = 20 kHz — 64.5 — THD Total harmonic distortion Temperature = 25 ℃ — -67.5 — bits dB (1). Based on characterization, not tested in production. Table 4-30.ADC dynamic accuracy at fADC = 36 MHz (1) Symbol Parameter Test conditions Min Typ ENOB Effective number of bits fADC = 36 MHz 10.3 10.4 — SNDR Signal-to-noise and distortion ratio VDDA = VDD = 3.3 V 63.8 64.4 — SNR Signal-to-noise ratio Input Frequency = 20 64.2 65 — -70 -72 — Typ Max ±1 — ±1 — ±3 — kHz THD Total harmonic distortion Temperature = 25℃ Max Unit bits dB (1). Based on characterization, not tested in production. Table 4-31. ADC static accuracy at fADC = 14 MHz (1) Symbol Parameter Offset Offset error DNL Differential linearity error INL Integral linearity error Test conditions fADC = 14 MHz VDDA = VDD = 3.3 V Unit LSB (1). Based on characterization, not tested in production. 4.14 Temperature sensor characteristics Table 4-32. Temperature sensor characteristics (1) Symbol Parameter Min Typ Max Unit TL VSENSE linearity with temperature — ±1.5 — ℃ Avg_Slope Average slope — 4.3 — mV/℃ V25 Voltage at 25 °C — 1.45 — V ADC sampling time when reading the temperature — 17.1 — μs tS_temp (2) (1). Based on characterization, not tested in production. (2). Shortest sampling time can be determined in the application by multiple iterations. 4.15 I2C characteristics Table 4-33. I2C characteristics (1) (2) (3) 57 GD32F330xx Datasheet Symbol tSCL(H) Parameter Conditi ons SCL clock high time Standard mode Fast mode Fast mode plus Unit Min Max Min Max Min Max — 4.0 — 0.6 — 0.2 — μs tSCL (L) SCL clock low time — 4.7 — 1.3 — 0.5 — μs tsu(SDA) SDA setup time — 2 — 0.8 — 0.1 — μs — 250 — 250 — 130 — ns — — 1000 20 300 — 120 ns — 4 300 2 300 2 120 ns — 4.0 — 0.6 — 0.26 — μs th(SDA) tr(SDA/SCL) tf(SDA/SCL) th(STA) SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time (1). Guaranteed by design, not tested in production. (2). Test condition: GPIO_SPEED set 2MHz and external pull-up resistor value is 1kΩ when operate EEPROM with I2C. (3). The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the falling edge of SCL. 4.16 SPI characteristics Table 4-34. Standard SPI characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 21 MHz tSCK(H) SCK clock high time tSCK(L) SCK clock low time Master mode, fPCLKx = 84 MHz, presc = 8 Master mode, fPCLKx = 84 MHz, presc = 8 45.62 47.62 49.62 ns 45.62 47.62 49.62 ns SPI master mode tV(MO) Data output valid time — — 5 6 ns tH(MO) Data output hold time — 3 — — ns tSU(MI) Data input setup time — 1 — — ns tH(MI) Data input hold time — 0 — — ns SPI slave mode tSU(NSS) NSS enable setup time — 0 — — ns tH(NSS) NSS enable hold time — 1 — — ns tA(SO) Data output access time — 9 — 13 ns tDIS(SO) Data output disable time — 9 — 13 ns tV(SO) Data output valid time — — 14 16 ns tH(SO) Data output hold time — 11 — — ns tSU(SI) Data input setup time — 0 — — ns 58 GD32F330xx Datasheet Symbol Parameter Conditions Min Typ Max Unit tH(SI) Data input hold time — 3 — — ns (1). Based on characterization, not tested in production. 4.17 USART characteristics Table 4-35. USART characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency fPCLKx = 84 MHz — — 42 MHz tSCK(H) SCK clock high time fPCLKx = 84 MHz 11.9 — — ns tSCK(L) SCK clock low time fPCLKx = 84 MHz 11.9 — — ns (1). Guaranteed by design, not tested in production. 4.18 TIMER characteristics Table 4-36. TIMER characteristics (1) Symbol Parameter tres Timer resolution time fEXT Conditions Min Max Unit — 1 — tTIMERxCLK fTIMERxCLK = 84 MHz 11.9 — ns Timer external clock — 0 fTIMERxCLK/2 MHz frequency fTIMERxCLK = 84 MHz 0 42 MHz Timer resolution — — 16/32 bit — 1 65536 tTIMERxCLK fTIMERxCLK = 84 MHz 0.0119 780.2 μs — — fTIMERxCLK = 84 MHz — RES 16-bit counter clock period tCOUNTER when internal clock is selected tMAX_COUNT Maximum possible count 65536 × 65536 tTIMERxCLK 51.13 s (1). Guaranteed by design, not tested in production. 4.19 WDGT characteristics Table 4-37. FWDGT min/max timeout period at 40 kHz (IRC40K) (1) Min timeout RLD[11:0] Max timeout RLD[11:0] = Prescaler divider PR[2:0] bits 1/4 000 0.1 409.6 1/8 001 0.2 819.2 1/16 010 0.4 1638.4 1/32 011 0.8 3276.8 1/64 100 1.6 6553.6 1/128 101 3.2 13107.2 1/256 110 or 111 6.4 26214.4 = 0x000 0xFFF Unit ms 59 GD32F330xx Datasheet (1). Guaranteed by design, not tested in production. Table 4-38. WWDGT min-max timeout value at 84 MHz (fPCLK1) (1) Min timeout value Prescaler divider PSC[2:0] 1/1 00 37.9 1/2 01 75.9 1/4 10 151.7 1/8 11 303.4 CNT[6:0] = 0x40 Unit Max timeout value CNT[6:0] = 0x7F Unit 2.43 μs 4.85 9.71 ms 19.42 (1). Guaranteed by design, not tested in production. 4.20 Parameter conditions Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃. 60 GD32F330xx Datasheet 5 Package information 5.1 LQFP64 package outline dimensions Figure 5-1. LQFP64 package outline Table 5-1. LQFP64 package dimensions 61 GD32F330xx Datasheet Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 11.80 12.00 12.20 D1 9.90 10.00 10.10 E 11.80 12.00 12.20 eB 11.25 — 11.45 E1 9.90 10.00 10.10 e L 0.50 BSC 0.45 L1 θ — 0.75 1.00 REF 0 — 7° (Original dimensions are in millimeters) 62 GD32F330xx Datasheet 5.2 LQFP48 package outline dimensions Figure 5-2. LQFP48 package outline Table 5-2. LQFP48 package dimensions Symbol Min Typ Max A — — 1.60 A1 0.05 — 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.18 — 0.26 b1 0.17 0.20 0.23 c 0.13 — 0.17 c1 0.12 0.13 0.14 D 8.80 9.00 9.20 D1 6.90 7.00 7.10 E 8.80 9.00 9.20 eB 8.10 — 8.25 E1 6.90 7.00 7.10 e L 0.50 BSC 0.45 L1 θ — 0.75 1.00 REF 0 — 7° 63 GD32F330xx Datasheet (Original dimensions are in millimeters) 5.3 QFN32 package outline dimensions Figure 5-3. QEN32 package outline Table 5-3. QFN32 package dimensions Symbol Min Typ Max A 0.70 0.75 0.80 A1 — 0.02 0.05 D 4.90 5.00 5.10 D2 3.40 3.50 3.60 E 4.90 5.00 5.10 E2 3.40 3.50 3.60 b 0.18 0.25 0.30 c 0.18 0.20 0.25 e 0.50 BSC Ne 3.50 BSC L 0.35 0.40 0.45 h 0.30 0.35 0.40 (Original dimensions are in millmeters) 64 GD32F330xx Datasheet 5.4 QFN28 package outline dimensions Figure 5-4. QFN28 package outline Table 5-4. QFN28 package dimensions Symbol Min Typ Max A 0.70 0.75 0.80 A1 0 0.02 0.05 b 0.15 0.20 0.25 b1 0.14 REF c 0.18 0.20 0.25 D 3.90 4.00 4.10 D2 2.70 2.80 2.90 E 3.90 4.00 4.10 E2 2.70 2.80 2.90 e 0.40 BSC Ne 2.40 BSC Nd 2.40 BSC L 0.25 0.35 0.45 h 0.30 0.35 0.40 (Original dimensions are in millmeters) 65 GD32F330xx Datasheet 5.5 TSSOP20 package outline dimensions Figure 5-5. TSSOP20 package outline Table 5-5. TSSOP20 package dimensions Symbol Min Typ Max A — — 1.20 A1 0.05 — 0.15 A2 0.80 1.00 1.05 A3 0.39 0.44 0.49 b 0.20 — 0.29 b1 0.19 0.22 0.25 c 0.13 — 0.18 c1 0.12 0.13 0.14 D 6.40 6.50 6.60 E1 4.30 4.40 4.50 E 6.20 6.40 6.60 e 0.65 BSC L 0.45 0.60 0.75 θ 0° — 8° 66 GD32F330xx Datasheet 6 Ordering information Table 6-1. Part ordering code for GD32F330xx devices Ordering code Flash (KB) Package Package type GD32F330F4P6 16 TSSOP20 Green GD32F330F6P6 32 TSSOP20 Green GD32F330F8P6 64 TSSOP20 Green GD32F330G4U6 16 QFN28 Green GD32F330G6U6 32 QFN28 Green GD32F330G8U6 64 QFN28 Green GD32F330K4U6 16 QFN32 Green GD32F330K6U6 32 QFN32 Green GD32F330K8U6 64 QFN32 Green GD32F330C4T6 16 LQFP48 Green GD32F330C6T6 32 LQFP48 Green GD32F330C8T6 64 LQFP48 Green GD32F330CBT6 128 LQFP48 Green GD32F330R8T6 64 LQFP64 Green GD32F330RBT6 128 LQFP64 Green Temperature operating range Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C Industrial -40 °C to +85 °C 67 GD32F330xx Datasheet 7 Revision history Table 7-1. Revision history Revision No. Description Date 1.0 Initial Release Jun.6, 2017 1.1 Characteristics values updated Jun.20, 2017 1.2 Characteristics values updated Nov.20, 2017 1.3 Repair history accumulation error Jan.24, 2018 1.4 Characteristics values updated Jun.1, 2019 1.5 Characteristics values, logo, package information and ordering information updated Oct.8, 2019 68 GD32F330xx Datasheet Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights, trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property of their respective owner and referred to for identification purposes only. The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does not assume any liability arising out of the application or use of any Product described in this document. Any information provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Except for customized products which has been expressly identified in the applicable agreement, the Products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The Products are not designed, intended, or authorized for use as components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or Product could cause personal injury, death, property or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage, or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products. Information in this document is provided solely in connection with the Products. The Company reserves the right to make changes, corrections, modifications or improvements to this document and Products and services described herein at any time, without notice. © 2019 GigaDevice – All rights reserved 69