NCA9555
16-bit I2C-bus I/O port with interrupt
Datasheet (EN) 1.3
Product Overview
The NCA9555 is a 24-pin CMOS device that provides 16
bits of general-purpose parallel Input/Output (GPIO)
expansion for I2C-bus applications. It provides a simple
solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The NCA9555 consists of two 8-bit Configuration (Input or
Output selection); Input, Output and Polarity Inversion
(active HIGH or active LOW operation) registers. The
system master can enable the I/Os as either inputs or
outputs by writing to the I/O configuration bits. The data
for each Input or Output is kept in the corresponding Input
or Output register. The polarity of the read register can be
inverted with the Polarity Inversion register. All registers
can be read by the system master.
The NCA9555 open-drain interrupt output is activated
when any input state differs from its corresponding input
port register state and is used to indicate to the system
master that an input state has changed. The power-on
reset sets the registers to their default values and
initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C-bus
address and allow up to eight devices to share the same
I2C-bus.
ESD protection exceeds 2000 V HBM, 200 V MM, and
1000 V CDM
Latch-up testing exceeds 100 mA
Applications
GPIO expansion for I2C-bus applications
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics
Products with GPIO-Limited Processors
Device Information
Part Number
NCA9555
Package
TSSOP24
Body Size
7.80mm*4.40mm
Functional Block Diagrams
Key Features
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
I2C to Parallel Port Expander
Polarity Inversion register
Active LOW interrupt output
Compatible With Most Microcontrollers
Address by Three Hardware Address Pins for Use of up to
Eight Devices
Latched Outputs With High-Current Drive Capability for
Directly Driving LEDs
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 Hz to 400 kHz clock frequency
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Figure 1. NCA9555 Block Diagram
Page 1
NCA9555
Datasheet (EN) 1.3
INDEX
1. PIN CONFIGURATION AND FUNCTIONS ....................................................................................................................................... 3
2. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................. 5
3. RECOMMENDED OPERATING CONDITIONS ................................................................................................................................. 6
4. THERMAL INFORMATION ............................................................................................................................................................ 6
5. SPECIFICATIONS ........................................................................................................................................................................... 7
5.1. ELECTRICAL CHARACTERISTICS ....................................................................................................................................................... 7
5.2. DYNAMIC CHARACTERISTICS......................................................................................................................................................... 9
6. REGISTER DESCRIPTION ............................................................................................................................................................. 10
6.1. DEVICE ADDRESS ...................................................................................................................................................................... 10
6.2. COMMAND BYTE ...................................................................................................................................................................... 10
6.3. REGISTERS 0 AND 1 : INPUT PORT REGISTERS .................................................................................................................................. 11
6.4. REGISTERS 2 AND 3 : OUTPUT PORT REGISTERS ............................................................................................................................... 11
6.5. REGISTERS 4 AND 5 : POLARITY INVERSION REGISTERS ...................................................................................................................... 12
6.6. REGISTERS 6 AND 7 : CONFIGURATION REGISTERS...................................................................................................................... 12
6.7. POWER-ON RESET ............................................................................................................................................................... 13
6.8. I/O PORT.............................................................................................................................................................................. 13
7. BUS TRANSACTIONS .................................................................................................................................................................. 15
7.1. WRITING TO THE PORT REGISTERS ...................................................................................................................................... 15
7.2. READING THE PORT REGISTERS ........................................................................................................................................... 16
7.3. INTERRUPT OUTPUT .................................................................................................................................................................. 17
8. CHARACTERISTICS OF THE I2C-BUS ............................................................................................................................................. 17
8.1. BIT TRANSFER .......................................................................................................................................................................... 18
8.2. START AND STOP CONDITIONS ..................................................................................................................................................... 18
8.3. SYSTEM CONFIGURATION ........................................................................................................................................................... 18
8.4. ACKNOWLEDGE ....................................................................................................................................................................... 19
9. APPLICATION DESIGN-IN INFORMATION ................................................................................................................................... 19
10. TEST INFORMATION ................................................................................................................................................................. 21
11. PACKAGE INFORMATION ......................................................................................................................................................... 22
11.1. PACKAGE OUTLINE .................................................................................................................................................................. 23
12. TAPE AND REEL INFORMATION ............................................................................................................................................... 23
13. ORDER INFORMATION ............................................................................................................................................................. 24
14. DOCUMENTATION SUPPORT ................................................................................................................................................... 25
15. REVISION HISTORY ................................................................................................................................................................... 26
NCA9555
Datasheet (EN) 1.3
1. Pin Configuration and Functions
Figure 1.1. NCA9555 Package
Copyright © 2020, NOVOSENSE
Page 3
NCA9555
Datasheet (EN) 1.3
Table 1.1. Pin Description
Symbol
Pin
/INT
1
interrupt output (open-drain)
A1
2
address input 1
A2
3
address input 2
IO0_0
4
port 0 input/output
IO0_1
5
IO0_2
6
IO0_3
7
IO0_4
8
IO0_5
9
IO0_6
10
IO0_7
11
VSS
12
supply ground
IO1_0
13
port 1 input/output
IO1_1
14
IO1_2
15
IO1_3
16
IO1_4
17
IO1_5
18
IO1_6
19
IO1_7
20
A0
21
address input 0
SCL
22
serial clock line
SDA
23
serial data line
VDD
24
supply voltage
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Description
Page 4
NCA9555
Datasheet (EN) 1.3
2. Absolute Maximum Ratings
Parameters
Symbol
Min
Max
Unit
Supply voltage
VDD
-0.5
+6.0
V
Voltage on an input/output pin
VI/O
VSS-0.5
6.0
V
Output current
IO
-
±50
mA
Input current
II
-
±20
mA
Supply current
IDD
-
160
mA
Ground supply current
ISS
-
200
mA
Total power dissipation
Ptot
-
200
mW
Maximum junction temperature
Tj(max)
-
125
℃
Storage temperature
Tstg
-65
+150
℃
Ambient temperature
Tamb
-40
+85
℃
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Conditions
On an I/O pin
Operating
Page 5
NCA9555
Datasheet (EN) 1.3
3. Recommended Operating Conditions
Parameters
Symbol
Min
Supply voltage
VCCA
High-level input voltage
Max
Unit
Conditions
2.3
5.5
V
VIH
0.7*VCC
5.5
V
Low-level input voltage
VIL
-0.5
0.3*VCC
V
High-level output current
IOH
-10
mA
Low-level output current(P00-P07,P10-P17)
IOL
10
mA
Low-level output current(/INT,SDA)
IOL
3.5
mA
Operating free-air temperature
TA
85
℃
-40
4. Thermal Information
Parameters
Symbol
SOW-16
Junction-to-ambient thermal resistance
θJA
108.8
Junction-to-case(top) thermal resistance
θJC（top）
54
θJB
62.8
Junction-to-board thermal resistance
Copyright © 2020, NOVOSENSE
Unit
℃/W
Page 6
NCA9555
Datasheet (EN) 1.3
5. SPECIFICATIONS
5.1. Electrical characteristics
VCC = 2.3V to 5.5V;Tamb = -40℃ to +85℃; unless otherwise noted.
Parameters
Symbol
Min
Typ
Max
Unit
Conditions
Supply voltage
Range
VDD
2.3
-
5.5
V
Power On Reset
VPOR
-
0.94
1.5
V
no load; VI = VDD or VSS
Supply current
IDD
-
5.74
90
µA
Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz
Standby current
Istb
-
0.9
1.5
mA
Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0
kHz; I/O = inputs
-
0.25
1
µA
Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0
kHz; I/O = inputs
Supplies
[1]
Input SCL; Input and Output SDA
LOW-level input
voltage
VIL
-0.5
-
0.3*VDD
V
HIGH-level input
voltage
VIH
0.7*VDD
-
5.5
V
LOW-level
output current
IOL
3
-
-
mA
VDD = 2.3 V to 5.5 V; VOL = 0.4 V
Input leakage
current
IL
-1
-
+1
µA
VDD = 2.3 V to 5.5 V; VI = VDD or VSS
Input
capacitance
Ci
-
6
10
pF
VI = VSS
LOW-level input
voltage
VIL
-0.5
-
0.3*VDD
V
HIGH-level input
voltage
VIH
0.7*VDD
-
5.5
V
LOW-level
output current
IOL
8
13 to 23
-
mA
VDD = 2.3 V to 5.5 V; VOL = 0.5 V[2]
10
16 to 32
-
mA
VDD = 2.3 V to 5.5 V; VOL = 0.7 V[2]
1.8
-
-
V
IOH = -8 mA; VDD = 2.3 V[3]
I/Os
VOH
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NCA9555
Datasheet (EN) 1.3
HIGH-level
output voltage
1.7
-
-
V
IOH = -10 mA; VDD = 2.3 V[3]
2.6
-
-
V
IOH = -8 mA; VDD = 3.0 V[3]
2.5
-
-
V
IOH = -10 mA; VDD = 3.0 V[3]
4.3
-
-
V
IOH = -8 mA; VDD = 4.75V[3]
4.0
-
-
V
IOH = -10 mA; VDD = 4.75V[3]
HIGH-level input
leakage current
ILIH
-
-
1
µA
VDD = 5.5 V; VI = VDD
LOW-level input
leakage current
ILIL
-
-
-100
µA
VDD = 5.5 V; VI = VSS
Input
capacitance
Ci
-
3.7
5
pF
Output
capacitance
Co
-
3.7
5
pF
IOL
3
-
-
mA
Interrupt ̅̅̅̅̅̅
𝑰𝑵𝑻
LOW-level
output current
VDD = 2.3 V to 5.5 V; VOL=0.4V
Select Inputs A0, A1, A2
LOW-level input
voltage
VIL
-0.5
-
0.3*VDD
HIGH-level input
voltage
VIH
0.7*VDD
-
5.5
V
Input leakage
current
ILI
-
+1
µA
-1
V
VDD = 2.3 V to 5.5 V; VI = VDD or VSS
1.VDD must be lowered to 0.2V for at least 50µs in order to reset part.
2.Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of
100 mA for a device total of 200 mA.
3.The total current sourced by all I/Os must be limited to 160 mA.
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Page 8
NCA9555
Datasheet (EN) 1.3
Fig 1. VOH versus Supply Voltage
Fig 2. IDD versus number of I/Os held LOW
5.2. Dynamic Characteristics
Parameters
Symbol
Standard-mode I2C-bus
Fast-mode I2C-bus
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
bus free time between a STOP and START
condition
tBUF
4.7
-
1.3
-
µs
hold time (repeated) START condition
tHD;STA
4.0
-
0.6
-
µs
set-up time for a repeated START condition
tSU;STA
4.7
-
0.6
-
µs
set-up time for STOP condition
tSU;STO
4.0
-
0.6
-
µs
data valid acknowledge time
tVD;ACK[1]
0.3
3.45
0.1
0.9
µs
data hold time
tHD;DAT
0
-
0
-
ns
data valid time
tVD;DAT[2]
300
-
50
-
ns
data set-up time
tSU;DAT
250
-
100
-
ns
LOW period of the SCL clock
tLOW
4.7
-
1.3
-
µs
HIGH period of the SCL clock
tHIGH
4.0
-
0.6
-
µs
fall time of both SDA and SCL signals
tf
-
300
20 + 0.1Cb[3]
300
ns
rise time of both SDA and SCL signals
tr
-
1000
20 + 0.1Cb[3]
300
ns
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NCA9555
Datasheet (EN) 1.3
pulse width of spikes that must be
suppressed by the input filter
tSP
-
50
-
50
ns
data output valid time
tv(Q)
-
200
-
200
ns
data input set-up time
tsu(D)
150
-
150
-
ns
data input hold time
th(D)
1
-
1
-
µs
valid time on pin /INT
tv(INT_N) [4]
-
4
-
4
µs
reset time on pin /INT
trst(INT_N) [5]
-
4
-
4
µs
1.t
2.t
VD;ACK
VD;DAT
= time for acknowledgement signal from SCL LOW to SDA (out) LOW, see Figure 22.
= minimum time for SDA data out to be valid following SCL LOW, see Figure 22.
3.C = total capacitance of one bus line in pF.
b
4.t
5.t
V(INT_N)
is measured from 50% IO input to 0.3VDD on /INT
rst(INT_N)
is measured from 0.3VDD on SCL to 0.7VDD on /INT.
0.7 x VDD
0.3 x VDD
SDA
tBUF
tLOW
tr
tHD;STA
tf
tSP
0.7 x VDD
0.3 x VDD
SCL
tHD;STA
P
S
tSU;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STO
P
Fig 3. Definition of timing on I2C-bus
6. Register Description
The register map of the NCA9555 includes input port registers, output port registers, polarity inversion port registers and configuration
registers.
6.1. Device address
slave address
0
1
0
fixed
0
A2 A1 A0 R/W
programmable
Fig 4. NCA9555 device address
6.2. command byte
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which
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Page 10
NCA9555
Datasheet (EN) 1.3
of the following registers will be written or read.
Table 4. Command byte
Command
Register
0
Input port 0
1
Input port 1
2
Output port 0
3
Output port 1
4
Polarity Inversion port 0
5
Polarity Inversion port 1
6
Configuration port 0
7
Configuration port 1
6.3. registers 0 and 1 : input port registers
This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input
or an output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 5. Input Port 0 Register
Bit
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 6. Input Port 1 Register
Bit
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
6.4. registers 2 and 3 : output port registers
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit values in
this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
Table 7. Output Port 0 Register
Bit
7
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6
5
4
3
2
1
0
Page 11
NCA9555
Datasheet (EN) 1.3
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 8. Output Port 1 Register
Bit
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
6.5. registers 4 and 5 : polarity inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the
Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 9. Polarity Inversion Port 0 Register
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 10. Polarity Inversion Port 1 Register
Bit
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
6.6. Registers 6 and 7 : CONFIGURATION registers
This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin is
enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin
is enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At reset, the device's ports are inputs with a
pull-up to VDD.
Table 11. Configuration Port 0 Register
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NCA9555
Datasheet (EN) 1.3
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 12. Configuration Port 1 Register
Bit
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
6.7. POWER-ON RESET
When power is applied to VDD, an internal power-on reset holds the NCA9555 in a reset condition until VDD has reached VPOR. At
that point, the reset condition is released and the NCA9555 registers and I2C state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power supply is above VPOR. However, when it is
required to reset the part by lowering the power supply, it is necessary to lower it below 0.2 V for at least 50µs.
6.8. I/O PORT
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up to VDD. The input
voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between
the pin and either VDD or VSS.
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NCA9555
Datasheet (EN) 1.3
Output port
register data
Data from
shift register
Write
configuration
pulse
configuration
register
D
VDD
Q1
Q
FF
CK QB
Data from
shift register
Write pulse
100KΩ
I/O pin
D
Q
Q2
FF
CK
Output port
register
VSS
Input port
register
D
Read pulse
Q
FF
CK
Input port
register data
To INT
Data from shift register
Write polarity pulse
Polarity inversion
register
D Q
FF
CK
Polarity
inversion
register data
Fig 5. Simplified schematic of I/Os
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Page 14
NCA9555
Datasheet (EN) 1.3
7. BUS TRANSACTIONS
NCA9555
A0
A1
A2
SCL
I2C-BUS
CONTROL
INPUT
FILTER
SDA
16 bits
I/O
PORT
IO0_0 ~ IO0_7
Write pulse
IO1_0 ~ IO1_7
Read pulse
VDD
POWER-ON
RESET
VDD
LP FILTER
INT
VSS
Fig 6. Block Diagram of NCA9555
7.1. WRITING TO THE PORT REGISTERS
Data is transmitted to the NCA9555 by sending the device address and setting the least significant bit to a logic 0 (see Figure 4
“NCA9555 device address”). The command byte is sent after the address and determines which register will receive the data following
the command byte.
The eight registers within the NCA9555 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register
in the pair (see Figure 7 and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3), then the next byte will be
stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each
8-bit register may be updated independently of the other registers.
1
SCL
2
3
4
5
6
7
8
9
Command byte
slave address
SDA
S
0
1
0
START condition
0 A2 A1 A0 0
R/W
A
0
0
0
Acknowledge
from slave
0
0
0
Data to port 1
Data to port 0
1
0
A 0.7
DATA 0
0.0 A 1.7
Acknowledge
from slave
DATA 1
1.0 A
P
STOP
condition
Acknowledge
from slave
Write to port
Data out
from port 0
Data out
from port 1
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tv(Q)
tv(Q)
DATA VALID
Page 15
NCA9555
Datasheet (EN) 1.3
Fig 7. Write to output port registers
1
SCL
2
3
4
5
6
7
8
9
Command byte
slave address
SDA
S
0
1
0
0 A2 A1 A0 0
START condition
R/W
A
0
0
0
0
0
1
Data to register
Data to register
1
0
Acknowledge
from slave
A
DATA 0
A
Acknowledge
from slave
DATA 1
A
P
STOP
condition
Acknowledge
from slave
Fig 8. Write to config registers
7.2. READING THE PORT REGISTERS
In order to read data from the NCA9555, the bus master must first send the NCA9555 address with the least significant bit set to a logic
0 (see Figure 4 “NCA9555 device address”). The command byte is sent after the address and determines which register will be accessed.
After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined
by the command byte will then be sent by the NCA9555 (see Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the
rising edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the
information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There
is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not
acknowledge the data.
slave address
SDA
S
0
1
0
0 A2 A1 A0 0
START condition
R/W
A
A (cont.)
COMMAND BYTE
Acknowledge
from slave
Acknowledge
from slave
Data from lower or
upper byte of register
slave address
(cont.)
S
0
1
0
(repeated)
START condition
MSB
0 A2 A1 A0 1
A
Data from upper or
lower byte of register
LSB
DATA (first byte)
MSB
A
Acknowledge
from master
R/W
Acknowledge
from slave
LSB
DATA (last byte)
NA P
No acknowledge
from master
STOP
condition
At this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
Remark: Transfer of data can be stopped at any moment by a STOP condition.
Fig 9. Read from registers
Copyright © 2020, NOVOSENSE
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Datasheet (EN) 1.3
Data into port 0
DATA 00
DATA 01
DATA 02
th(D)
Data into port 1
DATA 03
tsu(D)
DATA 11
DATA 10
DATA 12
th(D)
tsu(D)
INT
tv(INT_N)
1
SCL
2
3
trst(INT_N)
4
5
6
7
8
9
0 A2 A1 A0 1
A
I0.x
slave address
SDA
S
0
1
0
START condition
A
Acknowledge
from slave
R/W
I0.x
I1.x
DATA 00
DATA 10
A
Acknowledge
from master
STOP condition
I1.x
DATA 03
A
Acknowledge
from master
DATA 12
1
P
Non acknowledge
from master
Acknowledge
from master
Read from port 0
Read from port 1
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid(output mode). It
is assumed that the command byte has previously been set to 00 (read Input Port register).
Fig 10. Read input port registers, scenario 1
Data into port 0
Data into port 1
INT
tv(INT_N)
SCL
1
2
0
1
3
trst(INT_N)
4
5
6
7
8
9
0 A2 A1 A0 1
A
I0.x
slave address
SDA
S
0
START condition
R/W
7
6
5
Acknowledge
from slave
4
3
I0.x
I1.x
2
1
0
A
7
6
5
Acknowledge
from master
4
3
2
1
0
A
7
6
5
Acknowledge
from master
4
3
STOP condition
I1.x
2
1
0
A
7
6
5
Acknowledge
from master
4
3
2
1
0
1
P
Non acknowledge
from master
Read from port 0
Read from port 1
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid(output mode). It
is assumed that the command byte has previously been set to 00 (read Input Port register).
Fig 11. Read input port registers, scenario 2
7.3. interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt
is deactivated when the input returns to its previous state or the Input Port register is read (see Figure 10). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a
read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the
contents of the Input Port register.
8. characteristics of the I2C-BUS
.
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial
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NCA9555
Datasheet (EN) 1.3
clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a
device. Data transfer may be initiated only when the bus is not busy.
8.1. bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as control signals (see Figure 12).
SDA
SCL
Data line
stable;
Data valid
Change
of data
allowed
Fig 12. Bit transfer
8.2. start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is
defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition
(P) (see Figure 13).
SDA
SCL
S
P
START condition
STOP condition
Fig 13. Definition of START and STOP conditions
8.3. system configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’
and the devices which are controlled by the master are the ‘slaves’ (see Figure 14).
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NCA9555
Datasheet (EN) 1.3
SCL
SDA
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
Fig 14. System configuration
8.4. Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each
byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas
the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse; set-up time and hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Data output
by transmitter
Not acknowledge
Data output
by receiver
acknowledge
SCL from master
1
2
S
8
9
Clock pulse for
acknowledgement
START condition
Fig 15. Acknowledgement on I2C-bus
9. APPLICATION DESIGN-IN INFORMATION
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NCA9555
Datasheet (EN) 1.3
VDD
(5 V)
10KΩ
10KΩ
10KΩ
2KΩ
VDD
VDD
MASTER
CONTROLLER
SCL
SCL
SDA
INT
INT
IO0_2
IO0_3
NCA9555
SDA
IO0_0
IO0_1
GND
SUB-SYSTEM 1
(e.g., temp
sensor)
IN
T
SUB-SYSTEM 2
(e.g., temp
sensor)
RESET
A
IO0_4
IO0_5
IO0_7
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
A1
IO1_5
IO1_6
VSS
SUB-SYSTEM 3
(e.g., alarm system)
IO0_6
A2
A0
B
Controlled switch
(e.g., CBT
device)
ALARM
10 DIGIT
NUMERIC
KEYPAD
VDD
IO1_7
Fig 16. Typical application
When the IO level of the NCA9555 is higher than the power supply voltage, the diode inside the chip to prevent backflow will be
turned on. In the case of power down and data input, the IO signal will be fed back to the VDD module (eg.master controller), which
will cause the data to be pulled low. In order to realize IO still has high resistance characteristics when power down,it is
recommended to connect a forward schottky diode to the power supply pin of NCA9555.
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Datasheet (EN) 1.3
10. Test information
VDD
PULSE
GENERATOR
VI
DUT
RL
500Ω
VO
VDD
open
GND
CL
50pF
RT
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance of Z o of the pulse generators.
Fig 17. Test circuitry for switching times
RL
From output under test
CL
50pF
RL
500Ω
500Ω
2VDD
open
GND
Fig 18. Load circuit
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NCA9555
Datasheet (EN) 1.3
trst(INT_N)
0.7 x VDD
0.3 x VDD
SCL
1st clock
2nd clock
8th clock
9th clock
0.7 x VDD
0.3 x VDD
INT
Fig 19. Parameter Measurement Waveform: trst(INT_N)
0.7 x VDD
0.3 x VDD
SCL
tVD;DAT
tVD;ACK
9th clock
0.7 x VDD
0.3 x VDD
SDA
Fig 20. Parameter Measurement Waveform: tVD; DAT & tVD;ACK
11. Package information
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NCA9555
Datasheet (EN) 1.3
11.1. package outline
Fig 21. Package outline for TSSOP24
12. TAPE AND REEL INFORMATION
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NCA9555
Datasheet (EN) 1.3
ALL DIMENSIONSIN MILLIMETERS UNLESS OTHERWISE STATED
Fig 22. tape and reel information for TSSOP24
13. Order information
Copyright © 2020, NOVOSENSE
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NCA9555
Datasheet (EN) 1.3
Part No.
Package Type
Pins
MSL Level
Package Qty
Temperature
NCA9555
TSSOP
24
Level 1
2500
-40 to 85℃
14. Documentation Support
Part Number
Product Folder
Datasheet
Technical Documents
Isolator selection guide
NCA9555
Click here
Click here
Click here
Click here
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NCA9555
Datasheet (EN) 1.3
15. Revision history
Revision
1.0
1.1
1.2
1.3
Description
Initial version
Added thermal information& order information
Changed 3.0 supply current,VPOR and IOL
Added application design-in information
Copyright © 2020, NOVOSENSE
Date
2019/2/27
2020/2/10
2020/5/31
2020/10/30
Page 26
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