RTL8367N-VB-CG
SINGLE-CHIP 5-PORT 10/100/1000M
SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. Pre-0.9
20 February 2014
Track ID: xxxx-xxxx-xx
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8367N-VB
Datasheet
COPYRIGHT
©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8367N-VB IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Pre-0.9
Release Date
2014/02/20
Summary
First Release.
Single-Chip 5-Port 10/100/1000M Switch Controller
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RTL8367N-VB
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS...............................................................................................................................................5
4.
APPLICATION EXAMPLE .............................................................................................................................................6
4.1.
5-PORT 1000BASE-T SWITCH ......................................................................................................................................6
5.
BLOCK DIAGRAM ...........................................................................................................................................................7
6.
PIN ASSIGNMENTS .........................................................................................................................................................8
6.1.
6.2.
7.
PACKAGE IDENTIFICATION ...........................................................................................................................................8
PIN ASSIGNMENTS TABLE ............................................................................................................................................9
PIN DESCRIPTIONS.......................................................................................................................................................11
7.1.
MEDIA DEPENDENT INTERFACE PINS .........................................................................................................................11
7.2.
LED PINS ...................................................................................................................................................................12
7.3.
CONFIGURATION STRAPPING PINS .............................................................................................................................13
7.3.1. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF) ......................................................14
7.4.
MICROPROCESSOR PINS .............................................................................................................................................14
7.5.
TEST PINS ..................................................................................................................................................................15
7.6.
MISCELLANEOUS PINS ...............................................................................................................................................15
7.7.
POWER AND GND PINS ..............................................................................................................................................16
8.
PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................17
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
9.
MDI INTERFACE ........................................................................................................................................................17
1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................17
1000BASE-T RECEIVE FUNCTION ..............................................................................................................................17
100BASE-TX TRANSMIT FUNCTION...........................................................................................................................17
100BASE-TX RECEIVE FUNCTION .............................................................................................................................18
10BASE-T TRANSMIT FUNCTION ...............................................................................................................................18
10BASE-T RECEIVE FUNCTION ..................................................................................................................................18
AUTO-NEGOTIATION FOR UTP ..................................................................................................................................18
CROSSOVER DETECTION AND AUTO CORRECTION .....................................................................................................19
POLARITY CORRECTION .............................................................................................................................................19
GENERAL FUNCTION DESCRIPTION......................................................................................................................20
9.1.
RESET ........................................................................................................................................................................20
9.1.1. Hardware Reset ....................................................................................................................................................20
9.1.2. Software Reset ......................................................................................................................................................20
9.2.
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................21
9.3.
HALF DUPLEX FLOW CONTROL .................................................................................................................................21
9.3.1. Back-Pressure Mode ............................................................................................................................................21
9.4.
SEARCH AND LEARNING ............................................................................................................................................22
9.5.
SVL AND IVL/SVL ...................................................................................................................................................22
9.6.
ILLEGAL FRAME FILTERING .......................................................................................................................................22
9.7.
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL .............................................................................22
9.8.
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................24
9.9.
PORT SECURITY FUNCTION ........................................................................................................................................24
9.10.
MIB COUNTERS .........................................................................................................................................................24
9.11.
PORT MIRRORING ......................................................................................................................................................24
9.12.
VLAN FUNCTION ......................................................................................................................................................25
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9.12.1.
Port-Based VLAN ............................................................................................................................................25
9.12.2.
IEEE 802.1Q Tag-Based VLAN.......................................................................................................................25
9.12.3.
Protocol-Based VLAN .....................................................................................................................................26
9.12.4.
Port VID ..........................................................................................................................................................26
9.13.
QOS FUNCTION ..........................................................................................................................................................27
9.13.1.
Input Bandwidth Control .................................................................................................................................27
9.13.2.
Priority Assignment .........................................................................................................................................27
9.13.3.
Priority Queue Scheduling...............................................................................................................................27
9.13.4.
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................28
9.13.5.
ACL-Based Priority .........................................................................................................................................28
9.14.
IGMP & MLD SNOOPING FUNCTION.........................................................................................................................29
9.15.
IEEE 802.1X FUNCTION .............................................................................................................................................30
9.15.1.
Port-Based Access Control..............................................................................................................................30
9.15.2.
Authorized Port-Based Access Control ...........................................................................................................30
9.15.3.
Port-Based Access Control Direction..............................................................................................................30
9.15.4.
MAC-Based Access Control.............................................................................................................................30
9.15.5.
MAC-Based Access Control Direction ............................................................................................................30
9.15.6.
Optional Unauthorized Behavior.....................................................................................................................31
9.15.7.
Guest VLAN .....................................................................................................................................................31
9.16.
IEEE 802.1D FUNCTION ............................................................................................................................................31
9.17.
EMBEDDED 8051........................................................................................................................................................31
9.18.
REALTEK CABLE TEST (RTCT) .................................................................................................................................32
9.19.
LED INDICATORS.......................................................................................................................................................32
9.20.
GREEN ETHERNET ......................................................................................................................................................34
9.20.1.
Link-On and Cable Length Power Saving .......................................................................................................34
9.20.2.
Link-Down Power Saving ................................................................................................................................34
9.21.
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ...............................................................................34
10.
INTERFACE DESCRIPTIONS .................................................................................................................................35
10.1.
10.2.
11.
EEPROM SMI HOST TO EEPROM ...........................................................................................................................35
EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................36
REGISTER DESCRIPTIONS ....................................................................................................................................37
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
11.8.
11.9.
11.10.
11.11.
11.12.
11.13.
12.
PCS REGISTER (PHY 0~4).........................................................................................................................................37
REGISTER 0: CONTROL ...............................................................................................................................................38
REGISTER 1: STATUS ..................................................................................................................................................39
REGISTER 2: PHY IDENTIFIER 1 .................................................................................................................................40
REGISTER 3: PHY IDENTIFIER 2 .................................................................................................................................40
REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................40
REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................41
REGISTER 6: AUTO-NEGOTIATION EXPANSION ..........................................................................................................42
REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER ..................................................................................42
REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................43
REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................43
REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................44
REGISTER 15: EXTENDED STATUS .........................................................................................................................44
ELECTRICAL CHARACTERISTICS......................................................................................................................45
12.1.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................45
12.2.
RECOMMENDED OPERATING RANGE..........................................................................................................................45
12.3.
THERMAL CHARACTERISTICS.....................................................................................................................................46
12.3.1.
Assembly Description ......................................................................................................................................46
12.3.2.
Material Properties .........................................................................................................................................46
12.3.3.
Simulation Conditions .....................................................................................................................................46
12.3.4.
Thermal Performance of QFN-88 on PCB Under Still Air Convection ..........................................................46
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12.3.5.
Thermal Performance of QFN-88 on PCB Under Forced Convection............................................................47
12.4.
DC CHARACTERISTICS ...............................................................................................................................................47
12.5.
AC CHARACTERISTICS ...............................................................................................................................................48
12.5.1.
EEPROM SMI Host Mode Timing Characteristics .........................................................................................48
12.5.2.
EEPROM SMI Slave Mode Timing Characteristics ........................................................................................49
12.5.3.
MDIO Slave Mode Timing Characteristics .....................................................................................................50
12.6.
POWER AND RESET CHARACTERISTICS ......................................................................................................................51
13.
13.1.
14.
MECHANICAL DIMENSIONS.................................................................................................................................52
MECHANICAL DIMENSIONS NOTES ............................................................................................................................53
ORDERING INFORMATION ...................................................................................................................................54
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List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................9
TABLE 2. MEDIA DEPENDENT INTERFACE PINS ...........................................................................................................................11
TABLE 3. LED PINS .....................................................................................................................................................................12
TABLE 4. CONFIGURATION STRAPPING PINS................................................................................................................................13
TABLE 5. CONFIGURATION STRAPPING PINS (DISAUTOLOAD, DIS_8051, AND EN_SPIF).....................................................14
TABLE 6. MICROPROCESSOR PINS ...............................................................................................................................................14
TABLE 7. TEST PINS.....................................................................................................................................................................15
TABLE 8. MISCELLANEOUS PINS .................................................................................................................................................15
TABLE 9. POWER AND GND PINS ................................................................................................................................................16
TABLE 10. MEDIA DEPENDENT INTERFACE PIN MAPPING ...........................................................................................................19
TABLE 11. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE .........................................................................................23
TABLE 12. IPV4/IPV6 MULTICAST ROUTING PROTOCOLS .............................................................................................................29
TABLE 13. LED DEFINITIONS........................................................................................................................................................32
TABLE 14. PCS REGISTER (PHY 0~4)...........................................................................................................................................37
TABLE 15. REGISTER 0: CONTROL ................................................................................................................................................38
TABLE 16. REGISTER 1: STATUS....................................................................................................................................................39
TABLE 17. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................40
TABLE 18. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................40
TABLE 19. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ...................................................................................................40
TABLE 20. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................41
TABLE 21. REGISTER 6: AUTO-NEGOTIATION EXPANSION ............................................................................................................42
TABLE 22. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER....................................................................................42
TABLE 23. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ...................................................................43
TABLE 24. REGISTER 9: 1000BASE-T CONTROL REGISTER ...........................................................................................................43
TABLE 25. REGISTER 10: 1000BASE-T STATUS REGISTER ............................................................................................................44
TABLE 26. REGISTER 15: EXTENDED STATUS ...............................................................................................................................44
TABLE 27. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................45
TABLE 28. RECOMMENDED OPERATING RANGE ...........................................................................................................................45
TABLE 29. ASSEMBLY DESCRIPTION .............................................................................................................................................46
TABLE 30. MATERIAL PROPERTIES ...............................................................................................................................................46
TABLE 31. SIMULATION CONDITIONS ...........................................................................................................................................46
TABLE 32. THERMAL PERFORMANCE OF QN-88 ON PCB UNDER STILL AIR CONVECTION...........................................................46
TABLE 33. THERMAL PERFORMANCE OF QFN-88 ON PCB UNDER FORCED CONVECTION ...........................................................47
TABLE 34. DC CHARACTERISTICS .................................................................................................................................................47
TABLE 35. EEPROM SMI HOST MODE TIMING CHARACTERISTICS .............................................................................................49
TABLE 36. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ...........................................................................................49
TABLE 37. MDIO TIMING CHARACTERISTICS AND REQUIREMENTS .............................................................................................50
TABLE 38. POWER AND RESET CHARACTERISTICS ........................................................................................................................51
TABLE 39. ORDERING INFORMATION ............................................................................................................................................54
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List of Figures
FIGURE 1. 5-PORT 1000BASE-T SWITCH .......................................................................................................................................6
FIGURE 2. BLOCK DIAGRAM ..........................................................................................................................................................7
FIGURE 3. PIN ASSIGNMENTS ........................................................................................................................................................8
FIGURE 4. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................19
FIGURE 5. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART ..................................................................................26
FIGURE 6. MAX-MIN SCHEDULING DIAGRAM ...........................................................................................................................28
FIGURE 7. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED...........................................................................33
FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED...................................................................................33
FIGURE 9. SMI START AND STOP COMMAND ..............................................................................................................................35
FIGURE 10. EEPROM SMI HOST TO EEPROM............................................................................................................................35
FIGURE 11. EEPROM SMI HOST MODE FRAME...........................................................................................................................35
FIGURE 12. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................36
FIGURE 13. EEPROM SMI READ COMMAND FOR SLAVE MODE ..................................................................................................36
FIGURE 14. EEPROM SMI HOST MODE TIMING CHARACTERISTICS ............................................................................................48
FIGURE 15. SCK/SDA POWER ON TIMING ....................................................................................................................................48
FIGURE 16. EEPROM AUTO-LOAD TIMING..................................................................................................................................48
FIGURE 17. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ..........................................................................................49
FIGURE 18. MDIO SOURCED BY MASTER (RTL8367N-VB LINK PARTNER CPU) .......................................................................50
FIGURE 19. MDIO SOURCED BY SLAVE (RTL8367N-VB) ...........................................................................................................50
FIGURE 20. POWER AND RESET CHARACTERISTICS .......................................................................................................................51
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1.
General Description
The RTL8367N-VB-CG is a QFN88, high-performance 5-port 10/100/1000M Ethernet switch with an
integrated low-power 5-port Giga-PHY that supports 1000Base-T, 100Base-TX, and 10Base-T.
The RTL8367N-VB integrates all the functions of a high-speed switch system; including SRAM for
packet buffering, non-blocking switch fabric, and internal register management into a single CMOS
device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal register
configuration.
The embedded packet storage SRAM in the RTL8367N-VB features superior memory management
technology to efficiently utilize memory space. The RTL8367N-VB integrates a 2K-entry look-up table
with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write
access from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured
as a static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used
to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The RTL8367N-VB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress.
When using this function, VID information carried in the VLAN tag will be changed to PVID.
The RTL8367N-VB supports standard 802.3x flow control frames for full duplex, and optional
backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the
availability of system resources, including the packet buffers and transmitting queues. The RTL8367NVB supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to nonblocked ports only. For IP multicast applications, the RTL8367N-VB supports IPv4 IGMPv1/v2/v3 and
IPv6 MLDv1/v2 snooping.
In order to support flexible traffic classification, the RTL8367N-VB supports 96-entry ACL rule check
and multiple action options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, force output tag format and rate policing. The rate policing mechanism supports from
8Kbps to 1Gbps (in 8Kbps steps).
In Bridge operation the RTL8367N-VB supports 16 sets of port configurations: disable, block, learning,
and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and
management application requirements, the RTL8367N-VB supports IEEE 802.1x Port-based/MAC-based
Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8367N-VB provides
a Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set
Port Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s
ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8367N-VB supports eight priority
assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag
priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a
weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input
bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average
packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or
Weighted Fair Queue (WFQ) or mixed.
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The RTL8367N-VB provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocolbased VLAN operation to separate logical connectivity from physical connectivity. The RTL8367N-VB
supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and
RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM
SMI Slave after reset.
In router applications, the router may want to know the input port of the incoming packet. The
RTL8367N-VB supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port.
The RTL8367N-VB also provides an option to admit VLAN tagged packets with a specific PVID only. If
this function is enabled, the RTL8367N-VB will drop all non-tagged packets and packets with an
incorrect PVID.
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2.
Features
Single-chip 5-port 10/100/1000M nonblocking switch architecture
Embedded 5-port 10/100/1000Base-T PHY
Each port supports full duplex
10/100/1000M connectivity (half duplex
only supported in 10/100M mode)
Full-duplex and half-duplex operation with
IEEE 802.3x flow control and backpressure
Supports 9216-byte jumbo packet length
forwarding at wire speed
Realtek Cable Test (RTCT) function
Supports 96-entry ACL Rules
Search keys support physical port,
Layer2, Layer3, and Layer4 information
Actions include mirror, redirect,
dropping, priority adjustment, traffic
policing, CVLAN decision, SVLAN
assignment, force output tag format,
interrupt and logging counter
Supports five types of user defined ACL
rule format for 96 ACL rules
Optional per-port enable/disable of ACL
function
Optional setting of per-port action to
take when ACL mismatch
Supports 4K VLANs and 32 Extra
Enhanced VLANs
Supports Un-tag definition in each
VLAN
Supports VLAN policing and VLAN
forwarding decision
Single-Chip 5-Port 10/100/1000M Switch Controller
Port-based, Tag-based, and Protocolbased VLAN
Up to 4 Protocol-based VLAN entries
Per-port and per-VLAN egress VLAN
tagging and un-tagging
Supports IVL, SVL, and IVL/SVL
2K-entry MAC address table with 4-way
hash algorithm
Up to 2K-entry L2/L3 Filtering Database
Per-port MAC learning limitation
System base MAC learning limitation
Spanning Tree port behavior configuration
IEEE 802.1w Rapid Spanning Tree
IEEE 802.1s Multiple Spanning Tree
with up to 16 Spanning Tree instances
IEEE 802.1x Access Control Protocol
Port-Based Access Control
MAC-Based Access Control
Guest VLAN
Supports Auto protection from Denial-ofService attacks
H/W IGMP/MLD Snooping
IEEE 802.1Q VLAN
3
IGMPv1/v2/v3 and MLD v1/v2
Supports ‘Fast Leave’
Static router port configuration
Dynamic router port learning and aging
Quality of Service (QoS)
Supports per-port Input Bandwidth
Control
Eight Priority Queues per port
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Per queue flow control
Traffic classification based on IEEE
802.1p/Q priority definition, physical
Port, IP DSCP field, ACL definition,
VLAN based priority, MAC based
priority, and SVLAN based priority
Min-Max Scheduling
Strict Priority and Weighted Fair Queue
(WFQ) to provide minimum bandwidth
One leaky bucket to constrain the
average packet rate of each queue
Supports rate limiting (32 shared meters,
with 8kbps granulation or packets per
second configuration)
Port Mirror function for one monitor port for
multiple mirroring ports
OAM and EEE LLDP (Energy Efficient
Ethernet Link Layer Discovery Protocol
Loop Detection
Security Filtering
Disable learning for each port
Disable learning-table aging for each
port
Drop unknown DA for each port
Broadcast/Multicast/Unknown DA storm
control protects system from attack by
hackers
Supports IEEE 802.3az Energy Efficient
Ethernet (EEE)
Supports Realtek Green Ethernet features
RFC MIB Counter
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
Link-On Cable Length Power Saving
Bridge MIB (RFC 1493)
Link-Down Power Saving
Bridge MIB Extension (RFC 2674)
Each port supports 2 LED outputs
Stacking VLAN and Port Isolation with
eight Enhanced Filtering Databases
Supports EEPROM SMI Slave interface to
access configuration register
IEEE 802.1ad Stacking VLAN
Supports 32K-byte EEPROM space for
configuration
Supports 64 SVLANs
Supports 32 L2/IPv4 Multicast mappings
to SVLAN
Integrated 8051 microprocessor
Supports MAC-based 1:N VLAN
Supports Flash Interface
25MHz crystal or 3.3V OSC input
QFN 88-pin package
Supports two IEEE 802.3ad Link
aggregation port groups
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3.
System Applications
5-Port 1000Base-T Switch
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4.
4.1.
Application Example
5-Port 1000Base-T Switch
Figure 1. 5-Port 1000Base-T Switch
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5.
Block Diagram
Figure 2. Block Diagram
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6.
Pin Assignments
Figure 3. Pin Assignments
6.1.
Package Identification
Green package is indicated by the ‘G’ and Version B is indicated by the ‘B’ in GXXXB (Figure 3).
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6.2.
Pin Assignments Table
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm)
(Typical Value = 75K Ohm)
IS: Input Pin With Schmitt Trigger
Name
P0MDICP
P0MDICPN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL
P2MDIAP
P2MDIAN
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
Table 1. Pin Assignments Table
Pin No. Type
Name
1
AI/O
P2MDIDP
2
AI/O
P2MDIDN
3
AI/O
AVDDH
4
AI/O
P3MDIAP
5
AP
P3MDIAN
6
AI/O
P3MDIBP
7
AI/O
P3MDIBN
8
AI/O
AVDDL
9
AI/O
P3MDICP
10
AP
P3MDICN
11
AI/O
P3MDIDP
12
AI/O
P3MDIDN
13
AI/O
AVDDH
14
AP
AGND
15
AP
MDIREF
16
AI/O
AVDDL
17
AI/O
RTT1
18
AI/O
AVDDH
19
AI/O
DVDDL
20
AP
AVDDH
21
AI/O
P4MDIAP
22
AI/O
P4MDIAN
Single-Chip 5-Port 10/100/1000M Switch Controller
9
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Type
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AG
AO
AP
AO
AP
P
AP
AI/O
AI/O
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
Name
P4MDIBP
P4MDIBN
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
AVDDL
GPIO01/UART_RX
GPIO02/UART_TX
GPIO04/SPIF_CLK
GPIO05/SPIF_D0
GPIO09/SPIF_D1
GPIO10/SPIF_CS
DVDDL
RESERVED
RESERVED
DVDDIO
DVDDL
GP O39/P4LED0/EEPROM_MOD
GPIO40/P4LED1
GPIO41/P3LED1
Pin No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Type
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AP
I/O
I/O
I/O
I/O
I/O
I/O
P
P
P
P
P
I/OPU
I/OPU
I/OPU
Single-Chip 5-Port 10/100/1000M Switch Controller
Name
GP O43/P3LED0/EN_SPIF
GP O44/DIS_8051
GP O45/P2LED0/DISAUTOLOAD
GPIO46/P2LED1
GP O48/P1LED0/RESERVED
GPIO49/P1LED1
GPIO51/P0LED1/LED_DA
GP O52/P0LED0/LED_CK/
SMI_SEL
NC
AVDDH
XTALO
XTALI
nRESET
SCK/EN_EEE
SDA
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
GND
10
Pin No.
68
69
70
71
72
73
74
75
Type
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
76
77
78
79
80
81
82
83
84
85
86
87
88
EPAD
N/A
AP
AO
AI
IPU
I/OPU
I/O
AP
AI/O
AI/O
AI/O
AI/O
AP
G
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
7.
Pin Descriptions
7.1.
Media Dependent Interface Pins
Pin Name
P0MDIAP/N
P0MDIBP/N
P0MDICP/N
P0MDIDP/N
P1MDIAP/N
P1MDIBP/N
P1MDICP/N
P1MDIDP/N
P2MDIAP/N
P2MDIBP/N
P2MDICP/N
P2MDIDP/N
P3MDIAP/N
P3MDIBP/N
P3MDICP/N
P3MDIDP/N
P4MDIAP/N
P4MDIBP/N
P4MDICP/N
P4MDIDP/N
Pin No.
84
85
86
87
1
2
3
4
6
7
8
9
11
12
13
14
16
17
18
19
21
22
23
24
26
27
28
29
31
32
33
34
43
44
45
46
48
49
50
51
Table 2. Media Dependent Interface Pins
Type Drive Description
AI/O
(mA)
10
Port 0 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-TX and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-TX and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-TX and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-TX and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Single-Chip 5-Port 10/100/1000M Switch Controller
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-TX and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
11
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
7.2.
LED Pins
LED0 and LED1 of Port n indicate information that can be defined via register or EEPROM. When the
LED pin is pulled low, the LED output polarity will be high active. When the LED pin is pulled high, the
LED output polarity will change from high active to low active. See section 9.19 LED Indicators, page 32
for more details.
Pin Name
Pin No.
Type
Table 3. LED Pins
Drive Description
P4LED1
/GPIO40
66
I/OPU
(mA)
-
P4LED0
/GP O39
/EEPROM_MOD
P3LED1
/GPIO41
65
I/OPU
-
67
I/OPU
-
P3LED0
/GP O43
/EN_SPIF
P2LED1
/GPIO46
68
I/OPU
-
71
I/OPU
-
P2LED0
/GP O45
/DISAUTOLOAD
P1LED1
/GPIO49
70
I/OPU
-
73
I/OPU
-
P1LED0
/GP O48
/RESERVED
P0LED1
/GPIO51
/LED_DA
P0LED0
/GP O52
/LED_CK
/SMI_SEL
72
I/OPU
-
74
I/OPU
-
75
I/OPU
-
Single-Chip 5-Port 10/100/1000M Switch Controller
Port 4 LED1 Output Signal.
P4LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 4 LED0 Output Signal.
P4LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 3 LED1 Output Signal.
P3LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 3 LED0 Output Signal.
P3LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 2 LED1 Output Signal.
P2LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 2 LED0 Output Signal.
P2LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 1 LED1 Output Signal.
P1LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 1 LED0 Output Signal.
P1LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 0 LED1 Output Signal.
P0LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
Port 0 LED0 Output Signal.
P0LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 32 for more details.
12
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
7.3.
Configuration Strapping Pins
Pin Name
EEPROM_MOD
/GP O39
/P4LED0
EN_SPIF
/GP O43
/P3LED0
DIS_8051
/GP O44
DISAUTOLOAD
/GP O45
/P2LED0
RESERVED
/GP O48
/P1LED0
Table 4. Configuration Strapping Pins
Pin No.
Type Description
65
I/OPU EEPROM Mode Selection.
Pull Up: EEPROM 24Cxx Size great than 16Kbits (24C32~24C256)
Pull Down: EEPROM 24Cxx Size less than or equal to 16Kbit
(24C02~24C16).
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active. See section 9.19 LED
Indicators, page 32 for more details.
68
I/OPU Enable SPI FLASH Interface.
Pull Up: Enable FLASH interface
Pull Down: Disable FLASH interface
Note 1: The strapping pin DISAUTOLOAD, DIS_8051, and EN_SPIF
are for power on or reset initial stage configuration. Refer to Table 5
Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and
EN_SPIF), page 14 for details.
Note 2: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active. See section 9.19LED
Indicators, page 32 for more details.
69
I/OPU Disable Embedded 8051.
Pull Up: Disable embedded 8051 upon power on or reset
Pull Down: Enable embedded 8051 upon power on or reset
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
70
I/OPU Disable EEPROM Autoload.
Pull Up: Disable EEPROM autoload upon power on or reset
Pull Down: Enable EEPROM autoload upon power on or reset
Note 1: When DIS_8051 = 1 and DISAUTOLOAD =0, the EEPROM
data will be treat as register configuration data upon power on or
reset initial stage. When DIS_8051 =0 and DISAUTOLOAD =0, the
EEPROM data will be loaded to embedded 8051 instruction memory
upon power on or reset.
Note 2: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active. See section 9.19 LED
Indicators, page 32 for more details.
72
I/OPU
Single-Chip 5-Port 10/100/1000M Switch Controller
Internal Use/Reserved.
Note: For normal operation, this pin must be pulled low via an
external 4.7k ohm resistor upon power on or reset.
When pulled low, the LED output polarity will be high active. See
section 9.19 LED Indicators, page 32 for more details.
13
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RTL8367N-VB
Datasheet
Pin Name
SMI_SEL
/GP O52
/P0LED0
/LED_CK
Pin No.
75
Type
I/OPU
EN_EEE
/SCK
75
I/OPU
7.3.1.
Description
EEPROM SMI/MII Management Interface Selection.
Pull Up: EEPROM SMI interface
Pull Down: MII Management Interface
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When pulled high, the LED output polarity will be low active. See
section 9.19 LED Indicators, page 32 for more details.
Enable IEEE 802.3az Energy Efficient Ethernet (EEE).
Pull Up: Enable Energy Efficient Ethernet (EEE) function
Pull Down: Disable Energy Efficient Ethernet (EEE) function
Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and
EN_SPIF)
Table 5. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF)
DISAUTOLOAD
1
Initial Stage (Power On or Reset) Loading Data
To
0
EEPROM
Embedded 8051 Instruction Memory
1
FLASH
Embedded 8051 Instruction Memory
1
0
EEPROM
Register
Irrelevant
Irrelevant
Do Nothing
Do Nothing
Microprocessor Pins
Pin Name
SCK/MMD_MDC/
EN_EEE
SDA/MMD_MDIO
UART_RX
UART_TX
SPIF_CLK
SPIF_D0
SPIF_D1
SPIF_CS
EN_SPIF
From
0
0
7.4.
DIS_8051
Pin No.
81
82
54
55
56
57
58
59
Table 6. Microprocessor Pins
Type Description
O
EEPROM SMI Interface Clock/MII Management Interface Clock (selected via
the hardware strapping pin 89, SMI_SEL).
I/O
EEPROM SMI Interface Data/MII Management Interface Data (selected via
the hardware strapping pin 89, SMI_SEL).
I
Universal Asynchronous Receiver Pin.
O
Universal Asynchronous Transmitter Pin.
O
Serial Clock Output (FLASH Interface).
I/O
Serial Data I/O 0 (FLASH Interface).
I/O
Serial Data I/O 1 (FLASH Interface).
O
Chip Selection (FLASH Interface).
Single-Chip 5-Port 10/100/1000M Switch Controller
14
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
7.5.
Test Pins
Table 7. Test Pins
Pin No. Type Description
39
AO Reserved for Internal Use. Must be left floating.
Pin Name
RTT1
7.6.
Miscellaneous Pins
Pin No.
79
Type
AI
XTALO
78
AO
MDIREF
37
AO
nRESET
80
IPU
RESERVED
61
I
RESERVED
62
I
GPIO01
/UART_RX
GPIO02
/UART_TX
GPIO04
/SPIF_CLK
GPIO05
/SPIF_D0
GPIO09
/SPIF_D1
GPIO10
/SPIF_CS
GP O39
/P4LED0
/EEPROM_MOD
GPIO40
/P4LED1
GPIO41
/P3LED1
54
I/O
Table 8. Miscellaneous Pins
Description
25MHz Crystal Clock Input and Feedback Pin.
25MHz +/-50ppm tolerance crystal reference or oscillator input.
When using a crystal, connect a loading capacitor from each pad to ground.
When either using an oscillator or driving an external 25MHz clock from
another device, XTALO should be kept floating.
The maximum XTALI input voltage is 3.3V.
25MHz Crystal Clock Output Pin.
25MHz +/-50ppm tolerance crystal output.
Reference Resistor.
A 2.49K ohm (1%) resistor must be connected between MDIREF and GND.
System Reset Input Pin.
When low active will reset the RTL8367N-VB.
Reserved.
Note: This pin must be pulled low via an external 1k~10 k ohm resistor upon
power on or reset.
Reserved.
Note: This pin must be pulled low via an external 1k~10 k ohm resistor upon
power on or reset.
General Purpose Input / Output Interface IO01.
55
I/O
General Purpose Input / Output Interface IO02.
56
I/O
General Purpose Input / Output Interface IO04.
57
I/O
General Purpose Input / Output Interface IO05.
58
I/O
General Purpose Input / Output Interface IO09.
59
I/O
General Purpose Input / Output Interface IO10.
65
OPU
General Purpose Output Interface O39.
66
I/OPU
General Purpose Input / Output Interface IO40.
67
I/OPU
General Purpose Input / Output Interface IO41.
Pin Name
XTALI
Single-Chip 5-Port 10/100/1000M Switch Controller
15
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
Pin Name
GP O43
/P3LED0
/EN_SPIF
GPIO44
/DIS_8051
GPIO45
/P2LED0
/DISAUTOLOAD
GPIO46
/P2LED1
GP O48
/P1LED0
/RESERVED
GPIO49
/P1LED1
GPIO51
/P0LED1
/LED_DA
GP O52
/P0LED0
/LED_CK
/SMI_SEL
7.7.
Pin Name
DVDDIO
DVDDL
AVDDH
AVDDL
PLLVDDL
GND
AGND
Pin No.
68
Type
OPU
Description
General Purpose Output Interface O43.
69
OPU
General Purpose Output Interface O44.
70
OPU
General Purpose Output Interface O45.
70
I/OPU
72
OPU
73
I/OPU
General Purpose Input / Output Interface IO49.
74
I/OPU
General Purpose Input / Output Interface IO51.
75
OPU
General Purpose Input / Output Interface IO46.
General Purpose Output Interface O48.
General Purpose Output Interface O52.
Power and GND Pins
Table 9. Power and GND Pins
Pin No.
Type Description
63
P
Digital I/O High Voltage Power for LED, SMI, nRESET.
41, 60, 64, 76
P
Digital Low Voltage Power.
AP
Analog High Voltage Power.
5, 25, 35, 40, 42, 52,
77, 83
AP
Analog Low Voltage Power.
10, 20, 30, 38, 47, 53,
88,
15
AP
PLL Low Voltage Power.
EPAD
G
GND.
36
AG Analog GND.
Single-Chip 5-Port 10/100/1000M Switch Controller
16
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
8.
8.1.
Physical Layer Functional Overview
MDI Interface
The RTL8367N-VB embeds five 10/100/1000M Ethernet PHYs in one chip. Each port uses a single
common MDI interface to support 1000Base-T, 100Base-TX, and 10Base-T. This interface consists of
four signal pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and
receive at the same time. The MDI interface has internal termination resistors, and therefore reduces
BOM cost and PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same
time. For 10/100 links and during auto-negotiation, only pairs A and B are used.
8.2.
1000Base-T Transmit Function
The 1000Base-TX transmit function performs 8B/10B coding, scrambling, and 4D-PAM5 encoding.
These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are
transmitted onto 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
8.3.
1000Base-T Receive Function
Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the
packet buffer manager.
8.4.
100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.
Single-Chip 5-Port 10/100/1000M Switch Controller
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RTL8367N-VB
Datasheet
8.5.
100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
8.6.
10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.
8.7.
10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
8.8.
Auto-Negotiation for UTP
The RTL8367N-VB obtains the states of duplex, speed, and flow control ability for each port in UTP
mode through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During autonegotiation, each port advertises its ability to its link partner and compares its ability with advertisements
received from its link partner. By default, the RTL8367N-VB advertises full capabilities (1000Full,
100Full, 100Half, 10Full, 10Half) together with flow control ability.
Single-Chip 5-Port 10/100/1000M Switch Controller
18
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
8.9.
Crossover Detection and Auto Correction
The RTL8367N-VB automatically determines whether or not it needs to crossover between pairs (see
Table 10) so that an external crossover cable is not required. When connecting to another device that does
not perform MDI crossover, when necessary, the RTL8367N-VB automatically switches its pin pairs to
communicate with the remote device. When connecting to another device that does have MDI crossover
capability, an algorithm determines which end performs the crossover function.
The crossover detection and auto correction function can be disabled via register configuration. The pin
mapping in MDI and MDI Crossover mode is given below.
Pairs
A
B
C
D
8.10.
Table 10. Media Dependent Interface Pin Mapping
MDI
MDI Crossover
1000Base-T
100Base-TX
10Base-T
1000Base-T
100Base-TX
A
TX
TX
B
RX
B
RX
RX
A
TX
C
Unused
Unused
D
Unused
D
Unused
Unused
C
Unused
10Base-T
RX
TX
Unused
Unused
Polarity Correction
The RTL8367N-VB automatically corrects polarity errors on the receiver pairs in 1000Base-T and
10Base-T modes. In 100Base-TX mode, the polarity is irrelevant.
In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle
symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes
unlocked only when the receiver loses lock.
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The
polarity becomes unlocked when the link is down.
RTL8367N-VB
Link Partner
RX +
_
+ TX
_
TX +
_
_
+
+ RX
_
Figure 4. Conceptual Example of Polarity Correction
Single-Chip 5-Port 10/100/1000M Switch Controller
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RTL8367N-VB
Datasheet
9.
General Function Description
9.1.
Reset
9.1.1.
Hardware Reset
In a power-on reset, an internal power-on reset pulse is generated and the RTL8367N-VB will start the
reset initialization procedures. These are:
•
•
•
•
•
Determine various default settings via the hardware strap pins at the end of the nRESET signal
Autoload the configuration from EEPROM if EEPROM is detected
Complete the embedded SRAM BIST process
Initialize the packet buffer descriptor allocation
Initialize the internal registers and prepare them to be accessed by the external CPU
9.1.2.
Software Reset
The RTL8367N-VB supports two software resets; a chip reset and a soft reset.
9.1.2.1
CHIP_RESET
When CHIP_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Download configuration from strap pin and EEPROM
2. Start embedded SRAM BIST (Built-In Self Test)
3. Clear all the Lookup and VLAN tables
4. Reset all registers to default values
5. Restart the auto-negotiation process
9.1.2.2
SOFT_RESET
When SOFT_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Clear the FIFO and re-start the packet buffer link list
2. Restart the auto-negotiation process
Single-Chip 5-Port 10/100/1000M Switch Controller
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RTL8367N-VB
Datasheet
9.2.
IEEE 802.3x Full Duplex Flow Control
The RTL8367N-VB supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be
decided in two ways:
•
•
When Auto-Negotiation is enabled, flow control depends on the result of NWay
When Auto-Negotiation is disabled, flow control depends on register definition
9.3.
Half Duplex Flow Control
In half duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The
scheduling of the retransmissions is determined by a controlled randomization process called “Truncated
Binary Exponential Backoff”. At the end of enforcing a collision (jamming), the switch delays before
attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The
number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed
random integer ‘r’ in the range:
0 ≤ r < 2k
where:
k = min (n, backoffLimit). The backoffLimit for the RTL8367N-VB is 9.
The half duplex back-off algorithm in the RTL8367N-VB does not have the maximum retry count
limitation of 16 (as defined in IEEE 802.3). This means packets in the switch will not be dropped if the
back-off retry count is over 16.
9.3.1.
Back-Pressure Mode
In Back-Pressure mode, the RTL8367N-VB sends a 4-byte jam pattern (data=0xAA) to collide with
incoming packets when congestion control is activated. The Jam pattern collides at the fourth byte
counted from the preamble. The RTL8367N-VB supports 48PASS1, which receives one packet after 48
consecutive jam collisions (data collisions are not included in the 48). Enable this function to prevent port
partition after 63 consecutive collisions (data collisions + consecutive jam collisions).
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9.4.
Search and Learning
Search
When a packet is received, the RTL8367N-VB uses the destination MAC address, Filtering Identifier
(FID) and Enhanced Filtering Identifier (EFID) to search the 2K-entry look-up table. The 48-bit MAC
address, 4-bit FID, and 3-bit EFID use a hash algorithm to calculate an 9-bit index value. The
RTL8367N-VB uses the index to compare the packet MAC address with the entries (MAC addresses) in
the look-up table. This is the ‘Address Search’. If the destination MAC address is not found, the switch
will broadcast the packet according to VLAN configuration.
Learning
The RTL8367N-VB uses the source MAC address, FID, and EFID of the incoming packet to hash into a
9-bit index. It then compares the source MAC address with the data (MAC addresses) in this index. If
there is a match with one of the entries, the RTL8367N-VB will update the entry with new information. If
there is no match and the 2K entries are not all occupied by other MAC addresses, the RTL8367N-VB
will record the source MAC address and ingress port number into an empty entry. This process is called
‘Learning’.
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The look-up engine will update the time stamp information of an entry whenever the corresponding
source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not
refreshed by the address learning process during the aging time period. The aging time of the RTL8367NVB is between 200 and 400 seconds (typical is 300 seconds).
9.5.
SVL and IVL/SVL
The RTL8367N-VB supports a 16-group Filtering Identifier (FID) for L2 search and learning. In default
operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning (SVL). If
VLAN entries are configured to different FIDs, then the same source MAC address with multiple FIDs
can be learned into different look-up table entries. This is called Independent VLAN Learning and Shared
VLAN Learning (IVL/SVL).
9.6.
Illegal Frame Filtering
Illegal frames such as CRC error packets, runt packets (length maximum length) will be discarded by the RTL8367N-VB. The maximum packet length may be
set from 1518 bytes to 16K bytes.
9.7.
IEEE 802.3 Reserved Group Addresses Filtering Control
The RTL8367N-VB supports the ability to drop/forward IEEE 802.3 specified reserved group MAC
addresses: 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these
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reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01
(802.3x Pause) and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 11 shows the
Reserved Multicast Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F.
Table 11. Reserved Multicast Address Configuration Table
Assignment
Bridge Group Address
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation
IEEE Std 802.3ad Slow Protocols-Multicast Address
IEEE Std 802.1X PAE Address
Provider Bridge Group Address
Undefined 802.1 Address
Value
01-80-C2-00-00-00
01-80-C2-00-00-01
01-80-C2-00-00-02
01-80-C2-00-00-03
01-80-C2-00-00-08
01-80-C2-00-00-04 ~
01-80-C2-00-00-07
&
01-80-C2-00-00-09 ~
01-80-C2-00-00-0C
&
01-80-C2-00-00-0F
01-80-C2-00-00-0D
01-80-C2-00-00-0E
01-80-C2-00-00-10
01-80-C2-00-00-11
01-80-C2-00-00-12
01-80-C2-00-00-13 ~
01-80-C2-00-00-17
&
01-80-C2-00-00-19
&
01-80-C2-00-00-1B ~
01-80-C2-00-00-1F
01-80-C2-00-00-18
01-80-C2-00-00-1a
01-80-C2-00-00-20
01-80-C2-00-00-21
01-80-C2-00-00-22
|
01-80-C2-00-00-2F
01-00-0C-CC-CC-CC
01-00-0C-CC-CC-CD
(01:80:c2:00:00:0e or
01:80:c2:00:00:03 or
01:80:c2:00:00:00)
&& ethertype = 0x88CC
Provider Bridge MVRP Address
IEEE Std 802.1AB Link Layer Discovery Protocol Address
All LANs Bridge Management Group Address
Load Server Generic Address
Loadable Device Generic Address
Undefined 802.1 Address
Generic Address for All Manager Stations
Generic Address for All Agent Stations
GMRP Address
GVRP Address
Undefined GARP Address
CDP(Cisco Discovery Protocol)
CSSTP(Cisco Shared Spanning Tree Protocol)
LLDP
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9.8.
Broadcast/Multicast/Unknown DA Storm Control
The RTL8367N-VB enables or disables per-port broadcast/multicast/unknown DA storm control by
setting registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets
exceeds a reference rate (number of Kbps per second or number of packets per second), all other
broadcast/multicast/unknown DA packets will be dropped. The reference rate is set via register
configuration.
9.9.
Port Security Function
The RTL8367N-VB supports three types of security function to prevent malicious attacks.
•
•
•
Per-port enable/disable SA auto-learning for an ingress packet
Per-port enable/disable look-up table aging update function for an ingress packet
Per-port enable/disable drop all unknown DA packets
9.10.
MIB Counters
The RTL8367N-VB supports a set of counters to support management functions.
•
•
•
•
•
•
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
Bridge MIB (RFC 1493)
Bridge MIB Extension (RFC 2674)
9.11.
Port Mirroring
The RTL8367N-VB supports one set of port mirroring functions for all ports. The TX, or RX, or both
TX/RX packets from multiple mirrored port can be mirrored to one monitor port.
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9.12.
VLAN Function
The RTL8367N-VB supports 4K VLAN groups. These can be configured as port-based VLANs,
IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering
options provide flexible VLAN configuration:
Ingress Filtering
• The acceptable frame type of the ingress process can be set to ‘Admit All’ , ‘Admit only Untagged’ or
‘Admit only Tagged’
• ‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set
Egress Filtering
• ‘Forward’ or ‘Discard’ Leaky VLAN frames between different VLAN domains
• ‘Forward’ or ‘Discard’ Multicast VLAN frames between different VLAN domains
The VLAN tag can be inserted or removed at the output port. The RTL8367N-VB will insert a Port VID
(PVID) for untagged frames, or remove the tag from tagged frames. The RTL8367N-VB also supports a
special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and
Gateway applications.
In router applications, the router may want to know which input port this packet came from. The
RTL8367N-VB supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on
egress. Using this function, VID information carried in the VLAN tag will be changed to PVID. The
RTL8367N-VB also provides an option to admit VLAN tagged packets with a specific PVID only. If this
function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.
9.12.1. Port-Based VLAN
This default configuration of the VLAN function can be modified via an attached serial EEPROM or
EEPROM SMI Slave interface. The 4K-entry VLAN Table designed into the RTL8367N-VB provides
full flexibility for users to configure the input ports to associate with different VLAN groups. Each input
port can join with more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a
VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to
determine their VLAN association. All the packets received on a given input port will be forwarded to
this port’s VLAN members.
9.12.2. IEEE 802.1Q Tag-Based VLAN
The RTL8367N-VB supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In 802.1Q
VLAN mapping, the RTL8367N-VB uses a 12-bit explicit identifier in the VLAN tag to associate
received packets with a VLAN. The RTL8367N-VB compares the explicit identifier in the VLAN tag
with the 4K VLAN Table to determine the VLAN association of this packet, and then forwards this
packet to the member set of that VLAN. Two VIDs are reserved for special purposes. One of them is all
1’s, which is reserved and currently unused. The other is all 0’s, which indicates a priority tag. A prioritytagged frame should be treated as an untagged frame.
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When ‘802.1Q tag aware VLAN’ is enabled, the RTL8367N-VB performs 802.1Q tag-based VLAN
mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q
tag aware VLAN’ is disabled, the RTL8367N-VB performs only port-based VLAN mapping both on
non-tagged and tagged frames. The processing flow when ‘802.1Q tag aware VLAN’ is enabled is
illustrated below.
Two VLAN ingress filtering functions are supported in registers by the RTL8367N-VB. One is the
‘VLAN tag admit control’, which provides the ability to receive VLAN-tagged frames only. Untagged or
priority tagged (VID=0) frames will be dropped. The other is ‘VLAN member set ingress filtering’,
which will drop frames if the ingress port is not in the member set.
9.12.3. Protocol-Based VLAN
The RTL8367N-VB supports a 4-group Protocol-based VLAN configuration. The packet format can be
RFC 1042, LLC, or Ethernet, as shown in Figure 5. There are 4 configuration tables to assign the frame
type and corresponding field value. Taking IP packet configuration as an example, the user can configure
the frame type to be ‘Ethernet’, and value to be ‘0x0800’. Each table will index to one of the entries in the
4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the
VLAN member configuration of the indexed entry to forward the packets.
Figure 5. Protocol-Based VLAN Frame Format and Flow Chart
9.12.4. Port VID
In a router application, the router may want to know which input port this packet came from. The
RTL8367N-VB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged
or priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control
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is enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the
RTL8367N-VB will drop non-tagged packets and packets with an incorrect PVID.
9.13.
QoS Function
The RTL8367N-VB supports 8 priority queues and input bandwidth control. Packet priority selection can
depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and ACLbased priority. When multiple priorities are enabled in the RTL8367N-VB, the packet’s priority will be
assigned based on the priority selection table.
Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as
Strict Priority (SP) or Weighted Fair Queue (WFQ) for packet scheduling algorithm.
9.13.1. Input Bandwidth Control
Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth
parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on
register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps).
9.13.2. Priority Assignment
Priority assignment specifies the priority of a received packet according to various rules. The RTL8367NVB can recognize the QoS priority information of incoming packets to give a different egress service
priority.
The RTL8367N-VB identifies the priority of packets based on several types of QoS priority information:
•
•
•
•
•
•
•
Port-based priority
802.1p/Q-based priority
IPv4/IPv6 DSCP-based priority
ACL-based priority
VLAN-based priority
MAC-based priority
SVLAN-based priority
9.13.3. Priority Queue Scheduling
The RTL8367N-VB supports MAX-MIN packet scheduling.
Packet scheduling offers two modes:
•
•
Average Packet Rate (APR) leaky bucket, which specifies the average rate of one queue
Weighted Fair Queue (WFQ), which decides which queue is selected in one slot time to guarantee the
minimal packet rate of one queue
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In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to
packet scheduling mode. Figure 6 shows the RTL8367N-VB packet-scheduling diagram.
Figure 6. MAX-MIN Scheduling Diagram
9.13.4. IEEE 802.1p/Q and DSCP Remarking
The RTL8367N-VB supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point)
remarking function. When packets egress from one of the 8 queues, the packet’s 802.1p/Q priority and IP
DSCP can optionally be remarked to a configured value. 802.1p/Q priority & IP DSCP value can be
remarked based on internal priority or original 802.1p/Q priority & IP DSCP value in packets.
9.13.5. ACL-Based Priority
The RTL8367N-VB supports 96-entry ACL (Access Control List) rules. When a packet is received, its
physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries.
If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is
valid, the action bit and priority bit will be applied.
•
•
•
•
If the action bit is ‘Drop’, the packet will be dropped. If the action bit is ‘CPU’, the packet will be
trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules
other than the ACL rule)
If the action bit is ‘Permit’, ACL rules will override other rules
If the action bit is ‘Mirror’, the packet will be forwarded to the mirror port and the L2 lookup result
destination port. The mirror port indicates the port configured in the port mirror mechanism
The priority bit will take effect only if the action bit is ‘CPU’, ‘Permit’, and ‘Mirror’. The Priority bit
is used to determine the packet queue ID according to the priority assignment mechanism
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9.14.
IGMP & MLD Snooping Function
The RTL8367N-VB supports hardware IGMPv1/v2/v3 and MLDv1/v2 snooping with a maximum of 256
groups (maximum 255 groups per port). These multicast groups are learned and deleted/aged out
automatically. For data packets of a known multicast group, the RTL8367N-VB forwards them according
to the learned group membership.
The RTL8367N-VB checks group membership every 125 seconds (default). If a specified port of the
RTL8367N-VB does not receive a report message after 3 (default) consecutive checks, the port is
removed from the multicast group. The 125 second interval and the number of consecutive checks before
ageing are user configurable default values.
IPv4 multicast data packets are forwarded per group IP. IPv6 multicast data packets are forwarded per
destination MAC. That is, IPv6 multicast groups that share the same destination MAC are treated as the
same group. This is called address ambiguity.
Some reserved range IP addresses will always be flooded to all ports. If IGMP or MLD report message
requests to join these groups, this request will be ignored silently. These reserved IP addresses could be
the following IP addresses and they are configurable.
IPv4: 224.0.0.0 ~ 224.0.0.255
IPv4: 224.0.0.0 ~ 224.0.1.255
IPv4: 239.255.255.0 ~ 239.255.255.255
IPv6: 33:33:00:00:00:00 ~ 33:33:00:00:00:FF (forwarded per destination MAC)
Due to address ambiguity, some IPv6 multicast addresses that are not reserved for network protocols will
be flooded, as the corresponding destination MAC address is inside the reserved IP address range
(Corresponding MAC address).
The RTL8367N-VB learns the ‘Dynamic Router Port’ automatically by monitoring Query messages (both
IGMP & MLD) and multicast routing protocol packets. Table 12 gives the multicast routing protocols
that the RTL8367N-VB recognizes. PIMv1 is confirmed by the IGMP header type and the other multicast
routing protocols are recognized by the destination IP in the IP header (in both IPv4 and IPv6).
IPv4
N/A
224.0.0.13
224.0.0.4
224.0.0.5
224.0.0.6
IPv6
N/A
FF02::D
FF02::4
FF02::5
FF02::6
Table 12. IPv4/IPv6 Multicast Routing Protocols
Multicast Routing Protocol
Check IGMP Header Type=0x14 (PIMv1)
PIMv2
DVMRP
MOSPF
MOSPF
Users can specify ‘Static Router Ports’ via API. This forces the ports to act as true router ports. All
reports and Leave/Done messages will be forwarded to the specified Static Router ports.
The RTL8367N-VB supports a ‘Fast Leave’ feature. When enabled, group membership will be removed
immediately the RTL8367N-VB receives an IGMPv2 Leave message or MLDv1 Done message.
Normally this feature is only enabled when there is only one host.
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The IGMP/MLD snooping feature is disabled by default. IGMP & MLD messages will be flooded to all
ports without any further processing. This feature can be enabled and configured via API. Contact your
Realtek support team for configuration details.
9.15.
IEEE 802.1x Function
The RTL8367N-VB supports IEEE 802.1x Port-based/MAC-based Access Control.
•
•
•
•
•
•
•
Port-Based Access Control for each port
Authorized Port-Based Access Control for each port
Port-Based Access Control Direction for each port
MAC-Based Access Control for each port
MAC-Based Access Control Direction
Optional Unauthorized Behavior
Guest VLAN
9.15.1. Port-Based Access Control
Each port of the RTL8367N-VB can be set to 802.1x port-based authenticated checking function usage
and authorized status. Ports with 802.1X unauthorized status will drop received/transmitted frames.
9.15.2. Authorized Port-Based Access Control
If a dedicated port is set to 802.1x port-based access control, and passes the 802.1x authorization, then its
port authorization status can be set to authorized.
9.15.3. Port-Based Access Control Direction
Ports with 802.1X unauthorized status will drop received/transmitted frames only when port authorization
direction is ‘BOTH’. If the authorization direction of an 802.1X unauthorized port is IN, incoming frames
to that port will be dropped, but outgoing frames will be transmitted.
9.15.4. MAC-Based Access Control
MAC-Based Access Control provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. When a logical port
or a MAC address is authenticated, the relevant source MAC address has the authorization to access the
network. A frame with a source MAC address that is not authenticated by the 802.1x function will be
dropped or trapped to the CPU.
9.15.5. MAC-Based Access Control Direction
Unidirectional and bi-directional control are two methods used to process frames in 802.1x. As the
system cannot predict which port the DA is on, a system-wide MAC-based access control direction setup
is provided for determining whether receiving or bi-directional should be authorized.
If MAC-based access control direction is BOTH, then received frames with unauthenticated SA or
unauthenticated DA will be dropped. When MAC-based access control direction is IN, only received
frames with unauthenticated SA will be dropped.
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9.15.6. Optional Unauthorized Behavior
Both in Port-Based Network Access Control and MAC-Based Access Control, a whole system control
setup is provided to determine unauthorized frame dropping, trapping to CPU, or tagging as belonging to
a Guest VLAN (see the following ‘Guest VLAN’ section).
9.15.7. Guest VLAN
When the RTL8367N-VB enables the Port-based or MAC-based 802.1x function, and the connected PC
does not support the 802.1x function or does not pass the authentication procedure, the RTL8367N-VB
will drop all packets from this port.
The RTL8367N-VB also supports one Guest VLAN to allow unauthorized ports or packets to be
forwarded to a limited VLAN domain. The user can configure one VLAN ID and member set for these
unauthorized packets.
9.16.
IEEE 802.1D Function
When using IEEE 802.1D, the RTL8367N-VB supports 16 sets and four status’ for each port for CPU
implementation 802.1D (STP) and 802.1s (MSTP) function:
•
•
•
•
Disabled: The port will not transmit/receive packets, and will not perform learning
Blocking: The port will only receive BPDU spanning tree protocol packets, but will not transmit any
packets, and will not perform learning
Learning: The port will receive any packet, including BPDU spanning tree protocol packets, and will
perform learning, but will only transmit BPDU spanning tree protocol packets
Forwarding: The port will transmit/receive all packets, and will perform learning
The RTL8367N-VB also supports a per-port transmission/reception enable/disable function. Users can
control the port state via register.
9.17.
Embedded 8051
An 8051 MCU is embedded in the RTL8367N-VB to support management functions. The 8051 MCU can
access all of the registers in the RTL8367N-VB through the internal bus. With the Network Interface
Circuit (NIC) acting as the data path, the 8051 MCU connects to the switch core and can transmit frames
to or receive frames from the Ethernet network. The features of the 8051 MCU are listed below:
•
•
•
•
•
•
256 Bytes fast internal RAM
On-chip 48K data memory
On-chip 16K code memory
Supports code-banking
12 KBytes NIC buffer
EEPROM read/write ability
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9.18.
Realtek Cable Test (RTCT)
The RTL8367N-VB physical layer transceivers use DSP technology to implement the Realtek Cable Test
(RTCT) feature. The RTCT function can be used to detect short, open, or impedance mismatch in each
differential pair. The RTL8367N-VB also provides LED support to indicate test status and results.
9.19.
LED Indicators
The RTL8367N-VB supports parallel LEDs for each port. Each port has two LED indicator pins, LED0
and LED1. Each pin may have different indicator information (defined in Table 13). Refer to section 7.2
LED Pins, page 12 for pin details. Upon reset, the RTL8367N-VB supports chip diagnostics and LED
operation test by blinking all LEDs once.
LED Statuses
LED_Off
Dup/Col
Link/Act
Spd1000
Spd100
Spd10
Spd1000/Act
Spd100/Act
Spd10/Act
Spd100 (10)/Act
Act
Table 13. LED Definitions
Description
LED Pin Output Disable.
Duplex/Collision Indicator. Blinking when collision occurs. Low for full duplex, and high for
half duplex mode.
Link, Activity Indicator. Low for link established. Link/Act Blinking when the corresponding
port is transmitting or receiving.
1000Mbps Speed Indicator. Low for 1000Mbps.
100Mbps Speed Indicator. Low for 100Mbps.
10Mbps Speed Indicator. Low for 10Mbps.
1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinking when the corresponding
port is transmitting or receiving.
100Mbps Speed/Activity Indicator. Low for 100Mbps. Blinking when the corresponding port
is transmitting or receiving.
10Mbps Speed/Activity Indicator. Low for 10Mbps. Blinking when the corresponding port is
transmitting or receiving.
10/100Mbps Speed/Activity Indicator. Low for 10/100Mbps. Blinking when the corresponding
port is transmitting or receiving.
Activity Indicator. Act blinking when the corresponding port is transmitting or receiving.
The LED pin also supports pin strapping configuration functions. The PnLED0 and PnLED1 pins are
dual-function pins: input operation for configuration upon reset, and output operation for LED after reset.
If the pin input is pulled high upon reset, the pin output is active low after reset. If the pin input is pulled
down upon reset, the pin output is active high after reset. For details refer to Figure 7, page 33, and Figure
8, page 33. Typical values for pull-up/pull-down resistors are 4.7KΩ.
The PnLED1 can be combined with PnLED0 as a Bi-color LED.
LED_PnLED1 should operate with the same polarity as other Bi-color LED pins. For example:
•
P0LED1 should pull up upon reset if P0LED1 is combined with P0LED0 as a Bi-color LED, and
P0LED0 input is pulled high upon reset. In this configuration, the output of these pins is active low
after reset
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•
P0LED1 should be pulled down upon reset if P0LED1 is combined with P0LED0 as a Bi-color LED,
and P0LED0 input is pulled down upon reset. In this configuration, the output of these pins is active
high after reset
Figure 7. Pull-Up and Pull-Down of LED Pins for Single-Color LED
Figure 8. Pull-Up and Pull-Down of LED Pins for Bi-Color LED
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9.20.
Green Ethernet
9.20.1. Link-On and Cable Length Power Saving
The RTL8367N-VB provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
9.20.2. Link-Down Power Saving
The RTL8367N-VB implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected. After it detects an incoming signal, it wakes up
from link-down power saving and operates in normal mode.
9.21.
IEEE 802.3az Energy Efficient Ethernet (EEE) Function
The RTL8367N-VB supports IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T and
100Base-TX in full duplex operation.
The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access
Control (MAC) sub-layer with 100Base-TX and 1000Base-T Physical Layers defined to support
operation in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the
link can disable portions of the functionality and save power during periods of low link utilization.
•
•
For 1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
For 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
The RTL8367N-VB MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner,
that a break in the data stream is expected, and components may use this information to enter power
saving modes that require additional time to resume normal operation. Similarly, it informs the LPI Client
that the link partner has sent such an indication.
Single-Chip 5-Port 10/100/1000M Switch Controller
34
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
10. Interface Descriptions
10.1.
EEPROM SMI Host to EEPROM
The EEPROM interface of the RTL8367N-VB uses the serial bus EEPROM Serial Management Interface
(SMI) to read the EEPROM space up to 256K-bits. When the RTL8367N-VB is powered up, it drives
SCK and SDA to read the registers from the EEPROM.
SCK
SDA
START
STOP
Figure 9. SMI Start and Stop Command
SCK
1
8
9
DATA IN
DATA OUT
ACKNOWLEDGE
START
Figure 10. EEPROM SMI Host to EEPROM
Figure 11. EEPROM SMI Host Mode Frame
Single-Chip 5-Port 10/100/1000M Switch Controller
35
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
10.2.
EEPROM SMI Slave for External CPU
When EEPROM auto-load is complete, the RTL8367N-VB registers can be accessed via SCK and SDA
by an external CPU. The device address of the RTL8367N-VB is 0x4. For the start and end of a
write/read command, SCK needs one extra clock before/after the start/stop signals.
Figure 12. EEPROM SMI Write Command for Slave Mode
Figure 13. EEPROM SMI Read Command for Slave Mode
Single-Chip 5-Port 10/100/1000M Switch Controller
36
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11. Register Descriptions
In this section the following abbreviations are used:
RO: Read Only
LH: Latch High until clear
RW: Read/Write
SC: Self Clearing
LL: Latch Low until clear
11.1.
Register
0
1
2
3
4
5
6
7
8
9
10
11~14
15
16~31
PCS Register (PHY 0~4)
Table 14. PCS Register (PHY 0~4)
Register Description
Control Register
Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Page Transmit Register
Auto-Negotiation Link Partner Next Page Register
1000Base-T Control Register
1000Base-T Status Register
Reserved
Extended Status
ASIC Control Register
Single-Chip 5-Port 10/100/1000M Switch Controller
37
Default
0x1140
0x7949
0x001C
0xC980
0x0DE1
0x0000
0x0004
0x2001
0x0000
0x0E00
0x0000
0x0000
0x2000
-
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11.2.
Reg.bit
0.15
0.14
0.13
0.12
0.11
0.10
0.9
0.8
0.7
0.6
0.[5:0]
Register 0: Control
Table 15. Register 0: Control
Mode Description
RW/SC 1: PHY reset
0: Normal operation
This bit is self-clearing.
Loopback
RW
1: Enable loopback. This will loopback TXD to RXD and ignore
all activity on the cable media
(Digital
Loopback)
0: Normal operation
This function is usable only when this PHY is operated in
10Base-T full duplex, 100Base-TX full duplex, or 1000Base-T full
duplex.
Speed Selection[0]
RW
[0.6, 0.13] Speed Selection[1:0]
11: Reserved
10: 1000Mbps
01: 100Mbps
00: 10Mbps
This bit can be set through SMI (Read/Write).
RW
1: Enable auto-negotiation process
Auto Negotiation
Enable
0: Disable auto-negotiation process
This bit can be set through SMI (Read/Write).
Power Down
RW
1: Power down. All functions will be disabled except SMI function
0: Normal operation
Isolate
RW
1: Electrically isolates the PHY from GMII. The PHY is still able
to respond to MDC/MDIO
0: Normal operation
RW/SC 1: Restart Auto-Negotiation process
Restart Auto
Negotiation
0: Normal operation
Duplex Mode
RW
1: Full duplex operation
0: Half duplex operation
This bit can be set through SMI (Read/Write).
Collision Test
RO
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted in
response to the assertion of TXEN within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the deassertion of TXEN.
Speed Selection[1]
RW
See bit 13
Reserved
RO
Reserved
Name
Reset
Single-Chip 5-Port 10/100/1000M Switch Controller
38
Default
0
0
0
1
0
0
0
1
0
1
000000
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11.3.
Reg.bit
1.15
Register 1: Status
Name
100Base-T4
Mode
RO
1.14
100Base-TX-FD
RO
1.13
100Base-TX-HD
RO
1.12
10Base-T-FD
RO
1.11
10Base-T-HD
RO
1.10
100Base-T2-FD
RO
1.9
100Base-T2-HD
RO
1.8
Extended Status
RO
1.7
1.6
Reserved
MF Preamble
Suppression
Auto-negotiate
Complete
Remote Fault
RO
RO
1.5
1.4
1.3
1.2
Auto-Negotiation
Ability
Link Status
1.1
Jabber Detect
1.0
Extended
Capability
RO
RO/LH
RO
Table 16. Register 1: Status
Description
0: No 100Base-T4 capability
The RTL8367N-VB does not support 100Base-T4 mode and this
bit should always be 0.
1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
1: 10Base-T full duplex capable
0: Not 10Base-T full duplex capable
1: 10Base-T half duplex capable
0: Not 10Base-T half duplex capable
0: Not 100Base-T2 full duplex capable
The RTL8367N-VB does not support 100Base-T2 mode and this
bit should always be 0.
0: Not 100Base-T2 half duplex capable
The RTL8367N-VB does not support 100Base-T2 mode and this
bit should always be 0.
1: Extended status information in Register 15
The RTL8367N-VB always supports Extended Status Register.
Reserved
The RTL8367N-VB will accept management frames with
preamble suppressed.
1: Auto-negotiation process completed
0: Auto-negotiation process not completed
1: Remote fault condition detected
0: No remote fault detected
This bit will remain set until it is cleared by reading register 1 via
the management interface.
1: Auto-negotiation capable (permanently =1)
RO/LL
1: Link is established. If the link fails, this bit will be 0 until after
reading this bit again
0: Link has failed since previous read
If the link fails, this bit will be set to 0 until bit is read.
RO/LH 1: Jabber detected
0: No Jabber detected
Jabber is supported only in 10Base-T mode.
RO
1: Extended register capable (permanently =1)
Single-Chip 5-Port 10/100/1000M Switch Controller
39
Default
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
1
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11.4.
Register 2: PHY Identifier 1
The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this
device. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the
vendor’s model number, and the model revision number. A PHY may return a value of zero in each of the
32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
Reg.bit
2.[15:0]
11.5.
Reg.bit
3.[15:10]
3.[9:4]
3.[3:0]
11.6.
Name
OUI
Table 17. Register 2: PHY Identifier 1
Mode Description
RO
Composed of the 3rd to 18th bits of the Organizationally Unique
Identifier (OUI), respectively.
Default
0x001C
Register 3: PHY Identifier 2
Name
OUI
Model Number
Revision Number
Table 18. Register 3: PHY Identifier 2
Mode Description
RO
Assigned to the 19th through 24th bits of the OUI
RO
Manufacturer’s model number
RO
Manufacturer’s revision number
Default
110010
011000
0000
Register 4: Auto-Negotiation Advertisement
This register contains the advertisement abilities of this device as they will be transmitted to its Link
Partner during Auto-negotiation.
Note: Each time the link ability of the RTL8367N-VB is reconfigured, the auto-negotiation process should
be executed to allow the configuration to take effect.
Reg.bit
4.15
4.14
4.13
4.12
4.11
4.10
4.9
4.8
4.7
Table 19. Register 4: Auto-Negotiation Advertisement
Name
Mode Description
Next Page
RO
1: Additional next pages exchange desired
0: No additional next pages exchange desired
Acknowledge
RO
Permanently=0
Remote Fault
RW
1: Advertises that the RTL8367N-VB has detected a remote fault
0: No remote fault detected
Reserved
RO
Reserved
Reserved
RW
Reserved
Pause
RW
1: Advertises that the RTL8367N-VB has flow control capability
0: No flow control capability
100Base-T4
RO
1: 100Base-T4 capable
0: Not 100Base-T4 capable (Permanently =0)
100Base-TX-FD
RW
1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
100Base-TX
RW
1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
Single-Chip 5-Port 10/100/1000M Switch Controller
40
Default
0
0
0
0
0
1
0
1
1
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
Reg.bit
4.6
Description
1: 10Base-T full duplex capable
0: Not 10Base-T full duplex capable
4.5
10Base-T
RW
1: 10Base-T half duplex capable
0: Not 10Base-T half duplex capable
4.[4:0] Selector Field
RO
[00001]=IEEE 802.3
Note 1: The setting of Register 4 has no effect unless auto-negotiation is restarted or the link goes down.
Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted.
11.7.
Name
10Base-T-FD
Mode
RW
Default
1
1
00001
Register 5: Auto-Negotiation Link Partner Ability
This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The
content changes after a successful Auto-negotiation.
Reg.bit
5.15
5.14
5.13
5.12
5.11
5.10
5.9
5.8
5.7
5.6
5.5
5.[4:0]
Table 20. Register 5: Auto-Negotiation Link Partner Ability
Mode Description
RO
1: Link partner desires Next Page transfer
0: Link partner does not desire Next Page transfer
Acknowledge
RO
1: Link Partner acknowledges reception of Fast Link Pulse (FLP)
words
0: Not acknowledged by Link Partner
Remote Fault
RO
1: Remote Fault indicated by Link Partner
0: No remote fault indicated by Link Partner
Reserved
RO
Reserved
Asymmetric Pause
RO
1: Asymmetric Flow control supported by Link Partner
0: No Asymmetric flow control supported by Link Partner. When
auto-negotiation is enabled, this bit reflects Link Partner ability
Pause
RO
1: Flow control supported by Link Partner.
0: No flow control supported by Link Partner.
When auto-negotiation is enabled, this bit reflects Link Partner
ability
100Base-T4
RO
1: 100Base-T4 supported by Link Partner
0: 100Base-T4 not supported by Link Partner
100Base-TX-FD
RO
1: 100Base-TX full duplex supported by Link Partner
0: 100Base-TX full duplex not supported by Link Partner
100Base-TX
RO
1: 100Base-TX half duplex supported by Link Partner
0: 100Base-TX half duplex not supported by Link Partner
10Base-T-FD
RO
1: 10Base-T full duplex supported by Link Partner
0: 10Base-T full duplex not supported by Link Partner
10Base-T
RO
1: 10Base-T half duplex supported by Link Partner
0: 10Base-T half duplex not supported by Link Partner
Selector Field
RO
[00001]=IEEE 802.3
Name
Next Page
Single-Chip 5-Port 10/100/1000M Switch Controller
41
Default
0
0
0
0
0
0
0
0
0
0
0
00000
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11.8.
Reg.bit
6.[15:5]
6.4
6.3
6.2
6.1
6.0
11.9.
Reg.bit
7.15
7.14
7.13
7.12
7.11
7.[10:0]
Register 6: Auto-Negotiation Expansion
Table 21. Register 6: Auto-Negotiation Expansion
Name
Mode Description
Reserved
RO
Ignore on read
RO
1: A fault has been detected via the Parallel Detection function
Parallel Detection
Fault
/LH
0: No fault has been detected via the Parallel Detection function
RO
1: Link Partner is Next Page able
Link Partner Next
Page Ability
0: Link Partner is not Next Page able
RO
Not supported. Permanently =0
Local Next Page
Ability
Page Received
RO
1: A New Page has been received
/LH
0: A New Page has not been received
RO
If Auto-Negotiation is enabled, this bit means:
Link Partner AutoNegotiation
1: Link Partner is Auto-Negotiation able
Ability
0: Link Partner is not Auto-Negotiation able
Default
0
0
0
1
0
0
Register 7: Auto-Negotiation Page Transmit Register
Table 22. Register 7: Auto-Negotiation Page Transmit Register
Name
Mode Description
Next Page
RW
1: Link partner desires Next Page transfer
0: Link partner does not desire Next Page transfer
Reserved
RO
1: A fault has been detected via the Parallel Detection function
0: No fault has been detected via the Parallel Detection function
Message Page
RW
1: Message page
0: No Message page ability
Acknowledge 2
RW
1: Local device has the ability to comply with the message
received
0: Local device has no ability to comply with the message received
Toggle
RO
Toggle bit
RW
Content of message/unformatted page
Message/
Unformatted Field
Single-Chip 5-Port 10/100/1000M Switch Controller
42
Default
0
0
1
0
0
1
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11.10. Register 8: Auto-Negotiation Link Partner Next Page
Register
Reg.bit
8.15
8.14
8.13
8.12
8.11
8.[10:0]
Table 23. Register 8: Auto-Negotiation Link Partner Next Page Register
Name
Mode Description
Next Page
RO
Received Link Code Word Bit 15
Acknowledge
RO
Received Link Code Word Bit 14
Message Page
RO
Received Link Code Word Bit 13
Acknowledge 2
RO
Received Link Code Word Bit 12
Toggle
RO
Received Link Code Word Bit 11
RO
Received Link Code Word Bit 10:0
Message/
Unformatted Field
Default
0
0
0
0
0
0
11.11. Register 9: 1000Base-T Control Register
Table 24. Register 9: 1000Base-T Control Register
Reg.bit Name
Mode Description
9.[15:13] Test Mode
RW
Test Mode Select.
000: Normal mode
001: Test mode 1 – Transmit waveform test
010: Test mode 2 – Transmit jitter test in MASTER mode
011: Test mode 3 – Transmit jitter test in SLAVE mode
100: Test mode 4 – Transmitter distortion test
101, 110, 111: Reserved
9.12
RW
1: Enable MASTER/SLAVE manual configuration
MASTER/SLAVE
Manual Configuration
0: Disable MASTER/SLAVE manual configuration
Enable
9.11
RW
MASTER/SLAVE
1: Configure PHY as MASTER during MASTER/SLAVE
Configuration Value
negotiation, only when bit 9.12 is set to logical one
0: Configure PHY as SLAVE during MASTER/SLAVE
negotiation, only when bit 9.12 is set to logical one
9.10
Port Type
RW
1: Multi-port device
0: Single-port device
9.9
1000Base-T Full Duplex
RW
1: Advertise PHY is 1000Base-T full duplex capable
0: Advertise PHY is not 1000Base-T full duplex capable
9.8
1000Base-T Half Duplex
RW
1: Advertise PHY is 1000Base-T half duplex capable
0: Advertise PHY is not 1000Base-T half duplex capable
9.[7:0] Reserved
RW
Reserved
Single-Chip 5-Port 10/100/1000M Switch Controller
43
Default
000
0
1
1
1
0
0
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
11.12. Register 10: 1000Base-T Status Register
Reg.bit
10.15
10.14
10.13
10.12
10.11
10.10
10.[9:8]
10.[7:0]
Table 25. Register 10: 1000Base-T Status Register
Name
Mode Description
MASTER/SLAVE
RO/LH/ 1: MASTER/SLAVE configuration fault detected
Configuration Fault
SC
0: No MASTER/SLAVE configuration fault detected
RO
1: Local PHY configuration resolved to MASTER
MASTER/SLAVE
Configuration Resolution
0: Local PHY configuration resolved to SLAVE
Local Receiver Status
RO
1: Local receiver OK
0: Local receiver not OK
Remote Receiver Status
RO
1: Remote receiver OK
0: Remote receiver not OK
RO
1: Link partner is capable of 1000Base-T full duplex
Link Partner 1000Base-T
Full Duplex
0: Link partner is not capable of 1000Base-T full duplex
1000Base-T Half Duplex
RO
1: Link partner is capable of 1000Base-T half duplex
0: Link partner is not capable of 1000Base-T half duplex
Reserved
RO
Reserved
Idle Error Count
RO/SC Idle Error Counter.
The counter stops automatically when it reaches 0xFF
Default
0
0
0
0
0
0
0
0
11.13. Register 15: Extended Status
Table 26. Register 15: Extended Status
Reg.bit Name
Mode Description
15.15
1000Base-X Full Duplex
RO
1: 1000Base-X full duplex capable
0: Not 1000Base-X full duplex capable
15.14
1000Base-X Half Duplex
RO
1: 1000Base-X half duplex capable
0: Not 1000Base-X half duplex capable
15.13
1000Base-T Full Duplex
RO
1: 1000Base-T full duplex capable
0: Not 1000Base-T full duplex capable
15.12
1000Base-T Half Duplex
RO
1: 1000Base-T half duplex capable
0: Not 1000Base-T half duplex capable
15.[11:0] Reserved
RO
Reserved
Single-Chip 5-Port 10/100/1000M Switch Controller
44
Default
0
0
1
0
0
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
12. Electrical Characteristics
12.1.
Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 27. Absolute Maximum Ratings
Parameter
Min
Junction Temperature (Tj)
Storage Temperature
-45
DVDDIO and AVDDH Supply Referenced to GND and AGND
GND-0.3
DVDDL, AVDDL, PLLVDDL, Supply Referenced to GND and
GND-0.3
AGND
Digital Input Voltage
GND-0.3
12.2.
Max
+125
+125
+3.63
Units
°C
°C
V
+1.21
V
VDDIO+0.3
V
Recommended Operating Range
Table 28. Recommended Operating Range
Parameter
Min
Typical
Ambient Operating Temperature (Ta)
0
DVDDIO and AVDDH Supply Voltage Range
3.135
3.3
DVDDL, AVDDL, PLLVDDL, Supply Voltage Range
1.045
1.1
Single-Chip 5-Port 10/100/1000M Switch Controller
45
Max
70
3.465
1.155
Units
°C
V
V
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
12.3.
Thermal Characteristics
12.3.1. Assembly Description
Package
PCB
Table 29. Assembly Description
Type
QFN88
Dimension (L×W)
10×10mm
Thickness
0.65mm
PCB Dimension (L×W)
TBD
PCB Thickness
TBD
Number of Cu Layer-PCB
TBD
12.3.2. Material Properties
Item
Package
Die
Silver Paste
Lead Frame
Mold Compound
PCB
Table 30. Material Properties
Material
Thermal Conductivity K (W/m-k)
Si
147
1033BF
2.5
CDA7025
168
7372
0.88
Cu
400
FR4
0.2
12.3.3. Simulation Conditions
Table 31. Simulation Conditions
1.8W
2L (2S)/4L (2S2P)
Air Flow = 0, 1, 2, m/s
Input Power
Test Board (PCB)
Control Condition
12.3.4. Thermal Performance of QFN-88 on PCB Under Still Air
Convection
Table 32. Thermal Performance of QN-88 on PCB Under Still Air Convection
θJA
θJC
ΨJT
TBD
TBD
TBD
TBD
TBD
TBD
4L PCB
2L PCB
Note:
θJA: Junction to ambient thermal resistance
θJC: Junction to case thermal resistance
ΨJT: Junction to top center of package thermal characterization
Single-Chip 5-Port 10/100/1000M Switch Controller
46
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
12.3.5. Thermal Performance of QFN-88 on PCB Under Forced
Convection
Table 33. Thermal Performance of QFN-88 on PCB Under Forced Convection
Air Flow (m/s)
0
1
2
4L PCB
θJA
TBD
TBD
TBD
2L PCB
θJA
TBD
TBD
TBD
Note:
θJA: Junction to ambient thermal resistance
12.4.
DC Characteristics
Table 34. DC Characteristics
Parameter
SYM
Min
Typical
System Idle (All UTP Port Link Down, without Extension Ports and LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
TBD
Power Supply Current for VDDL
IDVDDL, IAVDDL, IPLLVDDL
TBD
1000M Active (All UTP Ports Link/Active, without Extension Ports and LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
TBD
Power Supply Current for VDDL
IDVDDL, IAVDDL, IPLLVDDL
TBD
VDDIO=3.3V
TTL Input High Voltage
Vih
1.9
TTL Input Low Voltage
Vil
Output High Voltage
Voh
2.7
Output Low Voltage
Vol
VDDIO=2.5V
TTL Input High Voltage
Vih
1.7
TTL Input Low Voltage
Vil
Output High Voltage
Voh
2.25
Output Low Voltage
Vol
Note: DVDDIO=AVDDH=3.3V, DVDDL=AVDDL=PLLVDDL=1.1V.
Single-Chip 5-Port 10/100/1000M Switch Controller
47
Max
Units
-
mA
mA
-
mA
mA
0.7
0.6
V
V
V
V
0.7
0.4
V
V
V
V
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
12.5.
AC Characteristics
12.5.1. EEPROM SMI Host Mode Timing Characteristics
t1
t2
t3
SCK
t4
SDA
t5
t7
t6
t8
Data Valid
Data Valid
Figure 14. EEPROM SMI Host Mode Timing Characteristics
t9
nRESET
SCK
SDA
Figure 15. SCK/SDA Power on Timing
t10
SCK
Data Valid
SDA
Start
Condition
Stop
Condition
Figure 16. EEPROM Auto-Load Timing
Single-Chip 5-Port 10/100/1000M Switch Controller
48
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
Table 35. EEPROM SMI Host Mode Timing Characteristics
Symbol
Description
Type
Min
Typical
t1
SCK Clock Period
O
TBD
TBD
t2
SCK High Time
O
TBD
TBD
t3
SCK Low Time
O
TBD
TBD
t4
START Condition Setup Time
O
TBD
TBD
t5
START Condition Hold Time
O
TBD
TBD
t6
Data Hold Time
O
TBD
TBD
t7
Data Setup Time
O
TBD
TBD
t8
STOP Condition Setup Time
O
TBD
TBD
t9
SCK/SDA Active from Reset Ready
O
TBD
TBD
t10
8K-Bits EEPROM Auto-Load Time
O
TBD
TBD
SCK Rise Time (10% to 90%)
O
TBD
SCK Fall Time (90% to 10%)
O
TBD
Duty Cycle
O
TBD
TBD
Note: t6, t7, and t10 are measured with ATMEL AT24C08 EEPROM.
Max
TBD
TBD
TBD
Units
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
%
Max
-
Units
µs
µs
µs
µs
µs
ns
ns
µs
12.5.2. EEPROM SMI Slave Mode Timing Characteristics
Figure 17. EEPROM SMI Slave Mode Timing Characteristics
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Table 36. EEPROM SMI Slave Mode Timing Characteristics
Description
Type
Min
Typical
SCK High Time
I
TBD
SCK Low Time
I
TBD
START Condition Setup Time
I
TBD
START Condition Hold Time
I
TBD
Data Hold Time
I
TBD
Data Setup Time
I
TBD
Clock to Data Output Delay
O
TBD
STOP Condition Setup Time
I
TBD
-
Single-Chip 5-Port 10/100/1000M Switch Controller
49
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
12.5.3. MDIO Slave Mode Timing Characteristics
The RTL8367N-VB supports MDIO slave mode. The Master (the RTL8367N-VB link partner CPU) can
access the Slave (RTL8367N-VB) registers via the MDIO interface. The MDIO is a bi-directional signal
that can be sourced by the Master or the Slave. In a write command, the Master sources the MDIO signal.
In a read command, the Slave sources the MDIO signal.
•
•
The timing characteristics (t1, t2, and t3 in Table 37) of the Master (the RTL8367N-VB link partner
CPU) are provided by the Master when the Master sources the MDIO signal (Write command)
The timing characteristics (t4 in Table 37) of the Slave (RTL8367N-VB) are provided by the
RTL8367N-VB when the RTL8367N-VB sources the MDIO signal (Read command)
Figure 18. MDIO Sourced by Master (RTL8367N-VB Link Partner CPU)
Figure 19. MDIO Sourced by Slave (RTL8367N-VB)
Table 37. MDIO Timing Characteristics and Requirements
Parameter
SYM Description/Condition
Type Min Typical
MDC Clock Period
t1
Clock Period
I
TBD
t2
Input Setup Time
I
TBD
MDIO to MDC Rising Setup
Time (Write Data)
t3
Input Hold Time
I
TBD
MDIO to MDC Rising Hold
Time (Write Data)
t4
O
TBD
MDC to MDIO Delay Time
Clock (Falling Edge) to Data Delay
(Read Data)
Time
Single-Chip 5-Port 10/100/1000M Switch Controller
50
Max
-
Units
ns
ns
-
ns
TBD
ns
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
12.6.
Power and Reset Characteristics
Figure 20. Power and Reset Characteristics
Parameter
Reset Delay Time
Reset Low Time
VDDL Power Rising
Settling Time
Table 38. Power and Reset Characteristics
SYM Description/Condition
Type Min Typical
t1
The duration from all powers steady to
I
TBD
the reset signal released to high.
t2
The duration of reset signal remain low
time for issuing a reset to RTL8367NI
TBD
VB.
t3
DVDDL and AVDDL power rising
I
TBD
settling time.
Single-Chip 5-Port 10/100/1000M Switch Controller
51
Max
Units
-
ms
-
ms
-
ms
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
13. Mechanical Dimensions
Thermally Enhanced Quad Flat Package (QFN) 88 Leads 10×10mm Outline.
Single-Chip 5-Port 10/100/1000M Switch Controller
52
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
13.1.
Mechanical Dimensions Notes
Dimension in mm
Min
Nom
A
0.80
0.85
A1
0.00
0.02
A2
--0.65
A3
0.20 REF
b
0.15
0.20
D/E
10.00BSC
D1/E1
9.75BSC
D2/E2
6.65
6.90
e
0.40BSC
L
0.30
0.40
CONTROLLING DIMENSION: MILLIMETER (mm).
REFERENCE DOCUMENT: JEDEC MO-220.
Symbol
Single-Chip 5-Port 10/100/1000M Switch Controller
Max
0.90
0.05
0.70
Min
0.031
0.000
---
0.25
0.006
7.15
0.262
0.50
0.012
53
Dimension in inch
Nom
0.033
0.001
0.026
0.008 REF
0.008
0.394BSC
0.384BSC
0.272
0.016BSC
0.016
Max
0.035
0.002
0.028
0.010
0.282
0.020
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
RTL8367N-VB
Datasheet
14. Ordering Information
Table 39. Ordering Information
Part Number
Package
RTL8367N-VB-CG
QFN 88-Pin ‘Green’ Package
Note: See page 8 for package identification.
Status
-
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
Single-Chip 5-Port 10/100/1000M Switch Controller
54
Track ID: xxxx-xxxx-xx Rev. Pre-0.9
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