M031TD2AE

M031/M032 Arm® Cortex® -M 32-bit Microcontroller NuMicro® Family M031/M032 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Apr. 29, 2020 Page 1 of 283 Rev 2.01 M031/M032 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. M031/M032 TABLE OF CONTENTS 1 GENERAL DESCRIPTION............................................................................. 13 2 FEATURES .................................................................................................... 14 2.1 M031/M032 Features .................................................................................................. 14 3 PARTS INFORMATION ................................................................................. 22 3.1 Package Type .............................................................................................................. 22 3.2 M031/M032 Series Selection Guide ......................................................................... 23 3.2.1 M031 Base Series (M031Fx / M031Ex / M031Tx) .................................................... 23 3.2.2 M031 Base Series (M031Lx) ........................................................................................ 24 3.2.3 M031 Base Series (M031Sx) ........................................................................................ 25 3.2.4 M031 Base Series (M031Kx) ........................................................................................ 26 3.2.5 M032 USB Series (M032Fx / M032Ex / M032Tx) ..................................................... 27 3.2.6 M032 USB Series (M032Lx) ......................................................................................... 28 3.2.7 M032 USB Series (M032Sx) ......................................................................................... 29 3.2.8 M032 USB Series (M032Kx) ......................................................................................... 30 3.2.9 Naming Rule.................................................................................................................... 31 3.3 M031/M032 Series Feature Comparison Table ...................................................... 32 4 PIN CONFIGURATION .................................................................................. 33 4.1 Pin Configuration ......................................................................................................... 33 4.1.1 M031 Series Pin Diagram ............................................................................................. 33 4.1.2 M031 Series Multi-function Pin Diagram..................................................................... 39 M031/M032 SERIES DATASHEET 4.1.3 M032 Series Pin Diagram ............................................................................................. 99 4.1.4 M032 Series Multi-function Pin Diagram...................................................................105 4.2 Pin Mapping ............................................................................................................... 154 4.3 Pin Function Description .......................................................................................... 159 5 BLOCK DIAGRAM ....................................................................................... 165 6 FUNCTIONAL DESCRIPTION ..................................................................... 166 6.1 Arm® Cortex®-M0 Core ............................................................................................. 166 6.2 Clock Controller ......................................................................................................... 168 6.2.1 Overview ........................................................................................................................168 6.2.2 Clock Generator ............................................................................................................170 6.2.3 System Clock and SysTick Clock ...............................................................................172 6.2.4 Peripherals Clock .........................................................................................................174 6.2.5 Power-down Mode Clock ............................................................................................174 6.2.6 Clock Output..................................................................................................................175 6.2.7 USB Clock Source ........................................................................................................175 6.3 System Manager........................................................................................................ 177 6.3.1 Overview ........................................................................................................................177 Apr. 29, 2020 Page 2 of 283 Rev 2.01 M031/M032 6.3.2 System Reset ................................................................................................................177 6.3.3 System Power Distribution ..........................................................................................183 6.3.4 Power Modes and Wake-up Sources ........................................................................183 6.3.5 System Memory Map ...................................................................................................187 6.3.6 SRAM Memory Organization ......................................................................................189 6.3.7 SRAM Memory Organization with parity function ....................................................189 6.3.8 Chip Bus Matrix ............................................................................................................191 6.3.9 IRC Auto Trim ................................................................................................................191 6.3.10 Register Lock Control ..................................................................................................192 6.3.11 UART0_TXD/USCI0_DAT0 modulation with PWM .................................................192 6.3.12 System Timer (SysTick) ...............................................................................................193 6.3.13 Nested Vectored Interrupt Controller (NVIC) ............................................................194 6.4 Flash Memory Controller (FMC) .............................................................................. 197 6.4.1 Overview ........................................................................................................................197 6.5 General Purpose I/O (GPIO) ................................................................................... 198 6.5.1 Overview ........................................................................................................................198 6.5.2 Features .........................................................................................................................198 6.6 PDMA Controller (PDMA) ......................................................................................... 199 6.6.1 Overview ........................................................................................................................199 6.6.2 Features .........................................................................................................................199 6.7 Timer Controller (TMR) ............................................................................................. 200 6.7.1 Overview ........................................................................................................................200 6.7.2 Features .........................................................................................................................200 6.8.1 Overview ........................................................................................................................201 6.8.2 Features .........................................................................................................................201 6.9 Window Watchdog Timer (WWDT) ......................................................................... 202 6.9.1 Overview ........................................................................................................................202 6.9.2 Features .........................................................................................................................202 6.10 Real Time Clock (RTC) ....................................................................................... 203 6.10.1 Overview ........................................................................................................................203 6.10.2 Features .........................................................................................................................203 6.11 Basic PWM Generator and Capture Timer (BPWM) ...................................... 204 6.11.1 Overview ........................................................................................................................204 6.11.2 Features .........................................................................................................................204 6.12 PWM Generator and Capture Timer (PWM) ................................................... 205 6.12.1 Overview ........................................................................................................................205 6.12.2 Features .........................................................................................................................205 6.13 UART Interface Controller (UART).................................................................... 207 6.13.1 Overview ........................................................................................................................207 Apr. 29, 2020 Page 3 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 6.8 Watchdog Timer (WDT) ............................................................................................ 201 M031/M032 6.13.2 Features .........................................................................................................................207 6.14 Serial Peripheral Interface (SPI)........................................................................ 209 6.14.1 Overview ........................................................................................................................209 6.14.2 Features .........................................................................................................................209 6.15 Quad Serial Peripheral Interface (QSPI).......................................................... 210 6.15.1 Overview ........................................................................................................................210 6.15.2 Features .........................................................................................................................210 6.16 I2C Serial Interface Controller (I2C) ................................................................... 211 6.16.1 Overview ........................................................................................................................211 6.16.2 Features .........................................................................................................................211 6.17 USCI - Universal Serial Control Interface Controller (USCI)......................... 213 6.17.1 Overview ........................................................................................................................213 6.17.2 Features .........................................................................................................................213 6.18 USCI – UART Mode ............................................................................................ 214 6.18.1 Overview ........................................................................................................................214 6.18.2 Features .........................................................................................................................214 6.19 USCI - SPI Mode ................................................................................................. 215 6.19.1 Overview ........................................................................................................................215 6.19.2 Features .........................................................................................................................215 6.20 USCI - I2C Mode .................................................................................................. 217 6.20.1 Overview ........................................................................................................................217 6.20.2 Features .........................................................................................................................217 M031/M032 SERIES DATASHEET 6.21 External Bus Interface (EBI) .............................................................................. 218 6.21.1 Overview ........................................................................................................................218 6.21.2 Features .........................................................................................................................218 6.22 USB 2.0 Full-Speed Device Controller (USBD) .............................................. 219 6.22.1 Overview ........................................................................................................................219 6.22.2 Features .........................................................................................................................219 6.23 CRC Controller (CRC) ........................................................................................ 220 6.23.1 Overview ........................................................................................................................220 6.23.2 Features .........................................................................................................................220 6.24 Hardware Divider (HDIV) .................................................................................... 221 6.24.1 Overview ........................................................................................................................221 6.24.2 Features .........................................................................................................................221 6.25 Analog-to-Digital Converter (ADC).................................................................... 222 6.25.1 Overview ........................................................................................................................222 6.25.2 Features .........................................................................................................................222 6.26 Analog Comparator Controller (ACMP)............................................................ 224 6.26.1 Overview ........................................................................................................................224 Apr. 29, 2020 Page 4 of 283 Rev 2.01 M031/M032 6.26.2 Features .........................................................................................................................224 6.27 Peripherals Interconnection ............................................................................... 225 6.27.1 Overview ........................................................................................................................225 6.27.2 Peripherals Interconnect Matrix table ........................................................................225 7 APPLICATION CIRCUIT .............................................................................. 226 7.1 Power Supply Scheme ............................................................................................. 226 7.2 Peripheral Application Scheme ............................................................................... 227 8 ELECTRICAL CHARACTERISTICS ............................................................ 228 8.1 Absolute Maximum Ratings ..................................................................................... 228 8.1.1 Voltage Characteristics ................................................................................................228 8.1.2 Current Characteristics ................................................................................................228 8.1.3 Thermal Characteristics...............................................................................................230 8.1.4 EMC Characteristics ....................................................................................................231 8.1.5 Package Moisture Sensitivity(MSL) ...........................................................................232 8.1.6 Soldering Profile ...........................................................................................................233 8.2 General Operating Conditions ................................................................................. 234 8.3 DC Electrical Characteristics ................................................................................... 235 8.3.1 Supply Current Characteristics for M03xB/M03xC/M03xD/M03xE .......................235 8.3.2 Supply Current Characteristics for M03xG/M03xI ...................................................238 8.3.3 On-Chip Peripheral Current Consumption ................................................................241 8.3.4 Wakeup Time from Low-Power Modes .....................................................................243 8.3.5 I/O Current Injection Characteristics ..........................................................................244 8.4 AC Electrical Characteristics ................................................................................... 246 8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) .................................................246 8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................248 8.4.3 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics 249 8.4.4 External 4~32 MHz High Speed Clock Input Signal Characteristics ....................251 8.4.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics 252 8.4.6 External 32.768 kHz Low Speed Clock Input Signal Characteristics ...................253 8.4.7 PLL Characteristics ......................................................................................................254 8.4.8 I/O AC Characteristics .................................................................................................255 8.5 Analog Characteristics .............................................................................................. 256 8.5.1 LDO ................................................................................................................................256 8.5.2 Reset and Power Control Block Characteristics ......................................................256 8.5.3 12-bit SAR ADC ............................................................................................................258 8.5.4 Analog Comparator Controller (ACMP) .....................................................................261 8.6 Communications Characteristics ............................................................................ 262 Apr. 29, 2020 Page 5 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 8.3.6 I/O DC Characteristics .................................................................................................244 M031/M032 8.6.1 QSPI/SPI Dynamic Characteristics ............................................................................262 2 8.6.2 SPI - I S Dynamic Characteristics .............................................................................265 2 8.6.3 I C Dynamic Characteristics .......................................................................................267 8.6.4 USCI - SPI Dynamic Characteristics .........................................................................268 2 8.6.5 USCI - I C Dynamic Characteristics ..........................................................................271 8.6.6 USB Characteristics .....................................................................................................272 8.7 Flash DC Electrical Characteristics ........................................................................ 273 9 PACKAGE DIMENSIONS ............................................................................ 274 9.1 TSSOP 20 (4.4x6.5x0.9 mm)................................................................................... 274 9.2 TSSOP 28 (4.4x9.7x1.0 mm)................................................................................... 275 9.3 QFN 33L (4X4x0.8 mm Pitch:0.40 mm) ................................................................. 276 9.4 LQFP 48L (7x7x1.4 mm Footprint 2.0mm) ............................................................ 277 9.5 LQFP 64L (7x7x1.4 mm Footprint 2.0 mm) ........................................................... 278 9.6 LQFP 128L (14x14x1.4 mm Footprint 2.0 mm) .................................................... 279 10 ABBREVIATIONS ........................................................................................ 280 10.1 Abbreviations ........................................................................................................ 280 11 REVISION HISTORY ................................................................................... 282 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 6 of 283 Rev 2.01 M031/M032 LIST OF FIGURES Figure 4.1-1 M031 Series TSSOP 20-pin Diagram ........................................................................ 33 Figure 4.1-2 M031 Series TSSOP 28-pin Diagram ........................................................................ 34 Figure 4.1-3 M031 Series QFN 33-pin Diagram ............................................................................ 35 Figure 4.1-4 M031 Series LQFP 48-pin Diagram .......................................................................... 36 Figure 4.1-5 M031 Series LQFP 64-pin Diagram .......................................................................... 37 Figure 4.1-6 M031 Series LQFP 128-pin Diagram ........................................................................ 38 Figure 4.1-7 M031FB0AE Multi-function Pin Diagram ................................................................... 39 Figure 4.1-8 M031FC1AE Multi-function Pin Diagram ................................................................... 40 Figure 4.1-9 M031EB0AE Multi-function Pin Diagram ................................................................... 41 Figure 4.1-10 M031EC1AE Multi-function Pin Diagram................................................................. 42 Figure 4.1-11 M031TB0AE Multi-function Pin Diagram ................................................................. 44 Figure 4.1-12 M031TC1AE Multi-function Pin Diagram ................................................................. 46 Figure 4.1-13 M031TD2AE Multi-function Pin Diagram ................................................................. 48 Figure 4.1-14 M031LC2AE Multi-function Pin Diagram ................................................................. 50 Figure 4.1-15 M031LD2AE Multi-function Pin Diagram ................................................................. 53 Figure 4.1-16 M031LE3AE Multi-function Pin Diagram ................................................................. 56 Figure 4.1-17 M031LG6AE Multi-function Pin Diagram ................................................................. 59 Figure 4.1-18 M031LG8AE Multi-function Pin Diagram ................................................................. 62 Figure 4.1-19 M031SC2AE Multi-function Pin Diagram................................................................. 65 Figure 4.1-21 M031SE3AE Multi-function Pin Diagram ................................................................. 71 Figure 4.1-22 M031SG6AE Multi-function Pin Diagram ................................................................ 74 Figure 4.1-23 M031SG8AE Multi-function Pin Diagram ................................................................ 77 Figure 4.1-24 M031SIAAE Multi-function Pin Diagram .................................................................. 80 Figure 4.1-25 M031KG6AE Multi-function Pin Diagram ................................................................ 84 Figure 4.1-26 M031KG8AE Multi-function Pin Diagram ................................................................ 89 Figure 4.1-27 M031KIAAE Multi-function Pin Diagram .................................................................. 94 Figure 4.1-28 M032 Series TSSOP 20-pin Diagram...................................................................... 99 Figure 4.1-29 M032 Series TSSOP 28-pin Diagram.................................................................... 100 Figure 4.1-30 M032 Series QFN 33-pin Diagram ........................................................................ 101 Figure 4.1-31 M032 Series LQFP 48-pin Diagram ...................................................................... 102 Figure 4.1-32 M032 Series LQFP 64-pin Diagram ...................................................................... 103 Figure 4.1-33 M032 Series LQFP 128-pin Diagram .................................................................... 104 Figure 4.1-34 M032FC1AE Multi-function Pin Diagram ............................................................... 105 Figure 4.1-35 M032EC1AE Multi-function Pin Diagram............................................................... 106 Figure 4.1-36 M032TC1AE Multi-function Pin Diagram ............................................................... 108 Apr. 29, 2020 Page 7 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Figure 4.1-20 M031SD2AE Multi-function Pin Diagram................................................................. 68 M031/M032 Figure 4.1-37 M032TD2AE Multi-function Pin Diagram ............................................................... 110 Figure 4.1-38 M032LC2AE Multi-function Pin Diagram ............................................................... 112 Figure 4.1-39 M032LD2AE Multi-function Pin Diagram ............................................................... 115 Figure 4.1-40 M032LE3AE Multi-function Pin Diagram ............................................................... 118 Figure 4.1-41 M032LG6AE Multi-function Pin Diagram ............................................................... 121 Figure 4.1-42 M032LG8AE Multi-function Pin Diagram ............................................................... 124 Figure 4.1-43 M032SE3AE Multi-function Pin Diagram ............................................................... 127 Figure 4.1-44 M032SG6AE Multi-function Pin Diagram .............................................................. 130 Figure 4.1-45 M032SG8AE Multi-function Pin Diagram .............................................................. 133 Figure 4.1-46 M032SIAAE Multi-function Pin Diagram ................................................................ 136 Figure 4.1-47 M032KG6AE Multi-function Pin Diagram .............................................................. 139 Figure 4.1-48 M032KG8AE Multi-function Pin Diagram .............................................................. 144 Figure 4.1-49 M032KIAAE Multi-function Pin Diagram ................................................................ 149 ® Figure 5-1 NuMicro M031/M032 Block Diagram ........................................................................ 165 Figure 6-1 Functional Block Diagram ........................................................................................... 166 Figure 6.2-1 Clock Generator Global View Diagram (1/2) ........................................................... 169 Figure 6.2-2 Clock Generator Global View Diagram (2/2) ........................................................... 170 Figure 6.2-3 Clock Generator Block Diagram .............................................................................. 171 Figure 6.2-4 System Clock Block Diagram .................................................................................. 172 Figure 6.2-5 HXT Stop Protect Procedure ................................................................................... 173 Figure 6.2-6 LXT Stop Protect Procedure .................................................................................... 174 M031/M032 SERIES DATASHEET Figure 6.2-7 SysTick Clock Control Block Diagram ..................................................................... 174 Figure 6.2-8 Clock Output Block Diagram ................................................................................... 175 Figure 6.2-9 USBD Clock Source ................................................................................................ 176 Figure 6.3-1 System Reset Sources ............................................................................................ 178 Figure 6.3-2 nRESET Reset Waveform ....................................................................................... 180 Figure 6.3-3 Power-on Reset (POR) Waveform .......................................................................... 180 Figure 6.3-4 Low Voltage Reset (LVR) Waveform ....................................................................... 181 Figure 6.3-5 Brown-out Detector (BOD) Waveform ..................................................................... 182 ® Figure 6.3-6 NuMicro M031 Power Distribution Diagram ........................................................... 183 Figure 6.3-7 Power Mode State Machine .................................................................................... 185 Figure 6.3-8 SRAM Memory Organization ................................................................................... 189 ® Figure 6.3-9 NuMicro M031 Bus Matrix Diagram ....................................................................... 191 Figure 6.19-1 SPI Master Mode Application Block Diagram ........................................................ 215 Figure 6.19-2 SPI Slave Mode Application Block Diagram .......................................................... 215 2 Figure 6.20-1 I C Bus Timing ....................................................................................................... 217 Figure 8.1-1 Soldering Profile from J-STD-020C ......................................................................... 233 Apr. 29, 2020 Page 8 of 283 Rev 2.01 M031/M032 Figure 8.4-1 HIRC vs. Temperature ............................................................................................. 247 Figure 8.4-2 Typical Crystal Application Circuit ........................................................................... 250 Figure 8.4-3 Typical 32.768 kHz Crystal Application Circuit ........................................................ 252 Figure 8.5-1 Power Ramp Up/Down Condition ............................................................................ 257 Figure 8.6-1 QSPI/SPI Master Mode Timing Diagram ................................................................. 262 Figure 8.6-2 QSPI/SPI Slave Mode Timing Diagram ................................................................... 264 2 Figure 8.6-3 I S Master Mode Timing Diagram............................................................................ 265 2 Figure 8.6-4 I S Slave Mode Timing Diagram.............................................................................. 266 2 Figure 8.6-5 I C Timing Diagram ................................................................................................. 267 Figure 8.6-6 USCI-SPI Master Mode Timing Diagram ................................................................. 268 Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram ................................................................... 270 2 Figure 8.6-8 USCI-I C Timing Diagram ........................................................................................ 271 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 9 of 283 Rev 2.01 M031/M032 List of Tables ® Table 1-1 NuMicro M031/M032 Series Key Features Support Table .......................................... 13 Table 4.1-1 M031FB0AE Multi-function Pin Table ......................................................................... 39 Table 4.1-2 M031FC1AE Multi-function Pin Table ......................................................................... 40 Table 4.1-3 M031EB0AE Multi-function Pin Table ......................................................................... 42 Table 4.1-4 M031EC1AE Multi-function Pin Table ........................................................................ 43 Table 4.1-5 M031TB0AE Multi-function Pin Table ......................................................................... 45 Table 4.1-6 M031TC1AE Multi-function Pin Table ......................................................................... 47 Table 4.1-7 M031TD2AE Multi-function Pin Table ......................................................................... 49 Table 4.1-8 M031LC2AE Multi-function Pin Table ......................................................................... 52 Table 4.1-9 M031LD2AE Multi-function Pin Table ......................................................................... 55 Table 4.1-10 M031LE3AE Multi-function Pin Table ....................................................................... 58 Table 4.1-11 M031LG6AE Multi-function Pin Table....................................................................... 61 Table 4.1-12 M031LG8AE Multi-function Pin Table....................................................................... 64 Table 4.1-13 M031SC2AE Multi-function Pin Table ...................................................................... 67 Table 4.1-14 M031SD2AE Multi-function Pin Table ...................................................................... 70 Table 4.1-15 M031SE3AE Multi-function Pin Table....................................................................... 73 Table 4.1-16 M031SG6AE Multi-function Pin Table ...................................................................... 76 Table 4.1-17 M031SG8AE Multi-function Pin Table ...................................................................... 79 Table 4.1-18 M031SIAAE Multi-function Pin Table........................................................................ 82 Table 4.1-19 M031KG6AE Multi-function Pin Table ...................................................................... 88 M031/M032 SERIES DATASHEET Table 4.1-20 M031KG8AE Multi-function Pin Table ...................................................................... 93 Table 4.1-21 M031KIAAE Multi-function Pin Table........................................................................ 98 Table 4.1-22 M032FC1AE Multi-function Pin Table..................................................................... 105 Table 4.1-23 M032EC1AE Multi-function Pin Table .................................................................... 107 Table 4.1-24 M032TC1AE Multi-function Pin Table..................................................................... 109 Table 4.1-25 M032TD2AE Multi-function Pin Table..................................................................... 111 Table 4.1-26 M032LC2AE Multi-function Pin Table ..................................................................... 114 Table 4.1-27 M032LD2AE Multi-function Pin Table ..................................................................... 117 Table 4.1-28 M032LE3AE Multi-function Pin Table ..................................................................... 120 Table 4.1-29 M032LG6AE Multi-function Pin Table..................................................................... 123 Table 4.1-30 M032LG8AE Multi-function Pin Table..................................................................... 126 Table 4.1-31 M032SE2AE Multi-function Pin Table..................................................................... 129 Table 4.1-32 M032SG6AE Multi-function Pin Table .................................................................... 132 Table 4.1-33 M032SG8AE Multi-function Pin Table .................................................................... 135 Table 4.1-34 M032SIAAE Multi-function Pin Table...................................................................... 138 Table 4.1-35 M032KG6AE Multi-function Pin Table .................................................................... 143 Apr. 29, 2020 Page 10 of 283 Rev 2.01 M031/M032 Table 4.1-36 M032KG8AE Multi-function Pin Table .................................................................... 148 Table 4.1-37 M032KIAAE Multi-function Pin Table...................................................................... 153 Table 6.3-1 Reset Value of Registers .......................................................................................... 180 Table 6.3-2 Power Mode Table .................................................................................................... 184 Table 6.3-3 Power Mode Difference Table .................................................................................. 184 Table 6.3-4 Power Mode Difference Table .................................................................................. 184 Table 6.3-5 Clocks in Power Modes ............................................................................................ 186 Table 6.3-6 Condition of Entering Power-down Mode Again ....................................................... 187 Table 6.3-7 Address Space Assignments for On-Chip Controllers .............................................. 188 Table 6.3-8 Exception Model ....................................................................................................... 195 Table 6.3-9 Interrupt Number Table ............................................................................................. 196 ® Table 6.13-1 NuMicro M031/M032 Series UART Features ....................................................... 208 2 Table 6.16-1 I C Feature Comparison Table at Different Chip .................................................... 212 Table 6.21-1 EBI Features Comparison Table ............................................................................ 218 Table 6.25-1 ADC Features Comparison Table ........................................................................... 223 Table 6.26-1 Calibration Function Features Comparison Table at Different Chip ....................... 224 Table 6.27-1 Peripherals Interconnect Matrix table ..................................................................... 225 Table 8.1-1 Voltage Characteristics ............................................................................................. 228 Table 8.1-2 Current Characteristics ............................................................................................. 229 Table 8.1-3 Thermal Characteristics ............................................................................................ 230 Table 8.1-4 EMC Characteristics for M03xB/M03xC/M03xD/M03xE .......................................... 231 Table 8.1-6 Package Moisture Sensitivity (MSL) ......................................................................... 232 Table 8.1-7 Soldering Profile ........................................................................................................ 233 Table 8.2-1 General Operating Conditions .................................................................................. 234 Table 8.3-1 Current Consumption in Normal Run Mode.............................................................. 235 Table 8.3-2 Current Consumption in Idle Mode ........................................................................... 236 Table 8.3-3 Chip Current Consumption in Power-down Mode .................................................... 237 Table 8.3-4 Current Consumption in Normal Run Mode.............................................................. 238 Table 8.3-5 Current Consumption in Idle Mode ........................................................................... 239 Table 8.3-6 Chip Current Consumption in Power-down Mode .................................................... 240 Table 8.3-7 Peripheral Current Consumption .............................................................................. 242 Table 8.3-8 Low-power Mode Wakeup Timings .......................................................................... 243 Table 8.3-9 I/O Current Injection Characteristics ......................................................................... 244 Table 8.3-10 I/O Input Characteristics ......................................................................................... 244 Table 8.3-11 I/O Output Characteristics ...................................................................................... 245 Table 8.3-12 nRESET Input Characteristics ................................................................................ 245 Apr. 29, 2020 Page 11 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Table 8.1-5 EMC Characteristics for M03xG/M03xI .................................................................... 232 M031/M032 Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics .......................... 246 Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics .......................... 248 Table 8.4-3 External 4~32 MHz High Speed Crystal (HXT) Oscillator ........................................ 249 Table 8.4-4 External 4~32 MHz High Speed Crystal Characteristics .......................................... 250 Table 8.4-5 External 4~32 MHz High Speed Clock Input Signal ................................................. 251 Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator ........................................ 252 Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics ......................................... 252 Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal ................................................ 253 Table 8.4-9 PLL Characteristics ................................................................................................... 254 Table 8.4-10 I/O AC Characteristics ............................................................................................ 255 Table 8.5-1 Reset and Power Control Unit .................................................................................. 256 Table 8.5-2 ACMP Characteristics ............................................................................................... 261 Table 8.6-1 QSPI/SPI Master Mode Characteristics .................................................................... 262 Table 8.6-2 QSPI/SPI Slave Mode Characteristics ...................................................................... 263 2 Table 8.6-3 I S Characteristics .................................................................................................... 265 2 Table 8.6-4 I C Characteristics .................................................................................................... 267 Table 8.6-5 USCI-SPI Master Mode Characteristics ................................................................... 268 Table 8.6-6 USCI-SPI Slave Mode Characteristics ..................................................................... 269 2 Table 8.6-7 USCI-I C Characteristics .......................................................................................... 271 Table 8.6-8 USB Full-Speed Characteristics ............................................................................... 272 Table 8.6-9 USB Full-Speed PHY Characteristics ....................................................................... 272 M031/M032 SERIES DATASHEET Table 10.1-1 List of Abbreviations................................................................................................ 281 Apr. 29, 2020 Page 12 of 283 Rev 2.01 M031/M032 1 GENERAL DESCRIPTION ® ® ® The NuMicro M031/M032 series 32-bit microcontroller is based on Arm Cortex -M0 core with 32-bit hardware multiplier/divider. It features 1.8 ~ 3.6 V operating voltage, 5 V I/O tolerant, and runs up to 48/72 MHz within -40°C ~105°C. The M031/M032 series provides a solution for the applications that need 1.8 V low-voltage interface connection with enhanced fast 2 MSPS conversion rate 12-bit ADC, comparators and up-to 24-ch 96/144 MHz PWM control. It supports a fast and precise data conversion for the voltage, current, and sensor data, then fast response control to the external device. Additionally, the M031/M032 series also provides plenty of peripherals including Universal Serial Control Interface(USCI) that can be set as 2 2 UART/SPI/I C flexibly, up to 10 sets of UART, 4 sets of SPI, 4 sets of I C, and 1-wire UART interface for data communication between master and slave devices. The M031/M032 series provides Flash size from 16 Kbytes to 512 Kbytes, SRAM size from 2 Kbytes to 96 Kbytes. Supported packages from small form factor TSSOP 20-pin, TSSOP 28-pin, QFN 33-pin, LQFP 48-pin to LQFP 64-pin and LQFP 128-pin with pin-compatible for different part numbers makes the system design and parts change easily. Part Numbers with the M032 series are all based on the M031 series and enhanced with the crystalless USB 2.0 full-speed device feature for USB related applications. For the development, Nuvoton provides the NuMaker-PFM evaluation board and Nuvoton Nu-Link rd ® debugger. The 3 Party IDE such as Keil MDK, IAR EWArm, Eclippse IDE with GNU GCC compilers are also supported. Product Line M031/M032 UART I2C 8 2 SPI/ QSPI USCI Timer PWM RTC PDMA EBI ADC ACMP Divider USBD IEC60730 I2S 1 1 2 4 24 1 9 1 16 2 1 √ √ ® Table 1-1 NuMicro M031/M032 Series Key Features Support Table ® The NuMicro M031/M032 series is suitable for a wide range of applications such as: Laser Distance Meter  Air Detector/Cleaner  Mobile LCD Panel Controller  IoT Sensing Device  HMI Controller  Micro Printer  Gaming Keyboard and Mouse  WPC Wireless Charger Apr. 29, 2020 Page 13 of 283 M031/M032 SERIES DATASHEET  Rev 2.01 M031/M032 2 FEATURES 2.1 M031/M032 Features Core and System ® ®  Arm Cortex -M0 processor, running up to 72 MHz – 72 MHz at 2.0V-3.6V – 48 MHz at 1.8V-3.6V ® ® Arm Cortex -M0  Built-in Nested Vectored Interrupt Controller (NVIC)  24-bit system tick timer  Programmble and maskable interrupt  Low Power Sleep mode by WFI and WFE instructions Brown-out Detector (BOD) Low Voltage Reset (LVR) Security  Two-level BOD with brown-out interrupt and reset option. (2.5V/2.0V)  LVR with 1.7V threshold voltage level.  96-bit Unique ID (UID).  128-bit Unique Customer ID (UCID).  Signed (two’s complement) integer calculation 32-bit H/W Divider(HDIV)  32-bit dividend with 16-bit divisor calculation capacity  32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit) M031/M032 SERIES DATASHEET Memories  Dual bank 512 KB on-chip Application ROM (APROM) for OverThe-Air (OTA) upgrade.  Single bank up to 256 KB on-chip Application ROM (APROM).  Up to 8 KB on-chip Flash for user-defined loader (LDROM)  Up to 2048 bytes non-readble Security Protection ROM (SPROM) Flash  All on-chip Flash support 512 bytes or 2048 bytes page erase  Fast Flash programming verification with CRC-32 checksum calculation  On-chip Flash programming with In-Chip Programming (ICP), InSystem Programming (ISP) and In-Application Programming (IAP) capabilities  2-wired ICP Flash updating through SWD/ICE interface  Up to 96 KB on-chip SRAM SRAM Apr. 29, 2020 – 32 KB SRAM located in bank 0 that supports hardware parity check and retenion mode – 32/32 KB SRAM located in bank 1 and bank 2 Page 14 of 283 Rev 2.01 M031/M032  Byte-, half-word- and word-access  PDMA operation  Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials  Programmable initial value and seed value  Programmable order reverse setting and one’s complement setting for input data and CRC checksum Cyclic Redundancy Calculation (CRC)  8-bit, 16-bit, and 32-bit data width  8-bit write mode with 1-AHB clock cycle operation  16-bit write mode with 2-AHB clock cycle operation  32-bit write mode with 4-AHB clock cycle operation  Uses DMA to write data with performing CRC operation  Up to 9 independent and configurable channels for automatic data transfer between memories and peripherals  Basic and Scatter-Gather transfer modes Peripheral DMA (PDMA)  Each channel supports circular buffer management using ScatterGather Transfer mode  Fixed-priority and Round-robin priorities modes  Single and burst transfer types  Byte-, half-word- and word tranfer unit with count up to 65536  Incremental or fixed source and destination address Clocks External Clock Source  32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC function and low-power system operation  Supports clock failure detection for external crystal oscillators and exception generatation (NMI)  48 MHz High-speed Internal RC oscillator (HIRC) dedicated for crystal-less USB. Internal Clock Source  38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog timer and wakeup operation  Up to 144 MHz on-chip PLL, sourced from HIRC or HXT, allows CPU operation up to the maximim CPU frequency without the need for a high-frequency crystal  The RTC clock source includes Low-speed external crystal oscillator (LXT) Real-Time Clock (RTC)  Able to wake up CPU from idle or power-down mode  Supports ±5ppm within 5 seconds software clock accuracy compensation  Supports Alarm registers (second, minute, hour, day, month, year) Apr. 29, 2020 Page 15 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  4~32 MHz High-speed eXternal crystal oscillator (HXT) for precise timing operation M031/M032  Supports RTC Time Tick and Alarm Match interrupt  Automatic leap year recognition  Supports 1 Hz clock output for calibration Timers  Up to 4 sets of 32-bit timers with 24-bit up counter and one 8-bit pre-scale counter from independent clock source  One-shot, Periodic, Toggle and Continuous Counting operation modes 32-bit Timer  Supports event counting function to count the event from external pins  Supports external capture pin for interval measurement and resetting 24-bit up counter  Supports chip wake-up function, if a timer interrupt signal is generated  Up to two PWM modules, each module provides three 16-bit counter and 6 output channels.  Up to 12 independent input capture channels with 16-bit resolution counter  Supports dead time with maximum divided 12-bit prescale  Up, down or up-down PWM counter type PWM (PWM)  Supports complementary mode for 3 complementary paired PWM output channels  Counter synchronous start function M031/M032 SERIES DATASHEET  Brake function with auto recovery mechanism  Mask function and tri-state output for each PWM channel  Able to trigger ADC to start conversion  Two 16-bit counters with 12-bit clock prescale for twelve 144 MHz PWM output channels.  Up to 6 independent input capture channels with 16-bit resolution counter Basic PWM (BPWM)  Up, down or up-down PWM counter type  Counter synchronous start function  Mask function and tri-state output for each PWM channel  Able to trigger ADC to start conversion  20-bit free running up counter for WDT time-out interval  Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT with 9 selectable time-out period Watchdog  Able to wake up system from Power-down or Idle mode  Time-out event to trigger interrupt or reset system  Supports four WDT reset delay periods, including 1026, 130, 18 or 3 WDT_CLK reset delay period Apr. 29, 2020 Page 16 of 283 Rev 2.01 M031/M032  Configured to force WDT enabled on chip power-on or reset. Window Watchdog  Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit counter with 11-bit prescale  Suspended in Idle/Power-down mode Analog Interfaces  Analog input voltage range: 0 ~ AVDD  One 12-bit, 2 MSPS SAR ADC with up to 16 single-ended input channels or 8 differential input pairs; 10-bit accuracy is guaranteed.  Internal channels for band-gap VBG input.  Supports external VREF pin.  Supports calibration capability.  Four operation modes: Single mode, Burst mode, Single-cycle Scan mode and Continuous Scan mode. ADC  Analog-to-Digital conversion can be triggered by software enable (ADST), external pin (STADC), Timer 0~3 overflow pulse trigger, PWM trigger or BPWM trigger.  Each conversion result is held in data register of each channel with valid and overrun indicators.  Supports conversion result monitor by compare mode function.  Configurable ADC external sampling time.  PDMA operation.  Supports floating detect function.  Supports four multiplexed I/O pins at positive input  Supports I/O pins, band-gap, and 16-level Voltage divider from AVDD or VREF at negative input Analog Comparator (ACMP)  Supports wake up from Power-down by interrupt  Supports triggers for brake events and cycle-by-cycle control for PWM  Supports window compare mode and window latch mode  Supports hysteresis function  Supports calibration function Communication Interfaces  Low-power UARTs with up to 7.2 MHz baud rate. Low-power UART  Auto-Baud Rate measurement and baud rate compensation function.  Supports low power UART (LPUART): baud rate clock from LXT (32.768 kHz) with 9600bps in Power-down mode even system clock is stopped. Apr. 29, 2020 Page 17 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  Two Analog Comparators M031/M032  16-byte FIFOs with programmable level trigger  Auto flow control (nCTS and nRTS)  Supports IrDA (SIR) function  Supports RS-485 9-bit mode and direction control  Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function in idle mode.  Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction  Supports wake-up function  8-bit receiver FIFO time-out detection function  Supports break error, frame error, parity error and receive/transmit FIFO overflow detection function  PDMA operation.  Supports Single-wire function mode. 2  Three sets of I C devices with Master/Slave mode.  Supports Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps)  Supports 7 bits mode 2 IC  Programmable clocks allowing for versatile rate control  Supports multiple address recognition (four slave address with mask option) M031/M032 SERIES DATASHEET  Supports multi-address power-down wake-up function  PDMA operation 2  I C Port0 supports SMBus and PMBus  SPI Quad controller with Master/Slave mode.  Up to 24 MHz in Master mode and up to 16 MHz in Slave mode at 1.8V~3.6V system voltage.  Supports Dual and Quad I/O Transfer mode.  Supports one data channel half-duplex transfer.  Supports receive-only mode.  Configurable bit length of a transfer word from 8 to 32-bit. Quad SPI  Provides separate 8-level depth transmit and receive FIFO buffers.  Supports MSB first or LSB first transfer sequence.  Supports the byte reorder function.  Supports Byte or Word Suspend mode.  Supports 3-wired, no slave select signal, bi-direction interface.  PDMA operation.  Supports 2-bit Transfer mode. Apr. 29, 2020 Page 18 of 283 Rev 2.01 M031/M032 2  SPI/I S controllers with Master/Slave mode. SPI  Up to 24 MHz in Master mode and up to 16 MHz in Slave mode at 1.8V~3.6V system voltage.  Configurable bit length of a transfer word from 8 to 32-bit.  Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO buffers.  MSB first or LSB first transfer sequence.  Byte reorder function.  Supports Byte or Word Suspend mode. 2 SPI/I S  Supports one data channel half-duplex transfer.  Supports receive-only mode.  PDMA operation. 2 IS  Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit audio data sizes.  Provides separate 4-level depth transmit and receive FIFO buffers. 2  Supports PCM mode A, PCM mode B, I S and MSB justified data format.  PDMA operation.  Generates interrupt requests when buffer levels cross as programmable boundary 2  Two sets of USCI, configured as UART, SPI or I C function. UART  Supports one transmit buffer and two receive buffers for data payload.  Supports hardware auto flow control function and programmable flow control trigger level.  9-bit Data Transfer.  Baud rate detection by built-in capture event of baud rate generator. Universal Serial Control Interface (USCI)  Supports wake-up function.  PDMA operation. SPI  Supports Master or Slave mode operation.  Supports one transmit buffer and two receive buffer for data payload.  Configurable bit length of a transfer word from 4 to 16-bit.  Supports MSB first or LSB first transfer sequence.  Supports Word Suspend function.  Supports 3-wire, no slave select signal, bi-direction interface.  Supports wake-up function: input slave select transition. Apr. 29, 2020 Page 19 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  Supports single byte TX and RX buffer mode M031/M032  PDMA operation.  Supports one data channel half-duplex transfer. 2 IC  Supports master and slave device capability.  Supports one transmit buffer and two receive buffer for data payload.  Communication in standard mode (100 kbps), fast mode (up to 400 kbps), and Fast mode plus (1 Mbps).  Supports 7-bit mode (10-bit mode not supported).  Supports 10-bit bus time out capability.  Supports bus monitor mode.  Supports power-down wake-up by data toggle or address match.  Supports multiple address recognition.  Supports device address flag.  Programmable setup/hold time.  Supports up to two memory banks with individual adjustment of timing parameter.  Each bank supports dedicated external chip select pin with polarity control and up to 1 MB addressing space.  8-/16-bit data width. External Bus Interface (EBI)  Supports byte write in 16-bit data width mode.  Configurable idle cycle for different access condition: Idle of Write command finish (W2X) and Idle of Read-to-Read (R2R).  Supports Address/Data multiplexed mode. M031/M032 SERIES DATASHEET  Supports address bus and data bus separate mode.  Supports LCD interface i80 mode.  PDMA operation.  Supports four I/O modes: Quasi bi-direction, Push-Pull output, Open-Drain output and Input only with high impendence mode.  Configured as interrupt source with edge/level trigger setting. GPIO  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode.  Supports 5V-tolerance function except analog IO (PA.10, PA.11, PB.0~PB.15, PF.2~PF.5).  Enabling the pin interrupt function will also enable the wake-up function.  Input schmitt trigger function. Advanced Connectivity USB 2.0 Full Speed with on-chip transceiver Apr. 29, 2020  Compliant with USB Revision 2.0 Specification.  Supports suspend function when no bus activity existing for 3 ms.  8 configurable endpoints for configurable Isochronous, Bulk, Page 20 of 283 Rev 2.01 M031/M032 Interrupt and Control transfer types.  512 bytes configurable RAM for endpoint buffer.  Remote wake-up capability.  Supports Crystal-less function  Start of Frame (SOF) locked clock pulse generation  USB 2.0 link power management. M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 21 of 283 Rev 2.01 M031/M032 3 PARTS INFORMATION 3.1 Package Type Part No. TSSOP20 TSSOP28 QFN33 M031xB M031FB0AE M031EB0AE M031TB0AE M031xC M031FC1AE M031EC1AE M031xD LQFP48 LQFP64 M031TC1AE M031LC2AE M031SC2AE M031TD2AE M031LD2AE M031SD2AE M031LE3AE M031SE3AE M031LG6AE M031SG6AE M031KG6AE M031LG8AE M031SG8AE M031KG8AE M031SIAAE M031KIAAE M031xE M031xG M031xI M032xC M032FC1AE M031/M032 SERIES DATASHEET M032xD M032xE M032xG M032EC1AE M032TC1AE M032LC2AE M032TD2AE M032LD2AE M032LE3AE M032SE3AE M032LG6AE M032SG6AE M032KG6AE M032LG8AE M032SG8AE M032KG8AE M032SIAAE M032KIAAE M032xI Apr. 29, 2020 LQFP128 Page 22 of 283 Rev 2.01 M031/M032 3.2 M031/M032 Series Selection Guide 3.2.1 M031 Base Series (M031Fx / M031Ex / M031Tx) M031 Part Number FB0AE FC1AE EB0AE EC1AE TB0AE TC1AE TD2AE Flash (KB) 16 32 16 32 16 32 64 SRAM (KB) 2 4 2 4 2 4 8 LDROM (KB) 2 SPROM (Bytes) 512 System Frequency (MHz) 48 PLL (MHz) - - - - - - 96 I/O 15 15 23 23 27 27 27 32-bit Timer 2 4 2 4 2 4 4 USCI - - - - - - 1 6 6 12 - 2 5 - √ √ Connectivity UART 3 2 SPI/I S 1 QSPI - I²C/SMBus 2/0 USB FS 6 6 6 6 BPWM PDMA - 2 - 2 EBI - HDIV √ CRC √ IEC-60730 - HXT √ LXT - - - - RTC - Analog Comparator - - - - - - 2 12-bit SAR ADC 7 7 9 9 10 10 10 TSSOP20 TSSOP20 TSSOP28 TSSOP28 QFN33 QFN33 QFN33 Package Apr. 29, 2020 Page 23 of 283 Rev 2.01 M031/M032 SERIES DATASHEET PWM - M031/M032 3.2.2 M031 Base Series (M031Lx) M031 Part Number LD2AE LE3AE LG6AE LG8AE Flash (KB) 32 64 128 256 256 SRAM (KB) 8 8 16 32 64 LDROM (KB) 2 2 4 4 4 SPROM (Bytes) 512 512 512 2048 2048 System Frequency (MHz) 48 48 48 72 72 PLL (MHz) 96 96 96 144 144 Connectivity LC2AE I/O 42 32-bit Timer 4 USCI 1 1 1 2 2 UART 3 3 3 6 6 SPI/I2S QSPI I²C/SMBus USB FS 1 - - - 1 1 2/0 2/0 2/0 2/1 2/1 - - - - - PWM 12 M031/M032 SERIES DATASHEET BPWM - - - 12 12 PDMA 5 5 5 7 7 EBI - - √ √ √ √ √ √ √ CRC √ HDIV √ IEC-60730 - - - HXT √ LXT √ RTC - - - Analog Comparator 2 12-bit SAR ADC 12 Package Apr. 29, 2020 LQFP48 Page 24 of 283 Rev 2.01 M031/M032 3.2.3 M031 Base Series (M031Sx) M031 Part Number SD2AE SE3AE SG6AE SG8AE SIAAE Flash (KB) 32 64 128 256 256 512 SRAM (KB) 8 8 16 32 64 96 LDROM (KB) 2 2 4 4 4 8 SPROM (Bytes) 512 512 512 2048 2048 2048 System Frequency (MHz) 48 48 48 72 72 72 PLL (MHz) 96 96 96 144 144 144 Connectivity SC2AE I/O 55 32-bit Timer 4 USCI 1 1 1 2 2 2 UART 3 3 3 6 6 8 SPI/I2S QSPI I²C/SMBus 1 - - - 1 1 1 2/0 2/0 2/0 2/1 2/1 2/1 USB FS - PWM 12 - - - 12 12 12 PDMA 5 5 5 7 7 9 EBI - - √ √ √ √ √ √ √ √ √ √ CRC √ HDIV √ IEC-60730 - - - HXT √ LXT √ RTC - - - Analog Comparator 2 12-bit SAR ADC 16 Package Apr. 29, 2020 LQFP64 Page 25 of 283 Rev 2.01 M031/M032 SERIES DATASHEET BPWM M031/M032 3.2.4 M031 Base Series (M031Kx) M031 Part Number KG6AE KG8AE KIAAE Flash (KB) 256 256 512 SRAM (KB) 32 64 96 LDROM (KB) 4 4 8 SPROM (Bytes) 2048 System Frequency (MHz) 72 PLL (MHz) 144 I/O 111 32-bit Timer 4 USCI 2 Connectivity UART 6 6 SPI/I2S 1 QSPI 1 I²C/SMBus 2/1 USB FS - PWM 12 BPWM 12 M031/M032 SERIES DATASHEET PDMA 7 7 EBI √ CRC √ HDIV √ IEC-60730 √ HXT √ LXT √ RTC √ Analog Comparator 2 12-bit SAR ADC 16 Package Apr. 29, 2020 8 9 LQFP128 Page 26 of 283 Rev 2.01 M031/M032 3.2.5 M032 USB Series (M032Fx / M032Ex / M032Tx) M032 Part Number FC1AE EC1AE TC1AE TD2AE Flash (KB) 32 32 32 64 SRAM (KB) 4 4 4 8 LDROM (KB) 2 SPROM (Bytes) 512 System Frequency (MHz) 48 Connectivity PLL (MHz) - I/O 11 19 23 23 32-bit Timer 2 2 2 4 USCI 1 1 1 2 - 1 UART 1 SPI/I2S 1 QSPI - - I²C/SMBus - USB FS √ PWM 6 6 6 12 PDMA - - - 5 - √ EBI - CRC - HDIV - - IEC-60730 - HXT - LXT - RTC - Analog Comparator - 12-bit SAR ADC Package Apr. 29, 2020 3 9 10 10 TSSOP20 TSSOP28 QFN33 QFN33 Page 27 of 283 Rev 2.01 M031/M032 SERIES DATASHEET BPWM M031/M032 3.2.6 M032 USB Series (M032Lx) M032 Part Number LC2AE LD2AE LE3AE LG6AE LG8AE Flash (KB) 32 64 128 256 256 SRAM (KB) 8 8 16 32 64 LDROM (KB) 2 2 4 4 4 SPROM (Bytes) 512 512 512 2048 2048 System Frequency (MHz) 48 48 48 72 72 - - 96 144 144 Connectivity PLL (MHz) I/O 38 32-bit Timer 4 USCI 2 2 1 2 2 UART 1 1 3 6 6 SPI/I2S 1 QSPI 1 1 - 1 1 I²C/SMBus - - 2/0 2/1 2/1 √ USB FS PWM M031/M032 SERIES DATASHEET - - 12 12 12 BPWM 12 12 - 12 12 PDMA 5 5 5 7 7 EBI - - √ √ √ CRC - - √ √ √ √ HDIV IEC-60730 - - - √ √ HXT - - √ √ √ LXT - - √ √ √ RTC - - - √ √ Analog Comparator - - 2 2 2 12-bit SAR ADC Package Apr. 29, 2020 12 LQFP48 Page 28 of 283 Rev 2.01 M031/M032 3.2.7 M032 USB Series (M032Sx) M032 Part Number SG6AE SG8AE SIAAE Flash (KB) 128 256 256 512 SRAM (KB) 16 32 64 96 LDROM (KB) 4 4 4 8 SPROM (Bytes) 512 2048 2048 2048 System Frequency (MHz) 48 72 72 72 PLL (MHz) 96 144 144 144 Connectivity SE3AE I/O 51 32-bit Timer 4 USCI 1 2 2 2 UART 3 6 6 8 SPI/I2S QSPI I²C/SMBus 1 - 1 1 1 2/0 2/1 2/1 2/1 USB FS √ PWM 12 - 12 12 12 PDMA 5 7 7 9 √ √ √ √ EBI √ CRC √ HDIV √ IEC-60730 - √ HXT √ LXT √ RTC - √ Analog Comparator 2 12-bit SAR ADC 16 Package Apr. 29, 2020 LQFP64 Page 29 of 283 Rev 2.01 M031/M032 SERIES DATASHEET BPWM M031/M032 3.2.8 M032 USB Series (M032Kx) M032 Part Number KG6AE KG8AE KIAAE Flash (KB) 256 256 512 SRAM (KB) 32 64 96 LDROM (KB) 4 4 8 SPROM (Bytes) 2048 System Frequency (MHz) 72 PLL (MHz) 144 I/O 107 32-bit Timer 4 USCI 2 Connectivity UART 6 6 SPI/I2S 1 QSPI 1 I²C/SMBus 2/1 USB FS √ PWM 12 BPWM 12 M031/M032 SERIES DATASHEET PDMA 7 7 EBI √ CRC √ HDIV √ IEC-60730 √ HXT √ LXT √ RTC √ Analog Comparator 2 12-bit SAR ADC 16 Package Apr. 29, 2020 8 9 LQFP128 Page 30 of 283 Rev 2.01 M031/M032 3.2.9 Naming Rule M0 32 K I A A E Core Line Package Flash SRAM Reserve Temperature ® Cortex -M0 31: Base F: TSSOP20 B: 16 KB 0: 2 KB 32: USB (4.4x6.5 mm) C: 32 KB 1: 4 KB E: TSSOP28 D: 64 KB 2: 8/12 KB (4.4x9.7 mm) E: 128 KB 3: 16 KB T: QFN33 G: 256 KB 6: 32 KB (4x4 mm) I: 512 KB 8: 64 KB L: LQFP48 E:-40°C ~ 105°C A: 96 KB (7x7 mm) S: LQFP64 (7x7 mm) K: LQFP128 (14x14 mm) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 31 of 283 Rev 2.01 M031/M032 3.3 M031/M032 Series Feature Comparison Table Section M031xB/C/D/E M031xG/I Sub-section M032xC/D M032xE M032xG/I 6.3.6 SRAM Memory Organization ● ● - 6.3.7 SRAM Memory Organization with parity function - - ● 6.4.4.3 Physical and Virtual Address Concept - - ● 6.4.4.4 APROM Reboot Address Operation Model Selection - - -/● 6.4.4.14 Cache Memory Controller - - ● - - ● - - ● - ● 6.25.5.11 PWM trigger - ● ● 6.25.5.12 BPWM trigger ● - ● 6.25.5.17 Floating Detect Function ● - ● - - ● 6.26.5.7 Calibration function - -/-/-/● ● 6.21.5.3 EBI Data Width Connection - Address Bus and Data Bus Separate Mode - - ● 6.21.5.4 EBI Operating Control - Continuous Data Access Mode - - ● ● - - System Manager FMC 6.4.4.15 Embedded Flash Memory Programming 64-bit Programming and Multi-word Programming 6.4.4.17 Flash All-One Verification ISP Control Register (FMC_ISPCTL) INTEN (FMC_ISPCTL[24]) ADC 6.16.5.2 Operation Modes - Bus Management (SMBus/PMBus Compatiable) M031/M032 SERIES DATASHEET - Device Identification – Slave Address - Bus Protocols - Address Resolution Protocol (ARP) - Received Command and Data acknowledge control 2 IC - Host Notify Protocol - Bus Management Alert - Packet Error Checking - Time-out - Bus Management Time-out: - Bus Clock Low Time-out: - Bus Idle Detection ACMP EBI 6.22.7 Register Description USBD USB Configuration Register (USB_CFGx) DSQSYNC OUT Token Transaction Apr. 29, 2020 Page 32 of 283 Rev 2.01 M031/M032 4 PIN CONFIGURATION Users can find pin configuaration informations in chapter 4 or by using NuTool - PinConfig. The ® NuTool - PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily. 4.1 Pin Configuration 4.1.1 4.1.1.1 M031 Series Pin Diagram M031 Series TSSOP 20-Pin Diagram Corresponding Part Number: M031FB0AE, M031FC1AE 20 PF.1 LDO_CAP 2 19 PF.0 VDD 3 18 nRESET PB.14 4 17 PA.0 PB.13 5 16 PA.1 PB.12 6 15 PA.2 AVDD 7 14 PA.3 PB.5 8 13 PF.2 PB.4 9 12 PF.3 PB.3 10 11 PB.2 M031/M032 SERIES DATASHEET 1 TSSOP20 VSS Figure 4.1-1 M031 Series TSSOP 20-pin Diagram Apr. 29, 2020 Page 33 of 283 Rev 2.01 M031/M032 4.1.1.2 M031 Series TSSOP 28-Pin Diagram Corresponding Part Number: M031EB0AE, M031EC1AE 1 28 PC.0 PA.13 2 27 PC.1 PA.14 3 26 PF.1 PA.15 4 25 PF.0 VSS 5 24 nRESET LDO_CAP 6 23 PA.0 VDD 7 22 PA.1 PB.14 8 21 PA.2 PB.13 9 20 PA.3 PB.12 10 19 PF.2 AVDD 11 18 PF.3 PB.5 12 17 PB.0 PB.4 13 16 PB.1 PB.3 14 15 PB.2 TSSOP28 PA.12 Figure 4.1-2 M031 Series TSSOP 28-pin Diagram M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 34 of 283 Rev 2.01 M031/M032 4.1.1.3 M031 Series QFN 33-Pin Diagram VSS 25 LDO_CAP PA.15 PA.14 PA.13 PA.12 PC.0 PC.1 PF.1 PF.0 24 23 22 21 20 19 18 17 Corresponding Part Number: M031TB0AE, M031TC1AE, M031TD2AE 16 nRESET 26 15 PF.15 VDD 27 14 PA.0 PB.15 28 13 PA.1 PB.14 29 12 PA.2 PB.13 30 11 PA.3 PB.12 31 10 PF.2 9 PF.3 QFN33 33 VSS 3 4 5 6 7 8 PB.2 PB.1 PB.0 PF.5 PF.4 2 PB.4 PB.3 1 32 PB.5 AVDD Top transparent view M031/M032 SERIES DATASHEET Figure 4.1-3 M031 Series QFN 33-pin Diagram Apr. 29, 2020 Page 35 of 283 Rev 2.01 M031/M032 M031 Series LQFP 48-Pin Diagram PA.14 PA.13 PA.12 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 33 32 31 30 29 28 27 26 25 M031LD2AE, 34 M031LC2AE, PA.15 Number: 35 Part 36 Corresponding M031LG8AE M031LE3AE, VSS 37 24 nRESET LDO_CAP 38 23 PF.15 VDD 39 22 PA.0 PC.14 40 21 PA.1 PB.15 41 20 PA.2 PB.14 42 19 PA.3 PB.13 43 18 PA.4 PB.12 44 17 PA.5 AVDD 45 16 PA.6 AVSS 46 15 PA.7 PB.7 47 14 PF.2 PB.6 48 13 PF.3 7 8 9 10 11 12 PB.0 PA.11 PA.10 PA.9 PA.8 PF.5 PF.4 PB.2 6 4 PB.3 5 3 PB.4 PB.1 2 M031/M032 SERIES DATASHEET 1 LQFP48 PB.5 4.1.1.4 M031LG6AE, Figure 4.1-4 M031 Series LQFP 48-pin Diagram Apr. 29, 2020 Page 36 of 283 Rev 2.01 M031/M032 4.1.1.5 M031 Series LQFP 64-Pin Diagram PA.14 PA.13 PA.12 PD.0 PD.1 PD.2 PD.3 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SE3AE, PA.15 M031SD2AE, 47 M031SC2AE, 48 Corresponding Part Number: M031SG8AE, M031SIAAE M031SG6AE, VSS 49 32 nRESET LDO_CAP 50 31 PF.15 VDD 51 30 PA.0 PC.14 52 29 PA.1 PB.15 53 28 PA.2 PB.14 54 27 PA.3 PB.13 55 26 PA.4 PB.12 56 25 PA.5 AVDD 57 24 PD.15 VREF 58 23 VDD AVSS 59 22 VSS PB.11 60 21 PA.6 PB.10 61 20 PA.7 PB.9 62 19 PC.6 PB.8 63 18 PC.7 PB.7 64 17 PF.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.6 PF.14 PF.5 PF.4 PF.3 M031/M032 SERIES DATASHEET PB.6 LQFP64 Figure 4.1-5 M031 Series LQFP 64-pin Diagram Apr. 29, 2020 Page 37 of 283 Rev 2.01 M031/M032 4.1.1.6 M031 Series LQFP 128-Pin Diagram PA.15 PA.14 PA.13 PA.12 PD.13 PD.0 PD.1 PD.2 PD.3 PD.4 PD.5 PD.6 PD.7 PG.15 PG.14 PG.13 PG.12 PG.11 PG.10 PG.9 VDD VSS PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PD.8 PD.9 PF.1 PF.0 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Corresponding Part Number: M031KG6AE, M031KG8AE, M031KIAAE 97 64 nRESET PE.6 98 63 PE.15 PE.5 99 62 PE.14 PE.4 100 61 PF.15 PE.3 101 60 PA.0 PE.2 102 59 PA.1 VSS 103 58 PA.2 VDD 104 57 PA.3 PE.1 105 56 PA.4 PE.0 106 55 PA.5 PH.8 107 54 PD.15 PH.9 108 53 VDD PH.10 109 52 VSS PH.11 110 51 PA.6 PD.14 111 50 PA.7 VSS 112 49 PC.6 LDO_CAP 113 48 PC.7 VDD 114 47 PC.8 PC.14 115 46 PE.13 PB.15 116 45 PE.12 PB.14 117 44 PE.11 PB.13 118 43 PE.10 PB.12 119 42 PE.9 AVDD 120 41 PE.8 VREF 121 40 VDD AVSS 122 39 VSS PB.11 123 38 PF.2 PB.10 124 37 PF.3 PB.9 125 36 PH.7 PB.8 126 35 PH.6 PB.7 127 34 PH.5 PB.6 128 33 PH.4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB.4 PB.3 PB.2 PC.12 PC.11 PC.10 PC.9 PB.1 PB.0 VSS VDD PA.11 PA.10 PA.9 PA.8 PC.13 PD.12 PD.11 PD.10 PG.2 PG.3 PG.4 PF.11 PF.10 PF.9 PF.8 PF.7 PF.6 PF.14 PF.5 PF.4 LQFP128 PB.5 M031/M032 SERIES DATASHEET PE.7 Figure 4.1-6 M031 Series LQFP 128-pin Diagram Apr. 29, 2020 Page 38 of 283 Rev 2.01 M031/M032 4.1.2 M031 Series Multi-function Pin Diagram 4.1.2.1 M031 Series TSSOP 20-Pin Multi-function Pin Diagram Corresponding Part Number: M031FB0AE, M031FC1AE M031FB0AE 1 20 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 2 19 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VDD 3 18 nRESET CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 4 17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 5 16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 6 15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 AVDD 7 14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5 8 13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4 9 12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3 10 11 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3 TSSOP20 VSS LDO_CAP Figure 4.1-7 M031FB0AE Multi-function Pin Diagram Pin M031FB0AE Pin Function VSS 2 LDO_CAP 3 VDD 4 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO 5 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD 6 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD 7 AVDD 8 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 9 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 10 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / INT2 11 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3 12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO 15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 18 nRESET 19 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 20 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK M031/M032 SERIES DATASHEET 1 Table 4.1-1 M031FB0AE Multi-function Pin Table Apr. 29, 2020 Page 39 of 283 Rev 2.01 M031/M032 M031FC1AE 1 20 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 2 19 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VDD 3 18 nRESET CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 4 17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 5 16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 6 15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 AVDD 7 14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5 8 13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4 9 12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3 10 11 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 TSSOP20 VSS LDO_CAP Figure 4.1-8 M031FC1AE Multi-function Pin Diagram Pin M031FC1AE Pin Function M031/M032 SERIES DATASHEET 1 VSS 2 LDO_CAP 3 VDD 4 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO 5 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM2_EXT 6 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM3_EXT 7 AVDD 8 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 9 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 10 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 11 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO 15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 18 nRESET 19 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 20 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK Table 4.1-2 M031FC1AE Multi-function Pin Table Apr. 29, 2020 Page 40 of 283 Rev 2.01 M031/M032 4.1.2.2 M031 Series TSSOP 28-Pin Multi-function Pin Diagram Corresponding Part Number: M031EB0AE, M031EC1AE M031EB0AE 1 28 PC.0 / UART2_RXD / I2C0_SDA 2 27 PC.1 / UART2_TXD / I2C0_SCL UART0_TXD / PA.14 3 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK UART0_RXD / PA.15 4 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VSS 5 24 nRESET LDO_CAP 6 23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 VDD 7 22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 8 21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 9 20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 10 19 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 11 18 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5 12 17 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4 13 16 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0 INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3 14 15 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3 TSSOP28 I2C1_SCL / PA.12 I2C1_SDA / PA.13 Figure 4.1-9 M031EB0AE Multi-function Pin Diagram Pin M031EB0AE Pin Function PA.12 / I2C1_SCL 2 PA.13 / I2C1_SDA 3 PA.14 / UART0_TXD 4 PA.15 / UART0_RXD 5 VSS 6 LDO_CAP 7 VDD 8 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO 9 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD 10 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD 11 AVDD 12 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 13 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 14 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / INT2 15 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3 16 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0 17 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1 18 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 19 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO 21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 Apr. 29, 2020 Page 41 of 283 M031/M032 SERIES DATASHEET 1 Rev 2.01 M031/M032 Pin M031EB0AE Pin Function 22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 PC.1 / UART2_TXD / I2C0_SCL 28 PC.0 / UART2_RXD / I2C0_SDA Table 4.1-3 M031EB0AE Multi-function Pin Table M031EC1AE 1 28 PC.0 / UART2_RXD / I2C0_SDA 2 27 PC.1 / UART2_TXD / I2C0_SCL UART0_TXD / PA.14 3 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK UART0_RXD / PA.15 4 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VSS 5 24 nRESET LDO_CAP 6 23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 VDD 7 22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 8 21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 9 20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 10 19 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 11 18 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5 12 17 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4 13 16 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3 14 15 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 TSSOP28 I2C1_SCL / PA.12 I2C1_SDA / PA.13 Figure 4.1-10 M031EC1AE Multi-function Pin Diagram M031/M032 SERIES DATASHEET Pin M031EC1AE Pin Function 1 PA.12 / I2C1_SCL 2 PA.13 / I2C1_SDA 3 PA.14 / UART0_TXD 4 PA.15 / UART0_RXD 5 VSS 6 LDO_CAP 7 VDD 8 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO 9 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM2_EXT 10 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM3_EXT 11 AVDD 12 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 13 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 14 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 Apr. 29, 2020 Page 42 of 283 Rev 2.01 M031/M032 Pin M031EC1AE Pin Function 15 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 16 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0 17 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1 18 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 19 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO 21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 PC.1 / UART2_TXD / I2C0_SCL 28 PC.0 / UART2_RXD / I2C0_SDA Table 4.1-4 M031EC1AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 43 of 283 Rev 2.01 M031/M032 4.1.2.3 M031 Series QFN 33-Pin Multi-function Pin Diagram Corresponding Part Number: M031TB0AE, M031TC1AE, M031TD2AE PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / UART2_RXD / I2C0_SDA PC.1 / UART2_TXD / I2C0_SCL PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 24 23 22 21 20 19 18 17 M031TB0AE VSS 25 16 nRESET LDO_CAP 26 15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / CLKO / INT4 VDD 27 14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 PWM0_BRAKE1 / TM0_EXT / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15 28 13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 29 12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 30 11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 31 10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT QFN33 33 VSS 4 5 6 7 8 PWM0_BRAKE1 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 ADC0_ST / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 3 INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3 INT3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ADC0_CH2 / PB.2 2 9 PWM0_BRAKE0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 1 M031/M032 SERIES DATASHEET INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5 32 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4 AVDD Top transparent view PF.3 / UART0_TXD / I2C0_SCL / XT1_IN Figure 4.1-11 M031TB0AE Multi-function Pin Diagram Pin M031TB0AE Pin Function 1 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / INT2 Apr. 29, 2020 Page 44 of 283 Rev 2.01 M031/M032 Pin M031TB0AE Pin Function PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3 5 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1 7 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / ADC0_ST 8 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 9 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO 12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / CLKO / INT4 16 nRESET 17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 19 PC.1 / UART2_TXD / I2C0_SCL 20 PC.0 / UART2_RXD / I2C0_SDA 21 PA.12 / I2C1_SCL 22 PA.13 / I2C1_SDA 23 PA.14 / UART0_TXD 24 PA.15 / UART0_RXD 25 VSS 26 LDO_CAP 27 VDD 28 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT / PWM0_BRAKE1 29 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO 30 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD 31 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD 32 AVDD M031/M032 SERIES DATASHEET 4 Table 4.1-5 M031TB0AE Multi-function Pin Table Apr. 29, 2020 Page 45 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / UART2_RXD / I2C0_SDA PC.1 / UART2_TXD / I2C0_SCL PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 24 23 22 21 20 19 18 17 M031TC1AE VSS 25 16 nRESET LDO_CAP 26 15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 27 14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 PWM0_BRAKE1 / TM0_EXT / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15 28 13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 29 12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 30 11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 31 10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 32 Top transparent view QFN33 4 5 6 7 8 PWM0_BRAKE1 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 3 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ADC0_CH2 / PB.2 2 9 PWM0_BRAKE0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4 33 VSS PF.3 / UART0_TXD / I2C0_SCL / XT1_IN Figure 4.1-12 M031TC1AE Multi-function Pin Diagram Pin M031TC1AE Pin Function 1 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 Apr. 29, 2020 Page 46 of 283 Rev 2.01 M031/M032 Pin M031TC1AE Pin Function PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1 7 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 8 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 9 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO 12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 16 nRESET 17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 19 PC.1 / UART2_TXD / I2C0_SCL 20 PC.0 / UART2_RXD / I2C0_SDA 21 PA.12 / I2C1_SCL 22 PA.13 / I2C1_SDA 23 PA.14 / UART0_TXD 24 PA.15 / UART0_RXD 25 VSS 26 LDO_CAP 27 VDD 28 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT / PWM0_BRAKE1 29 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO 30 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM2_EXT 31 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM3_EXT 32 AVDD M031/M032 SERIES DATASHEET 5 Table 4.1-6 M031TC1AE Multi-function Pin Table Apr. 29, 2020 Page 47 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 24 23 22 21 20 19 18 17 M031TD2AE VSS 25 16 nRESET LDO_CAP 26 15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 27 14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 28 13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 29 12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 30 11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 31 10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 32 Top transparent view QFN33 2 3 4 5 6 7 8 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 9 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 1 33 VSS PF.3 / UART0_TXD / I2C0_SCL / XT1_IN Figure 4.1-13 M031TD2AE Multi-function Pin Diagram Pin M031TD2AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 5 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 Apr. 29, 2020 Page 48 of 283 Rev 2.01 M031/M032 Pin M031TD2AE Pin Function PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 8 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 9 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 16 nRESET 17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 19 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 20 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 21 PA.12 / I2C1_SCL 22 PA.13 / I2C1_SDA 23 PA.14 / UART0_TXD 24 PA.15 / UART0_RXD 25 VSS 26 LDO_CAP 27 VDD 28 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 29 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 30 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 31 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 32 AVDD Table 4.1-7 M031TD2AE Multi-function Pin Table Apr. 29, 2020 Page 49 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 7 M031/M032 4.1.2.4 M031 Series LQFP 48-Pin Multi-function Pin Diagram Corresponding M031LG8AE Part Number: M031LC2AE, M031LD2AE, M031LE3AE, M031LG6AE, PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / UART2_nCTS / PWM1_CH3 PC.3 / UART2_nRTS / PWM1_CH2 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M031LC2AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 40 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 41 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 42 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 45 16 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7 47 14 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6 48 13 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 8 9 TM1_EXT / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / UART1_TXD / USCI0_DAT1 / PA.9 12 7 TM0_EXT / USCI0_CLK / ACMP0_P0 / PA.11 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 6 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 11 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 4 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 10 3 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / PA.8 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-14 M031LC2AE Multi-function Pin Diagram Pin M031LC2AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 Apr. 29, 2020 Page 50 of 283 Rev 2.01 M031/M032 Pin M031LC2AE Pin Function PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 5 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT 8 PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT 9 PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT 10 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 13 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 14 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 15 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 28 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 29 PC.3 / UART2_nRTS / PWM1_CH2 30 PC.2 / UART2_nCTS / PWM1_CH3 31 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 32 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 PA.12 / I2C1_SCL 34 PA.13 / I2C1_SDA 35 PA.14 / UART0_TXD 36 PA.15 / UART0_RXD 37 VSS Apr. 29, 2020 Page 51 of 283 M031/M032 SERIES DATASHEET 4 Rev 2.01 M031/M032 Pin M031LC2AE Pin Function 38 LDO_CAP 39 VDD 40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-8 M031LC2AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 52 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / UART2_nCTS / PWM1_CH3 PC.3 / UART2_nRTS / PWM1_CH2 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M031LD2AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 40 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 41 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 42 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 45 16 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7 47 14 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6 48 13 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 8 9 TM1_EXT / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / UART1_TXD / USCI0_DAT1 / PA.9 12 7 TM0_EXT / USCI0_CLK / ACMP0_P0 / PA.11 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 6 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 11 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 4 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 10 3 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / PA.8 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-15 M031LD2AE Multi-function Pin Diagram Pin M031LD2AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 5 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 Apr. 29, 2020 Page 53 of 283 Rev 2.01 M031/M032 Pin M031LD2AE Pin Function M031/M032 SERIES DATASHEET 7 PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT 8 PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT 9 PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT 10 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 13 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 14 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 15 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 28 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 29 PC.3 / UART2_nRTS / PWM1_CH2 30 PC.2 / UART2_nCTS / PWM1_CH3 31 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 32 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 PA.12 / I2C1_SCL 34 PA.13 / I2C1_SDA 35 PA.14 / UART0_TXD 36 PA.15 / UART0_RXD 37 VSS 38 LDO_CAP 39 VDD 40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 Apr. 29, 2020 Page 54 of 283 Rev 2.01 M031/M032 Pin M031LD2AE Pin Function 41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-9 M031LD2AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 55 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M031LE3AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 40 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 41 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 42 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 45 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / EBI_nCS0 / UART1_TXD / EBI_nWRL / ADC0_CH7 / PB.7 47 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / EBI_nCS1 / UART1_RXD / EBI_nWRH / ADC0_CH6 / PB.6 48 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN 10 11 12 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 9 TM2_EXT / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 6 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 8 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 7 4 TM0_EXT / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 3 TM1_EXT / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 2 1 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-16 M031LE3AE Multi-function Pin Diagram Apr. 29, 2020 Page 56 of 283 Rev 2.01 M031/M032 Pin M031LE3AE Pin Function PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 5 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT 8 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT 9 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT 10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 28 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 29 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 30 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 31 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 32 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 PA.12 / I2C1_SCL Apr. 29, 2020 Page 57 of 283 M031/M032 SERIES DATASHEET 1 Rev 2.01 M031/M032 Pin M031LE3AE Pin Function 34 PA.13 / I2C1_SDA 35 PA.14 / UART0_TXD 36 PA.15 / UART0_RXD 37 VSS 38 LDO_CAP 39 VDD 40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 41 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-10 M031LE3AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 58 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M031LG6AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 40 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 41 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 42 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 45 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 47 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 48 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 12 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 8 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 11 7 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 6 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 10 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 9 4 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 3 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-17 M031LG6AE Multi-function Pin Diagram Pin M031LG6AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / Apr. 29, 2020 Page 59 of 283 Rev 2.01 M031/M032 Pin M031LG6AE Pin Function PWM0_CH3 / TM3 / INT3 M031/M032 SERIES DATASHEET 5 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 8 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 9 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 34 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 35 PA.14 / UART0_TXD / BPWM1_CH4 Apr. 29, 2020 Page 60 of 283 Rev 2.01 M031/M032 Pin M031LG6AE Pin Function 36 PA.15 / UART0_RXD / BPWM1_CH5 37 VSS 38 LDO_CAP 39 VDD 40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 41 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-11 M031LG6AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 61 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M031LG8AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 40 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 41 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 42 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 45 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 LQFP48 11 12 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 10 8 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 9 7 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 6 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 5 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 M031/M032 SERIES DATASHEET PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 4 13 3 48 2 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 1 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 14 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 15 47 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 46 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 Figure 4.1-18 M031LG8AE Multi-function Pin Diagram Pin M031LG8AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 Apr. 29, 2020 Page 62 of 283 Rev 2.01 M031/M032 Pin M031LG8AE Pin Function PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 8 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 9 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 34 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 35 PA.14 / UART0_TXD / BPWM1_CH4 36 PA.15 / UART0_RXD / BPWM1_CH5 Apr. 29, 2020 Page 63 of 283 M031/M032 SERIES DATASHEET 5 Rev 2.01 M031/M032 Pin M031LG8AE Pin Function 37 VSS 38 LDO_CAP 39 VDD 40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 41 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-12 M031LG8AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 64 of 283 Rev 2.01 M031/M032 4.1.2.5 M031 Series LQFP 64-Pin Multi-function Pin Diagram Corresponding Part Number: M031SG8AE, M031SIAAE M031SC2AE, M031SD2AE, M031SE3AE, M031SG6AE, PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PD.0 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / USCI0_DAT0 / SPI0_MISO PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / USCI0_CTL1 / SPI0_SS / UART0_TXD PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / UART2_nCTS / PWM1_CH3 PC.3 / UART2_nRTS / PWM1_CH2 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SC2AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 52 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 53 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 54 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / ADC0_CH11 / PB.11 60 21 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 I2C1_SDA / UART0_nRTS / ADC0_CH10 / PB.10 61 20 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 UART1_nCTS / UART0_TXD / ADC0_CH9 / PB.9 62 19 PC.6 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 UART1_nRTS / UART0_RXD / ADC0_CH8 / PB.8 63 18 PC.7 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7 64 17 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 5 6 7 8 9 10 11 12 13 14 15 16 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 TM0_EXT / USCI0_CLK / ACMP0_P0 / PA.11 TM1_EXT / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / UART1_TXD / USCI0_DAT1 / PA.9 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / PA.8 SPI0_MOSI / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 XT1_IN / I2C0_SCL / UART0_TXD / PF.3 4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 3 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-19 M031SC2AE Multi-function Pin Diagram Pin M031SC2AE Pin Function 1 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 65 of 283 Rev 2.01 M031/M032 Pin M031SC2AE Pin Function M031/M032 SERIES DATASHEET 4 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT 9 PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT 10 PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT 11 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 12 PF.6 / SPI0_MOSI 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 16 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 17 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 18 PC.7 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 19 PC.6 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 20 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 35 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 36 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 37 PC.3 / UART2_nRTS / PWM1_CH2 Apr. 29, 2020 Page 66 of 283 Rev 2.01 M031/M032 M031SC2AE Pin Function 38 PC.2 / UART2_nCTS / PWM1_CH3 39 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 40 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / USCI0_CTL1 / SPI0_SS / UART0_TXD 42 PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD 43 PD.1 / USCI0_DAT0 / SPI0_MISO 44 PD.0 / USCI0_CLK / SPI0_MOSI / TM2 45 PA.12 / I2C1_SCL 46 PA.13 / I2C1_SDA 47 PA.14 / UART0_TXD 48 PA.15 / UART0_RXD 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 53 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK 61 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA 62 PB.9 / ADC0_CH9 / UART0_TXD / UART1_nCTS 63 PB.8 / ADC0_CH8 / UART0_RXD / UART1_nRTS 64 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-13 M031SC2AE Multi-function Pin Table Apr. 29, 2020 Page 67 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PD.0 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / USCI0_DAT0 / SPI0_MISO PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / USCI0_CTL1 / SPI0_SS / UART0_TXD PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / UART2_nCTS / PWM1_CH3 PC.3 / UART2_nRTS / PWM1_CH2 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SD2AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 52 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 53 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 54 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD LQFP64 8 9 10 11 12 13 14 15 16 TM1_EXT / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / UART1_TXD / USCI0_DAT1 / PA.9 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / PA.8 SPI0_MOSI / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 XT1_IN / I2C0_SCL / UART0_TXD / PF.3 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET TM0_EXT / USCI0_CLK / ACMP0_P0 / PA.11 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 PC.7 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 17 7 18 64 6 63 5 PC.6 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 UART1_nRTS / UART0_RXD / ADC0_CH8 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 19 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 62 4 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 UART1_nCTS / UART0_TXD / ADC0_CH9 / PB.9 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 20 3 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 I2C1_SDA / UART0_nRTS / ADC0_CH10 / PB.10 61 2 VSS 21 1 22 60 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 59 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 AVSS SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / ADC0_CH11 / PB.11 Figure 4.1-20 M031SD2AE Multi-function Pin Diagram Pin M031SD2AE Pin Function 1 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 4 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 Apr. 29, 2020 Page 68 of 283 Rev 2.01 M031/M032 Pin M031SD2AE Pin Function PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT 9 PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT 10 PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT 11 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 12 PF.6 / SPI0_MOSI 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 16 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN 17 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT 18 PC.7 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 19 PC.6 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 20 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 35 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 36 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 37 PC.3 / UART2_nRTS / PWM1_CH2 38 PC.2 / UART2_nCTS / PWM1_CH3 Apr. 29, 2020 Page 69 of 283 M031/M032 SERIES DATASHEET 5 Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M031SD2AE Pin Function 39 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 40 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / USCI0_CTL1 / SPI0_SS / UART0_TXD 42 PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD 43 PD.1 / USCI0_DAT0 / SPI0_MISO 44 PD.0 / USCI0_CLK / SPI0_MOSI / TM2 45 PA.12 / I2C1_SCL 46 PA.13 / I2C1_SDA 47 PA.14 / UART0_TXD 48 PA.15 / UART0_RXD 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 53 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK 61 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA 62 PB.9 / ADC0_CH9 / UART0_TXD / UART1_nCTS 63 PB.8 / ADC0_CH8 / UART0_RXD / UART1_nRTS 64 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-14 M031SD2AE Multi-function Pin Table Apr. 29, 2020 Page 70 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART0_TXD PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SE3AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 I2C1_SDA / UART0_nRTS / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 UART1_nCTS / UART0_TXD / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 UART1_nRTS / UART0_RXD / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / EBI_nCS0 / UART1_TXD / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT 10 11 12 13 14 15 16 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 TM2_EXT / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 7 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 9 6 8 5 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 TM0_EXT / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 4 TM1_EXT / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 3 1 2 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / EBI_nCS1 / UART1_RXD / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 LQFP64 Figure 4.1-21 M031SE3AE Multi-function Pin Diagram Pin M031SE3AE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 4 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 Apr. 29, 2020 Page 71 of 283 Rev 2.01 M031/M032 Pin M031SE3AE Pin Function M031/M032 SERIES DATASHEET 6 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT 18 PC.7 / EBI_AD9 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 35 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 36 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 37 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 38 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 39 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O Apr. 29, 2020 Page 72 of 283 Rev 2.01 M031/M032 M031SE3AE Pin Function 40 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 45 PA.12 / I2C1_SCL 46 PA.13 / I2C1_SDA 47 PA.14 / UART0_TXD 48 PA.15 / UART0_RXD 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK 61 PB.10 / ADC0_CH10 / EBI_ADR17 / UART0_nRTS / I2C1_SDA 62 PB.9 / ADC0_CH9 / EBI_ADR18 / UART0_TXD / UART1_nCTS 63 PB.8 / ADC0_CH8 / EBI_ADR19 / UART0_RXD / UART1_nRTS 64 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-15 M031SE3AE Multi-function Pin Table Apr. 29, 2020 Page 73 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SG6AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-22 M031SG6AE Multi-function Pin Diagram Pin M031SG6AE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 74 of 283 Rev 2.01 M031/M032 Pin M031SG6AE Pin Function PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK Apr. 29, 2020 Page 75 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 4 M031/M032 M031/M032 SERIES DATASHEET Pin M031SG6AE Pin Function 35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 45 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 46 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 47 PA.14 / UART0_TXD / BPWM1_CH4 48 PA.15 / UART0_RXD / BPWM1_CH5 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 64 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-16 M031SG6AE Multi-function Pin Table Apr. 29, 2020 Page 76 of 283 Rev 2.01 M031/M032 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SG8AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-23 M031SG8AE Multi-function Pin Diagram Pin M031SG8AE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 77 of 283 Rev 2.01 M031/M032 Pin M031SG8AE Pin Function M031/M032 SERIES DATASHEET 4 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK Apr. 29, 2020 Page 78 of 283 Rev 2.01 M031/M032 M031SG8AE Pin Function 35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 45 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 46 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 47 PA.14 / UART0_TXD / BPWM1_CH4 48 PA.15 / UART0_RXD / BPWM1_CH5 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 64 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-17 M031SG8AE Multi-function Pin Table Apr. 29, 2020 Page 79 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M031SIAAE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 BPWM1_CH2 / UART7_TXD / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 BPWM1_CH3 / UART7_RXD / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / UART6_TXD / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / UART6_RXD / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART7_TXD / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART7_RXD / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-24 M031SIAAE Multi-function Pin Diagram Pin M031SIAAE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 80 of 283 Rev 2.01 M031/M032 Pin M031SIAAE Pin Function PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK Apr. 29, 2020 Page 81 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 4 M031/M032 M031/M032 SERIES DATASHEET Pin M031SIAAE Pin Function 35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 45 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 46 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 47 PA.14 / UART0_TXD / BPWM1_CH4 48 PA.15 / UART0_RXD / BPWM1_CH5 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2 63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3 64 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-18 M031SIAAE Multi-function Pin Table Apr. 29, 2020 Page 82 of 283 Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 83 of 283 Rev 2.01 M031/M032 4.1.2.6 M031 Series LQFP 128-Pin Multi-function Pin Diagram Corresponding Part Number: M031KG6AE, M031KG8AE, M031KIAAE BPWM0_CH5 / PWM0_CH0 / UART5_TXD / PE.7 97 BPWM0_CH4 / PWM0_CH1 / UART5_RXD / USCI0_CTL0 / PE.6 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PD.8 / EBI_AD6 / UART2_nRTS PD.9 / EBI_AD7 / UART2_nCTS PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 65 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 66 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 VSS 72 67 VDD 73 68 PG.9 / EBI_AD0 / BPWM0_CH5 74 69 PG.10 / EBI_AD1 / BPWM0_CH4 75 70 PG.11 / EBI_AD2 / BPWM0_CH3 76 71 PG.12 / EBI_AD3 / BPWM0_CH2 PG.15 / CLKO / ADC0_ST 77 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK PG.14 / EBI_AD5 / BPWM0_CH0 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 PG.13 / EBI_AD4 / BPWM0_CH1 PD.5 / I2C1_SCL / USCI1_DAT0 83 78 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 84 79 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 85 80 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 86 81 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 87 82 PD.13 / EBI_AD10 / SPI0_I2SMCLK PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 88 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 89 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 93 90 PA.14 / UART0_TXD / BPWM1_CH4 94 91 PA.15 / UART0_RXD / BPWM1_CH5 95 92 96 M031KG6AE 64 nRESET 98 63 PE.15 / EBI_AD9 / UART2_RXD BPWM0_CH3 / PWM0_CH2 / USCI0_CTL1 / EBI_nRD / PE.5 99 62 PE.14 / EBI_AD8 / UART2_TXD BPWM0_CH2 / PWM0_CH3 / USCI0_DAT1 / EBI_nWR / PE.4 100 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / EBI_MCLK / PE.3 101 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 BPWM0_CH0 / PWM0_CH5 / USCI0_CLK / EBI_ALE / PE.2 102 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 VSS 103 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 VDD 104 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 UART4_nCTS / I2C1_SCL / UART3_TXD / QSPI0_MISO0 / EBI_AD10 / PE.1 105 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 UART4_nRTS / I2C1_SDA / UART3_RXD / QSPI0_MOSI0 / EBI_AD11 / PE.0 106 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 UART1_TXD / UART3_nRTS / QSPI0_CLK / EBI_AD12 / PH.8 107 54 PD.15 / PWM0_CH5 / TM3 / INT1 UART1_RXD / UART3_nCTS / QSPI0_SS / EBI_AD13 / PH.9 108 53 VDD UART0_TXD / UART4_TXD / QSPI0_MISO1 / EBI_AD14 / PH.10 109 52 VSS PWM0_CH5 / UART0_RXD / UART4_RXD / QSPI0_MOSI1 / EBI_AD15 / PH.11 110 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PWM0_CH4 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_nCS0 / PD.14 111 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 VSS 112 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 LDO_CAP 113 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 VDD 114 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 115 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 116 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 117 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 118 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 119 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 AVDD 120 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 VREF 121 40 VDD AVSS 122 39 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 123 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 124 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 125 36 PH.7 / EBI_ADR0 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 126 35 PH.6 / EBI_ADR1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 127 34 PH.5 / EBI_ADR2 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 128 33 PH.4 / EBI_ADR3 30 31 32 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 25 UART5_RXD / SPI0_I2SMCLK / EBI_ADR15 / PF.10 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 24 TM3 / UART5_TXD / EBI_ADR14 / PF.11 29 23 TM2 / EBI_ADR13 / PG.4 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 22 TM1 / I2C1_SDA / I2C0_SMBSUS / EBI_ADR12 / PG.3 28 21 TM0 / I2C1_SCL / I2C0_SMBAL / EBI_ADR11 / PG.2 UART4_TXD / SPI0_MISO / EBI_ADR18 / PF.7 20 UART1_RXD / PD.10 27 19 UART1_TXD / EBI_nCS1 / PD.11 UART5_nRTS / SPI0_SS / EBI_ADR16 / PF.9 18 INT5 / ADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART5_nCTS / SPI0_CLK / EBI_ADR17 / PF.8 17 ADC0_ST / CLKO / BPWM0_CH4 / UART2_TXD / USCI0_CTL0 / EBI_ADR10 / PC.13 26 16 14 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 15 13 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 VDD INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 11 9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 VSS 8 PWM1_CH3 / UART3_RXD / EBI_ADR7 / PC.9 10 7 PWM1_CH2 / UART3_TXD / EBI_ADR6 / PC.10 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 6 ACMP0_O / PWM1_CH0 / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 4 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 3 5 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP128 Figure 4.1-25 M031KG6AE Multi-function Pin Diagram Pin M031KG6AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 84 of 283 Rev 2.01 M031/M032 Pin M031KG6AE Pin Function PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 5 PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O 6 PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O 7 PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2 8 PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3 9 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 10 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 11 VSS 12 VDD 13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST 18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5 19 PD.11 / EBI_nCS1 / UART1_TXD 20 PD.10 / UART1_RXD 21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0 22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1 23 PG.4 / EBI_ADR13 / TM2 24 PF.11 / EBI_ADR14 / UART5_TXD / TM3 25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD 26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS 27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS 28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD 29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 33 PH.4 / EBI_ADR3 34 PH.5 / EBI_ADR2 Apr. 29, 2020 Page 85 of 283 M031/M032 SERIES DATASHEET 3 Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M031KG6AE Pin Function 35 PH.6 / EBI_ADR1 36 PH.7 / EBI_ADR0 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 39 VSS 40 VDD 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 52 VSS 53 VDD 54 PD.15 / PWM0_CH5 / TM3 / INT1 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 62 PE.14 / EBI_AD8 / UART2_TXD 63 PE.15 / EBI_AD9 / UART2_RXD 64 nRESET 65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 67 PD.9 / EBI_AD7 / UART2_nCTS Apr. 29, 2020 Page 86 of 283 Rev 2.01 M031/M032 M031KG6AE Pin Function 68 PD.8 / EBI_AD6 / UART2_nRTS 69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 75 VSS 76 VDD 77 PG.9 / EBI_AD0 / BPWM0_CH5 78 PG.10 / EBI_AD1 / BPWM0_CH4 79 PG.11 / EBI_AD2 / BPWM0_CH3 80 PG.12 / EBI_AD3 / BPWM0_CH2 81 PG.13 / EBI_AD4 / BPWM0_CH1 82 PG.14 / EBI_AD5 / BPWM0_CH0 83 PG.15 / CLKO / ADC0_ST 84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 86 PD.5 / I2C1_SCL / USCI1_DAT0 87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 92 PD.13 / EBI_AD10 / SPI0_I2SMCLK 93 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 94 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 95 PA.14 / UART0_TXD / BPWM1_CH4 96 PA.15 / UART0_RXD / BPWM1_CH5 97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5 98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4 99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3 100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2 101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1 Apr. 29, 2020 Page 87 of 283 M031/M032 SERIES DATASHEET Pin Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M031KG6AE Pin Function 102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0 103 VSS 104 VDD 105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS 106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS 107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD 108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD 109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD 110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5 111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4 112 VSS 113 LDO_CAP 114 VDD 115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 116 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 117 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 118 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 119 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 120 AVDD 121 VREF 122 AVSS 123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 127 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 128 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-19 M031KG6AE Multi-function Pin Table Apr. 29, 2020 Page 88 of 283 Rev 2.01 M031/M032 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 65 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 66 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 VSS 72 67 VDD 73 68 PG.9 / EBI_AD0 / BPWM0_CH5 74 69 PG.10 / EBI_AD1 / BPWM0_CH4 75 70 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3 76 71 PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2 PG.15 / CLKO / ADC0_ST 77 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1 PD.5 / I2C1_SCL / USCI1_DAT0 83 78 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 84 79 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 85 80 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 86 81 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 87 82 PD.13 / EBI_AD10 / SPI0_I2SMCLK PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 88 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 89 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 93 90 PA.14 / UART0_TXD / BPWM1_CH4 94 91 PA.15 / UART0_RXD / BPWM1_CH5 95 92 96 M031KG8AE BPWM0_CH5 / PWM0_CH0 / UART5_TXD / PE.7 97 64 nRESET BPWM0_CH4 / PWM0_CH1 / UART5_RXD / USCI0_CTL0 / PE.6 98 63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD BPWM0_CH3 / PWM0_CH2 / UART7_nRTS / UART6_TXD / USCI0_CTL1 / EBI_nRD / PE.5 99 62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD BPWM0_CH2 / PWM0_CH3 / UART7_nCTS / UART6_RXD / USCI0_DAT1 / EBI_nWR / PE.4 100 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 BPWM0_CH1 / PWM0_CH4 / UART7_TXD / UART6_nRTS / USCI0_DAT0 / EBI_MCLK / PE.3 101 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 BPWM0_CH0 / PWM0_CH5 / UART7_RXD / UART6_nCTS / USCI0_CLK / EBI_ALE / PE.2 102 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 VSS 103 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 VDD 104 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 UART4_nCTS / I2C1_SCL / UART3_TXD / QSPI0_MISO0 / EBI_AD10 / PE.1 105 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 UART4_nRTS / I2C1_SDA / UART3_RXD / QSPI0_MOSI0 / EBI_AD11 / PE.0 106 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 UART1_TXD / UART3_nRTS / QSPI0_CLK / EBI_AD12 / PH.8 107 54 PD.15 / PWM0_CH5 / TM3 / INT1 UART1_RXD / UART3_nCTS / QSPI0_SS / EBI_AD13 / PH.9 108 53 VDD UART0_TXD / UART4_TXD / QSPI0_MISO1 / EBI_AD14 / PH.10 109 52 VSS PWM0_CH5 / UART0_RXD / UART4_RXD / QSPI0_MOSI1 / EBI_AD15 / PH.11 110 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PWM0_CH4 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_nCS0 / PD.14 111 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 VSS 112 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 LDO_CAP 113 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 VDD 114 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 115 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 116 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 117 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 118 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 119 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 AVDD 120 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 VREF 121 40 VDD AVSS 122 39 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 123 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 124 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 BPWM1_CH2 / UART7_TXD / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 125 36 PH.7 / EBI_ADR0 / UART7_RXD BPWM1_CH3 / UART7_RXD / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 126 35 PH.6 / EBI_ADR1 / UART7_TXD ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 127 34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 128 33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD 30 31 32 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 25 UART5_RXD / SPI0_I2SMCLK / EBI_ADR15 / PF.10 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 24 TM3 / UART5_TXD / EBI_ADR14 / PF.11 29 23 TM2 / EBI_ADR13 / PG.4 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 22 TM1 / I2C1_SDA / I2C0_SMBSUS / EBI_ADR12 / PG.3 28 21 TM0 / I2C1_SCL / I2C0_SMBAL / EBI_ADR11 / PG.2 UART4_TXD / SPI0_MISO / EBI_ADR18 / PF.7 20 UART1_RXD / PD.10 27 19 UART1_TXD / EBI_nCS1 / PD.11 UART5_nRTS / SPI0_SS / EBI_ADR16 / PF.9 18 INT5 / ADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART5_nCTS / SPI0_CLK / EBI_ADR17 / PF.8 17 ADC0_ST / CLKO / BPWM0_CH4 / UART2_TXD / USCI0_CTL0 / EBI_ADR10 / PC.13 26 16 14 TM1_EXT / BPWM0_CH1 / UART6_RXD / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 15 13 TM0_EXT / BPWM0_CH0 / UART6_TXD / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM2_EXT / BPWM0_CH2 / UART7_TXD / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 VDD INT4 / TM3_EXT / BPWM0_CH3 / UART7_RXD / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 11 9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 VSS 8 PWM1_CH3 / UART3_RXD / UART6_nCTS / EBI_ADR7 / PC.9 10 7 PWM1_CH2 / UART3_TXD / UART6_nRTS / EBI_ADR6 / PC.10 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 6 ACMP0_O / PWM1_CH0 / UART6_TXD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 4 ACMP1_O / PWM1_CH1 / UART6_RXD / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 3 5 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP128 Figure 4.1-26 M031KG8AE Multi-function Pin Diagram Pin M031KG8AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / Apr. 29, 2020 Page 89 of 283 Rev 2.01 M031/M032 Pin M031KG8AE Pin Function PWM0_CH3 / TM3 / INT3 M031/M032 SERIES DATASHEET 5 PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O 6 PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O 7 PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2 8 PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3 9 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 10 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 11 VSS 12 VDD 13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST 18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5 19 PD.11 / EBI_nCS1 / UART1_TXD 20 PD.10 / UART1_RXD 21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0 22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1 23 PG.4 / EBI_ADR13 / TM2 24 PF.11 / EBI_ADR14 / UART5_TXD / TM3 25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD 26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS 27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS 28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD 29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 33 PH.4 / EBI_ADR3 34 PH.5 / EBI_ADR2 35 PH.6 / EBI_ADR1 36 PH.7 / EBI_ADR0 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 Apr. 29, 2020 Page 90 of 283 Rev 2.01 M031/M032 M031KG8AE Pin Function 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 39 VSS 40 VDD 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 52 VSS 53 VDD 54 PD.15 / PWM0_CH5 / TM3 / INT1 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 62 PE.14 / EBI_AD8 / UART2_TXD 63 PE.15 / EBI_AD9 / UART2_RXD 64 nRESET 65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 67 PD.9 / EBI_AD7 / UART2_nCTS 68 PD.8 / EBI_AD6 / UART2_nRTS 69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 Apr. 29, 2020 Page 91 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 M031/M032 SERIES DATASHEET Pin M031KG8AE Pin Function 71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 75 VSS 76 VDD 77 PG.9 / EBI_AD0 / BPWM0_CH5 78 PG.10 / EBI_AD1 / BPWM0_CH4 79 PG.11 / EBI_AD2 / BPWM0_CH3 80 PG.12 / EBI_AD3 / BPWM0_CH2 81 PG.13 / EBI_AD4 / BPWM0_CH1 82 PG.14 / EBI_AD5 / BPWM0_CH0 83 PG.15 / CLKO / ADC0_ST 84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 86 PD.5 / I2C1_SCL / USCI1_DAT0 87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 92 PD.13 / EBI_AD10 / SPI0_I2SMCLK 93 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 94 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 95 PA.14 / UART0_TXD / BPWM1_CH4 96 PA.15 / UART0_RXD / BPWM1_CH5 97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5 98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4 99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3 100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2 101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1 102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0 103 VSS 104 VDD Apr. 29, 2020 Page 92 of 283 Rev 2.01 M031/M032 M031KG8AE Pin Function 105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS 106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS 107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD 108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD 109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD 110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5 111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4 112 VSS 113 LDO_CAP 114 VDD 115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 116 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 117 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 118 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 119 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 120 AVDD 121 VREF 122 AVSS 123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 127 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 128 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-20 M031KG8AE Multi-function Pin Table Apr. 29, 2020 Page 93 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 65 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 66 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 VSS 72 67 VDD 73 68 PG.9 / EBI_AD0 / BPWM0_CH5 74 69 PG.10 / EBI_AD1 / BPWM0_CH4 75 70 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3 76 71 PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2 PG.15 / CLKO / ADC0_ST 77 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1 PD.5 / I2C1_SCL / USCI1_DAT0 83 78 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 84 79 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 85 80 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 86 81 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 87 82 PD.13 / EBI_AD10 / SPI0_I2SMCLK PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 88 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 89 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 93 90 PA.14 / UART0_TXD / BPWM1_CH4 94 91 PA.15 / UART0_RXD / BPWM1_CH5 95 92 96 M031KIAAE BPWM0_CH5 / PWM0_CH0 / UART5_TXD / PE.7 97 64 nRESET BPWM0_CH4 / PWM0_CH1 / UART5_RXD / USCI0_CTL0 / PE.6 98 63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD BPWM0_CH3 / PWM0_CH2 / UART7_nRTS / UART6_TXD / USCI0_CTL1 / EBI_nRD / PE.5 99 62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD BPWM0_CH2 / PWM0_CH3 / UART7_nCTS / UART6_RXD / USCI0_DAT1 / EBI_nWR / PE.4 100 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 BPWM0_CH1 / PWM0_CH4 / UART7_TXD / UART6_nRTS / USCI0_DAT0 / EBI_MCLK / PE.3 101 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 BPWM0_CH0 / PWM0_CH5 / UART7_RXD / UART6_nCTS / USCI0_CLK / EBI_ALE / PE.2 102 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 VSS 103 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 VDD 104 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 UART4_nCTS / I2C1_SCL / UART3_TXD / QSPI0_MISO0 / EBI_AD10 / PE.1 105 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 UART4_nRTS / I2C1_SDA / UART3_RXD / QSPI0_MOSI0 / EBI_AD11 / PE.0 106 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 UART1_TXD / UART3_nRTS / QSPI0_CLK / EBI_AD12 / PH.8 107 54 PD.15 / PWM0_CH5 / TM3 / INT1 UART1_RXD / UART3_nCTS / QSPI0_SS / EBI_AD13 / PH.9 108 53 VDD UART0_TXD / UART4_TXD / QSPI0_MISO1 / EBI_AD14 / PH.10 109 52 VSS PWM0_CH5 / UART0_RXD / UART4_RXD / QSPI0_MOSI1 / EBI_AD15 / PH.11 110 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PWM0_CH4 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_nCS0 / PD.14 111 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 VSS 112 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 LDO_CAP 113 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 VDD 114 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 115 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 116 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 117 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 118 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 119 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 AVDD 120 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 VREF 121 40 VDD AVSS 122 39 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 123 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 124 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 BPWM1_CH2 / UART7_TXD / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 125 36 PH.7 / EBI_ADR0 / UART7_RXD BPWM1_CH3 / UART7_RXD / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 126 35 PH.6 / EBI_ADR1 / UART7_TXD ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 127 34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 128 33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD 30 31 32 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 25 UART5_RXD / SPI0_I2SMCLK / EBI_ADR15 / PF.10 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 24 TM3 / UART5_TXD / EBI_ADR14 / PF.11 29 23 TM2 / EBI_ADR13 / PG.4 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 22 TM1 / I2C1_SDA / I2C0_SMBSUS / EBI_ADR12 / PG.3 28 21 TM0 / I2C1_SCL / I2C0_SMBAL / EBI_ADR11 / PG.2 UART4_TXD / SPI0_MISO / EBI_ADR18 / PF.7 20 UART1_RXD / PD.10 27 19 UART1_TXD / EBI_nCS1 / PD.11 UART5_nRTS / SPI0_SS / EBI_ADR16 / PF.9 18 INT5 / ADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART5_nCTS / SPI0_CLK / EBI_ADR17 / PF.8 17 ADC0_ST / CLKO / BPWM0_CH4 / UART2_TXD / USCI0_CTL0 / EBI_ADR10 / PC.13 26 16 14 TM1_EXT / BPWM0_CH1 / UART6_RXD / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 15 13 TM0_EXT / BPWM0_CH0 / UART6_TXD / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM2_EXT / BPWM0_CH2 / UART7_TXD / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 VDD INT4 / TM3_EXT / BPWM0_CH3 / UART7_RXD / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 11 9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 VSS 8 PWM1_CH3 / UART3_RXD / UART6_nCTS / EBI_ADR7 / PC.9 10 7 PWM1_CH2 / UART3_TXD / UART6_nRTS / EBI_ADR6 / PC.10 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 6 ACMP0_O / PWM1_CH0 / UART6_TXD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 4 ACMP1_O / PWM1_CH1 / UART6_RXD / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 3 5 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP128 Figure 4.1-27 M031KIAAE Multi-function Pin Diagram Pin M031KIAAE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / Apr. 29, 2020 Page 94 of 283 Rev 2.01 M031/M032 Pin M031KIAAE Pin Function PWM0_CH3 / TM3 / INT3 PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / UART6_TXD / PWM1_CH0 / ACMP0_O 6 PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / UART6_RXD / PWM1_CH1 / ACMP1_O 7 PC.10 / EBI_ADR6 / UART6_nRTS / UART3_TXD / PWM1_CH2 8 PC.9 / EBI_ADR7 / UART6_nCTS / UART3_RXD / PWM1_CH3 9 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 10 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 11 VSS 12 VDD 13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT 14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT 15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT 16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4 17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST 18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5 19 PD.11 / EBI_nCS1 / UART1_TXD 20 PD.10 / UART1_RXD 21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0 22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1 23 PG.4 / EBI_ADR13 / TM2 24 PF.11 / EBI_ADR14 / UART5_TXD / TM3 25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD 26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS 27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS 28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD 29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD 34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD 35 PH.6 / EBI_ADR1 / UART7_TXD 36 PH.7 / EBI_ADR0 / UART7_RXD 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 Apr. 29, 2020 Page 95 of 283 M031/M032 SERIES DATASHEET 5 Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M031KIAAE Pin Function 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 39 VSS 40 VDD 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 52 VSS 53 VDD 54 PD.15 / PWM0_CH5 / TM3 / INT1 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD 63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD 64 nRESET 65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 67 PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD 68 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD 69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 Apr. 29, 2020 Page 96 of 283 Rev 2.01 M031/M032 M031KIAAE Pin Function 71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 75 VSS 76 VDD 77 PG.9 / EBI_AD0 / BPWM0_CH5 78 PG.10 / EBI_AD1 / BPWM0_CH4 79 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3 80 PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2 81 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1 82 PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0 83 PG.15 / CLKO / ADC0_ST 84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 86 PD.5 / I2C1_SCL / USCI1_DAT0 87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 92 PD.13 / EBI_AD10 / SPI0_I2SMCLK 93 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2 94 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3 95 PA.14 / UART0_TXD / BPWM1_CH4 96 PA.15 / UART0_RXD / BPWM1_CH5 97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5 98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4 99 PE.5 / EBI_nRD / USCI0_CTL1 / UART6_TXD / UART7_nRTS / PWM0_CH2 / BPWM0_CH3 100 PE.4 / EBI_nWR / USCI0_DAT1 / UART6_RXD / UART7_nCTS / PWM0_CH3 / BPWM0_CH2 101 PE.3 / EBI_MCLK / USCI0_DAT0 / UART6_nRTS / UART7_TXD / PWM0_CH4 / BPWM0_CH1 102 PE.2 / EBI_ALE / USCI0_CLK / UART6_nCTS / UART7_RXD / PWM0_CH5 / BPWM0_CH0 103 VSS 104 VDD Apr. 29, 2020 Page 97 of 283 M031/M032 SERIES DATASHEET Pin Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M031KIAAE Pin Function 105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS 106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS 107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD 108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD 109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD 110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5 111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4 112 VSS 113 LDO_CAP 114 VDD 115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 116 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 117 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 118 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 119 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 120 AVDD 121 VREF 122 AVSS 123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2 126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3 127 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 128 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-21 M031KIAAE Multi-function Pin Table Apr. 29, 2020 Page 98 of 283 Rev 2.01 M031/M032 4.1.3 4.1.3.1 M032 Series Pin Diagram M032 Series TSSOP 20-Pin Diagram Corresponding Part Number: M032FC1AE 1 20 USB_VBUS USB_D+ 2 19 PF.1 USB_VDD33_CAP 3 18 PF.0 VSS 4 17 nRESET LDO_CAP 5 16 PA.0 VDD 6 15 PA.1 PB.14 7 14 PA.2 PB.13 8 13 PA.3 PB.12 9 12 PF.2 AVDD 10 11 PF.3 TSSOP20 USB_D- Figure 4.1-28 M032 Series TSSOP 20-pin Diagram M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 99 of 283 Rev 2.01 M031/M032 4.1.3.2 M032 Series TSSOP 28-Pin Diagram Corresponding Part Number: M032EC1AE 1 28 PC.0 USB_D- 2 27 PC.1 USB_D+ 3 26 PF.1 USB_VDD33_CAP 4 25 PF.0 VSS 5 24 nRESET LDO_CAP 6 23 PA.0 VDD 7 22 PA.1 PB.14 8 21 PA.2 PB.13 9 20 PA.3 PB.12 10 19 PF.2 AVDD 11 18 PF.3 PB.5 12 17 PB.0 PB.4 13 16 PB.1 PB.3 14 15 PB.2 TSSOP28 USB_VBUS Figure 4.1-29 M032 Series TSSOP 28-pin Diagram M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 100 of 283 Rev 2.01 M031/M032 4.1.3.3 M032 Series QFN 33-Pin Diagram VSS 25 LDO_CAP USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 PC.1 PF.1 PF.0 24 23 22 21 20 19 18 17 Corresponding Part Number: M032TC1AE, M032TD2AE 16 nRESET 26 15 PF.15 VDD 27 14 PA.0 PB.15 28 13 PA.1 PB.14 29 12 PA.2 PB.13 30 11 PA.3 PB.12 31 10 PF.2 9 PF.3 QFN33 33 VSS 3 4 5 6 7 8 PB.3 PB.2 PB.1 PB.0 PF.5 PF.4 2 PB.4 M031/M032 SERIES DATASHEET 1 32 PB.5 AVDD Top transparent view Figure 4.1-30 M032 Series QFN 33-pin Diagram Apr. 29, 2020 Page 101 of 283 Rev 2.01 M031/M032 M032 Series LQFP 48-Pin Diagram USB_D+ USB_D- USB_VBUS PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 33 32 31 30 29 28 27 26 25 M032LD2AE 34 M032LC2AE, USB_VDD33_CAP Number: 35 Part 36 Corresponding M032LG8AE ,M032LE3AE, VSS 37 24 nRESET LDO_CAP 38 23 PF.15 VDD 39 22 PA.0 PC.14 40 21 PA.1 PB.15 41 20 PA.2 PB.14 42 19 PA.3 PB.13 43 18 PA.4 PB.12 44 17 PA.5 AVDD 45 16 PA.6 AVSS 46 15 PA.7 PB.7 47 14 PF.2 PB.6 48 13 PF.3 8 9 10 11 12 PA.10 PA.9 PA.8 PF.5 PF.4 PB.1 7 5 PB.2 PB.0 4 PB.3 PA.11 3 PB.4 6 2 M031/M032 SERIES DATASHEET 1 LQFP48 PB.5 4.1.3.4 M032LG6AE, Figure 4.1-31 M032 Series LQFP 48-pin Diagram Apr. 29, 2020 Page 102 of 283 Rev 2.01 M031/M032 4.1.3.5 M032 Series LQFP 64-Pin Diagram USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 PD.1 PD.2 PD.3 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Corresponding Part Number: M032SE3AE, M032SG6AE, M032SG8AE, M032SIAAE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 VDD 51 30 PA.0 PC.14 52 29 PA.1 PB.15 53 28 PA.2 PB.14 54 27 PA.3 PB.13 55 26 PA.4 PB.12 56 25 PA.5 AVDD 57 24 PD.15 VREF 58 23 VDD AVSS 59 22 VSS PB.11 60 21 PA.6 PB.10 61 20 PA.7 PB.9 62 19 PC.6 PB.8 63 18 PC.7 PB.7 64 17 PF.2 8 9 10 11 12 13 14 15 16 PA.11 PA.10 PA.9 PA.8 PF.6 PF.14 PF.5 PF.4 PF.3 5 PB.2 7 4 PB.3 PB.0 3 PB.4 6 2 PB.1 1 PB.5 M031/M032 SERIES DATASHEET PB.6 LQFP64 Figure 4.1-32 M032 Series LQFP 64-pin Diagram Apr. 29, 2020 Page 103 of 283 Rev 2.01 M031/M032 4.1.3.6 M032 Series LQFP 128-Pin Diagram USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.13 PD.0 PD.1 PD.2 PD.3 PD.4 PD.5 PD.6 PD.7 PG.15 PG.14 PG.13 PG.12 PG.11 PG.10 PG.9 VDD VSS PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PD.8 PD.9 PF.1 PF.0 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Corresponding Part Number: M032KG6AE, M032KG8AE, M032KIAAE 97 64 nRESET PE.6 98 63 PE.15 PE.5 99 62 PE.14 PE.4 100 61 PF.15 PE.3 101 60 PA.0 PE.2 102 59 PA.1 VSS 103 58 PA.2 VDD 104 57 PA.3 PE.1 105 56 PA.4 PE.0 106 55 PA.5 PH.8 107 54 PD.15 PH.9 108 53 VDD PH.10 109 52 VSS PH.11 110 51 PA.6 PD.14 111 50 PA.7 VSS 112 49 PC.6 LDO_CAP 113 48 PC.7 VDD 114 47 PC.8 PC.14 115 46 PE.13 PB.15 116 45 PE.12 PB.14 117 44 PE.11 PB.13 118 43 PE.10 PB.12 119 42 PE.9 AVDD 120 41 PE.8 VREF 121 40 VDD AVSS 122 39 VSS PB.11 123 38 PF.2 PB.10 124 37 PF.3 PB.9 125 36 PH.7 PB.8 126 35 PH.6 PB.7 127 34 PH.5 PB.6 128 33 PH.4 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PD.11 PD.10 PG.2 PG.3 PG.4 PF.11 PF.10 PF.9 PF.8 PF.7 PF.6 PF.14 PF.5 PF.4 12 VDD PD.12 11 VSS 17 10 PB.0 PC.13 9 PB.1 16 8 PC.9 PA.8 7 PC.10 15 6 PC.11 PA.9 5 PC.12 14 4 PB.2 PA.10 3 PB.3 13 2 PA.11 1 PB.4 LQFP128 PB.5 M031/M032 SERIES DATASHEET PE.7 Figure 4.1-33 M032 Series LQFP 128-pin Diagram Apr. 29, 2020 Page 104 of 283 Rev 2.01 M031/M032 4.1.4 M032 Series Multi-function Pin Diagram 4.1.4.1 M032 Series TSSOP 20-Pin Multi-function Pin Diagram Corresponding Part Number: M032FC1AE M032FC1AE 1 20 USB_VBUS 2 19 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK USB_VDD33_CAP 3 18 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT VSS 4 17 nRESET LDO_CAP 5 16 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 VDD 6 15 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 CLKO / TM1_EXT / BPWM0_CH2 / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 7 14 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 BPWM0_CH1 / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 8 13 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO BPWM0_CH0 / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 9 12 PF.2 / UART0_RXD / USCI1_CTL1 AVDD 10 11 PF.3 / UART0_TXD / USCI1_CTL0 TSSOP20 USB_DUSB_D+ Figure 4.1-34 M032FC1AE Multi-function Pin Diagram Pin M032FC1AE Pin Function USB_D- 2 USB_D+ 3 USB_VDD33_CAP 4 VSS 5 LDO_CAP 6 VDD 7 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / BPWM0_CH2 / TM1_EXT / CLKO 8 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / BPWM0_CH1 9 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 10 AVDD 11 PF.3 / UART0_TXD / USCI1_CTL0 12 PF.2 / UART0_RXD / USCI1_CTL1 13 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO 14 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 15 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 16 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 17 nRESET 18 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT 19 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK 20 USB_VBUS M031/M032 SERIES DATASHEET 1 Table 4.1-22 M032FC1AE Multi-function Pin Table Apr. 29, 2020 Page 105 of 283 Rev 2.01 M031/M032 4.1.4.2 M032 Series TSSOP 28-Pin Multi-function Pin Diagram Corresponding Part Number: M032EC1AE M032EC1AE 1 28 PC.0 / BPWM0_CH4 USB_D- 2 27 PC.1 / BPWM0_CH5 / ADC0_ST USB_D+ 3 26 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK USB_VDD33_CAP 4 25 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT VSS 5 24 nRESET LDO_CAP 6 23 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 VDD 7 22 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 CLKO / TM1_EXT / BPWM0_CH2 / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 8 21 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 BPWM0_CH1 / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 9 20 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO BPWM0_CH0 / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 10 19 PF.2 / UART0_RXD / USCI1_CTL1 AVDD 11 18 PF.3 / UART0_TXD / USCI1_CTL0 INT0 / TM0 / USCI1_CTL0 / ADC0_CH5 / PB.5 12 17 PB.0 / ADC0_CH0 / SPI0_I2SMCLK INT1 / TM1 / USCI1_CTL1 / ADC0_CH4 / PB.4 13 16 PB.1 / ADC0_CH1 / USCI1_CLK INT2 / USCI1_DAT1 / ADC0_CH3 / PB.3 14 15 PB.2 / ADC0_CH2 / USCI1_DAT0 / INT3 TSSOP28 USB_VBUS Figure 4.1-35 M032EC1AE Multi-function Pin Diagram Pin M032EC1AE Pin Function M031/M032 SERIES DATASHEET 1 USB_VBUS 2 USB_D- 3 USB_D+ 4 USB_VDD33_CAP 5 VSS 6 LDO_CAP 7 VDD 8 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / BPWM0_CH2 / TM1_EXT / CLKO 9 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / BPWM0_CH1 10 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 11 AVDD 12 PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0 13 PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1 14 PB.3 / ADC0_CH3 / USCI1_DAT1 / INT2 15 PB.2 / ADC0_CH2 / USCI1_DAT0 / INT3 16 PB.1 / ADC0_CH1 / USCI1_CLK 17 PB.0 / ADC0_CH0 / SPI0_I2SMCLK 18 PF.3 / UART0_TXD / USCI1_CTL0 19 PF.2 / UART0_RXD / USCI1_CTL1 Apr. 29, 2020 Page 106 of 283 Rev 2.01 M031/M032 Pin M032EC1AE Pin Function 20 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO 21 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 22 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 23 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 24 nRESET 25 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT 26 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK 27 PC.1 / BPWM0_CH5 / ADC0_ST 28 PC.0 / BPWM0_CH4 Table 4.1-23 M032EC1AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 107 of 283 Rev 2.01 M031/M032 4.1.4.3 M032 Series QFN 33-Pin Multi-function Pin Diagram Corresponding Part Number: M032TC1AE, M032TD2AE USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / BPWM0_CH4 PC.1 / BPWM0_CH5 / ADC0_ST PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT 24 23 22 21 20 19 18 17 M032TC1AE VSS 25 16 nRESET LDO_CAP 26 15 PF.15 / TM2 / CLKO / INT4 VDD 27 14 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 TM0_EXT / BPWM0_CH3 / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15 28 13 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 CLKO / TM1_EXT / BPWM0_CH2 / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14 29 12 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 BPWM0_CH1 / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13 30 11 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO BPWM0_CH0 / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12 31 10 PF.2 / UART0_RXD / USCI1_CTL1 9 PF.3 / UART0_TXD / USCI1_CTL0 QFN33 33 VSS 1 2 3 4 5 6 7 8 INT2 / USCI1_DAT1 / ADC0_CH3 / PB.3 INT3 / USCI1_DAT0 / ADC0_CH2 / PB.2 USCI1_CLK / ADC0_CH1 / PB.1 SPI0_I2SMCLK / ADC0_CH0 / PB.0 ADC0_ST / BPWM0_CH4 / PF.5 BPWM0_CH5 / PF.4 M031/M032 SERIES DATASHEET INT1 / TM1 / USCI1_CTL1 / ADC0_CH4 / PB.4 32 INT0 / TM0 / USCI1_CTL0 / ADC0_CH5 / PB.5 AVDD Top transparent view Figure 4.1-36 M032TC1AE Multi-function Pin Diagram Pin M032TC1AE Pin Function 1 PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0 2 PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1 3 PB.3 / ADC0_CH3 / USCI1_DAT1 / INT2 Apr. 29, 2020 Page 108 of 283 Rev 2.01 M031/M032 Pin M032TC1AE Pin Function PB.2 / ADC0_CH2 / USCI1_DAT0 / INT3 5 PB.1 / ADC0_CH1 / USCI1_CLK 6 PB.0 / ADC0_CH0 / SPI0_I2SMCLK 7 PF.5 / BPWM0_CH4 / ADC0_ST 8 PF.4 / BPWM0_CH5 9 PF.3 / UART0_TXD / USCI1_CTL0 10 PF.2 / UART0_RXD / USCI1_CTL1 11 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO 12 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 13 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 14 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 15 PF.15 / CLKO / INT4 16 nRESET 17 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT 18 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK 19 PC.1 / BPWM0_CH5 / ADC0_ST 20 PC.0 / BPWM0_CH4 21 USB_VBUS 22 USB_D- 23 USB_D+ 24 USB_VDD33_CAP 25 VSS 26 LDO_CAP 27 VDD 28 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / BPWM0_CH3 / TM0_EXT 29 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / BPWM0_CH2 / TM1_EXT / CLKO 30 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / BPWM0_CH1 31 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 32 AVDD M031/M032 SERIES DATASHEET 4 Table 4.1-24 M032TC1AE Multi-function Pin Table Apr. 29, 2020 Page 109 of 283 Rev 2.01 M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT 24 23 22 21 20 19 18 17 M032TD2AE VSS 25 16 nRESET LDO_CAP 26 15 PF.15 / TM2 / CLKO / INT4 VDD 27 14 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 TM0_EXT / BPWM0_CH3 / BPWM1_CH4 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 28 13 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 CLKO / TM1_EXT / BPWM0_CH2 / BPWM1_CH5 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 29 12 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 TM2_EXT / BPWM0_CH1 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ADC0_CH13 / PB.13 30 11 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO TM3_EXT / BPWM0_CH0 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ADC0_CH12 / PB.12 31 10 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1 AVDD 32 Top transparent view QFN33 2 3 4 5 6 7 8 INT3 / TM3 / USCI1_DAT0 / ADC0_CH2 / PB.2 QSPI0_MISO1 / USCI1_CLK / ADC0_CH1 / PB.1 QSPI0_MOSI1 / SPI0_I2SMCLK / ADC0_CH0 / PB.0 ADC0_ST / BPWM0_CH4 / QSPI0_MISO1 / PF.5 BPWM0_CH5 / QSPI0_MOSI1 / PF.4 M031/M032 SERIES DATASHEET INT1 / TM1 / USCI1_CTL1 / ADC0_CH4 / PB.4 INT0 / TM0 / USCI1_CTL0 / ADC0_CH5 / PB.5 9 INT2 / TM2 / USCI1_DAT1 / ADC0_CH3 / PB.3 1 33 VSS PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0 Figure 4.1-37 M032TD2AE Multi-function Pin Diagram Pin M032TD2AE Pin Function 1 PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0 2 PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1 3 PB.3 / ADC0_CH3 / USCI1_DAT1 / TM2 / INT2 4 PB.2 / ADC0_CH2 / USCI1_DAT0 / TM3 / INT3 5 PB.1 / ADC0_CH1 / USCI1_CLK / QSPI0_MISO1 Apr. 29, 2020 Page 110 of 283 Rev 2.01 M031/M032 Pin M032TD2AE Pin Function PB.0 / ADC0_CH0 / SPI0_I2SMCLK / QSPI0_MOSI1 7 PF.5 / QSPI0_MISO1 / BPWM0_CH4 / ADC0_ST 8 PF.4 / QSPI0_MOSI1 / BPWM0_CH5 9 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0 10 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1 11 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO 12 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 13 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 14 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 15 PF.15 / TM2 / CLKO / INT4 16 nRESET 17 PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT 18 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK 19 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST 20 PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4 21 USB_VBUS 22 USB_D- 23 USB_D+ 24 USB_VDD33_CAP 25 VSS 26 LDO_CAP 27 VDD 28 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / BPWM1_CH4 / BPWM0_CH3 / TM0_EXT 29 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / BPWM1_CH5 / BPWM0_CH2 / TM1_EXT / CLKO 30 PB.13 / ADC0_CH13 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / BPWM0_CH1 / TM2_EXT 31 PB.12 / ADC0_CH12 / SPI0_MOSI / USCI0_CLK / UART0_RXD / BPWM0_CH0 / TM3_EXT 32 AVDD Table 4.1-25 M032TD2AE Multi-function Pin Table Apr. 29, 2020 Page 111 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 6 M031/M032 4.1.4.4 M032 Series LQFP 48-Pin Multi-function Pin Diagram Corresponding M032LG8AE Part Number: M032LC2AE, M032LD2AE, M032LE3AE, M032LG6AE, USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST PC.2 / QSPI0_CLK PC.3 / QSPI0_SS PC.4 / QSPI0_MOSI1 PC.5 / QSPI0_MISO1 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M032LC2AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 40 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 TM0_EXT / BPWM0_CH3 / BPWM1_CH4 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 41 20 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 CLKO / TM1_EXT / BPWM0_CH2 / BPWM1_CH5 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 42 19 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO TM2_EXT / BPWM0_CH1 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ADC0_CH13 / PB.13 43 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4 TM3_EXT / BPWM0_CH0 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ADC0_CH12 / PB.12 44 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5 AVDD 45 16 PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0 AVSS 46 15 PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1 INT5 / BPWM1_CH4 / USCI1_DAT0 / ADC0_CH7 / PB.7 47 14 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1 INT4 / BPWM1_CH5 / USCI1_DAT1 / ADC0_CH6 / PB.6 48 13 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0 8 9 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / PA.10 TM2_EXT / BPWM0_CH2 / USCI0_DAT1 / PA.9 12 7 TM0_EXT / BPWM0_CH0 / USCI0_CLK / PA.11 BPWM0_CH5 / QSPI0_MOSI1 / PF.4 6 QSPI0_MOSI1 / SPI0_I2SMCLK / ADC0_CH0 / PB.0 11 5 QSPI0_MISO1 / USCI1_CLK / ADC0_CH1 / PB.1 ADC0_ST / BPWM0_CH4 / QSPI0_MISO1 / PF.5 4 INT3 / TM3 / USCI1_DAT0 / ADC0_CH2 / PB.2 10 3 INT4 / TM3_EXT / BPWM0_CH3 / USCI0_CTL1 / PA.8 2 1 INT1 / TM1 / USCI1_CTL1 / ADC0_CH4 / PB.4 INT0 / TM0 / USCI1_CTL0 / ADC0_CH5 / PB.5 M031/M032 SERIES DATASHEET INT2 / TM2 / USCI1_DAT1 / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-38 M032LC2AE Multi-function Pin Diagram Pin M032LC2AE Pin Function 1 PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0 2 PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1 3 PB.3 / ADC0_CH3 / USCI1_DAT1 / TM2 / INT2 Apr. 29, 2020 Page 112 of 283 Rev 2.01 M031/M032 Pin M032LC2AE Pin Function PB.2 / ADC0_CH2 / USCI1_DAT0 / TM3 / INT3 5 PB.1 / ADC0_CH1 / USCI1_CLK / QSPI0_MISO1 6 PB.0 / ADC0_CH0 / SPI0_I2SMCLK / QSPI0_MOSI1 7 PA.11 / USCI0_CLK / BPWM0_CH0 / TM0_EXT 8 PA.10 / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 9 PA.9 / USCI0_DAT1 / BPWM0_CH2 / TM2_EXT 10 PA.8 / USCI0_CTL1 / BPWM0_CH3 / TM3_EXT / INT4 11 PF.5 / QSPI0_MISO1 / BPWM0_CH4 / ADC0_ST 12 PF.4 / QSPI0_MOSI1 / BPWM0_CH5 13 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0 14 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1 15 PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1 16 PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4 19 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO 20 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 23 PF.15 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT 26 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK 27 PC.5 / QSPI0_MISO1 28 PC.4 / QSPI0_MOSI1 29 PC.3 / QSPI0_SS 30 PC.2 / QSPI0_CLK 31 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST 32 PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4 33 USB_VBUS 34 USB_D- 35 USB_D+ 36 USB_VDD33_CAP 37 VSS Apr. 29, 2020 Page 113 of 283 M031/M032 SERIES DATASHEET 4 Rev 2.01 M031/M032 Pin M032LC2AE Pin Function 38 LDO_CAP 39 VDD 40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / BPWM1_CH4 / BPWM0_CH3 / TM0_EXT 42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / BPWM1_CH5 / BPWM0_CH2 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / BPWM0_CH1 / TM2_EXT 44 PB.12 / ADC0_CH12 / SPI0_MOSI / USCI0_CLK / UART0_RXD / BPWM0_CH0 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / USCI1_DAT0 / BPWM1_CH4 / INT5 48 PB.6 / ADC0_CH6 / USCI1_DAT1 / BPWM1_CH5 / INT4 Table 4.1-26 M032LC2AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 114 of 283 Rev 2.01 M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST PC.2 / QSPI0_CLK PC.3 / QSPI0_SS PC.4 / QSPI0_MOSI1 PC.5 / QSPI0_MISO1 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M032LD2AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 40 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 TM0_EXT / BPWM0_CH3 / BPWM1_CH4 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15 41 20 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 CLKO / TM1_EXT / BPWM0_CH2 / BPWM1_CH5 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14 42 19 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO TM2_EXT / BPWM0_CH1 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ADC0_CH13 / PB.13 43 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4 TM3_EXT / BPWM0_CH0 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ADC0_CH12 / PB.12 44 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5 AVDD 45 16 PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0 AVSS 46 15 PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1 INT5 / BPWM1_CH4 / USCI1_DAT0 / ADC0_CH7 / PB.7 47 14 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1 INT4 / BPWM1_CH5 / USCI1_DAT1 / ADC0_CH6 / PB.6 48 13 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0 8 9 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / PA.10 TM2_EXT / BPWM0_CH2 / USCI0_DAT1 / PA.9 12 7 TM0_EXT / BPWM0_CH0 / USCI0_CLK / PA.11 BPWM0_CH5 / QSPI0_MOSI1 / PF.4 6 QSPI0_MOSI1 / SPI0_I2SMCLK / ADC0_CH0 / PB.0 11 5 QSPI0_MISO1 / USCI1_CLK / ADC0_CH1 / PB.1 ADC0_ST / BPWM0_CH4 / QSPI0_MISO1 / PF.5 4 INT3 / TM3 / USCI1_DAT0 / ADC0_CH2 / PB.2 10 3 INT4 / TM3_EXT / BPWM0_CH3 / USCI0_CTL1 / PA.8 2 1 INT0 / TM0 / USCI1_CTL0 / ADC0_CH5 / PB.5 INT1 / TM1 / USCI1_CTL1 / ADC0_CH4 / PB.4 M031/M032 SERIES DATASHEET INT2 / TM2 / USCI1_DAT1 / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-39 M032LD2AE Multi-function Pin Diagram Pin M032LD2AE Pin Function 1 PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0 2 PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1 3 PB.3 / ADC0_CH3 / USCI1_DAT1 / TM2 / INT2 4 PB.2 / ADC0_CH2 / USCI1_DAT0 / TM3 / INT3 5 PB.1 / ADC0_CH1 / USCI1_CLK / QSPI0_MISO1 Apr. 29, 2020 Page 115 of 283 Rev 2.01 M031/M032 Pin M032LD2AE Pin Function M031/M032 SERIES DATASHEET 6 PB.0 / ADC0_CH0 / SPI0_I2SMCLK / QSPI0_MOSI1 7 PA.11 / USCI0_CLK / BPWM0_CH0 / TM0_EXT 8 PA.10 / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 9 PA.9 / USCI0_DAT1 / BPWM0_CH2 / TM2_EXT 10 PA.8 / USCI0_CTL1 / BPWM0_CH3 / TM3_EXT / INT4 11 PF.5 / QSPI0_MISO1 / BPWM0_CH4 / ADC0_ST 12 PF.4 / QSPI0_MOSI1 / BPWM0_CH5 13 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0 14 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1 15 PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1 16 PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4 19 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO 20 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0 23 PF.15 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT 26 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK 27 PC.5 / QSPI0_MISO1 28 PC.4 / QSPI0_MOSI1 29 PC.3 / QSPI0_SS 30 PC.2 / QSPI0_CLK 31 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST 32 PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4 33 USB_VBUS 34 USB_D- 35 USB_D+ 36 USB_VDD33_CAP 37 VSS 38 LDO_CAP 39 VDD Apr. 29, 2020 Page 116 of 283 Rev 2.01 M031/M032 Pin M032LD2AE Pin Function 40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / BPWM1_CH4 / BPWM0_CH3 / TM0_EXT 42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / BPWM1_CH5 / BPWM0_CH2 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / BPWM0_CH1 / TM2_EXT 44 PB.12 / ADC0_CH12 / SPI0_MOSI / USCI0_CLK / UART0_RXD / BPWM0_CH0 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / USCI1_DAT0 / BPWM1_CH4 / INT5 48 PB.6 / ADC0_CH6 / USCI1_DAT1 / BPWM1_CH5 / INT4 Table 4.1-27 M032LD2AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 117 of 283 Rev 2.01 M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M032LE3AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 40 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 41 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 42 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 45 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / EBI_nCS0 / UART1_TXD / EBI_nWRL / ADC0_CH7 / PB.7 47 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / EBI_nCS1 / UART1_RXD / EBI_nWRH / ADC0_CH6 / PB.6 48 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN 10 11 12 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 TM2_EXT / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 9 6 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 8 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 7 4 TM0_EXT / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 3 TM1_EXT / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 2 1 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-40 M032LE3AE Multi-function Pin Diagram Pin M032LE3AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 5 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 Apr. 29, 2020 Page 118 of 283 Rev 2.01 M031/M032 Pin M032LE3AE Pin Function PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT 8 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT 9 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT 10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 28 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 29 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 30 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 31 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 32 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 USB_VBUS 34 USB_D- 35 USB_D+ 36 USB_VDD33_CAP 37 VSS 38 LDO_CAP 39 VDD Apr. 29, 2020 Page 119 of 283 M031/M032 SERIES DATASHEET 6 Rev 2.01 M031/M032 Pin M032LE3AE Pin Function 40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 41 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-28 M032LE3AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 120 of 283 Rev 2.01 M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M032LG6AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 40 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 41 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 42 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 45 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 47 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 48 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 8 9 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 7 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 6 11 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 4 10 3 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-41 M032LG6AE Multi-function Pin Diagram Pin M032LG6AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / Apr. 29, 2020 Page 121 of 283 Rev 2.01 M031/M032 Pin M032LG6AE Pin Function PWM0_CH3 / TM3 / INT3 M031/M032 SERIES DATASHEET 5 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 8 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 9 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 USB_VBUS 34 USB_D- 35 USB_D+ Apr. 29, 2020 Page 122 of 283 Rev 2.01 M031/M032 Pin M032LG6AE Pin Function 36 USB_VDD33_CAP 37 VSS 38 LDO_CAP 39 VDD 40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 41 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-29 M032LG6AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 123 of 283 Rev 2.01 M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 M032LG8AE VSS 37 24 nRESET LDO_CAP 38 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 39 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 40 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 41 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 42 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 43 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 44 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 45 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 AVSS 46 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 47 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 48 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 8 9 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 7 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 6 11 5 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 4 10 3 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP48 Figure 4.1-42 M032LG8AE Multi-function Pin Diagram Pin M032LG8AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / Apr. 29, 2020 Page 124 of 283 Rev 2.01 M031/M032 Pin M032LG8AE Pin Function PWM0_CH3 / TM3 / INT3 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 6 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 7 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 8 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 9 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 19 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 20 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 24 nRESET 25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 33 USB_VBUS 34 USB_D- 35 USB_D+ Apr. 29, 2020 Page 125 of 283 M031/M032 SERIES DATASHEET 5 Rev 2.01 M031/M032 Pin M032LG8AE Pin Function 36 USB_VDD33_CAP 37 VSS 38 LDO_CAP 39 VDD 40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 41 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 43 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 45 AVDD 46 AVSS 47 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 48 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-30 M032LG8AE Multi-function Pin Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 126 of 283 Rev 2.01 M031/M032 4.1.4.5 M032 Series LQFP 64-Pin Multi-function Pin Diagram Corresponding Part Number: M032SE3AE, M032SG6AE, M032SG8AE, M032SIAAE USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART0_TXD PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M032SE3AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 TM1 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 I2C1_SDA / UART0_nRTS / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 UART1_nCTS / UART0_TXD / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 UART1_nRTS / UART0_RXD / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / EBI_nCS0 / UART1_TXD / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT 10 11 12 13 14 15 16 INT4 / TM3_EXT / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / ADC0_CH0 / PB.0 TM2_EXT / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 7 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC0_CH1 / PB.1 9 6 8 5 INT3 / TM3 / PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP0_P1 / ADC0_CH2 / PB.2 TM0_EXT / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 4 TM1_EXT / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 3 1 2 INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / EBI_nCS1 / UART1_RXD / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP0_N / ADC0_CH3 / PB.3 LQFP64 Figure 4.1-43 M032SE3AE Multi-function Pin Diagram Pin M032SE3AE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0 Apr. 29, 2020 Page 127 of 283 Rev 2.01 M031/M032 Pin M032SE3AE Pin Function M031/M032 SERIES DATASHEET 3 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1 4 PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT 18 PC.7 / EBI_AD9 / UART0_nCTS / PWM1_CH2 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART0_nRTS / PWM1_CH3 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0 26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1 27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4 30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 35 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0 36 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1 Apr. 29, 2020 Page 128 of 283 Rev 2.01 M031/M032 M032SE3AE Pin Function 37 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2 38 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3 39 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O 40 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 45 USB_VBUS 46 USB_D- 47 USB_D+ 48 USB_VDD33_CAP 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK 61 PB.10 / ADC0_CH10 / EBI_ADR17 / UART0_nRTS / I2C1_SDA 62 PB.9 / ADC0_CH9 / EBI_ADR18 / UART0_TXD / UART1_nCTS 63 PB.8 / ADC0_CH8 / EBI_ADR19 / UART0_RXD / UART1_nRTS 64 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-31 M032SE2AE Multi-function Pin Table Apr. 29, 2020 Page 129 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M032SG6AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-44 M032SG6AE Multi-function Pin Diagram Pin M032SG6AE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 130 of 283 Rev 2.01 M031/M032 Pin M032SG6AE Pin Function PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK Apr. 29, 2020 Page 131 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 4 M031/M032 M031/M032 SERIES DATASHEET Pin M032SG6AE Pin Function 35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 45 USB_VBUS 46 USB_D- 47 USB_D+ 48 USB_VDD33_CAP 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 64 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-32 M032SG6AE Multi-function Pin Table Apr. 29, 2020 Page 132 of 283 Rev 2.01 M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M032SG8AE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-45 M032SG8AE Multi-function Pin Diagram Pin M032SG8AE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 133 of 283 Rev 2.01 M031/M032 Pin M032SG8AE Pin Function M031/M032 SERIES DATASHEET 4 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 5 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK Apr. 29, 2020 Page 134 of 283 Rev 2.01 M031/M032 M032SG8AE Pin Function 35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 45 USB_VBUS 46 USB_D- 47 USB_D+ 48 USB_VDD33_CAP 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 64 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-33 M032SG8AE Multi-function Pin Table Apr. 29, 2020 Page 135 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 M032SIAAE VSS 49 32 nRESET LDO_CAP 50 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 VDD 51 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 52 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 53 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 54 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 55 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 56 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 AVDD 57 24 PD.15 / PWM0_CH5 / TM3 / INT1 VREF 58 23 VDD AVSS 59 22 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 60 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 61 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 BPWM1_CH2 / UART7_TXD / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 62 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 BPWM1_CH3 / UART7_RXD / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 63 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 64 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / UART6_TXD / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / UART6_RXD / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART7_TXD / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART7_RXD / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP64 Figure 4.1-46 M032SIAAE Multi-function Pin Diagram Pin M032SIAAE Pin Function 1 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O 2 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 3 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 4 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 Apr. 29, 2020 Page 136 of 283 Rev 2.01 M031/M032 Pin M032SIAAE Pin Function PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 6 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 7 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 8 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT 9 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT 10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT 11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4 12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 22 VSS 23 VDD 24 PD.15 / PWM0_CH5 / TM3 / INT1 25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 26 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 27 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 28 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 32 nRESET 33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 Apr. 29, 2020 Page 137 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 5 M031/M032 M031/M032 SERIES DATASHEET Pin M032SIAAE Pin Function 36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 45 USB_VBUS 46 USB_D- 47 USB_D+ 48 USB_VDD33_CAP 49 VSS 50 LDO_CAP 51 VDD 52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 53 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 55 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 57 AVDD 58 VREF 59 AVSS 60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2 63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3 64 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O Table 4.1-34 M032SIAAE Multi-function Pin Table Apr. 29, 2020 Page 138 of 283 Rev 2.01 M031/M032 4.1.4.6 M032 Series LQFP 128-Pin Multi-function Pin Diagram Corresponding Part Number: M032KG6AE, M032KG8AE, M032KIAAE BPWM0_CH5 / PWM0_CH0 / UART5_TXD / PE.7 97 BPWM0_CH4 / PWM0_CH1 / UART5_RXD / USCI0_CTL0 / PE.6 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PD.8 / EBI_AD6 / UART2_nRTS PD.9 / EBI_AD7 / UART2_nCTS PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 65 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 66 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 VSS 72 67 VDD 73 68 PG.9 / EBI_AD0 / BPWM0_CH5 74 69 PG.10 / EBI_AD1 / BPWM0_CH4 75 70 PG.11 / EBI_AD2 / BPWM0_CH3 76 71 PG.12 / EBI_AD3 / BPWM0_CH2 PG.15 / CLKO / ADC0_ST 77 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK PG.14 / EBI_AD5 / BPWM0_CH0 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 PG.13 / EBI_AD4 / BPWM0_CH1 PD.5 / I2C1_SCL / USCI1_DAT0 83 78 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 84 79 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 85 80 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 86 81 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 87 82 PD.13 / EBI_AD10 / SPI0_I2SMCLK PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 88 USB_VBUS 89 USB_D- 93 90 USB_D+ 94 91 USB_VDD33_CAP 95 92 96 M032KG6AE 64 nRESET 98 63 PE.15 / EBI_AD9 / UART2_RXD BPWM0_CH3 / PWM0_CH2 / USCI0_CTL1 / EBI_nRD / PE.5 99 62 PE.14 / EBI_AD8 / UART2_TXD BPWM0_CH2 / PWM0_CH3 / USCI0_DAT1 / EBI_nWR / PE.4 100 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / EBI_MCLK / PE.3 101 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 BPWM0_CH0 / PWM0_CH5 / USCI0_CLK / EBI_ALE / PE.2 102 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 VSS 103 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 VDD 104 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 UART4_nCTS / I2C1_SCL / UART3_TXD / QSPI0_MISO0 / EBI_AD10 / PE.1 105 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 UART4_nRTS / I2C1_SDA / UART3_RXD / QSPI0_MOSI0 / EBI_AD11 / PE.0 106 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 UART1_TXD / UART3_nRTS / QSPI0_CLK / EBI_AD12 / PH.8 107 54 PD.15 / PWM0_CH5 / TM3 / INT1 UART1_RXD / UART3_nCTS / QSPI0_SS / EBI_AD13 / PH.9 108 53 VDD UART0_TXD / UART4_TXD / QSPI0_MISO1 / EBI_AD14 / PH.10 109 52 VSS PWM0_CH5 / UART0_RXD / UART4_RXD / QSPI0_MOSI1 / EBI_AD15 / PH.11 110 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PWM0_CH4 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_nCS0 / PD.14 111 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 VSS 112 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 LDO_CAP 113 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 VDD 114 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 115 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 116 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 117 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 118 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 119 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 AVDD 120 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 VREF 121 40 VDD AVSS 122 39 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 123 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 124 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 125 36 PH.7 / EBI_ADR0 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 126 35 PH.6 / EBI_ADR1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 127 34 PH.5 / EBI_ADR2 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 128 33 PH.4 / EBI_ADR3 30 31 32 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 25 UART5_RXD / SPI0_I2SMCLK / EBI_ADR15 / PF.10 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 24 TM3 / UART5_TXD / EBI_ADR14 / PF.11 29 23 TM2 / EBI_ADR13 / PG.4 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 22 TM1 / I2C1_SDA / I2C0_SMBSUS / EBI_ADR12 / PG.3 28 21 TM0 / I2C1_SCL / I2C0_SMBAL / EBI_ADR11 / PG.2 UART4_TXD / SPI0_MISO / EBI_ADR18 / PF.7 20 UART1_RXD / PD.10 27 19 UART1_TXD / EBI_nCS1 / PD.11 UART5_nRTS / SPI0_SS / EBI_ADR16 / PF.9 18 INT5 / ADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART5_nCTS / SPI0_CLK / EBI_ADR17 / PF.8 17 ADC0_ST / CLKO / BPWM0_CH4 / UART2_TXD / USCI0_CTL0 / EBI_ADR10 / PC.13 26 16 14 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 15 13 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 VDD INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 11 9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 VSS 8 PWM1_CH3 / UART3_RXD / EBI_ADR7 / PC.9 10 7 PWM1_CH2 / UART3_TXD / EBI_ADR6 / PC.10 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 6 ACMP0_O / PWM1_CH0 / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 4 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 3 5 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP128 Figure 4.1-47 M032KG6AE Multi-function Pin Diagram Pin M032KG6AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 Apr. 29, 2020 Page 139 of 283 Rev 2.01 M031/M032 Pin M032KG6AE Pin Function M031/M032 SERIES DATASHEET 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 5 PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O 6 PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O 7 PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2 8 PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3 9 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 10 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 11 VSS 12 VDD 13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST 18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5 19 PD.11 / EBI_nCS1 / UART1_TXD 20 PD.10 / UART1_RXD 21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0 22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1 23 PG.4 / EBI_ADR13 / TM2 24 PF.11 / EBI_ADR14 / UART5_TXD / TM3 25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD 26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS 27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS 28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD 29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 33 PH.4 / EBI_ADR3 34 PH.5 / EBI_ADR2 Apr. 29, 2020 Page 140 of 283 Rev 2.01 M031/M032 M032KG6AE Pin Function 35 PH.6 / EBI_ADR1 36 PH.7 / EBI_ADR0 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 39 VSS 40 VDD 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 52 VSS 53 VDD 54 PD.15 / PWM0_CH5 / TM3 / INT1 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 62 PE.14 / EBI_AD8 / UART2_TXD 63 PE.15 / EBI_AD9 / UART2_RXD 64 nRESET 65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 67 PD.9 / EBI_AD7 / UART2_nCTS Apr. 29, 2020 Page 141 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 M031/M032 SERIES DATASHEET Pin M032KG6AE Pin Function 68 PD.8 / EBI_AD6 / UART2_nRTS 69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 75 VSS 76 VDD 77 PG.9 / EBI_AD0 / BPWM0_CH5 78 PG.10 / EBI_AD1 / BPWM0_CH4 79 PG.11 / EBI_AD2 / BPWM0_CH3 80 PG.12 / EBI_AD3 / BPWM0_CH2 81 PG.13 / EBI_AD4 / BPWM0_CH1 82 PG.14 / EBI_AD5 / BPWM0_CH0 83 PG.15 / CLKO / ADC0_ST 84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 86 PD.5 / I2C1_SCL / USCI1_DAT0 87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 92 PD.13 / EBI_AD10 / SPI0_I2SMCLK 93 USB_VBUS 94 USB_D- 95 USB_D+ 96 USB_VDD33_CAP 97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5 98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4 99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3 100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2 101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1 Apr. 29, 2020 Page 142 of 283 Rev 2.01 M031/M032 M032KG6AE Pin Function 102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0 103 VSS 104 VDD 105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS 106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS 107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD 108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD 109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD 110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5 111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4 112 VSS 113 LDO_CAP 114 VDD 115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 116 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 117 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 118 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 119 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 120 AVDD 121 VREF 122 AVSS 123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 127 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 128 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-35 M032KG6AE Multi-function Pin Table Apr. 29, 2020 Page 143 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PD.8 / EBI_AD6 / UART2_nRTS PD.9 / EBI_AD7 / UART2_nCTS PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 65 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 66 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 VSS 72 67 VDD 73 68 PG.9 / EBI_AD0 / BPWM0_CH5 74 69 PG.10 / EBI_AD1 / BPWM0_CH4 75 70 PG.11 / EBI_AD2 / BPWM0_CH3 76 71 PG.12 / EBI_AD3 / BPWM0_CH2 PG.15 / CLKO / ADC0_ST 77 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK PG.14 / EBI_AD5 / BPWM0_CH0 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 PG.13 / EBI_AD4 / BPWM0_CH1 PD.5 / I2C1_SCL / USCI1_DAT0 83 78 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 84 79 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 85 80 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 86 81 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 87 82 PD.13 / EBI_AD10 / SPI0_I2SMCLK PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 88 USB_VBUS 89 USB_D- 90 USB_D+ 91 USB_VDD33_CAP 93 92 94 nRESET 63 PE.15 / EBI_AD9 / UART2_RXD 99 62 PE.14 / EBI_AD8 / UART2_TXD 100 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / EBI_MCLK / PE.3 101 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 BPWM0_CH0 / PWM0_CH5 / USCI0_CLK / EBI_ALE / PE.2 102 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 VSS 103 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 VDD 104 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 UART4_nCTS / I2C1_SCL / UART3_TXD / QSPI0_MISO0 / EBI_AD10 / PE.1 105 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 UART4_nRTS / I2C1_SDA / UART3_RXD / QSPI0_MOSI0 / EBI_AD11 / PE.0 106 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 UART1_TXD / UART3_nRTS / QSPI0_CLK / EBI_AD12 / PH.8 107 54 PD.15 / PWM0_CH5 / TM3 / INT1 UART1_RXD / UART3_nCTS / QSPI0_SS / EBI_AD13 / PH.9 108 53 VDD UART0_TXD / UART4_TXD / QSPI0_MISO1 / EBI_AD14 / PH.10 109 52 VSS PWM0_CH5 / UART0_RXD / UART4_RXD / QSPI0_MOSI1 / EBI_AD15 / PH.11 110 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PWM0_CH4 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_nCS0 / PD.14 111 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 VSS 112 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 LDO_CAP 113 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 VDD 114 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 115 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 116 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 117 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 118 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 119 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 AVDD 120 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 VREF 121 40 VDD AVSS 122 39 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 123 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 124 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 BPWM1_CH2 / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 125 36 PH.7 / EBI_ADR0 BPWM1_CH3 / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 126 35 PH.6 / EBI_ADR1 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 127 34 PH.5 / EBI_ADR2 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 128 33 PH.4 / EBI_ADR3 30 31 32 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 25 UART5_RXD / SPI0_I2SMCLK / EBI_ADR15 / PF.10 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 24 TM3 / UART5_TXD / EBI_ADR14 / PF.11 29 23 TM2 / EBI_ADR13 / PG.4 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 22 TM1 / I2C1_SDA / I2C0_SMBSUS / EBI_ADR12 / PG.3 28 21 TM0 / I2C1_SCL / I2C0_SMBAL / EBI_ADR11 / PG.2 UART4_TXD / SPI0_MISO / EBI_ADR18 / PF.7 20 UART1_RXD / PD.10 27 19 UART1_TXD / EBI_nCS1 / PD.11 UART5_nRTS / SPI0_SS / EBI_ADR16 / PF.9 18 INT5 / ADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART5_nCTS / SPI0_CLK / EBI_ADR17 / PF.8 17 ADC0_ST / CLKO / BPWM0_CH4 / UART2_TXD / USCI0_CTL0 / EBI_ADR10 / PC.13 26 16 14 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 15 13 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 12 VDD INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 11 9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 VSS 8 PWM1_CH3 / UART3_RXD / EBI_ADR7 / PC.9 10 7 PWM1_CH2 / UART3_TXD / EBI_ADR6 / PC.10 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 6 ACMP0_O / PWM1_CH0 / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 4 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 3 5 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 M031/M032 SERIES DATASHEET INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 LQFP128 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 97 95 64 98 BPWM0_CH3 / PWM0_CH2 / USCI0_CTL1 / EBI_nRD / PE.5 BPWM0_CH2 / PWM0_CH3 / USCI0_DAT1 / EBI_nWR / PE.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 BPWM0_CH5 / PWM0_CH0 / UART5_TXD / PE.7 BPWM0_CH4 / PWM0_CH1 / UART5_RXD / USCI0_CTL0 / PE.6 96 M032KG8AE Figure 4.1-48 M032KG8AE Multi-function Pin Diagram Pin M032KG8AE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / Apr. 29, 2020 Page 144 of 283 Rev 2.01 M031/M032 Pin M032KG8AE Pin Function PWM0_CH3 / TM3 / INT3 PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O 6 PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O 7 PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2 8 PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3 9 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 10 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 11 VSS 12 VDD 13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT 14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT 15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT 16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4 17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST 18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5 19 PD.11 / EBI_nCS1 / UART1_TXD 20 PD.10 / UART1_RXD 21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0 22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1 23 PG.4 / EBI_ADR13 / TM2 24 PF.11 / EBI_ADR14 / UART5_TXD / TM3 25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD 26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS 27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS 28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD 29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 33 PH.4 / EBI_ADR3 34 PH.5 / EBI_ADR2 35 PH.6 / EBI_ADR1 36 PH.7 / EBI_ADR0 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 Apr. 29, 2020 Page 145 of 283 M031/M032 SERIES DATASHEET 5 Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M032KG8AE Pin Function 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 39 VSS 40 VDD 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 52 VSS 53 VDD 54 PD.15 / PWM0_CH5 / TM3 / INT1 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 62 PE.14 / EBI_AD8 / UART2_TXD 63 PE.15 / EBI_AD9 / UART2_RXD 64 nRESET 65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 67 PD.9 / EBI_AD7 / UART2_nCTS 68 PD.8 / EBI_AD6 / UART2_nRTS 69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 Apr. 29, 2020 Page 146 of 283 Rev 2.01 M031/M032 M032KG8AE Pin Function 71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 75 VSS 76 VDD 77 PG.9 / EBI_AD0 / BPWM0_CH5 78 PG.10 / EBI_AD1 / BPWM0_CH4 79 PG.11 / EBI_AD2 / BPWM0_CH3 80 PG.12 / EBI_AD3 / BPWM0_CH2 81 PG.13 / EBI_AD4 / BPWM0_CH1 82 PG.14 / EBI_AD5 / BPWM0_CH0 83 PG.15 / CLKO / ADC0_ST 84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 86 PD.5 / I2C1_SCL / USCI1_DAT0 87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 92 PD.13 / EBI_AD10 / SPI0_I2SMCLK 93 USB_VBUS 94 USB_D- 95 USB_D+ 96 USB_VDD33_CAP 97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5 98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4 99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3 100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2 101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1 102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0 103 VSS 104 VDD Apr. 29, 2020 Page 147 of 283 M031/M032 SERIES DATASHEET Pin Rev 2.01 M031/M032 M031/M032 SERIES DATASHEET Pin M032KG8AE Pin Function 105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS 106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS 107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD 108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD 109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD 110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5 111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4 112 VSS 113 LDO_CAP 114 VDD 115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 116 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 117 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 118 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 119 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 120 AVDD 121 VREF 122 AVSS 123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2 126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3 127 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 128 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-36 M032KG8AE Multi-function Pin Table Apr. 29, 2020 Page 148 of 283 Rev 2.01 M031/M032 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 65 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 66 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 67 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 71 68 VSS 72 69 VDD 73 70 PG.9 / EBI_AD0 / BPWM0_CH5 74 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1 PG.10 / EBI_AD1 / BPWM0_CH4 PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0 75 PG.15 / CLKO / ADC0_ST PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 81 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 82 76 PD.5 / I2C1_SCL / USCI1_DAT0 83 77 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 84 78 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 85 79 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 86 80 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 87 PD.13 / EBI_AD10 / SPI0_I2SMCLK 92 88 USB_VBUS 93 89 USB_D94 90 USB_D+ 95 91 USB_VDD33_CAP 96 M032KIAAE BPWM0_CH5 / PWM0_CH0 / UART5_TXD / PE.7 97 64 nRESET BPWM0_CH4 / PWM0_CH1 / UART5_RXD / USCI0_CTL0 / PE.6 98 63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD BPWM0_CH3 / PWM0_CH2 / UART7_nRTS / UART6_TXD / USCI0_CTL1 / EBI_nRD / PE.5 99 62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD BPWM0_CH2 / PWM0_CH3 / UART7_nCTS / UART6_RXD / USCI0_DAT1 / EBI_nWR / PE.4 100 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 BPWM0_CH1 / PWM0_CH4 / UART7_TXD / UART6_nRTS / USCI0_DAT0 / EBI_MCLK / PE.3 101 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 BPWM0_CH0 / PWM0_CH5 / UART7_RXD / UART6_nCTS / USCI0_CLK / EBI_ALE / PE.2 102 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 VSS 103 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 VDD 104 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 UART4_nCTS / I2C1_SCL / UART3_TXD / QSPI0_MISO0 / EBI_AD10 / PE.1 105 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 UART4_nRTS / I2C1_SDA / UART3_RXD / QSPI0_MOSI0 / EBI_AD11 / PE.0 106 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 UART1_TXD / UART3_nRTS / QSPI0_CLK / EBI_AD12 / PH.8 107 54 PD.15 / PWM0_CH5 / TM3 / INT1 UART1_RXD / UART3_nCTS / QSPI0_SS / EBI_AD13 / PH.9 108 53 VDD UART0_TXD / UART4_TXD / QSPI0_MISO1 / EBI_AD14 / PH.10 109 52 VSS PWM0_CH5 / UART0_RXD / UART4_RXD / QSPI0_MOSI1 / EBI_AD15 / PH.11 110 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PWM0_CH4 / USCI0_CTL0 / SPI0_I2SMCLK / EBI_nCS0 / PD.14 111 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 VSS 112 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 LDO_CAP 113 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 VDD 114 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 115 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART3_TXD / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / ADC0_CH15 / PB.15 116 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 CLKO / TM1_EXT / PWM1_CH1 / UART3_RXD / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / ADC0_CH14 / PB.14 117 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 TM2_EXT / PWM1_CH2 / UART3_nRTS / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13 118 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 TM3_EXT / PWM1_CH3 / UART3_nCTS / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12 119 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 AVDD 120 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 VREF 121 40 VDD AVSS 122 39 VSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART4_TXD / UART0_nCTS / EBI_ADR16 / ADC0_CH11 / PB.11 123 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 BPWM1_CH1 / I2C1_SDA / UART4_RXD / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / ADC0_CH10 / PB.10 124 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 BPWM1_CH2 / UART7_TXD / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / ADC0_CH9 / PB.9 125 36 PH.7 / EBI_ADR0 / UART7_RXD BPWM1_CH3 / UART7_RXD / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / ADC0_CH8 / PB.8 126 35 PH.6 / EBI_ADR1 / UART7_TXD ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / ADC0_CH7 / PB.7 127 34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / ADC0_CH6 / PB.6 128 33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD 25 26 TM3 / UART5_TXD / EBI_ADR14 / PF.11 UART5_RXD / SPI0_I2SMCLK / EBI_ADR15 / PF.10 UART5_nRTS / SPI0_SS / EBI_ADR16 / PF.9 32 24 TM2 / EBI_ADR13 / PG.4 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 23 TM1 / I2C1_SDA / I2C0_SMBSUS / EBI_ADR12 / PG.3 31 22 TM0 / I2C1_SCL / I2C0_SMBAL / EBI_ADR11 / PG.2 ADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 21 UART1_RXD / PD.10 30 20 UART1_TXD / EBI_nCS1 / PD.11 INT5 / TM3 / CLKO / PWM0_CH4 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 19 INT5 / ADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 29 18 ADC0_ST / CLKO / BPWM0_CH4 / UART2_TXD / USCI0_CTL0 / EBI_ADR10 / PC.13 EBI_nCS0 / UART4_RXD / SPI0_MOSI / EBI_ADR19 / PF.6 17 28 16 INT4 / TM3_EXT / BPWM0_CH3 / UART7_RXD / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 27 15 TM2_EXT / BPWM0_CH2 / UART7_TXD / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 UART5_nCTS / SPI0_CLK / EBI_ADR17 / PF.8 14 TM1_EXT / BPWM0_CH1 / UART6_RXD / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 UART4_TXD / SPI0_MISO / EBI_ADR18 / PF.7 13 9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / ADC0_CH1 / PB.1 TM0_EXT / BPWM0_CH0 / UART6_TXD / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 8 PWM1_CH3 / UART3_RXD / UART6_nCTS / EBI_ADR7 / PC.9 12 7 PWM1_CH2 / UART3_TXD / UART6_nRTS / EBI_ADR6 / PC.10 VDD 6 ACMP1_O / PWM1_CH1 / UART6_RXD / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 11 5 ACMP0_O / PWM1_CH0 / UART6_TXD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 VSS 4 10 3 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / ADC0_CH0 / PB.0 2 1 INT0 / TM0 / UART2_TXD / PWM0_CH0 / USCI1_CTL0 / UART5_TXD / I2C0_SCL / EBI_ADR0 / ACMP1_N / ADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / USCI1_CTL1 / UART5_RXD / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / ADC0_CH4 / PB.4 INT3 / TM3 / PWM0_CH3 / USCI1_DAT0 / UART5_nCTS / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / ADC0_CH2 / PB.2 M031/M032 SERIES DATASHEET INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / USCI1_DAT1 / UART5_nRTS / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / ADC0_CH3 / PB.3 LQFP128 Figure 4.1-49 M032KIAAE Multi-function Pin Diagram Pin M032KIAAE Pin Function 1 PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD / TM0 / INT0 2 PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD / TM1 / INT1 3 PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2 4 PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 / PWM0_CH3 / TM3 / INT3 Apr. 29, 2020 Page 149 of 283 Rev 2.01 M031/M032 Pin M032KIAAE Pin Function M031/M032 SERIES DATASHEET 5 PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / UART6_TXD / PWM1_CH0 / ACMP0_O 6 PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / UART6_RXD / PWM1_CH1 / ACMP1_O 7 PC.10 / EBI_ADR6 / UART6_nRTS / UART3_TXD / PWM1_CH2 8 PC.9 / EBI_ADR7 / UART6_nCTS / UART3_RXD / PWM1_CH3 9 PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 10 PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 11 VSS 12 VDD 13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT 14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT 15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT 16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4 17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST 18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5 19 PD.11 / EBI_nCS1 / UART1_TXD 20 PD.10 / UART1_RXD 21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0 22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1 23 PG.4 / EBI_ADR13 / TM2 24 PF.11 / EBI_ADR14 / UART5_TXD / TM3 25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD 26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS 27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS 28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD 29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0 30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5 31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST 32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT 33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD 34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD 35 PH.6 / EBI_ADR1 / UART7_TXD 36 PH.7 / EBI_ADR0 / UART7_RXD 37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 Apr. 29, 2020 Page 150 of 283 Rev 2.01 M031/M032 M032KIAAE Pin Function 38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 39 VSS 40 VDD 41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0 44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4 48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 52 VSS 53 VDD 54 PD.15 / PWM0_CH5 / TM3 / INT1 55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0 56 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 / PWM0_CH1 57 PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 58 PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4 62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD 63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD 64 nRESET 65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT 66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK 67 PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD 68 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD 69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0 70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1 Apr. 29, 2020 Page 151 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 M031/M032 SERIES DATASHEET Pin M032KIAAE Pin Function 71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2 72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3 73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST 74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O 75 VSS 76 VDD 77 PG.9 / EBI_AD0 / BPWM0_CH5 78 PG.10 / EBI_AD1 / BPWM0_CH4 79 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3 80 PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2 81 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1 82 PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0 83 PG.15 / CLKO / ADC0_ST 84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK 85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 86 PD.5 / I2C1_SCL / USCI1_DAT0 87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD 89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD 90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD 91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2 92 PD.13 / EBI_AD10 / SPI0_I2SMCLK 93 USB_VBUS 94 USB_D- 95 USB_D+ 96 USB_VDD33_CAP 97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5 98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4 99 PE.5 / EBI_nRD / USCI0_CTL1 / UART6_TXD / UART7_nRTS / PWM0_CH2 / BPWM0_CH3 100 PE.4 / EBI_nWR / USCI0_DAT1 / UART6_RXD / UART7_nCTS / PWM0_CH3 / BPWM0_CH2 101 PE.3 / EBI_MCLK / USCI0_DAT0 / UART6_nRTS / UART7_TXD / PWM0_CH4 / BPWM0_CH1 102 PE.2 / EBI_ALE / USCI0_CLK / UART6_nCTS / UART7_RXD / PWM0_CH5 / BPWM0_CH0 103 VSS 104 VDD Apr. 29, 2020 Page 152 of 283 Rev 2.01 M031/M032 M032KIAAE Pin Function 105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS 106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS 107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD 108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD 109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD 110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5 111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4 112 VSS 113 LDO_CAP 114 VDD 115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1 116 PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1 117 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 / TM1_EXT / CLKO 118 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / UART3_nRTS / PWM1_CH2 / TM2_EXT 119 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / UART3_nCTS / PWM1_CH3 / TM3_EXT 120 AVDD 121 VREF 122 AVSS 123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0 124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1 125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2 126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3 127 PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O 128 PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O Table 4.1-37 M032KIAAE Multi-function Pin Table Apr. 29, 2020 Page 153 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Pin M031/M032 4.2 Pin Mapping Different part number with the same package might have different function. Please refer to the selection guide in section 3.2, Pin Configuration in section 4.1 or NuTool - PinConfig. Corresponding Part Number: M031xB, M031xC, M031xD, M031xE, M031xG, M031xI, M032xC, M032xD, M032xE, M032xG, M032xI series. M031 Series Pin Name M032 Series 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PB.5 8 12 1 1 2 1 12 1 1 2 1 PB.4 9 13 2 2 3 2 13 2 2 3 2 PB.3 10 14 3 3 4 3 14 3 3 4 3 PB.2 11 15 4 4 5 4 15 4 4 5 4 PC.12 5 5 PC.11 6 6 PC.10 7 7 PC.9 8 8 PB.1 16 5 5 6 9 16 5 5 6 9 PB.0 17 6 6 7 10 17 6 6 7 10 VSS 11 11 VDD 12 12 M031/M032 SERIES DATASHEET PA.11 7 8 13 7 8 13 PA.10 8 9 14 8 9 14 PA.9 9 10 15 9 10 15 PA.8 10 11 16 10 11 16 PC.13 17 17 PD.12 18 18 PD.11 19 19 PD.10 20 20 PG.2 21 21 PG.3 22 22 PG.4 23 23 PF.11 24 24 PF.10 25 25 PF.9 26 26 PF.8 27 27 PF.7 28 28 PF.6 Apr. 29, 2020 12 29 Page 154 of 283 12 29 Rev 2.01 M031/M032 M031 Series Pin Name M032 Series 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PF.14 13 30 13 30 PF.5 7 11 14 31 7 11 14 31 PF.4 8 12 15 32 8 12 15 32 PH.4 33 33 PH.5 34 34 PH.6 35 35 PH.7 36 36 PF.3 12 18 9 13 16 37 11 18 9 13 16 37 PF.2 13 19 10 14 17 38 12 19 10 14 17 38 VSS 39 39 VDD 40 40 PE.8 41 41 PE.9 42 42 PE.10 43 43 PE.11 44 44 PE.12 45 45 PE.13 46 46 PC.8 47 47 18 48 18 48 PC.6 19 49 19 49 PA.7 15 20 50 15 20 50 PA.6 16 21 51 16 21 51 VSS 22 52 22 52 VDD 23 53 23 53 PD.15 24 54 24 54 PA.5 17 25 55 17 25 55 PA.4 18 26 56 18 26 56 PA.3 14 20 11 19 27 57 13 20 11 19 27 57 PA.2 15 21 12 20 28 58 14 21 12 20 28 58 PA.1 16 22 13 21 29 59 15 22 13 21 29 59 PA.0 17 23 14 22 30 60 16 23 14 22 30 60 15 23 31 61 15 23 31 61 PF.15 PE.14 62 62 PE.15 63 63 Apr. 29, 2020 Page 155 of 283 Rev 2.01 M031/M032 SERIES DATASHEET PC.7 M031/M032 M031 Series Pin Name nRESET M032 Series 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 18 24 16 24 32 64 17 24 16 24 32 64 19 25 17 25 33 65 18 25 17 25 33 65 20 26 18 26 34 66 19 26 18 26 34 66 PF.0 ICE_DAT PF.1 ICE_CLK PD.9 67 67 PD.8 68 68 PC.5 27 35 69 27 35 69 PC.4 28 36 70 28 36 70 PC.3 29 37 71 29 37 71 PC.2 30 38 72 30 38 72 PC.1 27 19 31 39 73 27 19 31 39 73 PC.0 28 20 32 40 74 28 20 32 40 74 M031/M032 SERIES DATASHEET VSS 75 75 VDD 76 76 PG.9 77 77 PG.10 78 78 PG.11 79 79 PG.12 80 80 PG.13 81 81 PG.14 82 82 PG.15 83 83 PD.7 84 84 PD.6 85 85 PD.5 86 86 PD.4 87 87 PD.3 41 88 41 88 PD.2 42 89 42 89 PD.1 43 90 43 90 PD.0 44 91 44 91 PD.13 92 92 NC NC NC Apr. 29, 2020 Page 156 of 283 Rev 2.01 M031/M032 M031 Series Pin Name M032 Series 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin NC PA.12 1 21 33 45 93 PA.13 2 22 34 46 94 PA.14 3 23 35 47 95 PA.15 4 24 36 48 96 USB_VBUS 20 1 21 33 45 93 USB_D- 1 2 22 34 46 94 USB_D+ 2 3 23 35 47 95 USB_VDD33_CAP 3 4 24 36 48 96 97 97 PE.6 98 98 PE.5 99 99 PE.4 100 100 PE.3 101 101 PE.2 102 102 VSS 103 103 VDD 104 104 PE.1 105 105 PE.0 106 106 PH.8 107 107 PH.9 108 108 PH.10 109 109 PH.11 110 110 PD.14 111 111 VSS 1 5 25 37 49 112 4 5 25 37 49 112 LDO_CAP 2 6 26 38 50 113 5 6 26 38 50 113 VDD 3 7 27 39 51 114 6 7 27 39 51 114 40 52 115 40 52 115 28 41 53 116 28 41 53 116 PC.14 PB.15 PB.14 4 8 29 42 54 117 7 8 29 42 54 117 PB.13 5 9 30 43 55 118 8 9 30 43 55 118 PB.12 6 10 31 44 56 119 9 10 31 44 56 119 AVDD 7 11 32 45 57 120 10 11 32 45 57 120 58 121 58 121 VREF Apr. 29, 2020 Page 157 of 283 Rev 2.01 M031/M032 SERIES DATASHEET PE.7 M031/M032 M031 Series Pin Name AVSS M032 Series 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 46 59 122 PB.11 60 PB.10 46 59 122 123 60 123 61 124 61 124 PB.9 62 125 62 125 PB.8 63 126 63 126 PB.7 47 64 127 47 64 127 PB.6 48 1 128 48 1 128 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 158 of 283 Rev 2.01 M031/M032 4.3 Group ACMP0 ACMP1 BPWM0 Pin Name Type Description ACMP0_N A Analog comparator 0 negative input pin. ACMP0_O O Analog comparator 0 output pin. ACMP0_P0 A Analog comparator 0 positive input 0 pin. ACMP0_P1 A Analog comparator 0 positive input 1 pin. ACMP0_P2 A Analog comparator 0 positive input 2 pin. ACMP0_P3 A Analog comparator 0 positive input 3 pin. ACMP0_WLAT I Analog comparator 0 window latch input pin ACMP1_N A Analog comparator 1 negative input pin. ACMP1_O O Analog comparator 1 output pin. ACMP1_P0 A Analog comparator 1 positive input 0 pin. ACMP1_P1 A Analog comparator 1 positive input 1 pin. ACMP1_P2 A Analog comparator 1 positive input 2 pin. ACMP1_P3 A Analog comparator 1 positive input 3 pin. ACMP1_WLAT I Analog comparator 1 window latch input pin ADC0_CH0 A ADC0 channel 0 analog input. ADC0_CH1 A ADC0 channel 1 analog input. ADC0_CH2 A ADC0 channel 2 analog input. ADC0_CH3 A ADC0 channel 3 analog input. ADC0_CH4 A ADC0 channel 4 analog input. ADC0_CH5 A ADC0 channel 5 analog input. ADC0_CH6 A ADC0 channel 6 analog input. ADC0_CH7 A ADC0 channel 7 analog input. ADC0_CH8 A ADC0 channel 8 analog input. ADC0_CH9 A ADC0 channel 9 analog input. ADC0_CH10 A ADC0 channel 10 analog input. ADC0_CH11 A ADC0 channel 11 analog input. ADC0_CH12 A ADC0 channel 12 analog input. ADC0_CH13 A ADC0 channel 13 analog input. ADC0_CH14 A ADC0 channel 14 analog input. ADC0_CH15 A ADC0 channel 15 analog input. ADC0_ST I ADC0 external trigger input pin. BPWM0_CH0 I/O BPWM0 channel 0 output/capture input. BPWM0_CH1 I/O BPWM0 channel 1 output/capture input. BPWM0_CH2 I/O BPWM0 channel 2 output/capture input. Apr. 29, 2020 Page 159 of 283 M031/M032 SERIES DATASHEET ADC0 Pin Function Description Rev 2.01 M031/M032 Group Pin Name Type Description BPWM0_CH3 I/O BPWM0 channel 3 output/capture input. BPWM0_CH4 I/O BPWM0 channel 4 output/capture input. BPWM0_CH5 I/O BPWM0 channel 5 output/capture input. BPWM1_CH0 I/O BPWM1 channel 0 output/capture input. BPWM1_CH1 I/O BPWM1 channel 1 output/capture input. BPWM1_CH2 I/O BPWM1 channel 2 output/capture input. BPWM1_CH3 I/O BPWM1 channel 3 output/capture input. BPWM1_CH4 I/O BPWM1 channel 4 output/capture input. BPWM1_CH5 I/O BPWM1 channel 5 output/capture input. CLKO O EBI_AD0 I/O EBI address/data bus bit 0. EBI_AD1 I/O EBI address/data bus bit 1. EBI_AD2 I/O EBI address/data bus bit 2. EBI_AD3 I/O EBI address/data bus bit 3. EBI_AD4 I/O EBI address/data bus bit 4. EBI_AD5 I/O EBI address/data bus bit 5. EBI_AD6 I/O EBI address/data bus bit 6. EBI_AD7 I/O EBI address/data bus bit 7. EBI_AD8 I/O EBI address/data bus bit 8. EBI_AD9 I/O EBI address/data bus bit 9. EBI_AD10 I/O EBI address/data bus bit 10. EBI_AD11 I/O EBI address/data bus bit 11. EBI_AD12 I/O EBI address/data bus bit 12. EBI_AD13 I/O EBI address/data bus bit 13. EBI_AD14 I/O EBI address/data bus bit 14. EBI_AD15 I/O EBI address/data bus bit 15. EBI_ADR0 O EBI address bus bit 0. EBI_ADR1 O EBI address bus bit 1. EBI_ADR2 O EBI address bus bit 2. EBI_ADR3 O EBI address bus bit 3. EBI_ADR4 O EBI address bus bit 4. EBI_ADR5 O EBI address bus bit 5. EBI_ADR6 O EBI address bus bit 6. EBI_ADR7 O EBI address bus bit 7. EBI_ADR8 O EBI address bus bit 8. EBI_ADR9 O EBI address bus bit 9. BPWM1 CLKO Clock Out M031/M032 SERIES DATASHEET EBI Apr. 29, 2020 Page 160 of 283 Rev 2.01 M031/M032 Group GPIO Pin Name Type Description O EBI address bus bit 10. EBI_ADR11 O EBI address bus bit 11. EBI_ADR12 O EBI address bus bit 12. EBI_ADR13 O EBI address bus bit 13. EBI_ADR14 O EBI address bus bit 14. EBI_ADR15 O EBI address bus bit 15. EBI_ADR16 O EBI address bus bit 16. EBI_ADR17 O EBI address bus bit 17. EBI_ADR18 O EBI address bus bit 18. EBI_ADR19 O EBI address bus bit 19. EBI_ALE O EBI address latch enable output pin. EBI_MCLK O EBI external clock output pin. EBI_nCS0 O EBI chip select 0 output pin. EBI_nCS1 O EBI chip select 1 output pin. EBI_nRD O EBI read enable output pin. EBI_nWR O EBI write enable output pin. EBI_nWRH O EBI high byte write enable output pin EBI_nWRL O EBI low byte write enable output pin. PA.x~PH.x I/O General purpose digital I/O pin. I2C0_SCL I/O I2C0 clock pin. I2C0_SDA I/O I2C0 data input/output pin. I2C0_SMBAL O I2C0 SMBus SMBALTER pin I2C0_SMBSUS O I2C0 SMBus SMBSUS pin (PMBus CONTROL pin) I2C1_SCL I/O I2C1 clock pin. I2C1_SDA I/O I2C1 data input/output pin. I2C0 I2C1 ICE_CLK ICE_DAT ICE nRESET Serial wired debugger clock pin Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin Serial wired debugger data pin I/O Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. I Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. I INT0 INT0 I External interrupt 0 input pin. INT1 INT1 I External interrupt 1 input pin. INT3 INT3 I External interrupt 3 input pin. INT4 INT4 I External interrupt 4 input pin. INT5 INT5 I External interrupt 5 input pin. PWM0 PWM0_BRAKE0 I PWM0 Brake 0 input pin. Apr. 29, 2020 Page 161 of 283 Rev 2.01 M031/M032 SERIES DATASHEET EBI_ADR10 M031/M032 Group Pin Name PWM0_BRAKE1 Type Description I PWM0 Brake 1 input pin. PWM0_CH0 I/O PWM0 channel 0 output/capture input. PWM0_CH1 I/O PWM0 channel 1 output/capture input. PWM0_CH2 I/O PWM0 channel 2 output/capture input. PWM0_CH3 I/O PWM0 channel 3 output/capture input. PWM0_CH4 I/O PWM0 channel 4 output/capture input. PWM0_CH5 I/O PWM0 channel 5 output/capture input. PWM1_BRAKE0 I PWM1 Brake 0 input pin. PWM1_BRAKE1 I PWM1 Brake 1 input pin. PWM1_CH0 I/O PWM1 channel 0 output/capture input. PWM1_CH1 I/O PWM1 channel 1 output/capture input. PWM1_CH2 I/O PWM1 channel 2 output/capture input. PWM1_CH3 I/O PWM1 channel 3 output/capture input. PWM1_CH4 I/O PWM1 channel 4 output/capture input. PWM1_CH5 I/O PWM1 channel 5 output/capture input. PWM1 Power M031/M032 SERIES DATASHEET VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. VSS P Ground pin for digital circuit. AVDD P Power supply for internal analog circuit. AVSS P Ground pin for analog circuit. VREF A ADC reference voltage input. Note: This pin needs to be connected with a 1uF capacitor. LDO_CAP A LDO output pin. Note: This pin needs to be connected with a 1uF capacitor. QSPI0_CLK I/O Quad SPI0 serial clock pin. QSPI0_MISO0 I/O Quad SPI0 MISO0 (Master In, Slave Out) pin. QSPI0_MISO1 I/O Quad SPI0 MISO1 (Master In, Slave Out) pin. QSPI0_MOSI0 I/O Quad SPI0 MOSI0 (Master Out, Slave In) pin. QSPI0_MOSI1 I/O Quad SPI0 MOSI1 (Master Out, Slave In) pin. QSPI0_SS I/O Quad SPI0 slave select pin. SPI0_CLK I/O SPI0 serial clock pin. SPI0_I2SMCLK I/O SPI0 I2S master clock output pin SPI0_MISO I/O SPI0 MISO (Master In, Slave Out) pin. SPI0_MOSI I/O SPI0 MOSI (Master Out, Slave In) pin. SPI0_SS I/O SPI0 slave select pin. TM0 I/O Timer0 event counter input/toggle output pin. TM0_EXT I/O Timer0 external capture input/toggle output pin. TM1 I/O Timer1 event counter input/toggle output pin. QSPI0 SPI0 TM0 TM1 Apr. 29, 2020 Page 162 of 283 Rev 2.01 M031/M032 Group Pin Name Type Description TM1_EXT I/O Timer1 external capture input/toggle output pin. TM2 I/O Timer2 event counter input/toggle output pin. TM2_EXT I/O Timer2 external capture input/toggle output pin. TM3 I/O Timer3 event counter input/toggle output pin. TM3_EXT I/O Timer3 external capture input/toggle output pin. TM2 TM3 UART0_RXD I UART0 data receiver input pin. UART0_TXD O UART0 data transmitter output pin. UART0_nCTS I UART0 clear to Send input pin. UART0_nRTS O UART0 request to Send output pin. UART1_RXD I UART1 data receiver input pin. UART1_TXD O UART1 data transmitter output pin. UART1_nCTS I UART1 clear to Send input pin. UART1_nRTS O UART1 request to Send output pin. UART2_RXD I UART2 data receiver input pin. UART2_TXD O UART2 data transmitter output pin. UART2_nCTS I UART2 clear to Send input pin. UART2_nRTS O UART2 request to Send output pin. UART3_RXD I UART3 data receiver input pin. UART3_TXD O UART3 data transmitter output pin. UART3_nCTS I UART3 clear to Send input pin. UART3_nRTS O UART3 request to Send output pin. UART4_RXD I UART4 data receiver input pin. UART4_TXD O UART4 data transmitter output pin. UART4_nCTS I UART4 clear to Send input pin. UART4_nRTS O UART4 request to Send output pin. UART5_RXD I UART5 data receiver input pin. UART5_TXD O UART5 data transmitter output pin. UART5_nCTS I UART5 clear to Send input pin. UART5_nRTS O UART5 request to Send output pin. UART6_RXD I UART6 data receiver input pin. UART6_TXD O UART6 data transmitter output pin. UART6_nCTS I UART6 clear to Send input pin. UART6_nRTS O UART6 request to Send output pin. UART7_RXD I UART7 data receiver input pin. UART7_TXD O UART7 data transmitter output pin. UART7_nCTS I UART7 clear to Send input pin. UART0 UART1 UART2 UART3 M031/M032 SERIES DATASHEET UART4 UART5 UART6 UART7 Apr. 29, 2020 Page 163 of 283 Rev 2.01 M031/M032 Group Pin Name Type Description UART7_nRTS O UART7 request to Send output pin. USB_VBUS P Power supply from USB host or HUB. USB_D- A USB differential signal D-. USB_D+ A USB differential signal D+. USB_VDD33_CAP A Internal power regulator output 3.3V decoupling pin. USB USCI0 USCI1 USCI0_CLK I/O USCI0 clock pin. USCI0_CTL0 I/O USCI0 control 0 pin. USCI0_CTL1 I/O USCI0 control 1 pin. USCI0_DAT0 I/O USCI0 data 0 pin. USCI0_DAT1 I/O USCI0 data 1 pin. USCI1_CLK I/O USCI1 clock pin. USCI1_CTL0 I/O USCI1 control 0 pin. USCI1_CTL1 I/O USCI1 control 1 pin. USCI1_DAT0 I/O USCI1 data 0 pin. USCI1_DAT1 I/O USCI1 data 1 pin. X32_IN I External 32.768 kHz crystal input pin. X32_OUT O External 32.768 kHz crystal output pin. XT1_IN I External 4~24 MHz (high speed) crystal input pin. XT1_OUT O External 4~24 MHz (high speed) crystal output pin. X32 XT1 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 164 of 283 Rev 2.01 M031/M032 5 BLOCK DIAGRAM USB*: Only supported in the M032 series. ® Figure 5-1 NuMicro M031/M032 Block Diagram M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 165 of 283 Rev 2.01 M031/M032 6 FUNCTIONAL DESCRIPTION 6.1 Arm® Cortex® -M0 Core ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ® functionality. The processor can execute Thumb code and is compatible with other Cortex -M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. Cortex-M0 Components Cortex-M0 Processor Debug Nested Vectored Interrupt Controller (NVIC) Interrupts Wakeup Interrupt Controller (WIC) Cortex-M0 Processor Core Breakpoint and Watchpoint Unit Bus matrix Debugger interface AHB-Lite interface Debug Access Port (DAP) Serial Wire or JTAG debug port Figure 6-1 Functional Block Diagram M031/M032 SERIES DATASHEET The implemented device provides:   A low gate count processor: ® ® – Arm 6-M Thumb instruction set – Thumb-2 technology – Arm 6-M compliant 24-bit SysTick timer – A 32-bit hardware multiplier – System interface supported with little-endian data accesses – Ability to have deterministic, fixed-latency, interrupt handling – Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling – C Application Binary Interface compliant exception model. This is the Armv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers – Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or return from interrupt sleep-on-exit feature ® NVIC: – Apr. 29, 2020 32 external interrupt inputs, each with four levels of priority Page 166 of 283 Rev 2.01 M031/M032   – Dedicated Non-maskable Interrupt (NMI) input – Supports for both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode Debug support: – Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling – Single step and vector catch capabilities Bus interfaces: – Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory – Single 32-bit slave port that supports the DAP (Debug Access Port) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 167 of 283 Rev 2.01 M031/M032 6.2 Clock Controller 6.2.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode ® until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~32 MHz external high speed crystal (HXT), 48 MHz internal high speed RC oscillator (HIRC) and Programmable PLL output clock frequency (PLLFOUT) to reduce the overall system power consumption.Figure 6.2-1 and Figure 6.2-2 shows the clock generator and the overview of the clock source control. M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 168 of 283 Rev 2.01 M031/M032 HIRC 48MHz HXT 4~32MHz LXT 32.768 kHz LIRC 38.4 kHz /1,/2,/4,/8,/16 PCLK0 I2C0 PCLK1 ACMP ADC PWM0 HIRC 1/4 1 PLLFOUT PLL FOUT HXT BPWM0 I2C1 TMR0 PWM1 TMR1 BPWM1 UART0 TMR2 0 CLK_PLLCTL[19] CPU CRC HIRC 111 LIRC EBI 011 PLLFOUT LXT HXT FMC HCLK 1/(HCLKDIV+1) 010 TMR3 UART4 UART1 UART6 UART3 WDT UART5 QSPI0 UART7 PDMA 001 SRAM 000 HDIV CLK_CLKSEL0[2:0] USCI0 SPI0 USBD USCI1 /1,/2,/4,/8,/16 LIRC HCLK UART2 11 1/2048 LIRC 10 LXT RTC WDT 11 WWDT HCLK 1/2048 10 01 CLK_CLKSEL1[3:2] CLK_CLKSEL1[1:0] LIRC LIRC 101 PCLK0/PCLK1 HIRC LXT PLLOUT HXT 100 PCLK0/PCLK1 UART0 1/(UART0DIV+1) HIRC 011 1/(UART1DIV+1) UART1 010 1/(UART2DIV+1) UART2 PLLOUT 1/(UART3DIV+1) UART3 HXT LXT 001 000 CLK_CLKSEL1[26:24] CLK_CLKSEL1[30:28] CLK_CLKSEL3[26:24] CLK_CLKSEL3[30:28] HCLK HXT 1/(UART4DIV+1) UART4 011 1/(UART5DIV+1) UART5 010 1/(UART6DIV+1) UART6 1/(UART7DIV+1) UART7 100 001 000 CLK_CLKSEL3[18:16] CLK_CLKSEL3[22:20] CLK_CLKSEL3[10: 8] CLK_CLKSEL3[14:12] 1/2 111 1/2 011 1/2 010 USBDSEL (CLK_CLKSEL0[8]) CPUCLK 1 HIRC SysTick LXT 001 HXT 0 PLLFOUT /(USBDIV + 1) 48MHz 0 1 USB1.1 Device Controller SYST_CTRL[2] 000 CLK_CLKSEL0[5:3] PLLFOUT HIRC LIRC HIRC HCLK LXT HXT DIV1EN (CLK_CLKOCTL[5]) 110 CLK1HZEN (CLK_CLKOCTL[6]) 101 100 PCLK1 0 0 011 1 010 CLKO 1 001 000 CLK_CLKSEL1[6:4] LIRC LXT HIRC 11 /2 (CLK_CLKOCTL[3:0]+1) 10 1/(ADCDIV + 1) PLLFOUT 01 HXT 00 ADC ADCSEL (CLKSEL2[21:20]) 0 1 Hz clock from RTC /32768 1 RTCSEL(CLK_CLKSEL3[8]) Figure 6.2-1 Clock Generator Global View Diagram (1/2) Apr. 29, 2020 Page 169 of 283 Rev 2.01 M031/M032 SERIES DATASHEET HIRC 101 M031/M032 HIRC LIRC TM0/TM1 HIRC 111 LIRC 101 011 PCLK0 LXT 010 PCLK1 LXT 001 HXT HXT 000 HIRC 11 PCLK1 PLLFOUT HXT 1/(SPI0_CLKDIV[8:0]+1) 01 00 PCLK0 LXT PLLFOUT 10 1/(QSPI0_CLKDIV[8:0]+1) QSPI0 01 00 PCLK1 1 PWM 0 PLLFOUT 0 1 PWM 1 0 CLK_CLKSEL2[1] PCLK1 1 BPWM 0 PLLFOUT 0 CLK_CLKSEL2[8] LIRC 000 CLK_CLKSEL2[3:2] CLK_CLKSEL2[0] PLLFOUT SPI0 HXT CLK_CLKSEL2[5:4] PCLK0 001 11 PCLK1 10 PLLFOUT TMR2 TMR3 010 CLK_CLKSEL1 [18:16] CLK_CLKSEL1[22:20] CLK_CLKSEL1 [10:8] CLK_CLKSEL1[14:12] HIRC 101 011 TM2/TM3 TMR0 TMR1 111 1 BPWM 1 0 CLK_CLKSEL2[9] 1 RTC 0 M031/M032 SERIES DATASHEET CLK_CLKSEL3[8] Figure 6.2-2 Clock Generator Global View Diagram (2/2) 6.2.2 Clock Generator The clock generator consists of 6 clock sources, which are listed below:  32.768 kHz external low speed crystal oscillator (LXT)  4~32 MHz external high speed crystal oscillator (HXT)  Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from external 4~32 MHz external high speed crystal (HXT) or 48 MHz internal high speed oscillator (HIRC/4)  48 MHz internal high speed RC oscillator (HIRC)  38.4 kHz internal low speed RC oscillator (LIRC) Apr. 29, 2020 Page 170 of 283 Rev 2.01 M031/M032 LXTEN (CLK_PWRCTL[1]) X32_IN External 32.768 kHz Crystal (LXT) LXT X32_OUT HXTEN (CLK_PWRCTL[0]) HXT XT1_IN External 4~32 MHz Crystal (HXT) XT1_OUT PLLSRC (CLK_PLLCTL[19]) HIRCEN (CLK_PWRCTL[2]) 0 PLL FOUT PLL 1 Internal 48 MHz Oscillator (HIRC) /4 LIRCEN (CLK_PWRCTL[3]) Internal 38.4 kHz Oscillator (LIRC) HIRC LIRC Figure 6.2-3 Clock Generator Block Diagram M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 171 of 283 Rev 2.01 M031/M032 6.2.3 System Clock and SysTick Clock The system clock has 5 clock sources, which were generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in Figure 6.2-4 HCLKSEL (CLK_CLKSEL0[2:0]) HIRC LIRC PLLFOUT LXT HXT 111 CPUCLK 011 1/(HCLK_N+1) 1/(HCLKDIV+1) HCLKDIV (CLK_CLKDIV0[3:0]) 010 001 000 CPU in Power Down Mode HCLK PCLK0 PCLK1 CPU AHB APB0 APB1 Figure 6.2-4 System Clock Block Diagram There are two clock fail detectors to observe HXT and LXT clock source and they have individual enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically. When LXT detector is enabled, the LIRC clock is enabled automatically. M031/M032 SERIES DATASHEET When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop being detected on the following condition: system clock source comes from HXT or system clock source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIEN (CLK_CLKDCTL[5]) is set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again. The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.2-5. Apr. 29, 2020 Page 172 of 283 Rev 2.01 M031/M032 Set HXTFDEN To enable HXT clock detector NO HXTFIF = 1? YES System clock source = “HXT” or “PLL with HXT” ? NO System clock keep original clock YES Switch system clock to HIRC Figure 6.2-5 HXT Stop Protect Procedure The LXT clock stop detect and system clock switch to LIRC procedure is shown in Figure 6.2-6. Apr. 29, 2020 Page 173 of 283 Rev 2.01 M031/M032 SERIES DATASHEET When LXT clock detector is enabled, the system clock will auto switch to LIRC if LXT clock stop being detected when system clock source comes from LXT. If LXT clock stop condition is detected, the LXTFIF (CLK_CLKDSTS[1]) is set to 1 and chip will enter interrupt if LXTFIEN (CLK_CLKDCTL[13]) is set to 1. User can trying to recover LXT by disable LXT and enable LXT again to check if the clock stable bit is set to 1 or not. If LXT clock stable bit is set to 1, it means LXT is recover to oscillate after re-enable action and user can switch system clock to LXT again. M031/M032 Set LXTFDEN To enable LXT clock detector NO LXTFIF = 1? YES System clock source = “LXT ? System clock keep original clock NO YES Switch system clock to LIRC Figure 6.2-6 LXT Stop Protect Procedure ® M031/M032 SERIES DATASHEET The clock source of SysTick in Cortex -M0 core can use CPU clock or external clock (SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown in Figure 6.2-7. STCLKSEL (CLK_CLKSEL0[5:3]) HIRC HCLK HXT LXT HXT 1/2 111 1/2 011 1/2 010 STCLK 001 000 Figure 6.2-7 SysTick Clock Control Block Diagram 6.2.4 Peripherals Clock The peripherals clock has different clock source switch setting, which depends on the different peripheral. Please refer to the CLK_CLKSELx register description. 6.2.5 Power-down Mode Clock Apr. 29, 2020 Page 174 of 283 Rev 2.01 M031/M032 When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are disabled. Some clock sources and peripherals clock are still active in Power-down mode. For theses clocks, which still keep active, are listed below:   6.2.6 Clock Generator – 38.4 kHz internal low speed RC oscillator (LIRC) clock – 32.768 kHz external low speed crystal oscillator (LXT) clock Peripherals Clock (When the modules adopt LXT or LIRC as clock source) Clock Output This device is equipped with a power-of-2 frequency divider which is composed by16 chained divideby-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the 1 16 frequency from Fin/2 to Fin/2 where Fin is input clock frequency to the clock divider. (N+1) The output formula is Fout = Fin/2 , where Fin is the input clock frequency, Fout is the clock divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]). When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and stays in low state. CLKOEN (CLK_CLKOCTL[4]) PLL LIRC HIRC HCLK HXT 1/2 1/22 FREQSEL (CLK_CLKOCTL[3:0]) 16 chained divide-by-2 counter 1/23 …... 1/215 DIV1EN (CLK_CLKOCTL[5]) 1/216 110 0000 0001 : : 1110 1111 100 011 010 CLK1HZEN (CLK_CLKOCTL[6]) 16 to 1 MUX 0 0 CLKO 1 1 M031/M032 SERIES DATASHEET LXT Enable divide-by-2 counter 001 000 RTCSEL(CLK_CLKSEL3[8]) CLKOSEL (CLK_CLKSEL1[6:4]) LIRC 0 /32768 LXT 1 Hz clock from RTC 1 Figure 6.2-8 Clock Output Block Diagram 6.2.7 USB Clock Source The clock source of USBD is generated from 48 MHz HIRC or programmable PLL output. The generated clocks are shown in Figure 6.2-9. USBDIV is the clock divider output frequency, the output formula is (PLLFOUT frequency) / (USBDIV + 1). Apr. 29, 2020 Page 175 of 283 Rev 2.01 M031/M032 PLLFOUT /(USBDIV + 1) HIRC48M USB Device Controller USBDSEL Figure 6.2-9 USBD Clock Source M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 176 of 283 Rev 2.01 M031/M032 6.3 System Manager 6.3.1 Overview System management includes the following sections: 6.3.2  System Reset  System Power Distribution  SRAM Memory Orginization  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control register System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from peripheral signals. Software reset can trigger reset through setting control registers.  – Power-on Reset – Low level on the nRESET pin – Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset) – Low Voltage Reset (LVR) – Brown-out Detector Reset (BOD Reset) – CPU Lockup Reset Software Reset Sources – CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0]) – MCU Reset to reboot but keeping the booting setting from APROM or LDROM by writing 1 to SYSRESETREQ (AIRCR[2]) – CPU Reset for Cortex -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1]) – nRESET glitch filter time 32us Apr. 29, 2020 ® Page 177 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  Hardware Reset Sources M031/M032 Glitch Filter 32 us nRESET ~50k ohm @3.3v VDD POROFF(SYS_PORCTL[15:0]) Power-on Reset LVREN(SYS_BODCTL[7]) AVDD Reset Pulse Width ~3.2ms Low Voltage Reset BODRSTEN(SYS_BODCTL[3]) Brown-out Reset WDT/WWDT Reset Reset Pulse Width 64 WDT clocks CPU Lockup Reset Reset Pulse Width 2 system clocks System Reset CHIP Reset CHIPRST(SYS_IPRST0[0]) MCU Reset SYSRSTREQ(AIRCR[2]) Software Reset Reset Pulse Width 2 system clocks CPU Reset CPURST(SYS_IPRST0[1]) Figure 6.3-1 System Reset Sources ® There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset ® ® Cortex -M0 only; the other reset sources will reset Cortex -M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6.3-1. Reset Sources M031/M032 SERIES DATASHEET Register POR nRESET WDT LVR BOD Lockup CHIP MCU CPU SYS_RSTSTS 0x001 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 CHIPRST 0x0 - - - - - - - - Reload from CONFIG0 Reload Reload Reload from from from CONFIG0 CONFIG0 CONFIG0 (CLK_PWRCTL[0]) Reload from CONFIG0 Reload Reload Reload Reload Reload Reload from from from from from from CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 Reload from CONFIG0 LXTEN 0x0 - - - - - - - - 0x0 - - - - - - - - 0x1 - - - - - - - - (SYS_IPRST0[0]) BODEN (SYS_BODCTL[0]) Reload Reload from from CONFIG0 CONFIG0 Reload from CONFIG0 BODVL (SYS_BODCTL[16]) BODRSTEN (SYS_BODCTL[3]) HXTEN (CLK_PWRCTL[1]) LXTSELXT (CLK_PWRCTL[24]) LXTGAIN Apr. 29, 2020 Page 178 of 283 Rev 2.01 M031/M032 (CLK_PWRCTL[25:26]) WDTCKEN 0x1 - 0x1 - - - 0x1 - - Reload from CONFIG0 Reload Reload Reload Reload Reload Reload from from from from from from CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 Reload from CONFIG0 0x3 0x3 - - - - - - - 0x0 - - - - - - - - 0x0 - - - - - - - - 0x0 - - - - - - - - 0x0 - - - - - - - - 0x0 0x0 - - - - - - - Reload from CONFIG0 Reload Reload Reload Reload from from from from CONFIG0 CONFIG0 CONFIG0 CONFIG0 Reload from CONFIG0 - - 0x0700 0x0700 0x0700 0x0700 0x0700 - 0x0700 - - WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - 0x3F0800 - - WWDT_STATUS 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_CNT 0x3F 0x3F 0x3F 0x3F 0x3F - 0x3F - - BS Reload from CONFIG0 Reload Reload Reload Reload from from from from CONFIG0 CONFIG0 CONFIG0 CONFIG0 Reload from CONFIG0 - - FMC_DFBA Reload from CONFIG1 Reload Reload Reload Reload from from from from CONFIG1 CONFIG1 CONFIG1 CONFIG1 Reload from CONFIG1 - - CBS Reload from CONFIG0 Reload Reload Reload Reload from from from from CONFIG0 CONFIG0 CONFIG0 CONFIG0 Reload from CONFIG0 - - Reload base on CONFIG0 - (CLK_APBCLK0[0]) HCLKSEL (CLK_CLKSEL0[2:0]) WDTSEL (CLK_CLKSEL1[1:0]) HXTSTB (CLK_STATUS[0]) LXTSTB (CLK_STATUS[1]) PLLSTB (CLK_STATUS[2]) HIRCSTB (CLK_STATUS[4]) CLKSFAIL (CLK_STATUS[7]) RSTEN (WDT_CTL[1]) WDTEN (WDT_CTL[7]) WDT_CTL except bit 1 and bit 7. (FMC_ISPSTS[2:1)) VECMAP (FMC_ISPSTS[23:9]) Other Peripheral Registers Apr. 29, 2020 Reload Reload Reload Reload Reload base on base on base on base on base on CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 Reset Value - Page 179 of 283 Rev 2.01 M031/M032 SERIES DATASHEET (FMC_ISPCTL[1]) M031/M032 FMC Registers Reset Value Note: ‘-‘ means that the value of register keeps original setting. Table 6.3-1 Reset Value of Registers 6.3.2.1 nRESET Reset The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 V DD and the state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Table 6.3-2 shows the nRESET reset waveform. nRESET 0.7 VDD 32 us 0.2 VDD 32 us nRESET Reset Figure 6.3-2 nRESET Reset Waveform M031/M032 SERIES DATASHEET 6.3.2.2 Power-on Reset (POR) The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.3-3 shows the power-on reset waveform. VPOR 0.1V VDD Power-on Reset Figure 6.3-3 Power-on Reset (POR) Waveform Apr. 29, 2020 Page 180 of 283 Rev 2.01 M031/M032 6.3.2.3 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN (SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch function. Figure 6.3-4 shows the Low Voltage Reset waveform. AVDD VLVR T1 ( < LVRDGSEL) T2 ( =LVRDGSEL) T3 ( =LVRDGSEL) Low Voltage Reset 200 us Delay for LVR stable LVREN 6.3.2.4 Brown-out Detector Reset (BOD Reset) If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation. When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL (SYS_BODCTL[16]) and the state keeps longer than De-glitch time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user configuration register CBODEN (CONFIG0 [19]), CBOV (CONFIG0 [23:21]) and CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure 6.3-5 shows the Brown-out Detector waveform. Apr. 29, 2020 Page 181 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Figure 6.3-4 Low Voltage Reset (LVR) Waveform M031/M032 AVDD VBODH VBODL Hysteresis T1 (< BODDGSEL) T2 (= BODDGSEL) BODOUT T3 (= BODDGSEL) BODRSTEN Brown-out Reset Figure 6.3-5 Brown-out Detector (BOD) Waveform 6.3.2.5 Watchdog Timer Reset (WDT) M031/M032 SERIES DATASHEET In most industrial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog time-out. User may decide to enable system reset during watchdog time-out to recover the system and take action for the system crash/out-of-control after reset. Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a watchdog reset and handle the failure of MCU after watchdog time-out reset by checking WDTRF(SYS_RSTSTS[2]). 6.3.2.6 CPU Lockup Reset CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate indication of seriously errant kernel software. This is the result of the CPU being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored. 6.3.2.7 CPU Reset, CHIP Reset and MCU Reset ® The CPU Reset means only Cortex -M0 core is reset and all other peripherals remain the same status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal. The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal. The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset. Apr. 29, 2020 Page 182 of 283 Rev 2.01 M031/M032 6.3.3 System Power Distribution In this chip, power distribution is divided into three segments:  Analog power from AVDD and AVSS provides the power for analog components operation.  Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1.8V power for digital operation and I/O pins.  USB transceiver power from VBUS offers the power for operating the USB transceiver. The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be ® located close to the corresponding pin. Figure 6.3-6 shows the NuMicro M031 power distribution. USB Transceiver AVSS Brown-out Detector Low Voltage Reset SRAM LDO_CAP Flash 3.3V VDD33 1uF 5V to 3.3V LDO VBUS Digital Logic 1.8V 1uF POR18 VDD to 1.8V LDO Power On Control 32.768 kHz crystal oscillator X32_IN (PF.5) X32_OUT (PF.4) IO Cell VDD POR33 38.4 kHz LIRC Oscillator M031/M032 SERIES DATASHEET XT1_OUT (PF.2) 4~32 MHz crystal oscillator 48 MHz HIRC48 Oscillator VSS PLL XT1_IN (PF.3) D- Analog Comparator 12-bit ADC AVDD D+ ® Figure 6.3-6 NuMicro M031 Power Distribution Diagram 6.3.4 Power Modes and Wake-up Sources The M031/M032 series has power manager unit to support several operating modes for saving power. Table 6.3-2 lists all power mode in the M031/M032 series. Mode CPU Operating Maximum Speed (MHz) LDO_CAP(V) Clock Disable Normal mode 72 MHz at 2.0V-3.6V 1.8 All clocks are disabled by control register. Apr. 29, 2020 Page 183 of 283 Rev 2.01 M031/M032 48 MHz at 1.8V-3.6V Idle mode CPU enter Sleep mode 1.8 Only CPU clock is disabled. Power-down mode CPU enters Power-down mode 1.8 Most clocks are disabled except LIRC/LXT, and only WDT/Timer/UART/RTC peripheral clocks still enable if their clock sources are selected as LIRC/LXT. Table 6.3-2 Power Mode Table There are different power mode entry settings and leaving condition for each power mode. Table 6.3-3 shows the entry setting for each power mode. When chip power-on, chip is running in normal mode. User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT:[7]) and execute WFI instruction. Register/Instruction SLEEPDEEP PDEN Mode (SCR[2]) (CLK_PWRCTL[7]) CPU Run WFI Instruction Normal mode 0 0 NO Idle mode 0 0 YES 1 1 YES (CPU enter Sleep mode) Power-down mode (CPU enters mode) Deep Sleep Table 6.3-3 Power Mode Difference Table There are several wake-up sources in Idle mode and Power-down mode. Table 6.3-4 lists the available clocks for each power mode. M031/M032 SERIES DATASHEET Power Mode Normal Mode Idle Mode Power-Down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and LIRC. SRAM content retended. Entry Condition Chip is in normal mode after system reset released CPU executes WFI instruction. CPU sets sleep mode enable and power down enable and executes WFI instruction. Wake-up Sources N/A All interrupts WDT, I²C, Timer, UART, BOD, GPIO, EINT, USCI, USBD, ACMP, and RTC Available Clocks All All except CPU clock LXT and LIRC After Wake-up N/A CPU back to normal mode CPU back to normal mode Table 6.3-4 Power Mode Difference Table Apr. 29, 2020 Page 184 of 283 Rev 2.01 M031/M032 System reset released Normal Mode CPU Clock ON HXT , HIRC , LXT , LIRC , HCLK , PCLK ON Flash ON CPU executes WFI Interrupts occur 1. SLEEPDEEP (SCS_SCR[2]) = 1 2. PDEN (CLK_PWRCTL[7]) = 1 and PDWKIF (CLK_PWRCTL[6]) = 1 3. CPU executes WFI Idle Mode CPU Clock OFF HXT , HIRC , LXT , LIRC , HCLK , PCLK ON Flash Halt Wake-up events occur Power-down Mode CPU Clock OFF HXT , HIRC , HCLK , PCLK OFF LXT, LIRC ON Flash Halt Figure 6.3-7 Power Mode State Machine 1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode. 2. LIRC (38.4 kHz OSC) ON or OFF depends on S/W setting in normal mode. 3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on. 4. If WDT clock source is selected as LIRC and LIRC is on. 5. If UART clock source is selected as LXT and LXT is on. 6. If RTC clock source is selected as LIRC/LXT and LIRC/LXT is on. Idle Mode Power-Down Mode HXT (4~32 MHz XTL) ON ON Halt HIRC48 (48 MHz OSC) ON ON Halt LXT (32768 Hz XTL) ON ON ON/OFF1 LIRC (38.4 kHz OSC) ON ON ON/OFF2 PLL ON/OFF ON/OFF Halt LDO ON ON ON CPU ON Halt Halt HCLK/PCLK ON ON Halt SRAM retention ON ON ON FLASH ON ON Halt GPIO ON ON Halt PDMA ON ON Halt TIMER ON ON ON/OFF3 PWM ON ON Halt BPWM ON ON Halt Apr. 29, 2020 Page 185 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Normal Mode M031/M032 WDT ON ON ON/OFF4 WWDT ON ON Halt UART ON ON ON/OFF5 USCI ON ON Halt IC ON ON Halt SPI ON ON Halt QSPI ON ON Halt USBD ON ON Halt ADC ON ON Halt ACMP ON ON Halt RTC ON ON ON/OFF6 2 Table 6.3-5 Clocks in Power Modes Wake-up sources in Power-down mode: WDT, I²C, Timer, UART, USCI, BOD, GPIO, USBD, ACMP, and RTC. After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table 6.3-5 lists the condition about how to enter Power-down mode again for each peripheral. *User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter Power-down mode. Wake-Up Wake-Up Condition Source M031/M032 SERIES DATASHEET BOD System Can Enter Power-Down Mode Again Condition* Brown-Out Detector Interrupt After software writes 1 to clear (SYS_BODCTL[4]). INT External Interrupt After software write 1 to clear the Px_INTSRC[n] bit. GPIO GPIO Interrupt After software write 1 to clear the Px_INTSRC[n] bit. Timer Interrupt After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF (TIMERx_INTSTS[0]). WDT WDT Interrupt After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect). RTC Alarm Interrupt After software writes 1 to clear ALMIF (RTC_INTSTS[0]). Time Tick Interrupt After software writes 1 to clear TICKIF (RTC_INTSTS[1]). TIMER UART0/1/4/5 nCTS wake-up After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]). Incoming Data wake-up After software writes 1 to clear DATWKF (UARTx_WKSTS[1]). Received FIFO Threshold Wake-up After software writes 1 to clear RFRTWKF (UARTx_WKSTS[2]). RS-485 AAD Mode Wake-up After software writes 1 to clear RS485WKF (UARTx_WKSTS[3]). Received FIFO Threshold Time-out Wake-up After software writes 1 to clear TOUTWKF (UARTx_WKSTS[4]). nCTS wake-up After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]). Incoming Data wake-up After software writes 1 to clear DATWKF (UARTx_WKSTS[1]). UART2/3/6/7 Apr. 29, 2020 Page 186 of 283 Rev 2.01 M031/M032 CTS Toggle After software writes 1 to clear WKF (UUART_WKSTS[0]). Data Toggle After software writes 1 to clear WKF (UUART_WKSTS[0]). Data toggle After software writes 1 to clear WKF (UI2C_WKSTS[0]). USCI UART USCI I2C After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], and then writes 1 to clear WKF (UI2C_WKSTS[0]). Address match USCI SPI SS Toggle After software writes 1 to clear WKF (USPI_WKSTS[0]). IC Address match After software writes 1 to clear WKIF (I2C_WKSTS[0]). USBD Remote Wake-up ACMP Comparator Power-Down Wake-Up Interrupt 2 After software writes 1 to clear BUSIF (USBD_INTSTS[0]). After software writes 1 to clear WKIF0 (ACMP_STATUS[8]) and WKIF1 (ACMP_STATUS[9]). Table 6.3-6 Condition of Entering Power-down Mode Again 6.3.5 System Memory Map ® The NuMicro M031/M032 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown inTable 6.3-7. The detailed register definition, memory space, and programming will be described in the following sections for each on-chip peripheral. The M031/M032 series only supports little-endian data format. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0007_FFFF FLASH_BA FLASH Memory Space (512 Kbytes) 0x2000_0000 – 0x2001_7FFF SRAM0_BA SRAM Memory Space (96 Kbytes) 0x6000_0000 – 0x6FFF_FFFF EXTMEM_BA External Memory Space (256 Mbytes) 0x4000_0000 – 0x4000_01FF SYS_BA System Control Registers 0x4000_0200 – 0x4000_02FF CLK_BA Clock Control Registers 0x4000_0300 – 0x4000_03FF NMI_BA NMI Control Registers 0x4000_4000 – 0x4000_4FFF GPIO_BA GPIO Control Registers 0x4000_8000 – 0x4000_8FFF PDMA_BA Peripheral DMA Control Registers 0x4000_C000 – 0x4000_CFFF FMC_BA Flash Memory Control Registers 0x4001_0000 – 0x4001_0FFF EBI_BA External Bus Interface Control Registers 0x4001_4000 – 0x4001_7FFF HDIV_BA Hardware Divider Register 0x4003_1000 – 0x4003_1FFF CRC_BA CRC Generator Registers M031/M032 SERIES DATASHEET Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF) APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4004_0000 – 0x4004_0FFF WDT_BA Watchdog Timer Control Registers 0x4004_1000 – 0x4004_1FFF RTC_BA RTC Control Registers 0x4004_3000 – 0x4004_3FFF ADC_BA Analog-Digital-Converter (ADC) Control Registers 0x4004_5000 – 0x4004_5FFF ACMP01_BA Analog Comparator 0/ 1 Control Registers 0x4005_0000 – 0x4005_0FFF TMR01_BA Timer0/Timer1 Control Registers Apr. 29, 2020 Page 187 of 283 Rev 2.01 M031/M032 0x4005_1000 – 0x4005_1FFF TMR23_BA Timer2/Timer3 Control Registers 0x4005_8000 – 0x4005_8FFF PWM0_BA PWM0 Control Registers 0x4005_9000 – 0x4005_9FFF PWM1_BA PWM1 Control Registers 0x4005_A000 – 0x4005_AFFF BPWM0_BA BPWM0 Control Registers 0x4005_B000 – 0x4005_BFFF BPWM1_BA BPWM1 Control Registers 0x4006_0000 – 0x4006_0FFF QSPI0_BA QSPI0 Control Registers 0x4006_1000 – 0x4006_1FFF SPI0_BA SPI0 Control Registers 0x4007_0000 – 0x4007_0FFF UART0_BA UART0 Control Registers 0x4007_1000 – 0x4007_1FFF UART1_BA UART1 Control Registers 0x4007_2000 – 0x4007_2FFF UART2_BA UART2 Control Registers 0x4007_3000 – 0x4007_3FFF UART3_BA UART3 Control Registers 0x4007_4000 – 0x4007_4FFF UART4_BA UART4 Control Registers 0x4007_5000 – 0x4007_5FFF UART5_BA UART5 Control Registers 0x4007_6000 – 0x4007_6FFF UART6_BA UART6 Control Registers 0x4007_7000 – 0x4007_7FFF UART7_BA UART7 Control Registers 0x4008_0000 – 0x4008_0FFF I2C0_BA I2C0 Control Registers 0x4008_1000 – 0x4008_1FFF I2C1_BA I2C1 Control Registers 0x400C_0000 – 0x400C_0FFF USBD_BA USB Device Control Register 0x400D_0000 – 0x400D_0FFF USCI0_BA USCI0 Control Registers 0x400D_1000 – 0x400D_1FFF USCI1_BA USCI1 Control Registers M031/M032 SERIES DATASHEET System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6.3-7 Address Space Assignments for On-Chip Controllers Apr. 29, 2020 Page 188 of 283 Rev 2.01 M031/M032 6.3.6 SRAM Memory Organization The M031 supports embedded SRAM with total 16 Kbytes size  Supports total 16 Kbytes SRAM  Supports byte / half word / word write  Supports oversize response error Table 6.3-9 shows the SRAM organization of M031. The address between 0x2000_4000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses. 0x3FFF_FFFF Reserved Reserved Reserved 512MB Reserved 0x2000_4000 M031/M032 SERIES DATASHEET 0x2000_2000 16K byte SRAM bank0 0x2000_1000 8K byte SRAM bank0 4K byte SRAM bank0 0x2000_0000 16K byte device 8K byte device 4K byte device 0x2000_0800 2K byte SRAM bank0 2K byte device Figure 6.3-8 SRAM Memory Organization 6.3.7 SRAM Memory Organization with parity function The M031 supports embedded SRAM with total 96 Kbytes size  Supports total 96 Kbytes SRAM  Supports parity error check function for SRAM bank0 section 0(32 Kbytes)  Supports byte / half word / word write  Supports oversize response error Table 6.3-9 shows the SRAM organization of M031. The address between 0x2001_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses. There are three section in SRAM bank0. The section 0 is addressed to 32 Kbytes with parity function, the section 1 is addressed to 32 Kbytes and the section 2 is addressed to 32 Kbytes. SRAM section 0 has byte parity error check function. When CPU is accessing SRAM section Apr. 29, 2020 Page 189 of 283 Rev 2.01 M031/M032 0, the parity error checking mechanism is dynamic operating. As parity error occured, the PERRIF (SYS_SRAM_STATUS[0]) will be asserted to 1 and the SYS_SRAM_ERRADDR register will recode the address with parity error. Chip will enter interrupt when SRAM parity error occurred if PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occured, chip will stop detecting SRAM parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit. 0x3FFF_FFFF Reserved Reserved 0x2001_8000 512MB 32K byte SRAM bank0 section 2 0x2001_0000 32K byte SRAM bank0 section 1 0x2000_8000 32K byte SRAM bank0 section 1 0x2000_8000 M031/M032 SERIES DATASHEET 32K byte SRAM bank0 section 0 32K byte SRAM bank0 section 0 96K byte device 64K byte device 0x2000_0000 Figure 6.3-10 SRAM Memory Organization Apr. 29, 2020 Page 190 of 283 Rev 2.01 M031/M032 6.3.8 Chip Bus Matrix The M031/M032 series supports Bus Matrix to manage the access arbitration between masters. The access arbitration use round-robin algorithm as the bus priority. PDMA Cortex® -M0 M1 M0 S0 FLASH S1 S2 SRAM APB0 S3 APB1 S4 AHB (ctrl) S5 EBI ® Figure 6.3-9 NuMicro M031 Bus Matrix Diagram 6.3.9 IRC Auto Trim This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode, automatically gets accurate output frequency, 0.25 % deviation within all temperature ranges. In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL (SYS_HIRCTRIMCTL [10] reference clock selection) to “1”, set FREQSEL (SYS_HIRCTRIMCTL [1:0] trim frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK (SYS_HIRCTRIMSTS[0] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate within 0.25% deviation. M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 191 of 283 Rev 2.01 M031/M032 6.3.10 Register Lock Control Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power-on reset till user to disable register protection. For user to program these protected registers, a register protection disable sequence needs to be followed by a special programming. The register protection disable sequence is writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100 continuously. Any different data value, different sequence or any other write to other address during these three data writing will abort the whole sequence. All proteced control registers are noted “(Write Protect)” and add an note “Note: This bit is write protected. Refer to the SYS_REGLCTL register “ in register description field. 6.3.11 UART0_TXD/USCI0_DAT0 modulation with PWM This chip supports UART0_TXD/USCI_DAT0 to modulate with PWM channel. User can set MODPWMSEL(SYS_MODCTL[7:4]) to choose which PWM0 channel to modulate with UART0_TXD/USCI0_DAT0 and set MODEN(SYS_MODCTL[0]) to enable modulation function. User can set TXDINV(UART_LINE[8]) to inverse UART0_TXD or DATOINV(UUART_LINECTL[5]) to inverse USCI0_DAT0 before modulating with PWM. PWM0_CHx UART0_TXD/USCI0_DAT0 TXDINV = 0 & MODH = 0 M031/M032 SERIES DATASHEET TXDINV = 0 & MODH = 1 TXDINV = 1 & MODH = 0 TXDINV = 1 & MODH = 1 Figure 6.3-11 UART0_TXD/USCI0_DAT0 Modulated with PWM Channel Apr. 29, 2020 Page 192 of 283 Rev 2.01 M031/M032 6.3.12 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clearon-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than an arbitrary value when it is enabled. If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. ® ® For more detailed information, please refer to the “Arm Cortex -M0 Technical Reference Manual” and ® “Arm v6-M Architecture Reference Manual”. M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 193 of 283 Rev 2.01 M031/M032 6.3.13 Nested Vectored Interrupt Controller (NVIC) ® The Cortex -M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and provides following features:  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. ® ® For more detailed information, please refer to the “Arm Cortex -M0 Technical Reference Manual” and ® “Arm v6-M Architecture Reference Manual”. M031/M032 SERIES DATASHEET 6.3.13.1 Exception Model and System Interrupt Map Table 6.3-8 lists the exception model supported by the M031/M032 series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest userconfigurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable Apr. 29, 2020 Page 194 of 283 Rev 2.01 M031/M032 SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6.3-8 Exception Model Vector Number Interrupt Number (Bit In Registers) Interrupt Interrupt Name Interrupt Description - - System exceptions 16 0 BODOUT Brown-Out low voltage detected interrupt 17 1 WDT_INT Watchdog Timer interrupt 18 2 EINT024 External interrupt fromEINT0,2,4. 19 3 EINT135 External interrupt fromEINT1.3.5 20 4 GPABGH_INT External interrupt from PA, PB, PG, PH pin 21 5 GPCDEF_INT External interrupt from PC, PD, PE, PF pin 22 6 PWM0_INT PWM0 interrupt 23 7 PWM1_INT PWM1 interrupt 24 8 TMR0_INT Timer 0 interrupt 25 9 TMR1_INT Timer 1 interrupt 26 10 TMR2_INT Timer 2 interrupt 27 11 TMR3_INT Timer 3 interrupt 28 12 UART02_INT UART0,2 interrupt 29 13 UART13_INT UART1,3 interrupt 30 14 SPI0_INT SPI0 interrupt 31 15 QSPI0_INT QSPI0 interrupt 32 16 Reserved Reserved 33 17 UART57_INT UART5,7 interrupt 34 18 I2C0_INT I2C0 interrupt 35 19 I2C1_INT I2C1 interrupt 36 20 BPWM0_INT BPWM0 interrupt 37 21 BPWM1_INT BPWM1 interrupt 38 22 USCI01 USCI0,1 interrupt 39 23 USBD_INT USB device interrupt 40 24 Reserved Reserved 41 25 ACMP01_INT ACMP0 and ACMP1 interrupt 42 26 PDMA_INT PDMA interrupt 43 27 UART46_INT UART4,6 interrupt Apr. 29, 2020 Page 195 of 283 M031/M032 SERIES DATASHEET 0 ~ 15 Rev 2.01 M031/M032 44 28 PWRWU_INT Clock controller interrupt for chip wake-up from power-down state 45 29 ADC_INT ADC interrupt 46 30 CLKFAIL Clock fail detected or IRC Auto Trim interrupt or SRAM parity check error interrupt 47 31 RTC_INT RTC interrupt Table 6.3-9 Interrupt Number Table 6.3.13.2 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Vector Table Word Offset Description 0 SP_main – The Main stack pointer Vector Number Exception Entry Pointer using that Vector Number Table 7.2-10 Vector Figure Format 6.3.13.3 Operation Description M031/M032 SERIES DATASHEET NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. W hen an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. Apr. 29, 2020 Page 196 of 283 Rev 2.01 M031/M032 6.4 Flash Memory Controller (FMC) 6.4.1 Overview This chip is equipped with 16/32/64/128/256/512 Kbytes on-chip embedded Flash (the chip with 512 Kbytes consists of two 256 Kbytes BANK0 and BANK1). A User Configuration block is provided for system initialization. A loader ROM (LDROM) is used for In-System-Programming (ISP) function. A security protection ROM (SPROM) can conceal user program. For M031xG/I and M032xG/I, a 4 Kbytes cache with zero wait cycle is implemented to improve the performance of code/data fetching. This chip also supports In-Application-Programming (IAP) function. User switches the code executing without the chip reset after the embedded Flash is updated. M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 197 of 283 Rev 2.01 M031/M032 6.5 General Purpose I/O (GPIO) 6.5.1 Overview This chip has up to 111 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 111 pins are arranged in 5 ports named as PA, PB, PC, PD, PE, PF, PG and PH. PA and PB has 16 pins on port. PC has 15 pins on port. PD and PE has 16 pins on port. PF has 14 pins on port. PG has 10 pins on port. PH has 8 pins on port. Each of the 111 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are depending on CIOINI (CONFIG0[10]). 6.5.2 Features  Four I/O modes: – Quasi-bidirectional mode – Push-Pull Output mode – Open-Drain Output mode – Input only with high impendence mode  I/O pin can be configured as interrupt source with edge/level setting  Input schmitt trigger function  Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting – CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset – CIOINI = 1, all GPIO pins in input mode after chip reset M031/M032 SERIES DATASHEET  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode  Enabling the pin interrupt function will also enable the wake-up function Apr. 29, 2020 Page 198 of 283 Rev 2.01 M031/M032 6.6 PDMA Controller (PDMA) 6.6.1 Overview The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The PDMA controller has a total of 9 channels and each channel can perform transfer between memory and peripherals or between memory and memory. 6.6.2 Features  Supports 9 independently configurable channels  Selectable 2 level of priority (fixed priority or round-robin priority)  Supports transfer data width of 8, 16, and 32 bits  Supports source and destination address increment size can be byte, half-word, word or no increment  Supports software and I C, SPI/I S, UART, USCI, ADC, PWM , QSPI and TIMER request  Supports Scatter-Gather mode to perform sophisticated transfer through the use of the descriptor link list table  Supports single and burst transfer type  Supports time-out function on channel 0 and channel1 2 2 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 199 of 283 Rev 2.01 M031/M032 6.7 Timer Controller (TMR) 6.7.1 Overview The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.7.2 Features 6.7.2.1 Timer Function Features M031/M032 SERIES DATASHEET  Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])  Supports event counting function  Supports event counting source from internal USB SOF signal  24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])  Supports external capture pin event for interval measurement  Supports external capture pin event to reset 24-bit up counter  Supports internal capture triggered while internal ACMP output signal and LIRC transition  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated  Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM, ADC, PDMA, BPWM function  Supports Inter-Timer trigger mode Apr. 29, 2020 Page 200 of 283 Rev 2.01 M031/M032 6.8 Watchdog Timer (WDT) 6.8.1 Overview The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake up system from Idle/Power-down mode. 6.8.2 Features  20-bit free running up counter for WDT time-out interval  Selectable time-out interval (2 ~ 2 ) and the time-out interval is 416us ~ 27.3 s if WDT_CLK = 38.4 kHz (LIRC).  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset delay period  Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in Config0 register  Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT. 4 20 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 201 of 283 Rev 2.01 M031/M032 6.9 Window Watchdog Timer (WWDT) 6.9.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.9.2 Features  6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value (CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible  Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit prescale counter period of WWDT counter  WWDT counter suspends in Idle/Power-down mode M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 202 of 283 Rev 2.01 M031/M032 6.10 Real Time Clock (RTC) 6.10.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. 6.10.2 Features Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in RTC_CAL (year, month, day) for RTC time and calendar check.  Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in RTC_TALM and RTC_CALM.  Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in RTC_TAMSK and RTC_CAMSK.  Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.  Supports Leap Year indication in RTC_LEAPYEAR register.  Supports Day of the Week counter in RTC_WEEKDAY register.  Frequency of RTC clock source compensate by RTC_FREQADJ register.  All time and calendar message expressed in BCD format.  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.  Supports RTC Time Tick and Alarm Match interrupt.  Supports 1 Hz clock output.  Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated. Apr. 29, 2020 Page 203 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  M031/M032 6.11 Basic PWM Generator and Capture Timer (BPWM) 6.11.1 Overview The chip provides two BPWM generators － BPWM0 and BPWM1 as shown in BPWM Generator Overview Block Diagram. Each BPWM supports 6 channels of BPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit BPWM counter with 16-bit comparator. The BPWM counter supports up, down and up-down counter types, all 6 channels share one counter. BPWM uses the comparator compared with counter to generate events. These events are used to generate BPWM pulse, interrupt and trigger signal for ADC to start conversion. For BPWM output control unit, it supports polarity output, independent pin mask and tri-state output enable. The BPWM generator also supports input capture function to latch BPWM counter value to corresponding register when input channel has a rising transition, falling transition or both transition is happened. 6.11.2 Features 6.11.2.1 BPWM Function Features  Supports maximum clock frequency up to 144 MHz.  Supports up to two BPWM modules; each module provides 6 output channels  Supports independent mode for BPWM output/Capture input channel  Supports 12-bit prescalar from 1 to 4096  Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter – Up, down and up/down counter operation type  Supports mask function and tri-state enable for each BPWM pin  Supports interrupt in the following events: M031/M032 SERIES DATASHEET –  BPWM counter matches 0, period value or compared value Supports trigger ADC in the following events: – BPWM counter matches 0, period value or compared value 6.11.2.2 Capture Function Features  Supports up to 12 capture input channels with 16-bit resolution  Supports rising or falling capture condition  Supports input rising/falling capture interrupt  Supports rising/falling capture with counter reload option Apr. 29, 2020 Page 204 of 283 Rev 2.01 M031/M032 6.12 PWM Generator and Capture Timer (PWM) 6.12.1 Overview The chip provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types. PWM uses comparator compared with counter to generate events. These events use to generate PWM pulse, interrupt and trigger signal for ADC to start conversion. The PWM generator supports two standard PWM output modes: Independent mode and Complementary mode, they have difference architecture. In Complementary mode, there are two comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control unit, it supports polarity output, independent pin mask and brake functions. The PWM generator also supports input capture function to latch PWM counter value to the corresponding register when input channel has a rising transition, falling transition or both transition is happened. Capture function also support PDMA to transfer captured data to memory. 6.12.2 Features 6.12.2.1 PWM Function Features  Supports maximum clock frequency up to 144 MHz  Supports up to two PWM modules, each module provides 6 output channels  Supports independent mode for PWM output/Capture input channel  Supports complementary mode for 3 complementary paired PWM output channel – Dead-time insertion with 12-bit resolution – Two compared values during one period Supports 12-bit prescaler from 1 to 4096  Supports 16-bit resolution PWM counter – Up, down and up-down counter operation type  Supports mask function and tri-state enable for each PWM pin  Supports brake function   – Brake source from pin and system safety events (clock failed, Brown-out detection, SRAM parity error and CPU lockup) – Noise filter for brake source from pin – Edge detect brake source to control brake state until brake interrupt cleared – Level detect brake source to auto recover function after brake condition removed Supports interrupt on the following events: – PWM counter matches 0, period value or compared value – Brake condition happened Supports trigger ADC on the following events: – PWM counter matches 0, period value or compared value 6.12.2.2 Capture Function Features  Supports up to 12 capture input channels with 16-bit resolution Apr. 29, 2020 Page 205 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  M031/M032  Supports rising or falling capture condition  Supports input rising/falling capture interrupt  Supports rising/falling capture with counter reload option  Supports PDMA transfer function for PWM all channels M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 206 of 283 Rev 2.01 M031/M032 6.13 UART Interface Controller (UART) 6.13.1 Overview The chip provides eight channels of Universal Asynchronous Receiver/Transmitters (UART). The UART controller performs Normal Speed UART and supports flow control function. The UART controller performs a serial-to-parallel conversion on data received from the peripheral and a parallelto-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten types of interrupts. The UART controller also supports IrDA SIR, RS-485 and Single-wire function modes and auto-baud rate measuring function. 6.13.2 Features  Full-duplex asynchronous communications  Separates receive and transmit 16/16 bytes or 1/1 byte entry FIFO for data payloads  Supports hardware auto-flow control  Programmable receiver buffer trigger level  Supports programmable baud rate generator for each channel individually  Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function (Only UART0 /UART1 /UART4 /UART5 with Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function)  Supports 8-bit receiver buffer time-out detection function  Programmable transmitting data delay time between the last stop and the next start bit by setting DLY (UART_TOUT [15:8])  Supports Auto-Baud Rate measurement and baud rate compensation function –  Supports break error, frame error, parity error and receive/transmit buffer overflow detection function  Fully programmable serial-interface characteristics  – Programmable number of data bit, 5-, 6-, 7-, 8- bit character – Programmable parity bit, even, odd, no parity or stick parity bit generation and detection – Programmable stop bit, 1, 1.5, or 2 stop bit generation Supports IrDA SIR function mode –  Supports for 3/16 bit duration for normal mode Supports RS-485 function mode – Supports RS-485 9-bit mode – Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction  Supports PDMA transfer function  Support Single-wire function mode. UART Feature Apr. 29, 2020 UART0/ UART1/ UART4/ UART2/ UART3/ UART6/ USCI-UART UART5 UART7 Page 207 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Support 9600 bps for UART_CLK is selected LXT. (Only UART0 /UART1 /UART4 /UART5 with this feature) M031/M032 TX: 1byte FIFO 16 Bytes 1 Bytes Auto Flow Control (CTS/RTS) √ √ √ IrDA √ √ - LIN - - - RS-485 Function Mode √ √ √ nCTS Wake-up √ √ √ Incoming Data Wake-up √ √ √ √ - RS-485 Address Match (AAD mode) √ Wake-up - Auto-Baud Rate Measurement √ √ √ STOP Bit Length 1, 1.5, 2 bit 1, 1.5, 2 bit 1, 2 bit Word Length 5, 6, 7, 8 bits 5, 6, 7, 8 bits 6~13 bits Even / Odd Parity √ √ √ Stick Bit √ √ - Received Data threshold Wake-up FIFO reached RX: 2byte - Note: √= Supported ® Table 6.13-1 NuMicro M031/M032 Series UART Features M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 208 of 283 Rev 2.01 M031/M032 6.14 Serial Peripheral Interface (SPI) 6.14.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The chip contains one set of SPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each SPI controller can be configured as a master or a slave device and supports the PDMA function 2 to access the data buffer. Each SPI controller also supports I S mode to connect external audio CODEC. 6.14.2 Features  – Supports one set of SPI controller – Supports Master or Slave mode operation – Configurable bit length of a transaction word from 8 to 32-bit – Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO buffers which depends on SPI setting of data width – Supports MSB first or LSB first transfer sequence – Supports Byte Reorder function – Supports Byte or Word Suspend mode – Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD = 1.8~3.6V) – Supports one data channel half-duplex transfer – Supports receive-only mode – Supports PDMA transfer 2 I S Mode 2 – Supports one set of I S by SPI controller – Interface with external audio CODEC – Supports Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports monaural and stereo audio data – Supports PCM mode A, PCM mode B, I S and MSB justified data format – Each provides two 4-level FIFO data buffers, one for transmitting and the other for receiving – Supports two PDMA requests, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary Apr. 29, 2020 2 Page 209 of 283 Rev 2.01 M031/M032 SERIES DATASHEET  SPI Mode M031/M032 6.15 Quad Serial Peripheral Interface (QSPI) 6.15.1 Overview The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The chip contains one QSPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access the data buffer. 6.15.2 Features M031/M032 SERIES DATASHEET  Supports one QSPI controller  Supports Master or Slave mode operation  Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD = 1.8~3.6V)  Supports 2-bit Transfer mode  Supports Dual and Quad I/O Transfer mode  Configurable bit length of a transaction word from 8 to 32-bit  Provides separate 8-level depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Supports Byte Reorder function  Supports Byte or Word Suspend mode  Supports PDMA transfer  Supports 3-Wire, no slave selection signal, bi-direction interface  Supports one data channel half-duplex transfer  Supports receive-only mode Apr. 29, 2020 Page 210 of 283 Rev 2.01 M031/M032 I2C Serial Interface Controller (I2C) 6.16 6.16.1 Overview 2 I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange 2 between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. 2 There are two sets of I C controllers which support Power-down wake-up function. 6.16.2 Features 2 The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to the 2 bus. The main features of the I C bus include: 2  Supports up to two I C ports  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allow devices with different bit rates to communicate via one serial bus  Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflow  Programmable clocks allow for versatile rate control  Supports 7-bit addressing  Supports multiple address recognition (four slave address with mask option)  Supports Power-down wake-up function  Supports PDMA with one buffer capability  Supports setup/hold time programmable  Supports Bus Management (SM/PM compatible) function 2 M031xB/C/D/E M031xG/I M032xB/C/D/E M032xG/I Sub-Section 6.16.5.2 Operation Modes - Bus Management (SMBus/PMBus Compatiable) - Device Identification – Slave Address ● 6.16.5 Functional Description - Bus Protocols - Address Resolution Protocol (ARP) - Received Command and Data acknowledge control - Host Notify Protocol Apr. 29, 2020 Page 211 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Section 2 M031/M032 - Bus Management Alert - Packet Error Checking - Time-out - Bus Management Time-out: - Bus Clock Low Time-out: - Bus Idle Detection ● I2C Bus Manage Control Register (I2C_BUSCTL) I2C Bus Management (I2C_BUSTCTL) Register Description Timer Control Register ● I2C Bus Management Status Register (I2C_BUSSTS) ● I2C Byte Number Register (I2C_PKTSIZE) ● I2C PEC Value Register (I2C_PKTCRC) ● I2C Bus Management Timer Register (I2C_BUSTOUT) ● I2C Clock Low Timer Register (I2C_CLKTOUT) ● 2 Table 6.16-1 I C Feature Comparison Table at Different Chip M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 212 of 283 Rev 2.01 M031/M032 6.17 USCI - Universal Serial Control Interface Controller (USCI) 6.17.1 Overview The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial 2 communication protocols. The user can configure this controller as UART, SPI, or I C functional protocol. 6.17.2 Features The controller can be individually configured to match the application needs. The following protocols are supported:  UART  SPI  IC 2 M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 213 of 283 Rev 2.01 M031/M032 6.18 USCI – UART Mode 6.18.1 Overview The asynchronous serial channel UART covers the reception and the transmission of asynchronous data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being independent, frames can start at different points in time for transmission and reception. The UART controller also provides auto flow control. There are two conditions to wake-up the system. 6.18.2 Features  Supports one transmit buffer and two receive buffer for data payload  Supports hardware auto flow control function  Supports programmable baud-rate generator  Support 9-bit Data Transfer (Support 9-bit RS-485)  Baud rate detection possible by built-in capture event of baud rate generator  Supports PDMA capability  Supports Wake-up function (Data and nCTS Wakeup Only) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 214 of 283 Rev 2.01 M031/M032 6.19 USCI - SPI Mode 6.19.1 Overview The SPI protocol of USCI controller applies to synchronous serial data communication and allows full duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1 This SPI protocol can operate as Master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to communicate with the off-chip SPI Slave or master device. The application block diagrams in Master and Slave mode are shown below. USCI USCI SPI SPI Master Master SPI Slave Device SPI_MOSI Master Transmit Data (USCIx_DAT0) SPI_MISO Master Receive Data (USCIx_DAT1) SPI_CLK Serial Bus Clock (USCIx_CLK) SPI_SS Slave Select (USCIx_CTL) SPI_MOSI SPI_MISO SPI_CLK SPI_SS Note: x = 0,1 Figure 6.19-1 SPI Master Mode Application Block Diagram M031/M032 SERIES DATASHEET USCI USCI SPI SPI Slave Slave SPI Master Device SPI_MOSI Slave Receive Data (USCIx_DAT0) SPI_MISO Slave Transmit Data (USCIx_DAT1) SPI_CLK Serial Bus Clock (USCIx_CLK) SPI_SS Slave Select (USCIx_CTL) SPI_MOSI SPI_MISO SPI_CLK SPI_SS Note: x = 0,1 Figure 6.19-2 SPI Slave Mode Application Block Diagram 6.19.2 Features  Supports Master or Slave mode operation (the maximum frequency -- Master = fPCLK / 2, Slave < fPCLK / 5)  Configurable bit length of a transfer word from 4 to 16-bit  Supports one transmit buffer and two receive buffers for data payload  Supports MSB first or LSB first transfer sequence Apr. 29, 2020 Page 215 of 283 Rev 2.01 M031/M032  Supports Word Suspend function  Supports PDMA transfer  Supports 3-wire, no slave select signal, bi-direction interface  Supports wake-up function by slave select signal in Slave mode  Supports one data channel half-duplex transfer M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 216 of 283 Rev 2.01 M031/M032 6.20 USCI - I2C Mode 6.20.1 Overview 2 On I C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure 2 6.20-1 for more detailed I C BUS Timing. STOP Repeated START START STOP SDA tBUF tLOW tr SCL tf tHIGH tHD_STA tSU_DAT tHD_DAT tSU_STA tSU_STO 2 Figure 6.20-1 I C Bus Timing 2 2 The device’s on-chip I C provides the serial interface that meets the I C bus standard mode 2 2 specification. The I C port handles byte transfers autonomously. The I C mode is selected by 2 FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I C bus via 2 2 two pins: SDA and SCL. When I/O pins are used as I C ports, user must set the pins function to I C in advance. 2 Note: Pull-up resistor is needed for I C operation because the SDA and SCL are set to open-drain 2 pins when USCI is selected to I C operation mode . M031/M032 SERIES DATASHEET 6.20.2 Features  Full master and slave device capability  Supports of 7-bit addressing, as well as 10-bit addressing  Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)  Supports multi-master bus  Supports one transmit buffer and two receive buffer for data payload  Supports 10-bit bus time-out capability  Supports bus monitor mode.  Supports Power down wake-up by received ‘START’ symbol or address match  Supports setup/hold time programmable  Supports multiple address recognition (two slave address with mask option) Apr. 29, 2020 Page 217 of 283 Rev 2.01 M031/M032 6.21 External Bus Interface (EBI) 6.21.1 Overview This chip is equipped with an external bus interface (EBI) for external device use. To save the connections between an external device and a chip, EBI is operating at address bus and data bus multiplex mode. The EBI supports two chip selects that can connect two external devices with different timing setting requirements. 6.21.2 Features  Supports up to two memory banks  Supports dedicated external chip select pin with polarity control for each bank  Supports accessible space up to 1 Mbytes for each bank, actually external addressable space is dependent on package pin out  Supports 8-/16-bit data width  Supports byte write in 16-bit data width mode  Supports Address/Data multiplexed Mode  Supports Timing parameters individual adjustment for each memory block  Supports LCD interface i80 mode  Supports PDMA mode  Supports variable external bus base clock (MCLK) which based on HCLK  Supports configurable idle cycle for different access condition: Idle of Write command finish (W2X) and Idle of Read-to-Read (R2R)  Supports address bus and data bus separate mode M031/M032 SERIES DATASHEET M032xC/D M031xB/C/D/ E M031xG/I M032xE M032xG/I 6.21.5.3 EBI Data Width Connection - Address Bus and Data Bus Separate Mode ● 6.21.5.4 EBI Operating Control - Continuous Data Access Mode ● Table 6.21-1 EBI Features Comparison Table Apr. 29, 2020 Page 218 of 283 Rev 2.01 M031/M032 6.22 USB 2.0 Full-Speed Device Controller (USBD) 6.22.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There are 512 Bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the effective starting address of SRAM for each endpoint buffer through buffer segmentation register (USBD_BUFSEGx). There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. There are four different interrupt events in this controller. They are the no-event-wake-up, device plugin or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status Register USBD_EPSTS0 to acknowledge what kind of event occurring in this endpoint. A software-disconnect function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the SE0 bit, host will enumerate the USB device again. 6.22.2 Features  Compliant with USB 2.0 Full-Speed specification  Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET, USB and BUS)  Supports Control/Bulk/Interrupt/Isochronous transfer type  Supports suspend function when no bus activity existing for 3 ms  Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 512 byte buffer size  Provides remote wake-up capability - M031xB/C/D/E M031xG/I M032xC/D M032xE M032xG/I ● - - Section 6.22.7 Register Description USB Configuration Register (USB_CFGx) DSQSYNC OUT Token Transaction Apr. 29, 2020 Page 219 of 283 Rev 2.01 M031/M032 SERIES DATASHEET For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification Revision 2.0. M031/M032 6.23 CRC Controller (CRC) 6.23.1 Overview The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings. 6.23.2 Features  Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 16 5 CRC-CCITT: X – CRC-8: X + X + X + 1 – CRC-16: X 16 +X 15 +X +1 – CRC-32: X 32 +X 26 +X 8 +X 12 – +X +1 2 2 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 4 2 +X +X +X +X +X +X+1  Programmable seed value  Supports programmable order reverse setting for input data and CRC checksum  Supports programmable 1’s complement setting for input data and CRC checksum  Supports 8/16/32-bit of data width  – 8-bit write mode: 1-AHB clock cycle operation – 16-bit write mode: 2-AHB clock cycle operation – 32-bit write mode: 4-AHB clock cycle operation Supports using PDMA to write data to perform CRC operation M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 220 of 283 Rev 2.01 M031/M032 6.24 Hardware Divider (HDIV) 6.24.1 Overview The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a signed, integer divider with both quotient and remainder outputs. 6.24.2 Features  Signed (two’s complement) integer calculation  32-bit dividend with 16-bit divisor calculation capacity  32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)  Divided by zero warning flag  Write divisor to trigger calculation M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 221 of 283 Rev 2.01 M031/M032 6.25 Analog-to-Digital Converter (ADC) 6.25.1 Overview The ADC contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter) with 16 input channels. The A/D converter supports four operation modes: Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D converter can be started by software, external pin (STADC), timer0~3 overflow pulse trigger, PWM trigger or BPWM trigger. 6.25.2 Features  Operating voltage: 1.8V~3.6V.  Analog input voltage: 0 ~ AVDD.  Supports external reference voltage from VREF pin.  12-bit resolution and 10-bit accuracy is guaranteed.  Up to 16 single-end analog input channels or 8 differential analog input channels.  Maximum ADC peripheral clock frequency is 34 MHz.  Up to 2 MSPS sampling rate.  Scan on enabled channels  Threshold voltage detection  Four operation modes: M031/M032 SERIES DATASHEET  – Single mode: A/D conversion is performed one time on a specified channel. – Burst mode: A/D converter samples and converts the specified single channel and sequentially stores the result in FIFO. – Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel. – Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode until software stops A/D conversion. An A/D conversion can be started by: – Software Write 1 to ADST bit – External pin (STADC) – Timer 0~3 overflow pulse trigger – BPWM trigger – PWM trigger  Each conversion result is held in data register of each channel with valid and overrun indicators.  Conversion result can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting.  Supports extend sample time function (0~255 ADC clock).  One internal channel from band-gap voltage (VBG).  One internal channel from internal pull-up/down circuit.  Supports PDMA transfer mode. Apr. 29, 2020 Page 222 of 283 Rev 2.01 M031/M032  Supports Calibration mode.  Supports Floating Detect Function Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle) Note2: If the internal channel for band-gap voltage is active, the maximum sampling rate will be 300k SPS. Note3: The ADC Clock frequency must be slower than or equal to PCLK. M031xB/C/D/E M031xG/I M032x/E M032xG/I - ● ● 6.25.5.12 BPWM trigger ● - ● 6.25.5.17 Floating Detect Function ● - ● M032xC/D 6.25.5.11 PWM trigger Table 6.25-1 ADC Features Comparison Table M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 223 of 283 Rev 2.01 M031/M032 6.26 Analog Comparator Controller (ACMP) 6.26.1 Overview The chip provides two comparators. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. Each comparator can be configured to generate an interrupt when the comparator output value changes. 6.26.2 Features  Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)  Supports hysteresis function  Supports wake-up function  Selectable input sources of positive input and negative input  ACMP0 supports: – 4 multiplexed I/O pins at positive sources:  –  ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3 3 negative sources:  ACMP0_N  Comparator Reference Voltage (CRV)  Internal band-gap voltage (VBG) ACMP1 supports – 4 multiplexed I/O pins at positive sources:  – ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3 3 negative sources: M031/M032 SERIES DATASHEET  ACMP1_N  Comparator Reference Voltage (CRV)  Internal band-gap voltage (VBG)  Shares one ACMP interrupt vector for all comparators  Interrupts generated when compare results change (Interrupt event condition is programmable)  Supports triggers for break events and cycle-by-cycle control for PWM  Supports window compare mode and window latch mode  Supports calibration function Section Sub-Section Function Description 6.26.5.7 Calibration function M031xB/C/D/E M031xG/I M032xB/C/D/E M032xG/I -/-/-/● ● Table 6.26-1 Calibration Function Features Comparison Table at Different Chip Apr. 29, 2020 Page 224 of 283 Rev 2.01 M031/M032 6.27 Peripherals Interconnection 6.27.1 Overview Some peripherals have interconnections which allow autonomous communication or synchronous action between peripherals without needing to involve the CPU. Peripherals interact without CPU saves CPU resources, reduces power consumption, operates with no software latency and fast responds. 6.27.2 Peripherals Interconnect Matrix table Destination Source HIRC TRIM BPWM PWM Timer UART/USCI ACMP - - - 3 6 - BOD - - - 3 - - Clock Fail - - - 3 - - CPU Lockup - - - 3 - - LIRC - - - - 6 - HXT - - - - - LXT - 2 - - BPWM 1 4 - - - PWM 1 - 4 4 - 8 Timer 1 - 5 5 7 - USBD - 2 - - - - Table 6.27-1 Peripherals Interconnect Matrix table Apr. 29, 2020 Page 225 of 283 Rev 2.01 M031/M032 SERIES DATASHEET ADC M031/M032 7 APPLICATION CIRCUIT 7.1 Power Supply Scheme as close to AVDD as possible L=30Z EXT_PWR AVDD L=30Z 1uF+0.1uF+0.01uF AVSS as close to the EXT_PWR as possible 10uF+0.1uF VREF 2.2uF+1uF+470pF L=30Z as close to VREF as possible LDO_CAP VSS 1uF as close to LDO as possible VDD M031/M032 SERIES DATASHEET EXT_VSS VSS 0.1uF*N as close to VDD as possible Apr. 29, 2020 Page 226 of 283 Rev 2.01 M031/M032 7.2 Peripheral Application Scheme DVCC 100K 100K VDD ICE_DAT SWD Interface ICE_CLK nRESET VSS 20pF USB Full Speed Slot USB_VBUS USB_DUSB_D+ USB_VCC33_CAP 27R 27R XT1_IN 1uF 4~32 MHz crystal 20pF DVCC XT1_OUT SPI Mode SPI_SS SPI_CLK SPI_MISO SPI_MOSI Crystal 20pF X32_IN VDD VSS SPI Device I2S Mode Audio codec 32.768 kHz crystal 20pF CS CLK MISO MOSI SPI_I2SMCLK SPI_CLK (I2S_BCLK) X32_OUT SPI_SS (I2S_LRCLK) Line In NUC8822 Line Out SPI_MOSI (I2S_DO) SPI_MISO (I2S_DI) DVCC M031/M032 Series Reset Circuit 10K DVCC nRESET DVCC 4.7K LDO_CAP LDO 4.7K I2C_SCL CLK VDD I2C_SDA DIO VSS I2C Device 1 uF 64K x 16-bit SRAM Addr[15:0] LATCH Q En EBI D EBI_ALE nCE EBI_nCS nOE EBI_nRD nWE nLB nUB Data[15:0] EBI_nWR EBI_nWRL EBI_nWRH RS 232 Transceiver PC COM Port UART_RXD ROUT UART_TXD TIN RIN TOUT UART EBI_AD[15:0] Note 1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin. Note 2: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. Apr. 29, 2020 Page 227 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 10 uF M031/M032 8 ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings Stresses above the absolute maximum ratings may cause permanent damage to the device. The limiting values are stress ratings only and cannot be used to functional operation of the device. Exposure to the absolute maximum ratings may affect device reliability and proper operation is not guaranteed. 8.1.1 Voltage Characteristics Symbol Description VDD-VSS[*1] ΔVDD |VDD –AVDD| ΔVSS |VSS - AVSS| Max Unit -0.3 4.0 V Variations between different power pins - 50 mV Allowed voltage difference for VDD and AVDD - 50 mV Variations between different ground pins - 50 mV Allowed voltage difference for VSS and AVSS - 50 mV VSS-0.3 5.5 V VSS-0.3 4.0 V DC power supply Input voltage on 5V-tolerance I/O VIN Input voltage on any other pin [*2] Min Note: 1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply. 2. Non 5V-tolerance I/O includes PA.10 ~ 11; PB.0 ~ 15; PF.2, 3, 4, 5; all USB pin and nRESET pin. V IN maximum value must be respected to avoid permanent damage. Refer to Table 8.1-2 for the values of the maximum allowed injected current Table 8.1-1 Voltage Characteristics M031/M032 SERIES DATASHEET 8.1.2 Current Characteristics Symbol ΣIDD[*1] ΣISS IIO IINJ(PIN) [*3] ΣIINJ(PIN) [*3] Description Min Max Maximum current into VDD - 150 Maximum current out of VSS - 100 Maximum current sunk by a I/O Pin - 20 Maximum current sourced by a I/O Pin - 20 Maximum current sunk by total I/O Pins[*2] - 100 Maximum current sourced by total I/O Pins[*2] - 100 Maximum injected current by a I/O Pin - ±5 Maximum injected current by total I/O Pins - ±25 Unit mA Note: 1. Maximum allowable current is a function of device maximum power dissipation. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins. 3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN 30 sec. Time with 5°C of actual peak temperature Peak temperature range 260°C Ramp-down rate 6°C/sec ax. Time 25°C to peak temperature 8 min. max Note: 1. Determined according to J-STD-020C Table 8.1-7 Soldering Profile Apr. 29, 2020 Page 233 of 283 Rev 2.01 M031/M032 8.2 General Operating Conditions (VDD-VSS = 1.8 ~ 3.6V, TA = 25C, HCLK = 48/72 MHz unless otherwise specified.) Symbol TA fHCLK VDD Parameter Temperature Min Typ Max Unit Test Conditions -40 - 105 °C - - 48 MHz VDD = 1.8 V~3.6V - - 72 MHz VDD = 2.0 V~3.6V 1.8 - 3.6 fHCLK up to 48 MHz 2.0 - 3.6 fHCLK up to 72 MHz Internal AHB clock frequency Operation voltage AVDD[*1] Analog operation voltage VREF Analog reference voltage VLDO LDO output voltage VBG[*4] Band-gap voltage CLDO[*2] LDO output capacitor on each pin RESR[*3] ESR of CLDO output capacitor 0.1 - 10 Ω IRUSH[*3] InRush current on voltage regulator power-on (POR or wakeup from Standby) - 150 - mA ERUSH[*3] InRush energy on voltage regulator power-on (POR or wakeup from Standby) - 2.25 - µC VDD V 1.8 - AVDD - 1.8 - 1.16 1.23 1.31 AVDD − VREF < 1.2 V μF 1 VDD = 1.8 V, TA = 105 °C, IRUSH = 150 mA for 15 us Note: M031/M032 SERIES DATASHEET 1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between V DD and AVDD can be tolerated during power-on and power-off operation . 2. To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor. Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease output noise and improves the load transient response. 3. Guaranteed by design, not tested in production 4. Based on characterization, not tested in production unless otherwise specified. Table 8.2-1 General Operating Conditions Apr. 29, 2020 Page 234 of 283 Rev 2.01 M031/M032 8.3 DC Electrical Characteristics 8.3.1 Supply Current Characteristics for M03xB/M03xC/M03xD/M03xE The current consumption is a combination of internal and external parameters and factors such as operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program location in memory and so on. The current consumption is measured as described in below condition and table to inform test characterization result.  All GPIO pins are in push pull mode and output high.  The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values for T A= 25 °C and VDD = 1. 8V ~ 3.6 V unless otherwise specified.  VDD = AVDD  When the peripherals are enabled HCLK is the system clock, f PCLK0, 1 = fHCLK.  Program run CoreMark code in Flash. ® Typ [*1] Symbol Conditions Normal run mode, executed from Flash, all peripherals disable Normal run mode, executed from Flash, all peripherals enable FHCLK Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C 48 MHz 8.5 9.78 10.18 10.80 32 MHz 5.6 6.44 6.90 7.41 24 MHz 5 5.75 6.13 6.63 12 MHz 3.6 4.14 4.49 4.93 4 MHz 2.4 2.76 3.08 3.47 38.4 kHz 0.099 0.114 0.385 0.711 32.768 kHz 0.098 0.113 0.383 0.710 48 MHz 19.5 22.43 23.19 24.21 32 MHz 12.6 14.49 15.21 15.98 24 MHz 9.5 10.93 11.52 12.26 12 MHz 5.6 6.44 6.90 7.48 4 MHz 2.9 3.34 3.71 4.17 38.4 kHz 0.107 0.123 0.396 0.724 32.768 kHz 0.105 0.121 0.392 0.720 mA Note: 1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. Table 8.3-1 Current Consumption in Normal Run Mode Apr. 29, 2020 Page 235 of 283 Rev 2.01 M031/M032 SERIES DATASHEET IDD_RUN Max[*1][*2] M031/M032 Max[*1] [*2] Typ Symbol Conditions FHCLK Unit TA = 25 °C Idle mode, all peripherals disable IDD_IDLE Idle mode, all peripherals enable TA = 25 °C TA = 85 °C TA = 105 °C 48 MHz 3.85 4.43 4.79 5.26 32 MHz 2.42 2.78 3.15 3.57 24 MHz 2.35 2.70 3.05 3.47 12 MHz 1.83 2.10 2.43 2.81 4 MHz 1.51 1.74 2.05 2.43 38.4 kHz 0.095 0.109 0.380 0.706 32.768 kHz 0.095 0.109 0.380 0.707 48 MHz 14.94 17.18 17.87 18.79 32 MHz 9.47 10.89 11.52 12.21 24 MHz 7.2 8.28 8.81 9.47 12 MHz 4.3 4.95 5.38 5.90 4 MHz 2.43 2.79 3.16 3.59 38.4 kHz 0.103 0.118 0.392 0.720 32.768 kHz 0.102 0.117 0.389 0.718 mA Note: 1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. M031/M032 SERIES DATASHEET Table 8.3-2 Current Consumption in Idle Mode Apr. 29, 2020 Page 236 of 283 Rev 2.01 M031/M032 Typ[*2] Max[*3][*4] LXT[*1] LIRC Test Conditions 32.768 kHz 38.4 kHz TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C Power-down mode, all peripherals disable - - 12 25 [*5] 350 700 Power-down mode, WDT/Timer/UART enable V - 13.5 27.5 360 710 Symbol IDD_PD Unit µA Power-down mode, WDT/Timer/UART enable - V 12.5 26.5 365 715 Power-down mode, WDT use LIRC, UART/Timer use LXT V V 14 28 375 725 Note: 1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for typical values 2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled. 3. Based on characterization, not tested in production unless otherwise specified. 4. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be considered. 5. Based on characterization, tested in production. Table 8.3-3 Chip Current Consumption in Power-down Mode M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 237 of 283 Rev 2.01 M031/M032 8.3.2 Supply Current Characteristics for M03xG/M03xI The current consumption is a combination of internal and external parameters and factors such as operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program location in memory and so on. The current consumption is measured as described in below condition and table to inform test characterization result.  All GPIO pins are in push pull mode and output high.  The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values for T A= 25 °C and VDD = 1. 8V ~ 3.6 V unless otherwise specified.  VDD = AVDD  When the peripherals are enabled HCLK is the system clock, f PCLK0, 1 = fHCLK.  Program run CoreMark code in Flash. ® Typ [*1] Symbol Conditions Normal run mode, executed from Flash, all peripherals disable M031/M032 SERIES DATASHEET IDD_RUN Normal run mode, executed from Flash, all peripherals enable Max[*1][*2] FHCLK Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C 72 MHz[*3] 23.7 27.26 28.74 30.73 48 MHz 14.4 16.56 17.16 18.87 32 MHz 9.0 10.35 10.72 12.31 24 MHz 15.7 18.06 18.06 18.79 12 MHz 9.1 10.47 10.47 10.89 4 MHz 4.6 5.29 5.29 5.52 38.4 kHz 0.141 0.162 1.430 2.885 32.768 kHz 0.140 0.161 1.429 2.885 72 MHz[*3] 46.4 53.36 55.45 58.05 48 MHz 28.6 32.89 35.09 36.95 32 MHz 18.9 21.74 23.76 25.53 24 MHz 15.4 17.71 19.43 21.22 12 MHz 8.9 10.24 11.76 13.44 4 MHz 4.6 5.29 6.68 8.24 38.4 kHz 0.153 0.176 1.449 2.908 32.768 kHz 0.150 0.173 1.445 2.903 mA Note: 1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. 3. When chip works at VDD = 2.0~3.6V. Table 8.3-4 Current Consumption in Normal Run Mode Apr. 29, 2020 Page 238 of 283 Rev 2.01 M031/M032 Max[*1] [*2] Typ Symbol Conditions FHCLK Unit TA = 25 °C Idle mode, all peripherals disable IDD_IDLE Idle mode, all peripherals enable TA = 25 °C TA = 85 °C TA = 105 °C 72 MHz[*3] 9.9 11.39 12.59 14.13 48 MHz 3.9 4.49 5.85 7.39 32 MHz 2.6 2.99 4.34 5.84 24 MHz 2.7 3.11 4.44 5.95 12 MHz 2.1 2.42 3.73 5.23 4 MHz 1.7 1.96 3.26 4.74 38.4 kHz 0.133 0.153 1.421 2.877 32.768 kHz 0.133 0.153 1.422 2.878 72 MHz[*3] 32.6 37.49 39.69 41.60 48 MHz 19.1 21.97 23.87 25.72 32 MHz 12.5 14.38 16.14 17.86 24 MHz 10.5 12.08 13.65 15.38 12 MHz 6.2 7.13 8.58 10.19 4 MHz 3.3 3.80 5.15 6.68 38.4 kHz 0.145 0.167 1.438 2.898 32.768 kHz 0.143 0.164 1.434 2.893 mA Note: When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. 3. When chip works at VDD = 2.0~3.6V. M031/M032 SERIES DATASHEET 1. Table 8.3-5 Current Consumption in Idle Mode Apr. 29, 2020 Page 239 of 283 Rev 2.01 M031/M032 LXT[*1] LIRC Typ[*2] Test Conditions 32.768 kHz 38.4 kHz TA = TA = TA = 85 TA = 105 25 °C 25 °C °C °C Power-down mode, all peripherals disable - - 51.5 59.2 [*5] 1298 2732 [*5] Power-down mode, WDT/Timer/UART enable V - 53.3 61.3 1294 2747 Symbol Max[*3][*4] IDD_PD Unit µA Power-down mode, WDT/Timer/UART enable - V 53.4 61.4 1300 2751 Power-down mode, WDT use LIRC, UART/Timer use LXT V V 55.2 63.5 1306 2758 Note: 1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for typical values 2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled. 3. Based on characterization, not tested in production unless otherwise specified. 4. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be considered. 5. Based on characterization, tested in production. Table 8.3-6 Chip Current Consumption in Power-down Mode M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 240 of 283 Rev 2.01 M031/M032 8.3.3 On-Chip Peripheral Current Consumption  The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.  All GPIO pins are set as output high of push pull mode without multi-function.  HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK.  The result value is calculated by measuring the difference of current consumption between all peripherals clocked off and only one peripheral clocked on IDD[*1] PDMA 0.721 ISP 0.0002 EBI 0.236 HDIV 0.135 CRC 0.119 SRAM0IDLE 0.122 WDT/WWDT 0.125 RTC 0.102 TMR0 0.332 TMR1 0.303 TMR2 0.299 TMR3 0.292 CLKO 0.095 ACMP01[*3] 0.243 I2C0 0.159 I2C1 0.122 QSPI 0.914 SPI/I2S 1.878 UART0 0.629 UART1 0.575 UART2 0.631 UART3 0.614 UART4 0.584 UART5 0.647 UART6 0.549 UART7 0.654 USB FS Device 1.099 Apr. 29, 2020 [*2] ADC 0.962 USCI0 0.638 Page 241 of 283 Unit mA Rev 2.01 M031/M032 SERIES DATASHEET Peripheral M031/M032 USCI1 0.445 PWM0 1.257 PWM1 1.26 BPWM0 0.649 BPWM1 0.652 Note: 1. Guaranteed by characterization results, not tested in production. 2. When the ADC is turned on, add an additional power consumption per ADC for the analog part. 3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part. Table 8.3-7 Peripheral Current Consumption M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 242 of 283 Rev 2.01 M031/M032 8.3.4 Wakeup Time from Low-Power Modes The wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 48 MHz HIRC oscillator. Symbol tWU_IDLE tWU_NPD[*1][*2] Parameter Typ Max Unit Wakeup from IDLE mode 5 6 cycles Wakeup from normal power down mode 12 25 µs Note: 1. Based on test during characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first Table 8.3-8 Low-power Mode Wakeup Timings M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 243 of 283 Rev 2.01 M031/M032 8.3.5 I/O Current Injection Characteristics In general, I/O current injection due to external voltages below VSS or above VDD except 5V-tolenece I/O should be avoided during normal product operation. However, the analog compoenent of the MCU is most likely to be affected by the injection current , but it is not easily clarified when abnormal injection accidentally happens. It is recommended to add a Schottky diode (pin to ground or pin to VDD) to pins that include analog function which may potentially injection currents. Symbol Parameter IINJ(PIN) Injected current by a I/O Pin Negative injection Positive injection -0 0 Injected current on nReset pins -0 0 Injected current on PF2~PF5, PA10, mA PA11 and PB0~PB15 for analog input function -5 NA Unit Test Condition Injected current on any other 5Vtolerance I/O Table 8.3-9 I/O Current Injection Characteristics 8.3.6 8.3.6.1 I/O DC Characteristics PIN Input Characteristics Symbol Parameter Min Typ Max Unit M031/M032 SERIES DATASHEET VIL Input low voltage 0 - 0.3*VDD V VIH Input high voltage 0.7*VDD - VDD V - 0.2*VDD - V VHY[*1] Hysteresis voltage of schmitt input -1 ILK[*2] VSS < VIN < VDD, 1 Open-drain or input only mode A Input leakage current -1 RPU[*1] [*3] Pull up resistor Test Conditions VDD < VIN < 5 V, Open-drain or input only mode on any other 5v tolerance pins 1 - 45 kΩ - 120 - VDD = 3.3 V, Quasi mode VDD = 1.8 V, Quasi mode Note: 1. Guaranteed by characterization result, not tested in production. 2. Leakage could be higher than the maximum value, if abnormal injection happens. 3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than the maximum value, if positive current is injected on adjacent pins Table 8.3-10 I/O Input Characteristics Apr. 29, 2020 Page 244 of 283 Rev 2.01 M031/M032 8.3.6.2 I/O Output Characteristics Symbol Parameter Min Typ Max Unit -25.5 -28 -31 µA -19 -22 -24 µA -10.5 -13 -16 µA -8 -10 -15 mA -6 -8 -13 mA -3.5 -5.5 -10.5 mA 7.5 9 14.5 mA 6 7.5 13 mA 3.5 5 10.5 mA - 5 - pF Source current for quasibidirectional mode and high level ISR[*1] [*2] Source current for pushpull mode and high level ISK[*1] [*2] CIO [*1] Sink current for pushpull mode and low level I/O pin capacitance Test Conditions VDD = 3.3 V VIN=(VDD-0.4) V VDD = 2.5 V VIN=(VDD-0.4) V VDD = 1.8 V VIN=(VDD-0.4) V VDD = 3.3 V VIN=(VDD-0.4) V VDD = 2.5 V VIN=(VDD-0.4) V VDD = 1.8 V VIN=(VDD-0.4) V VDD = 3.3 V VIN= 0.4 V VDD = 2.5 V VIN= 0.4 V VDD = 1.8 V VIN= 0.4 V Note: 2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not exceed ΣIDD and ΣISS. Table 8.3-11 I/O Output Characteristics 8.3.6.3 nRESET Input Characteristics Symbol Parameter Min Typ Max Unit VILR Negative going threshold, nRESET - - 0.3*VDD V VIHR Positive going threshold, nRESET 0.7*VDD - - V - 45 - RRST[*1] Internal nRESET pull up resistor tFR[*1] Test Conditions VDD = 3.3 V KΩ - 120 - - 32 - VDD = 1.8 V Normal run and Idle mode µs nRESET input filtered pulse time 75 - 155 Power down mode Note: 1. Guaranteed by characterization result, not tested in production. 2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable. Table 8.3-12 nRESET Input Characteristics Apr. 29, 2020 Page 245 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 1. Guaranteed by characterization result, not tested in production. M031/M032 8.4 AC Electrical Characteristics 8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) The 48 MHz RC oscillator is calibrated in production. Symbol. VDD Parameter Operating voltage Oscillator frequnecy Min Typ Max Unit 1.8 - 3.6 V 47.52 48 48.48 MHz -1 - 1 % -2[*1] - 2[*1] % Test Conditions TA = 25 °C, VDD = 3.3V fHRC Frequency drift over temperarure and volatge IHRC[*1] Operating current - 1655 - µA TS[*2] Stable time - 11 15 µs TA = 25 °C, VDD = 3.3V TA = -40C ~ +105 °C, VDD = 1.8 ~ 3.6V TA = -40C ~ +105 °C, VDD = 1.8 ~ 3.6V Note: 1. Guaranteed by characterization result, not tested in production. 2. Guaranteed by design. Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 246 of 283 Rev 2.01 M031/M032 Test condition: VDD=3.6 V, Temp = -40~125°C (b) Test condition: VDD=1.8 V, Temp = -40~125°C M031/M032 SERIES DATASHEET (a) Note: 1. The graph is a statistical result using a limited number of samples. For the actual characteristic range, please refer to Table 8.4-1. Figure 8.4-1 HIRC vs. Temperature Apr. 29, 2020 Page 247 of 283 Rev 2.01 M031/M032 8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) Symbol VDD Parameter Operating voltage Oscillator frequnecy FLRC [*2] Min [*1] Typ Max [*1] Unit 1.8 - 3.6 V 38.016 38.4 38.784 kHz -1 - 1 % -15 - 15 % Frequency drift over temperarure and volatge Test Conditions TA = 25 °C, VDD = 3.3V TA=-40~105 °C VDD=1.8V~3.6V Without software calibration ILRC Operating current - 1 - µA TS Stable time - 500 - μs VDD = 3.3V TA=-40~105 °C VDD=1.8V~3.6V Note: 1. Guaranteed by characterization, not tested in production. 2. The 38.4 kHz low speed RC oscillator can be calibrated by user. 3. Guaranteed by design. Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 248 of 283 Rev 2.01 M031/M032 8.4.3 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Min[*1] Typ Max[*1] Unit 1.8 - 3.6 V Internal feedback resister - 200 - kΩ Oscillator frequency 4 - 32 MHz - 120 200 4 MHz, Gain = L0 170 300 8 MHz, Gain = L1 - 250 450 - 350 600 16 Mhz, Gain = L3 500 850 24 MHz, Gain = L4 - 650 1100 32 MHz, Gain = L7 - 1700 2200 4 MHz, Gain = L0 900 1100 8 MHz, Gain = L1 - 600 740 - 450 650 16 Mhz, Gain = L3 - 400 600 24 MHz, Gain = L4 - 350 550 32 MHz, Gain = L7 40 - 60 % - 1 - V Symbol VDD Rf fHXT IHXT TS Vpp Operating voltage Current consumption Stable time Duty cycle Peak-to-peak amplitude A s Test Conditions 12 MHz, Gain = L2 12 MHz, Gain = L2 Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-3 External 4~32 MHz High Speed Crystal (HXT) Oscillator Apr. 29, 2020 Page 249 of 283 Rev 2.01 M031/M032 SERIES DATASHEET DuHXT Parameter M031/M032 Symbol Rs Parameter Min [*1] Typ Max [*1] - - 150 Crystal @4 MHz - - 50 Crystal @12 MHz - - 40 - - 40 Crystal @24 MHz - - 40 Crystal @32 MHz Equivalent series resisotr(ESR) Unit Ω Test Conditions Crystal @16 MHz Note: 1. Guaranteed by characterization, not tested in production. 2. Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life. If Safety factor isn’t enough, the HXT gain should be increased. RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is only used to measure Safety factor (Sf) and is not suitable for mass production. XT1_OUT XT1_IN RADD C2 C1 Table 8.4-4 External 4~32 MHz High Speed Crystal Characteristics M031/M032 SERIES DATASHEET 8.4.3.1 Typical Crystal Application Circuits For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF range, designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C1 and C2. CRYSTAL C1 C2 R1 4 MHz ~ 32 MHz 10 ~ 25 pF 10 ~ 25 pF without XT1_OUT C2 XT1_IN R1 C1 Figure 8.4-2 Typical Crystal Application Circuit Apr. 29, 2020 Page 250 of 283 Rev 2.01 M031/M032 8.4.4 External 4~32 MHz High Speed Clock Input Signal Characteristics For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive external clock. The external clock signal has to respect the below Table. The characteristics result from tests performed using a wavefrom generator. Symbol fHXT_ext Parameter External user clock source frequency Min [*1] Typ Max [*1] Unit 1 - 32 MHz Test Conditions tCHCX Clock high time 8 - - ns tCLCX Clock low time 8 - - ns tCLCH Clock rise time - - 10 ns Low (10%) to high level (90%) rise time tCHCL Clock fall time - - 10 ns High (90%) to low level (10%) fall time 40 - 60 % DuE_HXT Duty cycle VIH Input high voltage 0.7*VDD - VDD V VIL Input low voltage VSS - 0.3*VDD V External clock source XT1_IN tCLCL M031/M032 SERIES DATASHEET tCLCH VIH VIL 90% tCLCX 10% tCHCL tCHCX Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-5 External 4~32 MHz High Speed Clock Input Signal Apr. 29, 2020 Page 251 of 283 Rev 2.01 M031/M032 8.4.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Symbol Parameter Min [*1] Typ Max [*1] Unit VDD Operation voltage 1.8 - 3.6 V TLXT Temperature range -40 - 105 C Rf Internal feedback resistor - 6.5 - MΩ FLXT Oscillator frequency ILXT Current consumption 32.768 Test Conditions kHz - 1.5 6 - 2 6 ESR=35 kΩ, Gain = L1 A ESR=70 kΩ, Gain = L2 TsLXT Stable time - 500 900 ms DuLXT Duty cycle 30 - 70 % Vpp Peak-to-peak amplitude TBD 500 - mV Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Symbol M031/M032 SERIES DATASHEET Rs Parameter Equivalnet Series Resisotr(ESR) Min Typ Max Unit Test Conditions - 35 70 kΩ Crystal @32.768 kHz Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics 8.4.5.1 Typical Crystal Application Circuits CRYSTAL 32.768 kHz, ESR < 70 KΩ C1 C2 R1 20 pF 20 pF without X32_OUT C2 X32_IN R1 C1 Figure 8.4-3 Typical 32.768 kHz Crystal Application Circuit Apr. 29, 2020 Page 252 of 283 Rev 2.01 M031/M032 8.4.6 External 32.768 kHz Low Speed Clock Input Signal Characteristics For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive external clock. The external clock signal has to respect the below Table. The characteristics result from tests performed using a wavefrom generator. Symbol Parameter Min [*1] Typ Max [*1] Unit - 32.768 - kHz Test Conditions fLSE_ext External clock source frequency tCHCX Clock high time 450 - - ns tCLCX Clock low time 450 - - ns tCLCH Clock rise time - - 50 ns Low (10%) to high level (90%) rise time tCHCL Clock fall time - - 50 ns High (90%) to low level (10%) fall time 40 - 60 % DuE_LXT Duty cycle Xin_VIH LXT input pin input high voltage 0.7*VDD - VDD V Xin_VIL LXT input pin input low voltage VSS - 0.3*VDD V External clock source X32_IN tCLCL tCLCH VIH 90% M031/M032 SERIES DATASHEET tCLCX 10% VIL tCHCL tCHCX Note: 1. Guaranteed by design, not tested in production Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal Apr. 29, 2020 Page 253 of 283 Rev 2.01 M031/M032 8.4.7 PLL Characteristics Min[*1] Typ Max[*1] Unit PLL input clock 3.2 - 32 MHz fPLL_OUT PLL multiplier output clock 50 - 144 MHz fPLL_REF PLL reference clock 0.8 - 8 MHz fPLL_VCO PLL voltage controlled oscillator 200 - 500 MHz PLL locking time - - 500 µs Jitter[*2] Cycle-to-cycle Jitter - 200 350 ps IDD Power consumption - 5 9 mA Symbol fPLL_in TL Parameter Test Conditions VDD =3.3V @ fPLL_OUT = 144 MHz Note: 1. Guaranteed by characterization, not tested in production 2. Guaranteed by design, not tested in production Table 8.4-9 PLL Characteristics M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 254 of 283 Rev 2.01 M031/M032 8.4.8 I/O AC Characteristics Symbol tf(IO)out tr(IO)out fmax(IO)out[*3] IDIO[*4] Parameter Typ. Max[*1]. - 5.5 - 3 Output high (90%) to low level (10%) fall time Unit Test Conditions[*2] CL = 30 pF, VDD >= 2.7 V CL = 10 pF, VDD >= 2.7 V ns - 8.5 CL = 30 pF, VDD >= 1.8 V - 4.5 CL = 10 pF, VDD >= 1.8 V - 5.5 CL = 30 pF, VDD >= 2.7 V - 3 Output low (10%) to high level (90%) rise time CL = 10 pF, VDD >= 2.7 V ns - 8.5 CL = 30 pF, VDD >= 1.8 V - 4.5 CL = 10 pF, VDD >= 1.8 V - 60 CL = 30 pF, VDD >= 2.7 V - 110 I/O maximum frequency CL = 10 pF, VDD >= 2.7 V MHz - 40 CL = 30 pF, VDD >= 1.8 V - 75 CL = 10 pF, VDD >= 1.8 V 2.77 - 1.19 - I/O dynamic current consumption CL = 30 pF, VDD = 3.3 V, f(IO)out = 24 MHz CL = 10 pF, VDD = 3.3 V, mA - CL = 30 pF, VDD = 3.3 V, f(IO)out = 6 MHz 0.3 - CL = 10 pF, VDD = 3.3 V, f(IO)out = 6 MHz Note: 1. Guaranteed by characterization result, not tested in production. 2. CL is a external capacitive load to simulate PCB and device loading. 3. The maximum frequency is defined by . 4. The I/O dynamic current consumption is defined by Table 8.4-10 I/O AC Characteristics Apr. 29, 2020 Page 255 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 0.69 f(IO)out = 24 MHz M031/M032 8.5 Analog Characteristics 8.5.1 LDO Symbol Parameter Min Typ Max Unit VDD Power supply 1.8 - 3.6 V VLDO Output voltage - 1.8 - V -40 - 105 °C TA Temperature Test Condition Note 1. It is recommended a 0.1μF bypass capacitor is connected between V DD and the closest VSS pin of the device. 2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest V SS pin of the device. 8.5.2 Reset and Power Control Block Characteristics The parameters in below table are derived from tests performed under ambient temperature. Symbol Parameter Min Typ Max Unit µA Test Conditions IPOR[*1] POR operating current - 20 30 ILVR[*1] LVR operating current - 2 3.6 AVDD = 3.6V IBOD[*1] BOD operating current - 3 5.5 AVDD = 3.6V VPOR POR reset voltage 1.35 1.5 1.65 VLVR LVR reset voltage 1.6 1.7 1.8 VBOD BOD brown-out detect voltage 1.8 2.0 2.2 BODVL = 0 2.3 2.5 2.7 BODVL = 1 V AVDD = 3.6V - M031/M032 SERIES DATASHEET TLVR_SU[*1] LVR startup time - 200 - TLVR_RE[*1] LVR respond time - 16 - - TBOD_SU[*1] BOD startup time - 1000 - - TBOD_RE[*1] BOD respond time - 120 - - RVDDR[*1] VDD rise time rate 10 - - RVDDF[*1] VDD fall time rate 10 - - POR Enabled 80 - - LVR Enabled 250 - - BOD 2.0V Enabled 150 - - BOD 2.5V Enabled µs µs/V - POR Enabled Note: 1. Guaranteed by characterization, not tested in production. 2. Design for specified applcaiton. Table 8.5-1 Reset and Power Control Unit Apr. 29, 2020 Page 256 of 283 Rev 2.01 M031/M032 VDD RVDDR RVDDF VBOD VLVR VPOR Time Figure 8.5-1 Power Ramp Up/Down Condition M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 257 of 283 Rev 2.01 M031/M032 8.5.3 12-bit SAR ADC Symbol Min Typ Max Unit Temperature -40 - 105 °C AVDD Analog operating voltage 1.8 - 3.6 V VREF Reference voltage 1.8 - AVDD V 0 - VREF V TA Parameter VIN ADC channel input voltage VCM Common-Mode Input Range VREF/2 V Test Conditions VDD = AVDD Full differential input AVDD = VDD = VREF = 3.3 V IADC[*1] Operating current (AVDD + VREF current) - - 355 µA FADC = 34 MHz TCONV = 17 * TADC NR FADC[*1] Resolution 12 Bit ADC Clock frequency 4 - 34 TSMP Sampling Time 1 - 256 TSMP = 1/FADC (EXTSMPT(ADC_ESMPCTL[7:0]) + 1 ) * TADC TCONV Conversion time 17 - 272 1/FADC TCONV = TSMP + 16 * TADC FSPS[*1] Sampling Rate 0.236 - 2 20 - - μs -2 - +2 LSB +4 LSB +2 LSB +4 LSB +4 LSB +4 LSB +4 LSB +10 LSB +4 LSB 1/TADC TEN M031/M032 SERIES DATASHEET INL[*1] Enable to ready time -1 - -4 - -4 - VREF = AVDD TSSOP20 and TSSOP28 VREF = AVDD, except TSSOP20 and TSSOP28 VREF = AVDD TSSOP20 and TSSOP28 VREF = AVDD, except TSSOP20 and TSSOP28 VREF = AVDD TSSOP20 and TSSOP28 VREF = AVDD, except TSSOP20 and TSSOP28 Offset error -4 EA[*1] except TSSOP20 and TSSOP28 Gain error -10 EO[*1]T VREF = AVDD, Differential Non-Linearity Error -1 EG[*1] FSPS = FADC / TCONV MSPS EXTSMPT(ADC_ESMPCTL[7:0]) =0 Integral Non-Linearity Error -4 DNL[*1] MHz Absolute Error Apr. 29, 2020 -4 - Page 258 of 283 VREF = AVDD TSSOP20 and TSSOP28 VREF = AVDD, except TSSOP20 and TSSOP28 Rev 2.01 M031/M032 Symbol Parameter Min Typ -8 ENOB[*1] [*1] SINAD Max Unit +8 LSB bits Effective number of bits - - TBD Signal-to-noise and distortion ratio - - TBD Signal-to-noise ratio - - TBD Test Conditions VREF = AVDD TSSOP20 and TSSOP28 FADC = 34 MHz AVDD = VDD = VREF = 3.3 V Input Frequency = 20 kHz SNR[*1] [*1] THD dB Total harmonic distortion - - TBD CIN[*1] Internal Capacitance - 2.9 - pF RIN[*1] Internal Switch Resistance - - 2 kΩ REX[*1] External input impedance - - 50 kΩ TA = 25 °C Note: 1. Guaranteed by characterization result, not tested in production. 2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on 12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real signal and reduce the ADC accuracy. VDD VEX EADC_CHx RIN 12-bit Converter CIN CEX Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins should be avoided to protect the conversion being performed on another analog input. It is recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may potentially inject currents. Apr. 29, 2020 Page 259 of 283 Rev 2.01 M031/M032 SERIES DATASHEET REX M031/M032 EF (Full scale error) = EO + EG Gain Error EG Offset Error EO 4095 4094 4093 4092 Ideal transfer curve 7 6 ADC output code 5 Actual transfer curve 4 3 2 DNL 1 1 LSB Offset Error EO Analog input voltage (LSB) 4095 M031/M032 SERIES DATASHEET Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. Apr. 29, 2020 Page 260 of 283 Rev 2.01 M031/M032 8.5.4 Analog Comparator Controller (ACMP) The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Min Typ Analog supply voltage 1.8 - 3.6 V TA Temperature -40 - 105 °C IDD Operating current - 30 45 A AVDD Parameter Max Unit Test Conditions VDD = AVDD VCM[*2] Input common mode voltage range 0.35 1/2 AVDD AVDD -0.3 VDI[*2] Differential input voltage sensitivity 10 20 - mV Hysteresis disable Voffset[*2] Input offset voltage - 10 20 mV Hysteresis disable Vhys[*2] Hysteresis window 40 90 140 mV DC voltage Gain 45 65 75 dB Av [*1] Td[*2] Propagation delay - - 400 nS TSetup[*2] Setup time - - 4 uS ACRV[*2] CRV output voltage -5 - 5 % RCRV[*2] Unit resistor value - 4.2 - kΩ Setup time - - 350 µS CRV output voltage settle to ±5% Operating current - 30 45 A TSETUP_CRV[*2] IDD_CRV[*2] AVDD x (1/6+CRVCTL/24) Note: 1. Guaranteed by design, not tested in production M031/M032 SERIES DATASHEET 2. Guaranteed by characteristic, not tested in production Table 8.5-2 ACMP Characteristics Apr. 29, 2020 Page 261 of 283 Rev 2.01 M031/M032 8.6 Communications Characteristics 8.6.1 QSPI/SPI Dynamic Characteristics Specificaitons[*1] Symbol FSPICLK 1/ TSPICLK Test Conditions Parameter Min Typ Max - - 24 SPI clock frequency Unit 2.7 V ≤ VDD ≤ 3.6 V, CL = 25 pF MHz - - 1.8 V ≤ VDD ≤ 3.6 V, CL = 25 pF 24 tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns tDS Data input setup time 2 - - ns tDH Data input hold time 4 - - ns - - 5 ns 2.7 V ≤ VDD ≤ 3.6 V, CL = 25 pF tV Data output valid time - - 8.5 ns 1.8 V ≤ VDD ≤ 3.6 V, CL = 25 pF Note: 1. Guaranteed by design. Table 8.6-1 QSPI/SPI Master Mode Characteristics tCLKH tCLKL CLKP=0 M031/M032 SERIES DATASHEET SPICLK CLKP=1 tV MOSI Data Valid Data Valid tDS MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid tV Data Valid MOSI tDS MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 8.6-1 QSPI/SPI Master Mode Timing Diagram Apr. 29, 2020 Page 262 of 283 Rev 2.01 M031/M032 Specificaitons[*1] Symbol FSPICLK 1/ TSPICLK Test Conditions Parameter Min Typ Max - - 16 SPI clock frequency Unit 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF MHz - - 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF 16 tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns 1 TSPICLK + 2ns tSS - 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF ns Slave select setup time 1 TSPICLK + 3ns - - 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF tSH Slave select hold time 1 TSPICLK - - ns tDS Data input setup time 1.5 - - ns tDH Data input hold time 3.5 - - ns - - 17.5 tV Data output valid time 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF ns - - 25 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-2 QSPI/SPI Slave Mode Characteristics M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 263 of 283 Rev 2.01 M031/M032 SSACTPOL=1 SPI SS tSS tSH SSACTPOL=0 tCLKH CLKPOL=0 TXNEG=1 RXNEG=0 tCLKL SPI Clock CLKPOL=1 TXNEG=0 RXNEG=1 tV SPI data output (SPI_MISO) Data Valid Data Valid tDS SPI data input (SPI_MOSI) Data Valid SSACTPOL=1 SPI SS tDH Data Valid tSS tSH SSACTPOL=0 CLKPOL=0 TXNEG=0 RXNEG=1 tCLKH tCLKL SPI Clock CLKPOL=1 TXNEG=1 RXNEG=0 tV M031/M032 SERIES DATASHEET SPI data output (SPI_MISO) Data Valid tDS SPI data input (SPI_MOSI) Data Valid tDH Data Valid Data Valid Figure 8.6-2 QSPI/SPI Slave Mode Timing Diagram Apr. 29, 2020 Page 264 of 283 Rev 2.01 M031/M032 SPI - I2S Dynamic Characteristics 8.6.2 Symbol Parameter Min [*1] Max [*1] 80 - I2S clock high time tw(CKH) 2 Unit Test Conditions Master fPCLK = 48 MHz, data: 24 bits, audio frequency = 128 kHz tw(CKL) I S clock low time 80 - tv(WS) WS valid time 2 6 th(WS) WS hold time 2 - Master mode tsu(WS) WS setup time 24 - Slave mode th(WS) WS hold time 0 - Slave mode 30 70 10 - Master receiver 7 - Slave receiver 7 - Master receiver 4 - Master mode ns 2 DuCy(SCK) tsu(SD_MR) I S slave input clock duty cycle Slave mode Data input setup time tsu(SD_SR) th(SD_MR) % Data input hold time th(SD_SR) Slave receiver ns tv(SD_ST) Data output valid time - 25 Slave transmitter (after enable edge) th(SD_ST) Data output hold time 4 - Slave transmitter (after enable edge) tv(SD_MT) Data output valid time - 4 Master transmitter (after enable edge) th(SD_MT) Data output hold time 0 - Master transmitter (after enable edge) Note: 1. Guaranteed by design. CK output CPOL = 0 tw(CKH) CPOL = 1 tw(CKL) tv(WS) th(WS) WS output tv(SD_ST) SDtransmit LSB transmit(2) MSB transmit tsu(SD_MR) SDreceive LSB receive(2) Bitn transmit th(SD_ST) LSB transmit th(SD_MR) MSB receive Bitn receive LSB receive 2 Figure 8.6-3 I S Master Mode Timing Diagram Apr. 29, 2020 Page 265 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 2 Table 8.6-3 I S Characteristics M031/M032 CK Input CPOL = 0 CPOL = 1 tw(CKH) tw(CKL) th(WS) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit tsu(SD_SR) SDreceive LSB receive(2) Bitn transmit th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive 2 Figure 8.6-4 I S Slave Mode Timing Diagram M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 266 of 283 Rev 2.01 M031/M032 8.6.3 I2C Dynamic Characteristics Symbol Parameter Standard Mode[1][2] Fast Mode[1][2] Min Max Min Max Unit tLOW SCL low period 4.7 - 1.3 - µs tHIGH SCL high period 4 - 0.6 - µs tSU; STA Repeated START condition setup time 4.7 - 0.6 - µs tHD; STA START condition hold time 4 - 0.6 - µs tSU; STO STOP condition setup time 4 - 0.6 - µs tBUF Bus free time 4.7[3] - 1.2[3] - µs tSU;DAT Data setup time 250 - 100 - ns tHD;DAT Data hold time 0[4] 3.45[5] 0[4] 0.8[5] µs tr SCL/SDA rise time - 1000 20+0.1Cb 300 ns tf SCL/SDA fall time - 300 - 300 ns Cb Capacitive load for each bus line - 400 - 400 pF Note: 1. Guaranteed by characteristic, not tested in production 2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz to achieve the maximum fast mode I2C frequency. 3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition. 5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 2 Table 8.6-4 I C Characteristics STOP Repeated START START STOP SDA tBUF tLOW tr SCL tHD;STA tf tHIGH tHD;DAT tSU;DAT tSU;STA tSU;STO 2 Figure 8.6-5 I C Timing Diagram Apr. 29, 2020 Page 267 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. M031/M032 8.6.4 USCI - SPI Dynamic Characteristics Symbol FSPICLK 1/ TSPICLK Parameter Min [*1] Typ Max[*1] - - 24 SPI clock frequency Unit Test Conditions 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF MHz - - 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF 24 tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns tDS Data input setup time 2 - - ns tDH Data input hold time 4 - - ns - - 5 ns 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF tV Data output valid time - - 8.5 ns 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-5 USCI-SPI Master Mode Characteristics tCLKH tCLKL CLKP=0 SPICLK CLKP=1 tV MOSI Data Valid Data Valid M031/M032 SERIES DATASHEET tDS MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid tV Data Valid MOSI tDS MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 8.6-6 USCI-SPI Master Mode Timing Diagram Apr. 29, 2020 Page 268 of 283 Rev 2.01 M031/M032 Symbol FSPICLK 1/ TSPICLK Parameter Min [*1] Typ Max [*1] - - 7 SPI clock frequency 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF MHz - - 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF 7 tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns 1 TSPICLK + 2ns tSS Test Conditions Unit - 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF ns Slave select setup time 1 TSPICLK + 3ns - - 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF tSH Slave select hold time 1 TSPICLK - - ns tDS Data input setup time 2 - - ns tDH Data input hold time 4 - - ns - - 65 tV Data output valid time 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF ns - - 70 1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-6 USCI-SPI Slave Mode Characteristics M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 269 of 283 Rev 2.01 M031/M032 SSACTPOL=1 SPI SS tSS tSH SSACTPOL=0 tCLKH CLKPOL=0 TXNEG=1 RXNEG=0 tCLKL SPI Clock CLKPOL=1 TXNEG=0 RXNEG=1 tV SPI data output (SPI_MISO) Data Valid Data Valid tDS SPI data input (SPI_MOSI) Data Valid SSACTPOL=1 SPI SS tDH Data Valid tSS tSH SSACTPOL=0 CLKPOL=0 TXNEG=0 RXNEG=1 tCLKH tCLKL SPI Clock CLKPOL=1 TXNEG=1 RXNEG=0 tV M031/M032 SERIES DATASHEET SPI data output (SPI_MISO) Data Valid tDS SPI data input (SPI_MOSI) Data Valid tDH Data Valid Data Valid Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram Apr. 29, 2020 Page 270 of 283 Rev 2.01 M031/M032 8.6.5 USCI - I2C Dynamic Characteristics Symbol Parameter Standard Mode[1][2] Fast Mode[1][2] Min Max Min Max Unit tLOW SCL low period 4.7 - 1.3 - µs tHIGH SCL high period 4 - 0.6 - µs tSU; STA Repeated START condition setup time 4.7 - 0.6 - µs tHD; STA START condition hold time 4 - 0.6 - µs tSU; STO STOP condition setup time 4 - 0.6 - µs tBUF Bus free time 4.7[3] - 1.2[3] - µs tSU;DAT Data setup time 250 - 100 - ns tHD;DAT Data hold time 0[4] 3.45[5] 0[4] 0.8[5] µs tr SCL/SDA rise time - 1000 20+0.1Cb 300 ns tf SCL/SDA fall time - 300 - 300 ns Cb Capacitive load for each bus line - 400 - 400 pF Note: 1. Guaranteed by characteristic, not tested in production 2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz to achieve the maximum fast mode I2C frequency. 3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition. 5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 2 Table 8.6-7 USCI-I C Characteristics STOP Repeated START START STOP SDA tBUF tLOW tr SCL tHD;STA tf tHIGH tHD;DAT tSU;DAT tSU;STA tSU;STO 2 Figure 8.6-8 USCI-I C Timing Diagram Apr. 29, 2020 Page 271 of 283 Rev 2.01 M031/M032 SERIES DATASHEET 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. M031/M032 8.6.6 USB Characteristics 8.6.6.1 USB Full-Speed Characteristics Symbol Parameter Min [*1] Typ Max [*1] Unit 5.25 V Test Conditions USB full speed transceiver operating voltage 4.4 USB Internal power regulator output 3.0 3.3 3.6 V VIH Input high (driven) 2.0 - - V - VIL Input low - - 0.8 V - VDI Differential input sensitivity 0.2 - - V |(USB_D+) - (USB_D-)| 0.8 - 2.5 V Includes VDI range 0.8 - 2.0 V - Receiver hysteresis - 200 - mV - VOL Output low (driven) 0 - 0.3 V - VOH Output high (driven) 2.8 - 3.6 V - VCRS Output signal cross voltage 1.3 - 2.0 V - RPU Pull-up resistor 1.19 - 1.9 kΩ - VTRM Termination voltage for upstream port pull-up (RPU) 3.0 - 3.6 V VBUS VDD33[*2] Differential VCM common-mode range Single-ended receiver threshold VSE M031/M032 SERIES DATASHEET ZDRV[*3] Driver output resistance - 10 - Ω Steady state drive CIN Transceiver capacitance - - 26 pF Pin to GND Note: 1. Guaranteed by characterization result, not tested in production. 2. To ensure stability, an external 1 μF output capacitor, 1uF external capacitor must be connected between the USB_VDD33_CAP pin and the closest GND pin of the device. 3. USB_D+ and USB_D- must be connected with series resistors to fit USB Full-speed spec request (28 ~ 44Ω). Table 8.6-8 USB Full-Speed Characteristics 8.6.6.2 USB Full-Speed PHY characteristics Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions TFR rise time 4 - 20 ns CL=50 pF TFF fall time 4 - 20 ns CL=50 pF rise and fall time matching 90 - 111.11 % TFRFF = TFR/TFF TFRFF Note: 1. Guaranteed by characterization result, not tested in production. Table 8.6-9 USB Full-Speed PHY Characteristics Apr. 29, 2020 Page 272 of 283 Rev 2.01 M031/M032 8.7 Flash DC Electrical Characteristics The devices are shipped to customers with the Flash memory erased. Symbol Parameter Min Typ Max Unit 1.62 1.8 1.98 V Test Condition VFLA[1] Supply voltage TERASE Page erase time - 20 - ms TPROG Program time - 60 - µs IDD1 Read current - 7 - mA IDD2 Program current - 8 - mA IDD3 Erase current - 12 - mA 20,000 - 65 - - year 20 kcycle[3] TJ = 55°C 10 - - year 20 kcycle[3] TJ = 85°C 4 - - year 20 kcycle[3] TJ = 125°C NENDUR TRET Endurance Data retention cycles[2] TA = 25°C TJ = -40°C~125°C Note: 1. VFLA is source from chip internal LDO output voltage. 2. Number of program/erase cycles. 3. Guaranteed by design. M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 273 of 283 Rev 2.01 M031/M032 9 PACKAGE DIMENSIONS 9.1 TSSOP 20 (4.4x6.5x0.9 mm) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 274 of 283 Rev 2.01 M031/M032 9.2 TSSOP 28 (4.4x9.7x1.0 mm) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 275 of 283 Rev 2.01 M031/M032 9.3 QFN 33L (4X4x0.8 mm Pitch:0.40 mm) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 276 of 283 Rev 2.01 M031/M032 9.4 LQFP 48L (7x7x1.4 mm Footprint 2.0mm) H 36 25 37 24 48 13 H 12 1  M031/M032 SERIES DATASHEET Controlling dimension : Millimeters Symbol A A1 A2 b c D E e HD HE L L1 Y 0 Apr. 29, 2020 Dimension in inch Dimension in mm Min Nom Max Min Nom Max 0.002 0.004 0.006 0.05 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.008 0.10 0.15 0.20 0.272 0.276 0.280 6.90 7.00 7.10 0.272 0.276 0.280 6.90 7.00 7.10 0.020 0.026 0.35 0.50 0.65 0.053 0.014 0.10 0.15 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 7 Page 277 of 283 0.10 0 7 Rev 2.01 M031/M032 9.5 LQFP 64L (7x7x1.4 mm Footprint 2.0 mm) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 278 of 283 Rev 2.01 M031/M032 9.6 LQFP 128L (14x14x1.4 mm Footprint 2.0 mm) M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 279 of 283 Rev 2.01 M031/M032 10 ABBREVIATIONS 10.1 Abbreviations M031/M032 SERIES DATASHEET Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EADC Enhanced Analog-to-Digital Converter EBI External Bus Interface EMAC Ethernet MAC Controller EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 12 MHz Internal High Speed RC Oscillator HXT 4~32 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation Apr. 29, 2020 Page 280 of 283 Rev 2.01 M031/M032 QEI Quadrature Encoder Interface SD Secure Digital SPI Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TK Touch Key TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 10.1-1 List of Abbreviations M031/M032 SERIES DATASHEET Apr. 29, 2020 Page 281 of 283 Rev 2.01 M031/M032 11 REVISION HISTORY Date Revision 2018.12.24 1.00 2019.02.25 1.01 Description Initial version. 1. Modified ISP ROM size in section 3.2. 2. Modified HIRC trim reference clock in section 6.27.2. 1. Updated TBD values in Chapter 8. 2. Changed test condition of data retention from TA to TJ in section 8.7. 2019.07.15 1.02 3. Updated Figure 6.3-6 to add a USB block and remove the temperature sensor block. 4. Added multi-function pin tables in section 4.1. 2019.08.26 1.03 2019.11.04 2.00 1. Updated Figure 8.4-1 HIRC vs. Temperature in section 8.4.1. 2. Removed Figure 8.4-2 LIRC vs. Temperature in section 8.4.2. Added new part numbers for M031xI / M032xI / M031xG / M032xG / M032xC / M032xD and updated the description of the new part numbers. 1. Modified Multi-function Pin Diagram name and Multi-function Pin Table in section 4.1.4.1 and 4.1.4.2. 2. Changed the Pin Description tables to Pin Mapping tables and Pin Function Description table in section 4.2 and 4.3. 3. Updated Supply Current Characteristics for M03xB/M03xC/M03xD/ M03xE in section 8.3.1. 4. Updated Band-gap voltage value in Table 8.2-1. 2020.04.29 2.01 5. Modified the value of SYS_RSTSTS after Power-On-Reset(POR) in Table 6.3-1 6. Updated I/O Output Characteristics in Table 8.3-11 M031/M032 SERIES DATASHEET 7. Added a note about the Safety factor for High Speed Crystal(HXT) in Table 8.4-4 8. Added notes about the hardware reference design for ICE_DAT, ICE_CLK and nRESET pins in section 4.3 and chapter 7. 9. Updated QFN 33L (4X4x0.8 mm Pitch:0.40 mm) Package Dimensions in section 9.3 Apr. 29, 2020 Page 282 of 283 Rev 2.01 M031/M032 Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Apr. 29, 2020 Page 283 of 283 Rev 2.01 M031/M032 SERIES DATASHEET Important Notice