AZC099-04S.R7G

AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Features

ESD Protect for 4 high-speed I/O channels Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air), ±15kV (contact) IEC 61000-4-4 (EFT) (5/50ns) 40A IEC 61000-4-5 (Lightning) (8/20µs) 5.5A For low operating voltage applications: 5V, 4.2V, 3.3V, 2.5V
Low capacitance : 1.0pF typical
Fast turn-on and Low clamping voltage
Array of surge rated diodes with internal equivalent TVS diode
Small package saves board space
Solid-state silicon-avalanche and active circuit triggering technology AZC099-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ±8kV contact discharge). One AZC099-04S can be used to replace 4 BAV99 devices in a 5V application or a lower than 5V application.
Applications Circuit Diagram 5 1 3 4 6 2 Video Graphics Cards USB2.0 Power and Data lines protection
Notebook and PC Computers
Monitors and Flat Panel Displays
IEEE 1394 Firewire Ports
SIM ports

Pin Configuration Description AZC099-04S is a high performance and low cost design which includes surge rated diode arrays to protect high speed data interfaces. The AZC099-04S family has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. AZC099-04S is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. Revision 2013/08/27 ©2013-2014 Amazing Micro. I/O 4 VDD I/O 3 6 5 4 1 2 3 GND I/O 2 I/O 1 JEDEC SOT23-6L (Top View) 1 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER PARAMETER RATING UNITS Peak Pulse Current (tp =8/20µs) IPP 5.5 A Operating Supply Voltage (VDD-GND) VDC 6 V ESD per IEC 61000-4-2 (Air) VESD 15 kV ESD per IEC 61000-4-2 (Contact) 15 Lead Soldering Temperature TSOL 260 (10 sec.) o Operating Temperature TOP -55 to +85 o o C C Storage Temperature TSTO -55 to +150 DC Voltage at any I/O pin VIO (GND – 0.5) to (VDD + 0.5) PARAMETER Reverse Stand-Off Voltage Reverse Leakage Current Channel Leakage Current Reverse Breakdown Voltage Forward Voltage ELECTRICAL CHARACTERISTICS SYMBOL CONDITIONS VRWM Pin 5 to pin 2, T=25 oC ILeak ICH_Leak VBV VF UNITS V VRWM = 5V, T=25 oC, Pin 5 to pin 2 2 µA VPin 5 = 5V, VPin 2 = 0V, T=25 oC 1 µA IPP=5A, tp=8/20µs, T=25 oC Any Channel pin to Ground IEC 61000-4-2 +6kV, T=25 oC, Contact mode, Any Channel pin to Ground. TYP V MAX 5 IBV = 1mA, T=25 oC Pin 5 to Pin 2 IF = 15mA, T=25 oC Pin 2 to Pin 5 MIN C 6.2 V 0.8 1.2 V 9 10 V Clamping Voltage VCL ESD Holding Voltage Vhold Channel Input Capacitance CIN Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC, Any Channel pin to Ground 1.0 1.2 pF Channel to Channel Input Capacitance CCROSS Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Between Channel pins 0.1 0.12 pF Variation of Channel Input Capacitance △CIN Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Channel_x pin to Ground - Channel_y pin to Ground 0.03 0.05 pF Revision 2013/08/27 ©2013-2014 Amazing Micro. 2 11.5 V www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Typical Characteristics Clamping Voltage vs. Peak Pulse Current Power Derating Curve 100 10.5 90 10.0 Clamping Voltage (V) 11.0 % of Rated Power or IPP 110 80 70 60 50 40 30 9.5 9.0 8.5 8.0 7.5 20 I/O pin to GND pin 6.5 10 6.0 4.5 0 0 25 50 75 100 125 150 5.0 Ambient Temperature, TA ( C) 4.5 1.8 4.0 1.6 Input Capacitance (pF) 2.0 3.5 3.0 2.5 2.0 1.0 Waveform Parameters: tr=8µ µs td=20µ µs I/O pin to GND pin 6.0 6.5 Typical Variation of CIN vs. VIN Forward Voltage vs. Forward Current 5.0 1.5 5.5 Peak pulse Current (A) o Forward Voltage (V) Waveform Parameters: tr=8µ µs td=20µ µs 7.0 0.5 1.4 1.2 1.0 0.8 0.6 0.4 VDD = 5V, GND = 0V, f = 1MHz, T=25 oC, 0.2 0.0 4.5 0.0 5.0 5.5 6.0 6.5 7.0 0 Peak pulse Current (A) 1 2 3 4 5 Input Voltage (V) Transmission Line Pulsing (TLP) Current (A) Transmission Line Pulsing (TLP) Measurement 18 16 14 12 10 I/O to GND 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 Transmission Line Pulsing (TLP) Voltage (V) Revision 2013/08/27 ©2013-2014 Amazing Micro. 3 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Applications Information A. Design Considerations The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (IESD1) will pass through the ESD current path1. Thus, the ESD clamping voltage VCL of data line can be described as follow: VCL = Fwd voltage drop of D1 + supply voltage of VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30A in 1ns. Here d(IESD1)/dt can be approximated by ∆IESD1/∆t, or 30/(1x10-9). So power-rail ESD clamp ing circuit just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The AZC099-04S has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (IESD2) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. AZC099-04S L2 I ESD2 VDD rail I ESD1 D1 L1 + data line Vp _ VESD + Protected IC V CL D2 _ GND rail ESD current path 1 (I ESD1) ESD current path 2 (I ESD2) Fig. 1 Application of positive ESD pulse between data line and GND rail. Revision 2013/08/27 ©2013-2014 Amazing Micro. 4 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces B. Device Connection The AZC099-04S is designed to protect four data lines and power rails from transient over-voltage (such as ESD stress pulse). The device connection of AZC099-04S is shown in the Fig. 2. In Fig. 2, the four protected data lines are connected to the ESD protection pins (pin1, pin3, pin4, and pin6) of AZC099-04S. The ground pin (pin2) of AZC099-04S is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 5) of AZC099-04S is a positive reference pin. This pin should directly connect to the VDD rail of PCB. When pin 5 of AZC099-04S is connected to the VDD rail, the leakage current data line I/O 1 To I/O-port Connector I/O 2 I/O 1 data line I/O 2 6 AZC099-04S 1 GND rail 2 3 To I/O-port Connector of ESD protection pin of AZC099-04S becomes very small. Because the pin 5 of AZC099-04S is directly connected to VDD rail, the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of AZC099-04S. AZC099-04S can provide protection for 4 I/O signal lines simultaneously. If the number of I/O signal lines is less than 4, the unused I/O pins can be simply left as NC pins. In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1µ µF chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the AZC099-04S. 5 4 I/O 3 VDD rail *Optional 0.1µ µF Chip Cap. I/O 3 data line I/O 4 data line To Protected IC To Protected IC I/O 4 Fig. 2 Data lines and power rails connection of AZC099-04S. Revision 2013/08/27 ©2013-2014 Amazing Micro. 5 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces C. Applications 1. Universal Serial Bus (USB) ESD Protection The AZC099-04S can be used to protect the USB port on the monitors, computers, peripherals or portable systems. The ESD protection scheme for dual USB ports is shown in Fig. 3. In the Fig.3, each device will protect up two USB ports. The voltage bus (VBUS) of USB ports (port1 and port2) are connected to the power pin (pin 5) of AZC099-04S. Each data line (D+/D-) of USB port is connected to the ESD protection pin of AZC099-04S. When ESD voltage pulse appears on the data line, the ESD pulse current will be conducted by AZC099-04S away from the USB controller chip. In addition, the ESD pulse current also can be conducted by AZC099-04S away from the USB controller chip when the ESD voltage pulse appears on the voltage bus (VBUS) of USB port. Therefore, the data lines (D+/D-) and voltage bus (VBUS) of two USB ports are complementally protected with an AZC099-04S. V BUS V BUS D+ RT D_ USB Port1 4 USB Controller 5 CT 6 CT RT GND CT 3 2 1 AZC099-04S V BUS CT D+ RT D _ USB Port2 RT GND GND Fig. 3 ESD Protection scheme for dual USB ports by using AZC099-04S. Revision 2013/08/27 ©2013-2014 Amazing Micro. 6 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces 2. Audio Interface ESD Protection For the audio interface, the Right/Left channel and TMC terminals should be protected from the ESD stress. The AZC099-04S can be used for the audio interface ESD protection. The ESD protection scheme for audio interface is shown in the Fig. 4. In the Fig. 4, the Right and Left channels of audio connector are connected to ESD protection pins (such as pin 1 and pin 6) of AZC099-04S. In addition, the TMC terminals of audio connector are also connected to ESD protection pins (such as pin 3 and pin 4) of AZC099-04S. For the power pin (pin 5) of AZC099-04S, it should directly connect to the VDD power supply. When ESD voltage pulse appears on the Right/Left channel or TMC terminals of audio connector, the ESD pulse current will be discharged by AZC099-04S. Therefore, the Right/Left channel and TMC terminals of audio chip are complementally protected with an AZC099-04S. Right Channel Left Channel 2 3 GND AZC099-04S 1 Audio Chip 6 5 VDD Audio Connector 4 TMC Term inal TMC Term inal Fig. 4 ESD Protection scheme for audio interface by using AZC099-04S. Revision 2013/08/27 ©2013-2014 Amazing Micro. 7 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces 3. Video (VGA) Interface ESD Protection For the video (VGA) interface, the exposed lines such as Red, Green, Blue, H-Sync, V-Sync, DDC CLK, and DDC DAT lines for plug and monitors should be protected from the ESD stress. The AZC099-04S also can be used for the video (VGA) interface ESD protection. The ESD protection scheme for video (VGA) interface is shown in the Fig. 5. In Fig. 5, each exposed line 2 3 AZC099-04S 1 GND of video interface should connect to the ESD protection pin of AZC099-04S. The power pin (pin 5) of AZC099-04S just directly connected to the VDD power supply. When ESD voltage appears on the signal line, the ESD pulse current will be discharged by AZC099-04S. Therefore, all exposed lines of video interface are complementally protected with an AZC099-04S. 6 VDD 5 4 Blue Green Red 5 1 15 11 V -Sync DDC CLK H-Sync 2 3 AZC099-04S 1 GND DDC DAT 6 5 VDD 4 Fig. 5 ESD Protection scheme for video (VGA) interface by using AZC099-04S. Revision 2013/08/27 ©2013-2014 Amazing Micro. 8 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces 4. SIM Port ESD Protection protection pin of AZC099-04S is left to be floated. When ESD voltage pulse appears on the one of the signal lines, the ESD pulse current will be conducted by AZC099-04S away from the controller chip. In addition, the ESD pulse current also can be conducted by AZC099-04S away from the controller chip when the ESD voltage pulse appears on the voltage bus (VCC) of SIM port. Therefore, the signal lines (I/O, Clock, and Reset) and voltage bus (VCC) of the SIM ports are all protected with an AZC099-04S. The AZC099-04S can be also used to protect the SIM port. The ESD protection scheme for a SIM port is shown in Fig. 6. In the Fig.6, the voltage bus (VCC) of SIM port is connected to the power pin (pin 5) of AZC099-04S. The ground bus (GND) of SIM port is connected to the ground pin (pin 2) of AZC099-04S. The other three signal lines, I/O, Clock, and Reset, are connected three ESD protection pins of AZC099-04S, respectively. The rest ESD I/O Clock Reset SIM VCC GND 2 3 6 AZC099-04S 1 5 4 Fig. 6 ESD Protection scheme for SIM port by using AZC099-04S Revision 2013/08/27 ©2013-2014 Amazing Micro. 9 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Mechanical Details SOT23-6L PACKAGE DIAGRAMS TOP VIEW PACKAGE DIMENSIONS Symbol Millimeters MIN. MIN. 1.45 A MAX. 0.057 A1 0 0.15 0.000 0.006 A2 0.9 1.3 0.035 0.051 b 0.3 0.5 0.012 0.020 c 0.08 0.21 0.003 0.008 D 2.72 3.12 0.107 0.123 E 1.4 1.8 0.055 0.071 E1 2.6 3 0.102 0.118 e 0.95BSC 0.037BSC e1 1.9BSC 0.075BSC L1 SIDE VIEW MAX. Inches 0.3 0.6 0.012 0.024 L 0.7REF 0.028REF L2 0.25BSC 0.010BSC Ɵ 0 0 8 8 Notes:
This dimension complies with JEDEC outline standard MO-178 Variation AB.
Dimensioning and tolerancing per ASME Y14.5M-1994.
All dimensions are in millimeters, and the dimensions in inches are for reference only.
1mm = 40 mils = 0.04 inches. END VIEW Revision 2013/08/27 ©2013-2014 Amazing Micro. 10 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces LAND LAYOUT Dimensions Index Millimeter Inches A 0.50~0.60 0.020~0.024 B 1.10 0.043 C 0.95 0.037 D 2.50 0.098 E 1.40 0.055 F 3.60 0.141 Notes: This LAND LAYOUT is purposes only. Please for reference consult your manufacturing partners to ensure your company’s PCB design guidelines are met. MARKING CODE Part Number S15X C99XY C99X AZC099-04S.R7F (ROHS) AZC099-04S.R7G (Green Part) Marking Code C99XY C96XY C99 = Device Code X = Date Code Y = Control Code Ordering Information PN# Material Type Reel size MOQ/internal box MOQ/carton AZC099-04S.R7G Green T/R 7 inch 4 reel=12,000/box 6 box=72,000/carton Revision 2013/08/27 ©2013-2014 Amazing Micro. 11 www.amazingIC.com AZC099-04S Low Capacitance ESD Protection Array For High Speed Data Interfaces Revision History Revision Modification Description Revision 2007/02/07 Original Release. Revision 2007/02/27 Update the VESD spec in the ABSOLUTE MAXIMUM RATINGS. Revision 2007/05/15 Update the Marking Code from C99X to C99XY. Revision 2007/10/19 Update the information of Land Layout. Revision 2008/01/21 Present the Mechanical Details by JEDEC formation. Revision 2008/03/24 Modify the description in the Features, from “5V operating voltage” to “For low operating voltage applications: 5V, 4.2V, 3.3V, 2.5V”. Revision 2008/08/01 Add the marking code for Green Part. Revision 2008/12/26 Update the value of “Index A” in the Land Layout. Revision 2009/12/16 Modify the indication of Marking Code. Revision 2010/08/16 Add the tolerances to the package dimensions of “D” and “E”. Revision 2010/08/23 Update the PACKAGE DIMENSIONS. Revision 2011/07/30 1. Update the Company Logo. 2. Add the Ordering Information. Revision 2013/08/27 1. Update the level of ESD per IEC 61000-4-2 . 2. Update the level of EFT per IEC 61000-4-4 . 3. Update the TYP value of ESD Holding Voltage. Revision 2013/08/27 ©2013-2014 Amazing Micro. 12 www.amazingIC.com